| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.98 | 95.29 | 93.64 | 95.33 | 94.46 | 97.53 | 99.62 |
| T2762 | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1148111804 | Jul 18 07:48:52 PM PDT 24 | Jul 18 07:49:05 PM PDT 24 | 213273752 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1337849869 | Jul 18 07:41:01 PM PDT 24 | Jul 18 07:58:40 PM PDT 24 | 21466071299 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/18.xbar_error_random.3565317403 | Jul 18 07:48:34 PM PDT 24 | Jul 18 07:49:18 PM PDT 24 | 518227399 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/29.xbar_same_source.638909918 | Jul 18 07:51:54 PM PDT 24 | Jul 18 07:52:25 PM PDT 24 | 954278836 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3537767186 | Jul 18 08:01:04 PM PDT 24 | Jul 18 08:04:52 PM PDT 24 | 1351738905 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2085705256 | Jul 18 08:05:02 PM PDT 24 | Jul 18 08:21:54 PM PDT 24 | 52544724219 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2873602105 | Jul 18 08:00:20 PM PDT 24 | Jul 18 08:00:39 PM PDT 24 | 359597728 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1505589 | Jul 18 07:47:36 PM PDT 24 | Jul 18 07:50:09 PM PDT 24 | 3568789974 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/0.xbar_random.2536022055 | Jul 18 07:40:02 PM PDT 24 | Jul 18 07:40:28 PM PDT 24 | 557266923 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3531555839 | Jul 18 07:44:14 PM PDT 24 | Jul 18 07:51:37 PM PDT 24 | 7476767257 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/51.xbar_same_source.3477675078 | Jul 18 07:56:55 PM PDT 24 | Jul 18 07:57:54 PM PDT 24 | 1898926889 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/17.xbar_smoke.561686647 | Jul 18 07:48:40 PM PDT 24 | Jul 18 07:48:48 PM PDT 24 | 49794313 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/65.xbar_error_random.3174954997 | Jul 18 07:59:44 PM PDT 24 | Jul 18 08:00:29 PM PDT 24 | 539581082 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.945202547 | Jul 18 07:48:44 PM PDT 24 | Jul 18 07:54:31 PM PDT 24 | 19870314610 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3580398549 | Jul 18 07:46:55 PM PDT 24 | Jul 18 07:47:17 PM PDT 24 | 466589393 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/93.xbar_same_source.274793588 | Jul 18 08:04:25 PM PDT 24 | Jul 18 08:05:12 PM PDT 24 | 1506260993 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1438486346 | Jul 18 07:58:27 PM PDT 24 | Jul 18 08:00:11 PM PDT 24 | 5803192542 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2949994733 | Jul 18 08:04:09 PM PDT 24 | Jul 18 08:04:37 PM PDT 24 | 268817600 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.921779860 | Jul 18 08:04:45 PM PDT 24 | Jul 18 08:24:35 PM PDT 24 | 64122077663 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2735824825 | Jul 18 07:58:12 PM PDT 24 | Jul 18 08:00:31 PM PDT 24 | 8225843922 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2394971166 | Jul 18 07:50:40 PM PDT 24 | Jul 18 07:55:29 PM PDT 24 | 4376389176 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1032868523 | Jul 18 07:41:02 PM PDT 24 | Jul 18 07:42:33 PM PDT 24 | 8626109048 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.367580752 | Jul 18 07:41:57 PM PDT 24 | Jul 18 07:42:07 PM PDT 24 | 55486358 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2608269191 | Jul 18 07:53:46 PM PDT 24 | Jul 18 07:55:14 PM PDT 24 | 5263345926 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2303933875 | Jul 18 07:44:16 PM PDT 24 | Jul 18 07:48:44 PM PDT 24 | 2864454781 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/0.xbar_error_random.704267830 | Jul 18 07:40:26 PM PDT 24 | Jul 18 07:40:39 PM PDT 24 | 312616048 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1671068769 | Jul 18 07:59:39 PM PDT 24 | Jul 18 08:01:46 PM PDT 24 | 293100906 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.439251383 | Jul 18 07:53:46 PM PDT 24 | Jul 18 07:55:03 PM PDT 24 | 4152046196 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1679141326 | Jul 18 07:56:33 PM PDT 24 | Jul 18 08:07:58 PM PDT 24 | 38536785795 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3072908374 | Jul 18 08:04:27 PM PDT 24 | Jul 18 08:04:44 PM PDT 24 | 199483536 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3997117462 | Jul 18 08:05:15 PM PDT 24 | Jul 18 08:05:28 PM PDT 24 | 78760138 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1966263015 | Jul 18 08:02:27 PM PDT 24 | Jul 18 08:09:09 PM PDT 24 | 4771494005 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.520858843 | Jul 18 07:42:33 PM PDT 24 | Jul 18 07:43:06 PM PDT 24 | 562304433 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2661605583 | Jul 18 07:48:42 PM PDT 24 | Jul 18 07:48:53 PM PDT 24 | 66176716 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3145965288 | Jul 18 07:44:11 PM PDT 24 | Jul 18 07:53:21 PM PDT 24 | 5799866114 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1914009572 | Jul 18 08:03:01 PM PDT 24 | Jul 18 08:38:47 PM PDT 24 | 107082234058 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/86.xbar_error_random.2365391123 | Jul 18 08:02:59 PM PDT 24 | Jul 18 08:03:08 PM PDT 24 | 106150188 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/8.xbar_smoke.2072417400 | Jul 18 07:44:35 PM PDT 24 | Jul 18 07:44:42 PM PDT 24 | 41628065 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1423562532 | Jul 18 07:59:57 PM PDT 24 | Jul 18 08:01:35 PM PDT 24 | 5455324326 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/52.xbar_error_random.1643949959 | Jul 18 07:56:57 PM PDT 24 | Jul 18 07:57:12 PM PDT 24 | 281569794 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/98.xbar_same_source.1082551875 | Jul 18 08:05:03 PM PDT 24 | Jul 18 08:05:23 PM PDT 24 | 584180375 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3363985761 | Jul 18 07:55:09 PM PDT 24 | Jul 18 07:56:43 PM PDT 24 | 1266354294 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2258262601 | Jul 18 08:02:28 PM PDT 24 | Jul 18 08:05:34 PM PDT 24 | 2107236929 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1619581591 | Jul 18 07:54:27 PM PDT 24 | Jul 18 07:55:04 PM PDT 24 | 742699142 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3885619203 | Jul 18 07:59:40 PM PDT 24 | Jul 18 07:59:47 PM PDT 24 | 50544330 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.407030467 | Jul 18 07:44:12 PM PDT 24 | Jul 18 07:45:07 PM PDT 24 | 4742077836 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3538022467 | Jul 18 07:41:16 PM PDT 24 | Jul 18 07:43:34 PM PDT 24 | 3182713998 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2632683031 | Jul 18 08:02:15 PM PDT 24 | Jul 18 08:03:43 PM PDT 24 | 5321455497 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.748248131 | Jul 18 08:04:04 PM PDT 24 | Jul 18 08:04:18 PM PDT 24 | 84264116 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/49.xbar_same_source.3050720966 | Jul 18 07:56:17 PM PDT 24 | Jul 18 07:57:17 PM PDT 24 | 1981963452 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3296645630 | Jul 18 07:46:02 PM PDT 24 | Jul 18 07:46:54 PM PDT 24 | 1291082606 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.758115584 | Jul 18 07:53:51 PM PDT 24 | Jul 18 07:54:30 PM PDT 24 | 1018969426 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3572727502 | Jul 18 07:48:40 PM PDT 24 | Jul 18 07:57:17 PM PDT 24 | 43889852934 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3311089691 | Jul 18 07:58:28 PM PDT 24 | Jul 18 08:05:42 PM PDT 24 | 40117352691 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1216918447 | Jul 18 07:42:19 PM PDT 24 | Jul 18 07:51:10 PM PDT 24 | 11299762129 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.621708965 | Jul 18 07:54:08 PM PDT 24 | Jul 18 08:13:59 PM PDT 24 | 110040101725 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/92.xbar_same_source.922961225 | Jul 18 08:04:04 PM PDT 24 | Jul 18 08:05:20 PM PDT 24 | 2564373170 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/14.xbar_stress_all.781980950 | Jul 18 07:47:13 PM PDT 24 | Jul 18 07:49:29 PM PDT 24 | 1912533976 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1558507535 | Jul 18 07:51:06 PM PDT 24 | Jul 18 07:54:58 PM PDT 24 | 3159746817 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1774603245 | Jul 18 07:47:49 PM PDT 24 | Jul 18 07:49:22 PM PDT 24 | 8387290952 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.67800453 | Jul 18 07:40:05 PM PDT 24 | Jul 18 07:41:39 PM PDT 24 | 8961343563 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.961135438 | Jul 18 07:48:51 PM PDT 24 | Jul 18 07:49:25 PM PDT 24 | 281538858 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.649181516 | Jul 18 07:59:59 PM PDT 24 | Jul 18 08:00:21 PM PDT 24 | 176667366 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3322636252 | Jul 18 08:03:52 PM PDT 24 | Jul 18 08:04:20 PM PDT 24 | 218172128 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3893537820 | Jul 18 08:03:52 PM PDT 24 | Jul 18 08:24:00 PM PDT 24 | 66697372176 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1590130426 | Jul 18 07:41:14 PM PDT 24 | Jul 18 07:41:52 PM PDT 24 | 272958897 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1014591680 | Jul 18 07:58:17 PM PDT 24 | Jul 18 08:01:25 PM PDT 24 | 11585989497 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2128384449 | Jul 18 07:58:28 PM PDT 24 | Jul 18 07:58:54 PM PDT 24 | 284978717 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3395162112 | Jul 18 08:04:46 PM PDT 24 | Jul 18 08:05:46 PM PDT 24 | 1585377432 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/18.chip_csr_rw.302926380 | Jul 18 07:48:42 PM PDT 24 | Jul 18 07:57:51 PM PDT 24 | 5823129700 ps | ||
| T685 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1127228215 | Jul 18 07:53:45 PM PDT 24 | Jul 18 08:02:58 PM PDT 24 | 13599135066 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.4273038658 | Jul 18 07:41:58 PM PDT 24 | Jul 18 07:48:44 PM PDT 24 | 22827398125 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3329749221 | Jul 18 07:57:54 PM PDT 24 | Jul 18 08:07:10 PM PDT 24 | 55467482798 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/73.xbar_error_random.2609910800 | Jul 18 08:00:42 PM PDT 24 | Jul 18 08:00:53 PM PDT 24 | 87091922 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/63.xbar_smoke.3183822531 | Jul 18 07:59:17 PM PDT 24 | Jul 18 07:59:28 PM PDT 24 | 211060170 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3764347322 | Jul 18 07:51:04 PM PDT 24 | Jul 18 07:51:12 PM PDT 24 | 42019966 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3093372251 | Jul 18 07:40:47 PM PDT 24 | Jul 18 08:55:48 PM PDT 24 | 30745198380 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/12.xbar_smoke.4207506895 | Jul 18 07:46:25 PM PDT 24 | Jul 18 07:46:34 PM PDT 24 | 144897876 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/61.xbar_smoke.3635594040 | Jul 18 07:58:28 PM PDT 24 | Jul 18 07:58:35 PM PDT 24 | 49066345 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1535671276 | Jul 18 08:01:05 PM PDT 24 | Jul 18 08:02:15 PM PDT 24 | 995855693 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/72.xbar_random.3858513724 | Jul 18 08:00:44 PM PDT 24 | Jul 18 08:00:58 PM PDT 24 | 135281040 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2722292752 | Jul 18 08:00:20 PM PDT 24 | Jul 18 08:05:44 PM PDT 24 | 10449278902 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3083069113 | Jul 18 07:43:28 PM PDT 24 | Jul 18 07:53:29 PM PDT 24 | 8126950116 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/89.xbar_error_random.571457095 | Jul 18 08:03:53 PM PDT 24 | Jul 18 08:05:02 PM PDT 24 | 1832401976 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2504337317 | Jul 18 07:59:41 PM PDT 24 | Jul 18 08:17:41 PM PDT 24 | 96104765114 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3509919938 | Jul 18 08:05:17 PM PDT 24 | Jul 18 08:07:14 PM PDT 24 | 6299786662 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.691765381 | Jul 18 07:52:34 PM PDT 24 | Jul 18 07:53:35 PM PDT 24 | 5629391286 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1673663238 | Jul 18 07:59:42 PM PDT 24 | Jul 18 07:59:56 PM PDT 24 | 95406170 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/41.xbar_smoke.1084454943 | Jul 18 07:54:51 PM PDT 24 | Jul 18 07:55:02 PM PDT 24 | 241562325 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/44.xbar_random.1595984806 | Jul 18 07:55:22 PM PDT 24 | Jul 18 07:56:39 PM PDT 24 | 2060527386 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3834430021 | Jul 18 07:41:55 PM PDT 24 | Jul 18 07:49:17 PM PDT 24 | 24240759492 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1047552241 | Jul 18 08:01:49 PM PDT 24 | Jul 18 08:04:11 PM PDT 24 | 337751123 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1214851395 | Jul 18 07:47:36 PM PDT 24 | Jul 18 07:50:33 PM PDT 24 | 10162482439 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1544068823 | Jul 18 07:49:00 PM PDT 24 | Jul 18 07:50:49 PM PDT 24 | 1394990255 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3863318478 | Jul 18 07:56:16 PM PDT 24 | Jul 18 07:56:25 PM PDT 24 | 63517509 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1045984471 | Jul 18 07:59:44 PM PDT 24 | Jul 18 08:01:11 PM PDT 24 | 1181769246 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1341640255 | Jul 18 08:05:17 PM PDT 24 | Jul 18 08:06:55 PM PDT 24 | 490754678 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2122261697 | Jul 18 08:01:51 PM PDT 24 | Jul 18 08:03:03 PM PDT 24 | 6682001200 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3141863096 | Jul 18 07:52:52 PM PDT 24 | Jul 18 08:03:55 PM PDT 24 | 14525510300 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2525924361 | Jul 18 07:47:52 PM PDT 24 | Jul 18 07:47:58 PM PDT 24 | 5802450 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3707028294 | Jul 18 07:49:50 PM PDT 24 | Jul 18 07:50:12 PM PDT 24 | 166773375 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/66.xbar_smoke.901916236 | Jul 18 07:59:40 PM PDT 24 | Jul 18 07:59:47 PM PDT 24 | 36964593 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1413454841 | Jul 18 07:59:25 PM PDT 24 | Jul 18 08:03:58 PM PDT 24 | 3630877732 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3305339717 | Jul 18 07:53:07 PM PDT 24 | Jul 18 07:54:45 PM PDT 24 | 1549210119 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2002490255 | Jul 18 07:48:42 PM PDT 24 | Jul 18 08:01:50 PM PDT 24 | 11983635875 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.424658308 | Jul 18 08:02:29 PM PDT 24 | Jul 18 08:08:30 PM PDT 24 | 19740291328 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.680465088 | Jul 18 07:56:58 PM PDT 24 | Jul 18 07:58:15 PM PDT 24 | 3923615629 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2323155430 | Jul 18 07:52:55 PM PDT 24 | Jul 18 07:53:16 PM PDT 24 | 272805280 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2308966972 | Jul 18 08:03:00 PM PDT 24 | Jul 18 08:09:36 PM PDT 24 | 5058225719 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3193549294 | Jul 18 08:02:12 PM PDT 24 | Jul 18 08:03:51 PM PDT 24 | 5411596772 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/31.xbar_stress_all.350789644 | Jul 18 07:52:32 PM PDT 24 | Jul 18 07:59:14 PM PDT 24 | 4283684708 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2994411954 | Jul 18 07:52:14 PM PDT 24 | Jul 18 07:52:37 PM PDT 24 | 194160535 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/22.xbar_same_source.1945207785 | Jul 18 07:50:14 PM PDT 24 | Jul 18 07:51:24 PM PDT 24 | 2141067382 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1063370246 | Jul 18 08:05:02 PM PDT 24 | Jul 18 08:05:10 PM PDT 24 | 59859199 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/13.xbar_error_random.382159949 | Jul 18 07:46:39 PM PDT 24 | Jul 18 07:47:37 PM PDT 24 | 1643063460 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/38.xbar_same_source.3099410921 | Jul 18 07:54:10 PM PDT 24 | Jul 18 07:55:04 PM PDT 24 | 1788988797 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2633935993 | Jul 18 07:54:05 PM PDT 24 | Jul 18 07:55:10 PM PDT 24 | 4033081396 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1054828255 | Jul 18 07:44:54 PM PDT 24 | Jul 18 07:55:34 PM PDT 24 | 56400277485 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3581880671 | Jul 18 07:53:26 PM PDT 24 | Jul 18 07:53:53 PM PDT 24 | 18373625 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/63.xbar_same_source.2601433179 | Jul 18 07:59:20 PM PDT 24 | Jul 18 08:00:13 PM PDT 24 | 1726778443 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3511366492 | Jul 18 07:51:18 PM PDT 24 | Jul 18 08:05:21 PM PDT 24 | 22313492453 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3216371608 | Jul 18 08:00:20 PM PDT 24 | Jul 18 08:30:17 PM PDT 24 | 91268969904 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/19.xbar_random.618289452 | Jul 18 07:48:58 PM PDT 24 | Jul 18 07:49:23 PM PDT 24 | 644011921 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/71.xbar_error_random.2211987704 | Jul 18 08:00:24 PM PDT 24 | Jul 18 08:00:31 PM PDT 24 | 38928485 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/34.xbar_smoke.2966997084 | Jul 18 07:52:51 PM PDT 24 | Jul 18 07:52:59 PM PDT 24 | 39946151 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2608508959 | Jul 18 08:04:45 PM PDT 24 | Jul 18 08:08:19 PM PDT 24 | 19688840143 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.574704338 | Jul 18 07:51:35 PM PDT 24 | Jul 18 07:52:31 PM PDT 24 | 502535783 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.172435533 | Jul 18 07:55:30 PM PDT 24 | Jul 18 08:00:03 PM PDT 24 | 1609412274 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3960054473 | Jul 18 07:44:54 PM PDT 24 | Jul 18 09:13:38 PM PDT 24 | 30918216987 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.703761989 | Jul 18 07:55:12 PM PDT 24 | Jul 18 07:56:38 PM PDT 24 | 4696172693 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2845724464 | Jul 18 08:03:54 PM PDT 24 | Jul 18 08:19:20 PM PDT 24 | 47622431069 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/79.xbar_smoke.4123512802 | Jul 18 08:01:58 PM PDT 24 | Jul 18 08:02:08 PM PDT 24 | 204364686 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.470187618 | Jul 18 07:47:50 PM PDT 24 | Jul 18 07:49:12 PM PDT 24 | 4567256531 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1282492522 | Jul 18 07:56:33 PM PDT 24 | Jul 18 07:58:30 PM PDT 24 | 6821281124 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/0.xbar_smoke.1754710732 | Jul 18 07:40:01 PM PDT 24 | Jul 18 07:40:12 PM PDT 24 | 239707150 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4197746839 | Jul 18 07:41:15 PM PDT 24 | Jul 18 08:27:44 PM PDT 24 | 158382540594 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/21.xbar_same_source.3701518376 | Jul 18 07:49:33 PM PDT 24 | Jul 18 07:49:48 PM PDT 24 | 430549245 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3069437162 | Jul 18 07:59:42 PM PDT 24 | Jul 18 08:06:02 PM PDT 24 | 20943461031 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.847906761 | Jul 18 07:53:51 PM PDT 24 | Jul 18 08:01:13 PM PDT 24 | 7871353728 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3418047506 | Jul 18 07:51:04 PM PDT 24 | Jul 18 07:51:15 PM PDT 24 | 58105201 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.676971763 | Jul 18 07:55:22 PM PDT 24 | Jul 18 08:10:49 PM PDT 24 | 52456944784 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1465169523 | Jul 18 07:56:14 PM PDT 24 | Jul 18 07:56:30 PM PDT 24 | 137914878 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1173120364 | Jul 18 08:02:11 PM PDT 24 | Jul 18 08:02:27 PM PDT 24 | 52522178 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/1.xbar_smoke.4100239413 | Jul 18 07:40:46 PM PDT 24 | Jul 18 07:40:54 PM PDT 24 | 54910613 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3952095728 | Jul 18 07:47:49 PM PDT 24 | Jul 18 07:48:02 PM PDT 24 | 111961111 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/3.xbar_smoke.2710832548 | Jul 18 07:41:42 PM PDT 24 | Jul 18 07:41:52 PM PDT 24 | 212450154 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.980363410 | Jul 18 07:53:48 PM PDT 24 | Jul 18 07:57:45 PM PDT 24 | 626081337 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/42.xbar_random.560170391 | Jul 18 07:54:49 PM PDT 24 | Jul 18 07:56:17 PM PDT 24 | 2196775197 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.615644133 | Jul 18 07:57:17 PM PDT 24 | Jul 18 08:06:20 PM PDT 24 | 30214961954 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/78.xbar_same_source.3343187086 | Jul 18 08:01:51 PM PDT 24 | Jul 18 08:03:11 PM PDT 24 | 2459367443 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.4264885714 | Jul 18 08:02:33 PM PDT 24 | Jul 18 08:02:41 PM PDT 24 | 45082805 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2970321917 | Jul 18 08:05:16 PM PDT 24 | Jul 18 08:05:24 PM PDT 24 | 48872929 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3602732107 | Jul 18 08:02:33 PM PDT 24 | Jul 18 08:03:03 PM PDT 24 | 757729581 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2848141253 | Jul 18 07:45:52 PM PDT 24 | Jul 18 07:48:15 PM PDT 24 | 273530961 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2631486076 | Jul 18 07:53:45 PM PDT 24 | Jul 18 07:55:00 PM PDT 24 | 6604504271 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2640374261 | Jul 18 07:46:23 PM PDT 24 | Jul 18 08:11:20 PM PDT 24 | 15888925294 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.560715281 | Jul 18 08:03:55 PM PDT 24 | Jul 18 08:05:54 PM PDT 24 | 3149158142 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/3.xbar_error_random.3928934103 | Jul 18 07:42:03 PM PDT 24 | Jul 18 07:42:35 PM PDT 24 | 414735575 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3863792130 | Jul 18 07:54:04 PM PDT 24 | Jul 18 07:57:18 PM PDT 24 | 2680363190 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1009266580 | Jul 18 07:52:32 PM PDT 24 | Jul 18 08:18:19 PM PDT 24 | 81588554496 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2612611906 | Jul 18 07:57:00 PM PDT 24 | Jul 18 07:58:34 PM PDT 24 | 8347504479 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/75.xbar_error_random.2865195724 | Jul 18 08:01:27 PM PDT 24 | Jul 18 08:01:56 PM PDT 24 | 775694088 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.476561813 | Jul 18 07:48:59 PM PDT 24 | Jul 18 07:52:39 PM PDT 24 | 12678650046 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2160110702 | Jul 18 07:51:55 PM PDT 24 | Jul 18 07:52:22 PM PDT 24 | 594995835 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3613756170 | Jul 18 07:52:32 PM PDT 24 | Jul 18 07:58:33 PM PDT 24 | 9275847102 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/49.xbar_random.25084479 | Jul 18 07:56:15 PM PDT 24 | Jul 18 07:56:22 PM PDT 24 | 28550025 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1720045221 | Jul 18 07:47:49 PM PDT 24 | Jul 18 07:58:20 PM PDT 24 | 5685752416 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1292628514 | Jul 18 07:53:28 PM PDT 24 | Jul 18 07:53:42 PM PDT 24 | 114863312 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2304587176 | Jul 18 08:02:27 PM PDT 24 | Jul 18 08:04:12 PM PDT 24 | 9869013047 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1483231431 | Jul 18 08:02:11 PM PDT 24 | Jul 18 08:03:26 PM PDT 24 | 3985611930 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3569444386 | Jul 18 08:03:29 PM PDT 24 | Jul 18 08:04:49 PM PDT 24 | 4455974662 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.4020889066 | Jul 18 08:00:13 PM PDT 24 | Jul 18 08:00:52 PM PDT 24 | 2293963504 ps | ||
| T37 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3444442978 | Jul 18 08:44:00 PM PDT 24 | Jul 18 08:49:22 PM PDT 24 | 4987044592 ps | ||
| T38 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3250051607 | Jul 18 08:43:56 PM PDT 24 | Jul 18 08:50:12 PM PDT 24 | 5470209268 ps | ||
| T39 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2481726563 | Jul 18 08:44:05 PM PDT 24 | Jul 18 08:47:41 PM PDT 24 | 4229547359 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2040208344 | Jul 18 08:43:59 PM PDT 24 | Jul 18 08:49:58 PM PDT 24 | 5639654297 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2393179602 | Jul 18 08:44:00 PM PDT 24 | Jul 18 08:49:07 PM PDT 24 | 5432224465 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.836086851 | Jul 18 08:44:10 PM PDT 24 | Jul 18 08:49:56 PM PDT 24 | 5090059980 ps | ||
| T195 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3646443505 | Jul 18 08:43:45 PM PDT 24 | Jul 18 08:48:41 PM PDT 24 | 5413487146 ps | ||
| T196 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1322016073 | Jul 18 08:44:18 PM PDT 24 | Jul 18 08:49:33 PM PDT 24 | 4664288580 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1107348666 | Jul 18 08:44:01 PM PDT 24 | Jul 18 08:47:45 PM PDT 24 | 4451040840 ps | ||
| T198 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1035586225 | Jul 18 08:43:47 PM PDT 24 | Jul 18 08:48:19 PM PDT 24 | 4933531396 ps |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.1406376630 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4347581000 ps |
| CPU time | 843.8 seconds |
| Started | Jul 18 08:35:39 PM PDT 24 |
| Finished | Jul 18 08:49:44 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-95e32c3c-0752-4f1a-91be-ef12ba99d0eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406376630 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1406376630 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.596459095 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 26865485496 ps |
| CPU time | 3700.7 seconds |
| Started | Jul 18 07:46:41 PM PDT 24 |
| Finished | Jul 18 08:48:23 PM PDT 24 |
| Peak memory | 593188 kb |
| Host | smart-2944cc8e-1886-45b6-b74d-98d8685d8a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596459095 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.596459095 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1995322161 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 73366019889 ps |
| CPU time | 828.56 seconds |
| Started | Jul 18 07:42:33 PM PDT 24 |
| Finished | Jul 18 07:56:22 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-26ea1f8e-e77b-4d4c-be2a-cffe01466fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995322161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1995322161 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2463724890 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 144673384745 ps |
| CPU time | 2733.07 seconds |
| Started | Jul 18 08:03:28 PM PDT 24 |
| Finished | Jul 18 08:49:02 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-cebc1161-1c06-4e89-b0a9-e200a5f6a983 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463724890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.2463724890 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3444442978 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4987044592 ps |
| CPU time | 320.39 seconds |
| Started | Jul 18 08:44:00 PM PDT 24 |
| Finished | Jul 18 08:49:22 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-8a92576b-8274-4416-b109-daa297e20223 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444442978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3444442978 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3168978075 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 14666313816 ps |
| CPU time | 3631.05 seconds |
| Started | Jul 18 08:25:38 PM PDT 24 |
| Finished | Jul 18 09:26:10 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-cec6292b-9b24-4f7e-8af7-775f07518b79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31689 78075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.3168978075 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2588624600 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 13769883285 ps |
| CPU time | 3261.82 seconds |
| Started | Jul 18 08:21:24 PM PDT 24 |
| Finished | Jul 18 09:15:47 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-66718cf1-0a70-4e3b-acd3-d4fedcf1b958 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588624600 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2588624600 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.843015111 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 76376131672 ps |
| CPU time | 1523.67 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 08:22:23 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-0fd6e5d1-1022-4e22-91a0-d26e22375f46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843015111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_d evice_slow_rsp.843015111 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2258375043 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 22902487243 ps |
| CPU time | 847.4 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:16:36 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-43c8fc86-673a-45f6-817b-0aa1869178fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258375043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2258375043 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3404080241 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 10314863384 ps |
| CPU time | 1174.81 seconds |
| Started | Jul 18 08:35:08 PM PDT 24 |
| Finished | Jul 18 08:54:43 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-2e9c0b31-cfc6-454e-853e-4bb7f69f5fde |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404080241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3404080241 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1811843985 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 6308914700 ps |
| CPU time | 1219.98 seconds |
| Started | Jul 18 08:37:14 PM PDT 24 |
| Finished | Jul 18 08:57:35 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-e5759255-33be-4e14-9147-059631c1c0f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811843985 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1811843985 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4014637640 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 114764136482 ps |
| CPU time | 2122.49 seconds |
| Started | Jul 18 07:42:32 PM PDT 24 |
| Finished | Jul 18 08:17:56 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f5ff7adb-9478-4ff3-b742-ccf07ed2d723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014637640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.4014637640 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.4116626896 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 91954035180 ps |
| CPU time | 1827.6 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 08:26:23 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-014c29c5-d514-4725-9d2e-62ddfccb3fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116626896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.4116626896 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.263896491 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 49904381708 ps |
| CPU time | 5586.03 seconds |
| Started | Jul 18 08:21:53 PM PDT 24 |
| Finished | Jul 18 09:55:01 PM PDT 24 |
| Peak memory | 620468 kb |
| Host | smart-1fcd29e9-e53a-44c4-aa0b-9a68deadfe55 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263896491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.263896491 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1017738580 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 3022672482 ps |
| CPU time | 339.32 seconds |
| Started | Jul 18 08:13:14 PM PDT 24 |
| Finished | Jul 18 08:18:54 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-f400b313-a3ef-4643-a706-cf292dc1239a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017 738580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1017738580 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3354166512 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 24569302280 ps |
| CPU time | 1272.04 seconds |
| Started | Jul 18 08:15:54 PM PDT 24 |
| Finished | Jul 18 08:37:07 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-5b0c50e2-1206-4051-96d0-8aaa16d72c41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3354166512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3354166512 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1362495205 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 6429855771 ps |
| CPU time | 622.09 seconds |
| Started | Jul 18 07:51:21 PM PDT 24 |
| Finished | Jul 18 08:01:44 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-09922a5b-9477-4463-b76c-2c721cf2f3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362495205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.1362495205 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.530517608 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 3079723292 ps |
| CPU time | 285.89 seconds |
| Started | Jul 18 08:38:21 PM PDT 24 |
| Finished | Jul 18 08:43:10 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-941287a1-c71a-4b03-b8f9-6812f009cdbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=530517608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.530517608 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.3021113926 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2860134060 ps |
| CPU time | 122.33 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:07:19 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-94772dba-e9cc-4a03-8cad-24b35bc12ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021113926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .3021113926 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.3559316014 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 3728343548 ps |
| CPU time | 556.05 seconds |
| Started | Jul 18 08:11:53 PM PDT 24 |
| Finished | Jul 18 08:21:10 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-679aece2-395d-4899-aebb-e9735489e2cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559316014 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.3559316014 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2383783486 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 77692564982 ps |
| CPU time | 1332.53 seconds |
| Started | Jul 18 07:45:00 PM PDT 24 |
| Finished | Jul 18 08:07:14 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-20d19836-39d8-4e5b-88b0-953784f002a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383783486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.2383783486 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3476665174 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3275629056 ps |
| CPU time | 592.19 seconds |
| Started | Jul 18 08:35:14 PM PDT 24 |
| Finished | Jul 18 08:45:07 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-e81ae701-aa8d-44ee-9d63-405072124dfc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476665174 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3476665174 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1218686001 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 5009400822 ps |
| CPU time | 450.92 seconds |
| Started | Jul 18 07:46:57 PM PDT 24 |
| Finished | Jul 18 07:54:30 PM PDT 24 |
| Peak memory | 599792 kb |
| Host | smart-b7825988-039c-4073-9df2-5ace6aff2706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218686001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1218686001 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.915522839 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 122103834672 ps |
| CPU time | 2102.84 seconds |
| Started | Jul 18 07:51:53 PM PDT 24 |
| Finished | Jul 18 08:26:57 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-2eb3ff92-5eec-4eed-82f6-f93db20bccd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915522839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.915522839 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.371867909 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 7190099226 ps |
| CPU time | 1171.83 seconds |
| Started | Jul 18 08:36:19 PM PDT 24 |
| Finished | Jul 18 08:55:53 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-146404ed-1bfd-4ab4-a20b-ee9e51c80b32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371867909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.371867909 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.730842586 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4663444255 ps |
| CPU time | 617.92 seconds |
| Started | Jul 18 08:30:47 PM PDT 24 |
| Finished | Jul 18 08:41:07 PM PDT 24 |
| Peak memory | 624892 kb |
| Host | smart-3d40eb0a-b573-49b9-af78-7e9aa9d5336f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730842586 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.730842586 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.445412862 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 31536104730 ps |
| CPU time | 569.23 seconds |
| Started | Jul 18 07:46:26 PM PDT 24 |
| Finished | Jul 18 07:55:56 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-86002b9d-6693-4b3c-b4d4-5368d92c7f8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445412862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_d evice_slow_rsp.445412862 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3969306536 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4797012936 ps |
| CPU time | 624.26 seconds |
| Started | Jul 18 08:14:28 PM PDT 24 |
| Finished | Jul 18 08:24:54 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-2a9fbc95-5a17-4669-8c54-b676e1bf332b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3969306536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.3969306536 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1496260218 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1326837951 ps |
| CPU time | 111.76 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:46:04 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-06910a43-65ea-423b-b410-d3f2e60e196f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496260218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1496260218 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.4046416673 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 10646082198 ps |
| CPU time | 912.8 seconds |
| Started | Jul 18 08:19:17 PM PDT 24 |
| Finished | Jul 18 08:34:31 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-70f87323-a828-49d5-93d8-5ade3add0571 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046416673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.4046416673 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3452884544 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3315408717 ps |
| CPU time | 308.79 seconds |
| Started | Jul 18 08:18:21 PM PDT 24 |
| Finished | Jul 18 08:23:31 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-23cc53c0-089a-44c2-ae2e-7f747ebe11fa |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452 884544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3452884544 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.317800175 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2294422390 ps |
| CPU time | 157.22 seconds |
| Started | Jul 18 07:51:18 PM PDT 24 |
| Finished | Jul 18 07:53:56 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-083c3964-831b-4382-8798-19f4e6cba228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317800175 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_reset_error.317800175 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1614284377 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5233449388 ps |
| CPU time | 446.59 seconds |
| Started | Jul 18 08:16:49 PM PDT 24 |
| Finished | Jul 18 08:24:17 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-1f28bdf7-a836-41de-9264-5c93317bafa2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16142843 77 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1614284377 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1999823967 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 42958868266 ps |
| CPU time | 5272.22 seconds |
| Started | Jul 18 08:20:01 PM PDT 24 |
| Finished | Jul 18 09:47:55 PM PDT 24 |
| Peak memory | 623864 kb |
| Host | smart-e2f91681-2f33-448a-a029-0a0f2662ef84 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1999823967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1999823967 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.2673562585 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5638907039 ps |
| CPU time | 530.1 seconds |
| Started | Jul 18 07:42:25 PM PDT 24 |
| Finished | Jul 18 07:51:15 PM PDT 24 |
| Peak memory | 599292 kb |
| Host | smart-06fa55c8-a2d0-43b9-be5a-f73f3a952ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673562585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.2673562585 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2084645345 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3468287952 ps |
| CPU time | 306.43 seconds |
| Started | Jul 18 08:41:43 PM PDT 24 |
| Finished | Jul 18 08:46:51 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-f0d534b4-7f7b-48e1-b8ed-857ca9b9904b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084645345 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2084645345 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1712856213 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 7582436804 ps |
| CPU time | 942.72 seconds |
| Started | Jul 18 08:38:00 PM PDT 24 |
| Finished | Jul 18 08:53:45 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-63cdd3c0-bfac-40e7-b1a3-3271f6c5311f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17128562 13 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.1712856213 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1991309754 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 3294739296 ps |
| CPU time | 309.51 seconds |
| Started | Jul 18 08:13:44 PM PDT 24 |
| Finished | Jul 18 08:18:55 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-c09360bb-eeb3-45ad-aaa2-8242e1d3a484 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991309754 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1991309754 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2955391471 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 5368854373 ps |
| CPU time | 334.73 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:59:20 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1c396546-1d19-41e3-b94c-73a9070e727d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955391471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2955391471 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.135611050 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5017623160 ps |
| CPU time | 692.83 seconds |
| Started | Jul 18 08:41:51 PM PDT 24 |
| Finished | Jul 18 08:53:25 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-c1630178-a134-45e7-baf6-cfb66f8126c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 135611050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.135611050 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.31807529 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 3222354137 ps |
| CPU time | 362.86 seconds |
| Started | Jul 18 08:29:11 PM PDT 24 |
| Finished | Jul 18 08:35:14 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-4efa93b5-6f88-4c67-9153-96393b6d5cea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180 7529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.31807529 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3538716667 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 8208973429 ps |
| CPU time | 97.52 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:02:20 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-2be6618d-b592-4415-bcf2-bd0f83a6c0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538716667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.3538716667 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3482040912 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 4057179962 ps |
| CPU time | 365.98 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 07:55:20 PM PDT 24 |
| Peak memory | 598556 kb |
| Host | smart-89b4fd3f-6454-41ea-a118-6a04618686c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482040912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3482040912 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1496569966 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 50194990223 ps |
| CPU time | 5939.43 seconds |
| Started | Jul 18 08:13:47 PM PDT 24 |
| Finished | Jul 18 09:52:49 PM PDT 24 |
| Peak memory | 624056 kb |
| Host | smart-09bf1ba0-63cf-4315-9f00-074b696f7cde |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496569966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1496569966 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2676807724 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 7346242571 ps |
| CPU time | 933.93 seconds |
| Started | Jul 18 08:34:04 PM PDT 24 |
| Finished | Jul 18 08:49:39 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-cea2c269-d37e-4aa2-91a5-f5cbf8f38902 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676807724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2676807724 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.618314398 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 5022904636 ps |
| CPU time | 500.62 seconds |
| Started | Jul 18 08:15:00 PM PDT 24 |
| Finished | Jul 18 08:23:23 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-577cdb55-5373-43d0-95e3-aaff1eac5d64 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618314398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ sram_ctrl_scrambled_access.618314398 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3447115389 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 5501662056 ps |
| CPU time | 566.59 seconds |
| Started | Jul 18 08:47:16 PM PDT 24 |
| Finished | Jul 18 08:56:44 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-e4c4f7ed-0edc-4178-857e-39258d90da7b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3447115389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3447115389 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.865634991 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4636619336 ps |
| CPU time | 364.1 seconds |
| Started | Jul 18 07:41:40 PM PDT 24 |
| Finished | Jul 18 07:47:45 PM PDT 24 |
| Peak memory | 599652 kb |
| Host | smart-c3737135-2eb6-4860-950f-653891a70b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865634991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.865634991 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.3949180795 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 7306423970 ps |
| CPU time | 734.26 seconds |
| Started | Jul 18 08:37:27 PM PDT 24 |
| Finished | Jul 18 08:49:43 PM PDT 24 |
| Peak memory | 621048 kb |
| Host | smart-da5a569d-424d-403c-95ba-871a143e21a0 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949180795 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3949180795 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.241968669 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 20621255330 ps |
| CPU time | 3206.7 seconds |
| Started | Jul 18 08:20:44 PM PDT 24 |
| Finished | Jul 18 09:14:12 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-a890665d-9247-4612-bf7f-cf5da42c92a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241968669 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.241968669 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1786448782 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3804491592 ps |
| CPU time | 347.92 seconds |
| Started | Jul 18 08:13:28 PM PDT 24 |
| Finished | Jul 18 08:19:18 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-6697892a-9ad6-4f6b-b052-d69b59678dce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786448782 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.1786448782 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3320838519 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 25447477140 ps |
| CPU time | 6244.47 seconds |
| Started | Jul 18 08:23:28 PM PDT 24 |
| Finished | Jul 18 10:07:34 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-e55b98e9-b995-4e31-833f-c1cd594f00dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320838519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3320838519 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3846378205 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 773439690 ps |
| CPU time | 305.93 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 08:04:29 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-b41ea172-9328-4651-97e6-e187cebc973b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846378205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.3846378205 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2563992010 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 5136028948 ps |
| CPU time | 795.87 seconds |
| Started | Jul 18 08:48:13 PM PDT 24 |
| Finished | Jul 18 09:01:29 PM PDT 24 |
| Peak memory | 650428 kb |
| Host | smart-ece1d1e6-e59d-45d5-8352-bb496e19fd2f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2563992010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2563992010 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.4048872517 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5535003760 ps |
| CPU time | 482.92 seconds |
| Started | Jul 18 08:46:15 PM PDT 24 |
| Finished | Jul 18 08:54:19 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-bff08322-ff06-469d-835a-fff653e21b9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4048872517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.4048872517 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.1339499032 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 4866028180 ps |
| CPU time | 533.61 seconds |
| Started | Jul 18 08:50:29 PM PDT 24 |
| Finished | Jul 18 08:59:24 PM PDT 24 |
| Peak memory | 650040 kb |
| Host | smart-14106c3a-6de2-4a7a-bda3-ef47d9c14ef1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1339499032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.1339499032 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2301009634 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 5086257570 ps |
| CPU time | 798.2 seconds |
| Started | Jul 18 08:12:08 PM PDT 24 |
| Finished | Jul 18 08:25:27 PM PDT 24 |
| Peak memory | 610888 kb |
| Host | smart-23b7cd62-6c7b-4de0-b70d-762904e01fd4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2301009634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.2301009634 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.295471458 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13515499180 ps |
| CPU time | 782.5 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 08:11:53 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-54689816-33f1-4743-9f87-aa447057710e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295471458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_ with_rand_reset.295471458 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.261633743 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 3928894678 ps |
| CPU time | 489.72 seconds |
| Started | Jul 18 08:30:07 PM PDT 24 |
| Finished | Jul 18 08:38:17 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-cb0aec09-6eb0-41a6-b407-53e237473c32 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26 1633743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.261633743 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3039074497 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 4258824864 ps |
| CPU time | 668 seconds |
| Started | Jul 18 08:41:50 PM PDT 24 |
| Finished | Jul 18 08:53:00 PM PDT 24 |
| Peak memory | 623824 kb |
| Host | smart-0ce10f7b-ce38-4de9-b508-be5238c8ab60 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039074497 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.3039074497 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1033826557 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2640831666 ps |
| CPU time | 307.83 seconds |
| Started | Jul 18 07:51:05 PM PDT 24 |
| Finished | Jul 18 07:56:15 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-4b01167b-ceaa-4fd6-b55a-3236c7df54c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033826557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.1033826557 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4044078626 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 3131218430 ps |
| CPU time | 178.47 seconds |
| Started | Jul 18 08:14:28 PM PDT 24 |
| Finished | Jul 18 08:17:28 PM PDT 24 |
| Peak memory | 620220 kb |
| Host | smart-1f87fc67-8bee-4d83-853a-a1c4183e2640 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440786 26 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.4044078626 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3250051607 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 5470209268 ps |
| CPU time | 374.87 seconds |
| Started | Jul 18 08:43:56 PM PDT 24 |
| Finished | Jul 18 08:50:12 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-6714744a-a0f8-493c-8b52-d0e010a7f1d3 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250051607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.3250051607 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.269094851 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 10699630028 ps |
| CPU time | 2892.41 seconds |
| Started | Jul 18 08:18:01 PM PDT 24 |
| Finished | Jul 18 09:06:14 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-6efce965-81eb-45ec-bbd3-f083a10f26d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269094851 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.269094851 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.623639272 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5855205050 ps |
| CPU time | 1185.95 seconds |
| Started | Jul 18 08:27:01 PM PDT 24 |
| Finished | Jul 18 08:46:49 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-cfa81a2e-d140-4ac3-bf92-a60af912047f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623639272 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.623639272 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3894028682 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 6113317266 ps |
| CPU time | 422.68 seconds |
| Started | Jul 18 07:41:41 PM PDT 24 |
| Finished | Jul 18 07:48:44 PM PDT 24 |
| Peak memory | 660844 kb |
| Host | smart-73218433-64dc-4821-beb0-64457f82d9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894028682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3894028682 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.1042152824 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3772147965 ps |
| CPU time | 355.41 seconds |
| Started | Jul 18 07:42:15 PM PDT 24 |
| Finished | Jul 18 07:48:11 PM PDT 24 |
| Peak memory | 599640 kb |
| Host | smart-c7d86953-3357-4af0-a554-c2e72668fd81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042152824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1042152824 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.698229835 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5354170400 ps |
| CPU time | 501.26 seconds |
| Started | Jul 18 08:20:02 PM PDT 24 |
| Finished | Jul 18 08:28:24 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-e3d02904-3b63-438c-9191-af36426e44f5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698229835 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.698229835 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.921410928 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2049020925 ps |
| CPU time | 78.63 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:04:02 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c6330b30-9afb-4ea0-afa7-9b0baf9f073e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921410928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device. 921410928 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.685571746 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 43583841260 ps |
| CPU time | 6057.59 seconds |
| Started | Jul 18 08:31:25 PM PDT 24 |
| Finished | Jul 18 10:12:23 PM PDT 24 |
| Peak memory | 620868 kb |
| Host | smart-7546ddde-3267-40b6-9725-413d1aaff23a |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=685571746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.685571746 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4246814228 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 8329847760 ps |
| CPU time | 1717.63 seconds |
| Started | Jul 18 08:20:50 PM PDT 24 |
| Finished | Jul 18 08:49:29 PM PDT 24 |
| Peak memory | 618864 kb |
| Host | smart-bfe27236-3a46-4457-9a91-7abc1db7832f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4246814228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4246814228 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.787437560 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5542827252 ps |
| CPU time | 968.44 seconds |
| Started | Jul 18 08:13:36 PM PDT 24 |
| Finished | Jul 18 08:29:46 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-588e4fe8-2eed-42f6-83bb-9ffe693f510f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787437560 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.787437560 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2248006844 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 9940214475 ps |
| CPU time | 546.36 seconds |
| Started | Jul 18 07:57:51 PM PDT 24 |
| Finished | Jul 18 08:06:58 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-fc2e1b3a-2de5-489a-a90d-23c4491a971b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248006844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2248006844 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4168213051 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 12980657646 ps |
| CPU time | 1331.01 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 08:08:53 PM PDT 24 |
| Peak memory | 597528 kb |
| Host | smart-a99e8a77-30a3-4433-ae78-1dad74022166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168213051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.4168213051 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.839783680 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 5409067240 ps |
| CPU time | 1240.67 seconds |
| Started | Jul 18 08:14:54 PM PDT 24 |
| Finished | Jul 18 08:35:36 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-781dea16-babd-4012-9cb0-f4cf2f6f7f5e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839783680 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_plic_all_irqs_0.839783680 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1475736909 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 4864497716 ps |
| CPU time | 570.26 seconds |
| Started | Jul 18 08:28:29 PM PDT 24 |
| Finished | Jul 18 08:38:01 PM PDT 24 |
| Peak memory | 612912 kb |
| Host | smart-6f708cc8-0b3d-4bf7-b878-13e1951760e7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475736909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1475736909 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3057445542 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3952582872 ps |
| CPU time | 366.49 seconds |
| Started | Jul 18 08:13:24 PM PDT 24 |
| Finished | Jul 18 08:19:31 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-b7c6a44b-5726-485d-b198-684d593befc2 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305744 5542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3057445542 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1861997376 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3750531632 ps |
| CPU time | 292.76 seconds |
| Started | Jul 18 07:40:03 PM PDT 24 |
| Finished | Jul 18 07:44:56 PM PDT 24 |
| Peak memory | 599636 kb |
| Host | smart-e7944861-c167-4cf2-acc5-080ddb60c2c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861997376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1861997376 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.518710844 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 14915750661 ps |
| CPU time | 869.69 seconds |
| Started | Jul 18 08:05:14 PM PDT 24 |
| Finished | Jul 18 08:19:44 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-deda6e20-29dd-4052-8129-b9e0e2062e79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518710844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_ with_rand_reset.518710844 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3866617836 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 705050861 ps |
| CPU time | 308.13 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:09:14 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e9f1e1ef-1e78-4c80-a8af-15b8e338669b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866617836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3866617836 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.1968299905 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4241172960 ps |
| CPU time | 295.64 seconds |
| Started | Jul 18 08:16:35 PM PDT 24 |
| Finished | Jul 18 08:21:32 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-f106d48f-d439-42db-91ae-6f9dc69d1447 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968299905 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.1968299905 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2321550271 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 7013777944 ps |
| CPU time | 544.09 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 07:56:19 PM PDT 24 |
| Peak memory | 636552 kb |
| Host | smart-bf649b33-fff8-4a6e-a604-2cd9c7f31475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321550271 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2321550271 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1518315367 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 44321302492 ps |
| CPU time | 5223.93 seconds |
| Started | Jul 18 08:12:32 PM PDT 24 |
| Finished | Jul 18 09:39:38 PM PDT 24 |
| Peak memory | 620776 kb |
| Host | smart-1722c5e3-0791-45d7-9f49-4aae9f3e96b5 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1518315367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1518315367 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.155206678 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 19398262968 ps |
| CPU time | 512.2 seconds |
| Started | Jul 18 08:14:13 PM PDT 24 |
| Finished | Jul 18 08:22:47 PM PDT 24 |
| Peak memory | 619184 kb |
| Host | smart-249d867e-9063-4b8e-9784-9d6c2eda587d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=155206678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.155206678 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3251244639 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3709463440 ps |
| CPU time | 470.92 seconds |
| Started | Jul 18 08:18:43 PM PDT 24 |
| Finished | Jul 18 08:26:35 PM PDT 24 |
| Peak memory | 619664 kb |
| Host | smart-c44e2a4e-79fd-4564-bf99-f701a6b6fe68 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 251244639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.3251244639 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2965666576 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4933502742 ps |
| CPU time | 613.94 seconds |
| Started | Jul 18 08:42:16 PM PDT 24 |
| Finished | Jul 18 08:52:31 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-70044a22-cbbe-4c6b-950e-3dbc72f89cb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29656665 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2965666576 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.1777978646 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 421074811 ps |
| CPU time | 34.66 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:44:02 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-a60b0763-6dd0-445a-990d-e231be31a9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777978646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 1777978646 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2759395761 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 772273166 ps |
| CPU time | 165.88 seconds |
| Started | Jul 18 07:53:09 PM PDT 24 |
| Finished | Jul 18 07:55:56 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-096c87b3-a5e3-4145-8ff8-dfaa8369c168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759395761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2759395761 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1290067769 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6187596628 ps |
| CPU time | 391.48 seconds |
| Started | Jul 18 07:40:53 PM PDT 24 |
| Finished | Jul 18 07:47:26 PM PDT 24 |
| Peak memory | 663016 kb |
| Host | smart-3e301a35-b829-431e-96e5-f202be7b3a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290067769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1290067769 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.877461635 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 429900630 ps |
| CPU time | 187.1 seconds |
| Started | Jul 18 08:00:07 PM PDT 24 |
| Finished | Jul 18 08:03:15 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e59fad54-4de9-40c7-af16-5801600f1e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877461635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_rand_reset.877461635 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1074708457 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2416921786 ps |
| CPU time | 120.97 seconds |
| Started | Jul 18 08:13:34 PM PDT 24 |
| Finished | Jul 18 08:15:36 PM PDT 24 |
| Peak memory | 621912 kb |
| Host | smart-48f9eff5-fe5c-4e03-8256-3ee26baddf7a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074708457 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.1074708457 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3392341541 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 20295661796 ps |
| CPU time | 2742.15 seconds |
| Started | Jul 18 08:19:08 PM PDT 24 |
| Finished | Jul 18 09:04:52 PM PDT 24 |
| Peak memory | 612408 kb |
| Host | smart-439d24de-31ba-4a4a-93c8-9762d6394ffb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392341541 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3392341541 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.956546323 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 3672717220 ps |
| CPU time | 208.32 seconds |
| Started | Jul 18 07:50:43 PM PDT 24 |
| Finished | Jul 18 07:54:12 PM PDT 24 |
| Peak memory | 598616 kb |
| Host | smart-af581d9b-980f-4537-80dc-3d381e97f530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956546323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.956546323 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.585699538 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 33634979079 ps |
| CPU time | 4403.43 seconds |
| Started | Jul 18 07:40:59 PM PDT 24 |
| Finished | Jul 18 08:54:24 PM PDT 24 |
| Peak memory | 593132 kb |
| Host | smart-547292cd-73a5-499b-95e0-c7017a306d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585699538 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.chip_same_csr_outstanding.585699538 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3540432580 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4730719534 ps |
| CPU time | 652.56 seconds |
| Started | Jul 18 08:28:30 PM PDT 24 |
| Finished | Jul 18 08:39:24 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-786d9c69-613f-43f8-9781-9ce0a84932f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540432580 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.3540432580 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.3564902293 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3444890656 ps |
| CPU time | 607.52 seconds |
| Started | Jul 18 08:27:27 PM PDT 24 |
| Finished | Jul 18 08:37:36 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-0f7e68ac-32d1-43de-a67a-78343b43ab0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564902293 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.3564902293 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.3581559370 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4329329816 ps |
| CPU time | 705.99 seconds |
| Started | Jul 18 08:26:58 PM PDT 24 |
| Finished | Jul 18 08:38:45 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-15a9f4ab-0ede-46bc-9646-2cc56c82a4f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581559370 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3581559370 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3250766099 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 4891223406 ps |
| CPU time | 694.07 seconds |
| Started | Jul 18 08:28:17 PM PDT 24 |
| Finished | Jul 18 08:39:53 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-f7b88bdd-452a-4ce9-bed2-4ed9bb5a2563 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3250766099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3250766099 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1516584331 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 5344042626 ps |
| CPU time | 391.74 seconds |
| Started | Jul 18 07:50:17 PM PDT 24 |
| Finished | Jul 18 07:56:51 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-4a1c8a33-5ad3-4937-97b5-23ed31ce742c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516584331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1516584331 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1672673560 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 14485731028 ps |
| CPU time | 786.53 seconds |
| Started | Jul 18 07:57:23 PM PDT 24 |
| Finished | Jul 18 08:10:30 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-3b6a5fd2-0a31-4503-b80e-b801abe4bc3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672673560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1672673560 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.976811526 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 9644137095 ps |
| CPU time | 581.73 seconds |
| Started | Jul 18 07:57:57 PM PDT 24 |
| Finished | Jul 18 08:07:40 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-8020e051-9e9c-4324-9251-3d9ffcada4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976811526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_ with_rand_reset.976811526 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4168793678 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 4465151056 ps |
| CPU time | 625.81 seconds |
| Started | Jul 18 08:16:39 PM PDT 24 |
| Finished | Jul 18 08:27:08 PM PDT 24 |
| Peak memory | 613360 kb |
| Host | smart-87cdbdaf-2812-45da-9e0c-73c61df2a1ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168793678 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.4168793678 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2879606770 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4149986040 ps |
| CPU time | 473.52 seconds |
| Started | Jul 18 08:19:36 PM PDT 24 |
| Finished | Jul 18 08:27:30 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-2d6608b5-f61b-4b0b-8473-ad1ef0450d4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879606770 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2879606770 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3066291234 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4890199164 ps |
| CPU time | 839.39 seconds |
| Started | Jul 18 08:13:56 PM PDT 24 |
| Finished | Jul 18 08:27:57 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-935420d9-c37c-4c6c-9bcd-58bcee3b989a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066291234 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.3066291234 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.242153288 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 5290066184 ps |
| CPU time | 575.54 seconds |
| Started | Jul 18 08:47:33 PM PDT 24 |
| Finished | Jul 18 08:57:10 PM PDT 24 |
| Peak memory | 650032 kb |
| Host | smart-466b89f2-08a0-4f36-a5e4-1276d0551fa2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 242153288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.242153288 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1474875901 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 4573826260 ps |
| CPU time | 511.64 seconds |
| Started | Jul 18 08:14:43 PM PDT 24 |
| Finished | Jul 18 08:23:16 PM PDT 24 |
| Peak memory | 620128 kb |
| Host | smart-566e0ff5-cd91-4a54-be16-b593c0f26b06 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147487 5901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1474875901 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.672030506 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 94136439911 ps |
| CPU time | 1030.74 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 08:06:25 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-9fe5bf3f-bdc4-481a-9271-261c9791cbc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672030506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.672030506 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.353922822 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 853876752 ps |
| CPU time | 64.56 seconds |
| Started | Jul 18 07:52:55 PM PDT 24 |
| Finished | Jul 18 07:54:00 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-0979bfe4-dab1-4a56-8b1d-c2a098f94f3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353922822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.353922822 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.473215608 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2548807105 ps |
| CPU time | 101.73 seconds |
| Started | Jul 18 08:31:35 PM PDT 24 |
| Finished | Jul 18 08:33:18 PM PDT 24 |
| Peak memory | 620560 kb |
| Host | smart-71749e2e-e884-4cd0-9dda-9450dfca54d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473215608 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.473215608 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3652375451 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 27396934683 ps |
| CPU time | 3856.38 seconds |
| Started | Jul 18 08:28:25 PM PDT 24 |
| Finished | Jul 18 09:32:43 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-ac1f8544-a2ab-4682-a3ef-11fed6fbd5a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652375451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.3652375451 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.1502274449 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 19095953502 ps |
| CPU time | 737.95 seconds |
| Started | Jul 18 08:01:28 PM PDT 24 |
| Finished | Jul 18 08:13:49 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a6ca31a9-b935-4a3c-94fd-814f4487f22f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502274449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.1502274449 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.945109812 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4998292580 ps |
| CPU time | 457.43 seconds |
| Started | Jul 18 07:44:36 PM PDT 24 |
| Finished | Jul 18 07:52:15 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-59081ef6-093b-4786-820c-0af32b76e194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945109812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.945109812 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.583362219 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4385196208 ps |
| CPU time | 631.23 seconds |
| Started | Jul 18 08:13:54 PM PDT 24 |
| Finished | Jul 18 08:24:27 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-67b2b11e-9c73-4580-b54c-b0589b0558a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583362219 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.583362219 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2873932732 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3334323096 ps |
| CPU time | 389.96 seconds |
| Started | Jul 18 08:48:27 PM PDT 24 |
| Finished | Jul 18 08:54:58 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-b2683bd3-fd60-4e10-8cfc-ec1125c56d52 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873932732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2873932732 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3323787902 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 8481001248 ps |
| CPU time | 1618.25 seconds |
| Started | Jul 18 08:13:50 PM PDT 24 |
| Finished | Jul 18 08:40:50 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-072a61fd-e504-4651-8247-b7d3ed47aa5f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33237 87902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3323787902 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3519326663 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4072511194 ps |
| CPU time | 429.42 seconds |
| Started | Jul 18 08:15:47 PM PDT 24 |
| Finished | Jul 18 08:22:58 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-c3f3bbaf-1fe9-47cd-949f-af8178b4f604 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519326663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.3519326663 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.311252287 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 6141074408 ps |
| CPU time | 794.05 seconds |
| Started | Jul 18 08:12:56 PM PDT 24 |
| Finished | Jul 18 08:26:11 PM PDT 24 |
| Peak memory | 650416 kb |
| Host | smart-9c9b8de0-d824-4197-9a33-b861bc8b215d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 311252287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.311252287 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2468407975 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 3652357896 ps |
| CPU time | 356.25 seconds |
| Started | Jul 18 08:22:57 PM PDT 24 |
| Finished | Jul 18 08:28:54 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-ff1dbac3-5f0d-4989-aa51-af1a8e8a7a13 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468407975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.2468407975 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935715883 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 4303945774 ps |
| CPU time | 431.92 seconds |
| Started | Jul 18 08:43:35 PM PDT 24 |
| Finished | Jul 18 08:50:48 PM PDT 24 |
| Peak memory | 649064 kb |
| Host | smart-b8e4525b-2d3c-4a8c-9704-92955231e79c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935715883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1935715883 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1809251308 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5273623080 ps |
| CPU time | 698.62 seconds |
| Started | Jul 18 08:42:51 PM PDT 24 |
| Finished | Jul 18 08:54:31 PM PDT 24 |
| Peak memory | 649860 kb |
| Host | smart-f67be6b6-253d-4143-896a-ab893b75696a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1809251308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1809251308 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3315628290 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 3287523196 ps |
| CPU time | 411.17 seconds |
| Started | Jul 18 08:43:34 PM PDT 24 |
| Finished | Jul 18 08:50:26 PM PDT 24 |
| Peak memory | 648500 kb |
| Host | smart-2f31b0fe-6a6d-4dc3-abe8-d0839f018fbc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315628290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3315628290 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1066997812 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4938444400 ps |
| CPU time | 526.62 seconds |
| Started | Jul 18 08:42:59 PM PDT 24 |
| Finished | Jul 18 08:51:47 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-3c8f5608-1527-44b3-9209-f289c832aea8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1066997812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1066997812 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069386735 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 3989613488 ps |
| CPU time | 396.96 seconds |
| Started | Jul 18 08:42:54 PM PDT 24 |
| Finished | Jul 18 08:49:32 PM PDT 24 |
| Peak memory | 648592 kb |
| Host | smart-52ece1bf-9f07-4531-9854-b51388795bbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069386735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3069386735 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.544617063 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3783861880 ps |
| CPU time | 350.88 seconds |
| Started | Jul 18 08:44:44 PM PDT 24 |
| Finished | Jul 18 08:50:36 PM PDT 24 |
| Peak memory | 648852 kb |
| Host | smart-2348797a-490c-44b7-b11b-b002c23e40e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544617063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_s w_alert_handler_lpg_sleep_mode_alerts.544617063 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.4157038919 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5225643328 ps |
| CPU time | 469.07 seconds |
| Started | Jul 18 08:45:42 PM PDT 24 |
| Finished | Jul 18 08:53:32 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-dc640667-af47-4d94-a4b2-7ffc98be61c4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4157038919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.4157038919 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2941882528 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 5542360220 ps |
| CPU time | 654.46 seconds |
| Started | Jul 18 08:42:58 PM PDT 24 |
| Finished | Jul 18 08:53:54 PM PDT 24 |
| Peak memory | 649920 kb |
| Host | smart-0e0446ac-b556-4e87-a81b-c78b56f2b6d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2941882528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2941882528 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.229807568 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4150911200 ps |
| CPU time | 409.73 seconds |
| Started | Jul 18 08:44:46 PM PDT 24 |
| Finished | Jul 18 08:51:38 PM PDT 24 |
| Peak memory | 648620 kb |
| Host | smart-392b3122-fd42-40e4-b440-e3955c187f0d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229807568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s w_alert_handler_lpg_sleep_mode_alerts.229807568 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.1414288342 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 4651767772 ps |
| CPU time | 688.68 seconds |
| Started | Jul 18 08:45:04 PM PDT 24 |
| Finished | Jul 18 08:56:34 PM PDT 24 |
| Peak memory | 649900 kb |
| Host | smart-6b44778f-50bd-4f20-bd6a-5475a2a89c6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1414288342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1414288342 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3952809533 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 3890252990 ps |
| CPU time | 542.98 seconds |
| Started | Jul 18 08:44:33 PM PDT 24 |
| Finished | Jul 18 08:53:37 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-fb9aa2fc-2bb8-45ed-83a1-aec35009a575 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952809533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3952809533 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1252837640 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 5079963890 ps |
| CPU time | 641.91 seconds |
| Started | Jul 18 08:44:55 PM PDT 24 |
| Finished | Jul 18 08:55:38 PM PDT 24 |
| Peak memory | 650100 kb |
| Host | smart-68475f60-4af4-4dfe-b1a3-3dd9d4c6d188 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1252837640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1252837640 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1675982092 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4323682100 ps |
| CPU time | 524.76 seconds |
| Started | Jul 18 08:53:30 PM PDT 24 |
| Finished | Jul 18 09:02:18 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-645b32cb-3b2e-4621-b368-325fab05a211 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675982092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1675982092 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2339942714 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5948678366 ps |
| CPU time | 589.48 seconds |
| Started | Jul 18 08:43:48 PM PDT 24 |
| Finished | Jul 18 08:53:39 PM PDT 24 |
| Peak memory | 650140 kb |
| Host | smart-3db96a77-eeed-49cd-aa2c-de44adccd25a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2339942714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2339942714 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2884728861 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5239531956 ps |
| CPU time | 512.55 seconds |
| Started | Jul 18 08:44:04 PM PDT 24 |
| Finished | Jul 18 08:52:38 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-9b980730-8f11-4064-9b7f-495b6390de59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2884728861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2884728861 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.154675605 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4236098960 ps |
| CPU time | 461.55 seconds |
| Started | Jul 18 08:34:48 PM PDT 24 |
| Finished | Jul 18 08:42:31 PM PDT 24 |
| Peak memory | 648608 kb |
| Host | smart-d1c00dff-05ce-477b-9361-3ac907ed52de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154675605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.154675605 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.3443193506 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4855806980 ps |
| CPU time | 624.55 seconds |
| Started | Jul 18 08:31:27 PM PDT 24 |
| Finished | Jul 18 08:41:53 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-230fb458-be9b-4412-8fa6-ec833bcd9d60 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3443193506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3443193506 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.1153051919 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 4411770848 ps |
| CPU time | 430.46 seconds |
| Started | Jul 18 08:44:18 PM PDT 24 |
| Finished | Jul 18 08:51:29 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-ddfcdad4-1bcb-4a90-8496-a572b5241b1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1153051919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.1153051919 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967550816 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3688720230 ps |
| CPU time | 452.97 seconds |
| Started | Jul 18 08:53:27 PM PDT 24 |
| Finished | Jul 18 09:01:02 PM PDT 24 |
| Peak memory | 648932 kb |
| Host | smart-d49a9125-1369-47f4-95f4-552a67542c89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967550816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3967550816 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241236969 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 3721276608 ps |
| CPU time | 598.64 seconds |
| Started | Jul 18 08:51:29 PM PDT 24 |
| Finished | Jul 18 09:01:30 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-39f2bc69-ed3a-4bfb-a6d8-40d6e4f3a157 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241236969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2241236969 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.593741552 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4526873144 ps |
| CPU time | 512.62 seconds |
| Started | Jul 18 08:45:08 PM PDT 24 |
| Finished | Jul 18 08:53:42 PM PDT 24 |
| Peak memory | 649320 kb |
| Host | smart-61c64717-f8e9-48f4-a048-eff48563f774 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593741552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_s w_alert_handler_lpg_sleep_mode_alerts.593741552 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1630920144 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 5388789190 ps |
| CPU time | 530.63 seconds |
| Started | Jul 18 08:44:27 PM PDT 24 |
| Finished | Jul 18 08:53:19 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-8c02f9fa-8036-46a9-9f1f-5f0fa462d842 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1630920144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1630920144 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944923510 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 3704065748 ps |
| CPU time | 395.15 seconds |
| Started | Jul 18 08:46:19 PM PDT 24 |
| Finished | Jul 18 08:52:55 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-642e3170-3e4d-4bd9-8eff-d4de08222569 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944923510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1944923510 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3837986974 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3155369768 ps |
| CPU time | 341.26 seconds |
| Started | Jul 18 08:45:44 PM PDT 24 |
| Finished | Jul 18 08:51:26 PM PDT 24 |
| Peak memory | 648592 kb |
| Host | smart-f5d5c18f-95cd-4837-9aae-b7bdc8f5f965 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837986974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3837986974 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3211009457 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4939663480 ps |
| CPU time | 573.97 seconds |
| Started | Jul 18 08:45:30 PM PDT 24 |
| Finished | Jul 18 08:55:06 PM PDT 24 |
| Peak memory | 650192 kb |
| Host | smart-8ca241b5-cea7-44a4-a4de-f91efedc3b11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3211009457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3211009457 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1825660523 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 6538843024 ps |
| CPU time | 815.71 seconds |
| Started | Jul 18 08:45:09 PM PDT 24 |
| Finished | Jul 18 08:58:46 PM PDT 24 |
| Peak memory | 650240 kb |
| Host | smart-6ec09649-b628-453d-b54d-6ebef528fd42 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1825660523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1825660523 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3195333782 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4181583662 ps |
| CPU time | 454.26 seconds |
| Started | Jul 18 08:47:38 PM PDT 24 |
| Finished | Jul 18 08:55:13 PM PDT 24 |
| Peak memory | 649096 kb |
| Host | smart-6ae98952-e649-499a-a1d0-9fd8daa2613e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195333782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3195333782 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3101388694 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 5532591152 ps |
| CPU time | 581.19 seconds |
| Started | Jul 18 08:45:08 PM PDT 24 |
| Finished | Jul 18 08:54:50 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-41780ba7-bd6b-410a-8efa-952a00177673 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3101388694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3101388694 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2225503711 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4378683608 ps |
| CPU time | 427.15 seconds |
| Started | Jul 18 08:47:42 PM PDT 24 |
| Finished | Jul 18 08:54:49 PM PDT 24 |
| Peak memory | 649420 kb |
| Host | smart-f69192aa-8354-4be5-a0ff-9655d8bfb2db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225503711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2225503711 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889566888 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3653808736 ps |
| CPU time | 528.79 seconds |
| Started | Jul 18 08:46:01 PM PDT 24 |
| Finished | Jul 18 08:54:50 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-4f2bd5d0-8fef-44e1-a014-59bf5163d504 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889566888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2889566888 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.424989898 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4271775496 ps |
| CPU time | 462.74 seconds |
| Started | Jul 18 08:46:31 PM PDT 24 |
| Finished | Jul 18 08:54:15 PM PDT 24 |
| Peak memory | 648600 kb |
| Host | smart-bc584823-811b-4fb6-96e7-ca83557a0e0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424989898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.424989898 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.1130208592 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4566499712 ps |
| CPU time | 534.68 seconds |
| Started | Jul 18 08:45:39 PM PDT 24 |
| Finished | Jul 18 08:54:35 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-d3997b14-5bea-4eb8-a71e-d354ef41d2f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1130208592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.1130208592 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.138020250 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3864623640 ps |
| CPU time | 518.36 seconds |
| Started | Jul 18 08:47:30 PM PDT 24 |
| Finished | Jul 18 08:56:10 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-7b0d554a-a3c0-4852-98cb-f6d907b78d21 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138020250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_s w_alert_handler_lpg_sleep_mode_alerts.138020250 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424544681 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 3614794700 ps |
| CPU time | 343.27 seconds |
| Started | Jul 18 08:46:59 PM PDT 24 |
| Finished | Jul 18 08:52:44 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-d2c3a0e5-3f5f-4889-98d1-fe150e729a2b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424544681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3424544681 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.4042889680 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6324242744 ps |
| CPU time | 810.17 seconds |
| Started | Jul 18 08:47:11 PM PDT 24 |
| Finished | Jul 18 09:00:43 PM PDT 24 |
| Peak memory | 651228 kb |
| Host | smart-cbd7719f-6596-4edd-99cd-3978b98635e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4042889680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.4042889680 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.58234569 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3616316804 ps |
| CPU time | 419.35 seconds |
| Started | Jul 18 08:46:39 PM PDT 24 |
| Finished | Jul 18 08:53:40 PM PDT 24 |
| Peak memory | 648600 kb |
| Host | smart-b12da429-417a-4374-bcda-0d8ebbd2f9e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58234569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw _alert_handler_lpg_sleep_mode_alerts.58234569 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1122162441 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 5499670240 ps |
| CPU time | 708.34 seconds |
| Started | Jul 18 08:46:13 PM PDT 24 |
| Finished | Jul 18 08:58:02 PM PDT 24 |
| Peak memory | 649924 kb |
| Host | smart-84cfe136-7ee5-4ed7-a0e4-d785c77c09a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1122162441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1122162441 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.649395560 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 4106883802 ps |
| CPU time | 396.82 seconds |
| Started | Jul 18 08:40:39 PM PDT 24 |
| Finished | Jul 18 08:47:16 PM PDT 24 |
| Peak memory | 648756 kb |
| Host | smart-aecfc59c-5f1d-43b8-a0e0-d3cfb3ea00c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649395560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw _alert_handler_lpg_sleep_mode_alerts.649395560 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3359661657 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4137038520 ps |
| CPU time | 613.7 seconds |
| Started | Jul 18 08:40:43 PM PDT 24 |
| Finished | Jul 18 08:50:58 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-335e3aa1-c96c-498f-bf99-899a96ce843d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3359661657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3359661657 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3733193511 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4117588656 ps |
| CPU time | 463.65 seconds |
| Started | Jul 18 08:46:39 PM PDT 24 |
| Finished | Jul 18 08:54:23 PM PDT 24 |
| Peak memory | 648808 kb |
| Host | smart-7b8228f3-c4c2-489c-be07-1e7c5fa32408 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733193511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3733193511 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.1310325285 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 5192014368 ps |
| CPU time | 431.87 seconds |
| Started | Jul 18 08:48:01 PM PDT 24 |
| Finished | Jul 18 08:55:15 PM PDT 24 |
| Peak memory | 650256 kb |
| Host | smart-c7515ab8-099e-416d-8a38-6319fc856ec1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1310325285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1310325285 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2221787204 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3704889684 ps |
| CPU time | 322.66 seconds |
| Started | Jul 18 08:47:23 PM PDT 24 |
| Finished | Jul 18 08:52:47 PM PDT 24 |
| Peak memory | 648536 kb |
| Host | smart-3188c578-b039-46dc-8e0c-fbf8e2a1938a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221787204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2221787204 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2580230554 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 4164413160 ps |
| CPU time | 533.11 seconds |
| Started | Jul 18 08:48:04 PM PDT 24 |
| Finished | Jul 18 08:56:58 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-00595914-e3dc-49f5-8d39-1033749b8465 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2580230554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2580230554 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.244999183 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4676315256 ps |
| CPU time | 507.69 seconds |
| Started | Jul 18 08:55:49 PM PDT 24 |
| Finished | Jul 18 09:04:18 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-5104ac96-7282-4272-b0f3-8aeb5ed894b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 244999183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.244999183 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3991524205 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 3388716884 ps |
| CPU time | 345.67 seconds |
| Started | Jul 18 08:48:44 PM PDT 24 |
| Finished | Jul 18 08:54:31 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-6e68b118-7fdc-4489-9540-d1448b8a1e67 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991524205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3991524205 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.3634501971 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4518692344 ps |
| CPU time | 625.33 seconds |
| Started | Jul 18 08:48:58 PM PDT 24 |
| Finished | Jul 18 08:59:25 PM PDT 24 |
| Peak memory | 649868 kb |
| Host | smart-070d1645-5d7c-49b3-aabc-f3f05625531b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3634501971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.3634501971 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.39679918 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3765361722 ps |
| CPU time | 329.02 seconds |
| Started | Jul 18 08:48:07 PM PDT 24 |
| Finished | Jul 18 08:53:37 PM PDT 24 |
| Peak memory | 648976 kb |
| Host | smart-44897a1f-2e33-4f65-b271-5e4d9df9c618 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39679918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw _alert_handler_lpg_sleep_mode_alerts.39679918 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3953951253 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 3880869254 ps |
| CPU time | 386.77 seconds |
| Started | Jul 18 08:49:52 PM PDT 24 |
| Finished | Jul 18 08:56:20 PM PDT 24 |
| Peak memory | 648648 kb |
| Host | smart-9a723ee6-2826-40c6-a6df-0496f243741a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953951253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3953951253 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.4070546612 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5106301808 ps |
| CPU time | 593.66 seconds |
| Started | Jul 18 08:47:11 PM PDT 24 |
| Finished | Jul 18 08:57:06 PM PDT 24 |
| Peak memory | 650092 kb |
| Host | smart-9d5f3abc-9da7-44a9-9767-05332e40d266 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4070546612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.4070546612 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.2641258997 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 5540114904 ps |
| CPU time | 667.09 seconds |
| Started | Jul 18 08:48:55 PM PDT 24 |
| Finished | Jul 18 09:00:03 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-19a8d5c8-4717-451f-8d7d-c90b848638d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2641258997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2641258997 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.713561337 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 4508637784 ps |
| CPU time | 474.2 seconds |
| Started | Jul 18 08:49:17 PM PDT 24 |
| Finished | Jul 18 08:57:12 PM PDT 24 |
| Peak memory | 649828 kb |
| Host | smart-5a98c35e-3e91-4162-8bc5-c14746b7ccbf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 713561337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.713561337 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.662626511 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 4904372500 ps |
| CPU time | 588.17 seconds |
| Started | Jul 18 08:47:21 PM PDT 24 |
| Finished | Jul 18 08:57:10 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-8552e4f5-ca0b-4696-9d51-4724e4a3840c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 662626511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.662626511 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.185137478 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4148374456 ps |
| CPU time | 348.25 seconds |
| Started | Jul 18 08:48:43 PM PDT 24 |
| Finished | Jul 18 08:54:32 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-db079667-7fcf-486e-9ed4-6373731e8e8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185137478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.185137478 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154160181 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3292955040 ps |
| CPU time | 404.28 seconds |
| Started | Jul 18 08:47:31 PM PDT 24 |
| Finished | Jul 18 08:54:16 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-d1a180b3-926f-47bd-aaaa-461aa4ef0ff2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154160181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3154160181 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.175972625 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3738054510 ps |
| CPU time | 295.3 seconds |
| Started | Jul 18 08:47:28 PM PDT 24 |
| Finished | Jul 18 08:52:25 PM PDT 24 |
| Peak memory | 648820 kb |
| Host | smart-b832eebf-bc8a-4d10-80ee-97b4c3015049 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175972625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_s w_alert_handler_lpg_sleep_mode_alerts.175972625 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980516286 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4226226654 ps |
| CPU time | 475.7 seconds |
| Started | Jul 18 08:48:28 PM PDT 24 |
| Finished | Jul 18 08:56:25 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-2ca4cd02-69ca-43fd-bfe6-15dd8f1aa034 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980516286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1980516286 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200030743 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3674802360 ps |
| CPU time | 388.95 seconds |
| Started | Jul 18 08:49:30 PM PDT 24 |
| Finished | Jul 18 08:56:00 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-ec355478-27f9-49f7-b7cd-b5e3ee3fcff3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200030743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3200030743 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200612743 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 3401511030 ps |
| CPU time | 305.68 seconds |
| Started | Jul 18 08:49:06 PM PDT 24 |
| Finished | Jul 18 08:54:13 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-406ec852-d3b1-4e1d-84b8-aa1dac14faa3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200612743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3200612743 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.932756890 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 5166418488 ps |
| CPU time | 634.6 seconds |
| Started | Jul 18 08:49:27 PM PDT 24 |
| Finished | Jul 18 09:00:03 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-35dbc6b1-cd4b-49a8-88bd-3bd4a4fc65cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 932756890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.932756890 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3285029 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2940832760 ps |
| CPU time | 376.34 seconds |
| Started | Jul 18 08:44:11 PM PDT 24 |
| Finished | Jul 18 08:50:28 PM PDT 24 |
| Peak memory | 647996 kb |
| Host | smart-1a5a2739-3961-410b-bb6c-af2a3b75524d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_a lert_handler_lpg_sleep_mode_alerts.3285029 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254335469 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3253691470 ps |
| CPU time | 320.09 seconds |
| Started | Jul 18 08:52:17 PM PDT 24 |
| Finished | Jul 18 08:57:38 PM PDT 24 |
| Peak memory | 648656 kb |
| Host | smart-94dbe9f8-d751-4e28-8ef6-8611f0adc6d8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254335469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3254335469 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.433944802 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 3576567248 ps |
| CPU time | 294.81 seconds |
| Started | Jul 18 08:50:36 PM PDT 24 |
| Finished | Jul 18 08:55:32 PM PDT 24 |
| Peak memory | 648664 kb |
| Host | smart-7094aa0c-b429-4210-b001-12933ee33552 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433944802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.433944802 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3489949688 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 5837578240 ps |
| CPU time | 611.67 seconds |
| Started | Jul 18 08:50:59 PM PDT 24 |
| Finished | Jul 18 09:01:12 PM PDT 24 |
| Peak memory | 650152 kb |
| Host | smart-59575cbf-4757-45e7-8a67-ff0f8df29720 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3489949688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3489949688 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.1847324229 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5053091376 ps |
| CPU time | 596.36 seconds |
| Started | Jul 18 08:43:15 PM PDT 24 |
| Finished | Jul 18 08:53:12 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-6200cac5-08d4-4454-afc2-7770d5c60a8a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1847324229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1847324229 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.1256922794 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4630568948 ps |
| CPU time | 508.2 seconds |
| Started | Jul 18 08:50:18 PM PDT 24 |
| Finished | Jul 18 08:58:47 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-bae73b0d-2c9f-4d46-8c32-ac47e120380c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1256922794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1256922794 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1043560979 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 4635155744 ps |
| CPU time | 396.38 seconds |
| Started | Jul 18 08:50:10 PM PDT 24 |
| Finished | Jul 18 08:56:48 PM PDT 24 |
| Peak memory | 649148 kb |
| Host | smart-7f472121-6a03-4da8-9e44-8a264a218c89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043560979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1043560979 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.973981412 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 5779449690 ps |
| CPU time | 543.25 seconds |
| Started | Jul 18 08:51:04 PM PDT 24 |
| Finished | Jul 18 09:00:09 PM PDT 24 |
| Peak memory | 649764 kb |
| Host | smart-308497a5-a759-4376-ae4f-5aba763e7b8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 973981412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.973981412 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.1313866668 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 5573537816 ps |
| CPU time | 647.15 seconds |
| Started | Jul 18 08:51:01 PM PDT 24 |
| Finished | Jul 18 09:01:50 PM PDT 24 |
| Peak memory | 651036 kb |
| Host | smart-ef17041f-c225-46af-89a4-d061c84a5538 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1313866668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.1313866668 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.410745580 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 7910258664 ps |
| CPU time | 1018.09 seconds |
| Started | Jul 18 08:14:36 PM PDT 24 |
| Finished | Jul 18 08:31:35 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-eb08d432-c2e4-4cf4-a68d-b1a17a51ae90 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410745580 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.410745580 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1797012573 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2368873866 ps |
| CPU time | 204.37 seconds |
| Started | Jul 18 08:19:53 PM PDT 24 |
| Finished | Jul 18 08:23:19 PM PDT 24 |
| Peak memory | 622636 kb |
| Host | smart-c8d70cea-fe8b-4217-ab10-ec0652b3b64b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797012573 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1797012573 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.394286116 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 24468955890 ps |
| CPU time | 1416.08 seconds |
| Started | Jul 18 08:15:34 PM PDT 24 |
| Finished | Jul 18 08:39:11 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-711cd7d9-c14c-4d93-bc1c-f1f8306f25e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=394286116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.394286116 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2007296105 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4154304748 ps |
| CPU time | 664.95 seconds |
| Started | Jul 18 08:15:25 PM PDT 24 |
| Finished | Jul 18 08:26:31 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-8c377981-e73a-4f66-b072-000ae066e099 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007296105 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2007296105 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3339179883 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6171354544 ps |
| CPU time | 1164.33 seconds |
| Started | Jul 18 08:25:33 PM PDT 24 |
| Finished | Jul 18 08:44:58 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-e7925455-ed3c-4cc6-8550-e5a55bcefdb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3339179883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.3339179883 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2436023839 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4096718900 ps |
| CPU time | 383.71 seconds |
| Started | Jul 18 08:15:22 PM PDT 24 |
| Finished | Jul 18 08:21:47 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-7ab2344f-b0c2-48c3-a90c-7c8de89f360e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436023839 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2436023839 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2286565122 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 5904788760 ps |
| CPU time | 400.9 seconds |
| Started | Jul 18 08:16:18 PM PDT 24 |
| Finished | Jul 18 08:22:59 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-3f436958-8cd4-4b2d-a848-c35e0c432510 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2286565122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2286565122 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.360628240 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 9435125724 ps |
| CPU time | 1662.7 seconds |
| Started | Jul 18 08:14:35 PM PDT 24 |
| Finished | Jul 18 08:42:19 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-19d0f92e-5f5e-4a74-84ab-f540a059ff2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=360628240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.360628240 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.1838641660 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 4864841608 ps |
| CPU time | 627.92 seconds |
| Started | Jul 18 08:12:29 PM PDT 24 |
| Finished | Jul 18 08:22:59 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-248ded29-b76b-4b1f-ae69-b31536839435 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838641660 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.1838641660 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2444861995 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4593684024 ps |
| CPU time | 681.48 seconds |
| Started | Jul 18 08:15:42 PM PDT 24 |
| Finished | Jul 18 08:27:05 PM PDT 24 |
| Peak memory | 624072 kb |
| Host | smart-a645ab61-70ca-470f-be87-55de905d81a0 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444861995 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.2444861995 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3048456497 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 5258920474 ps |
| CPU time | 913.36 seconds |
| Started | Jul 18 08:13:32 PM PDT 24 |
| Finished | Jul 18 08:28:47 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-8d266f48-739d-4317-b632-2d4c125f9c42 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048456497 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.3048456497 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1892031768 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3463470280 ps |
| CPU time | 354.81 seconds |
| Started | Jul 18 08:16:33 PM PDT 24 |
| Finished | Jul 18 08:22:29 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-0231904b-9239-4c5d-afd8-847b9139e501 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892031768 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1892031768 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3221224083 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 2729974230 ps |
| CPU time | 257.08 seconds |
| Started | Jul 18 08:16:00 PM PDT 24 |
| Finished | Jul 18 08:20:17 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-848f6797-fd2a-4cad-aa1e-8d8d1e71f81d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221224083 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3221224083 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3169167172 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 5815442177 ps |
| CPU time | 556.02 seconds |
| Started | Jul 18 08:15:18 PM PDT 24 |
| Finished | Jul 18 08:24:34 PM PDT 24 |
| Peak memory | 609616 kb |
| Host | smart-a707b7a3-0fa6-4502-8dd9-21accde5da33 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169167172 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3169167172 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2295484164 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 11018497431 ps |
| CPU time | 1005.47 seconds |
| Started | Jul 18 08:20:30 PM PDT 24 |
| Finished | Jul 18 08:37:17 PM PDT 24 |
| Peak memory | 624768 kb |
| Host | smart-93403ea7-5df9-453e-ad70-308660e28db7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295484164 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2295484164 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3523390706 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 46344010521 ps |
| CPU time | 5430.87 seconds |
| Started | Jul 18 08:19:57 PM PDT 24 |
| Finished | Jul 18 09:50:30 PM PDT 24 |
| Peak memory | 619240 kb |
| Host | smart-961b0ac0-889e-46d4-9dcd-fd0dffa92476 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523390706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.3523390706 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3097465005 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 35536815840 ps |
| CPU time | 3565.54 seconds |
| Started | Jul 18 08:13:22 PM PDT 24 |
| Finished | Jul 18 09:12:48 PM PDT 24 |
| Peak memory | 611692 kb |
| Host | smart-f274931f-ae2a-4cc7-b201-d035619bbb66 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097465005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.3097465005 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4287637859 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5672497112 ps |
| CPU time | 618.36 seconds |
| Started | Jul 18 08:16:49 PM PDT 24 |
| Finished | Jul 18 08:27:09 PM PDT 24 |
| Peak memory | 623732 kb |
| Host | smart-e3c91653-7579-4109-ad7d-cd7079af684e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287637859 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.4287637859 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2189917376 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 14615692130 ps |
| CPU time | 1508.79 seconds |
| Started | Jul 18 08:42:30 PM PDT 24 |
| Finished | Jul 18 09:07:39 PM PDT 24 |
| Peak memory | 622108 kb |
| Host | smart-22556587-b2f6-4f93-bfea-44b7208d9347 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2189917376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2189917376 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2248211384 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1892066383 ps |
| CPU time | 82.8 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 07:50:36 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-109d4d2d-5936-4cec-8c0d-62b070da8001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248211384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2248211384 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.4148035962 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 13421994583 ps |
| CPU time | 456.18 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-cac7551a-9206-4435-983b-ea6bacdc756f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148035962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.4148035962 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4180818004 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1552969443 ps |
| CPU time | 228.12 seconds |
| Started | Jul 18 07:43:14 PM PDT 24 |
| Finished | Jul 18 07:47:03 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-995f2cfa-2bdf-4a5d-9e0c-f1f350fa4de0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180818004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.4180818004 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3986830730 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1305970032 ps |
| CPU time | 113.13 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 07:58:52 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-413d7951-e4a0-45e9-9578-7f661517cad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986830730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3986830730 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3316891755 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3711490963 ps |
| CPU time | 407.85 seconds |
| Started | Jul 18 08:01:49 PM PDT 24 |
| Finished | Jul 18 08:08:39 PM PDT 24 |
| Peak memory | 577388 kb |
| Host | smart-6863a003-a39f-4c3c-b676-ee177d1f7b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316891755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.3316891755 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2006992077 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3987669834 ps |
| CPU time | 521.47 seconds |
| Started | Jul 18 08:36:35 PM PDT 24 |
| Finished | Jul 18 08:45:17 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-8e20f00a-1720-495f-a78a-bb377f5f1168 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006992077 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2006992077 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.2400313753 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2966426520 ps |
| CPU time | 318.8 seconds |
| Started | Jul 18 08:30:18 PM PDT 24 |
| Finished | Jul 18 08:35:38 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-d244505f-908d-46eb-ab37-65e9b9a9e11a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400313753 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.2400313753 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2202568842 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5477162358 ps |
| CPU time | 967.55 seconds |
| Started | Jul 18 08:14:05 PM PDT 24 |
| Finished | Jul 18 08:30:13 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-918a3a63-9db0-408b-855a-9ad916d0b49e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202568842 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2202568842 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.735102820 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4362737686 ps |
| CPU time | 298.2 seconds |
| Started | Jul 18 07:41:08 PM PDT 24 |
| Finished | Jul 18 07:46:07 PM PDT 24 |
| Peak memory | 661548 kb |
| Host | smart-98ee7163-b822-4f17-a3a8-567a8c224e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735102820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_re set.735102820 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.822511991 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 8643596770 ps |
| CPU time | 1636.14 seconds |
| Started | Jul 18 08:25:13 PM PDT 24 |
| Finished | Jul 18 08:52:32 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-80d67501-cfd8-4c2f-8544-0bbbb266a49b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822511 991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.822511991 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2531634116 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4167229558 ps |
| CPU time | 492.22 seconds |
| Started | Jul 18 08:15:49 PM PDT 24 |
| Finished | Jul 18 08:24:02 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-1805ac45-92e7-4cb9-b2fd-26ec98f772d4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2531634116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2531634116 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2991218418 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 15008886338 ps |
| CPU time | 3941.22 seconds |
| Started | Jul 18 08:22:20 PM PDT 24 |
| Finished | Jul 18 09:28:04 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-e5b34d1c-5cc2-4e82-8518-a7a0011bbd3c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991218418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2991218418 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2806847619 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 51245963418 ps |
| CPU time | 9663.93 seconds |
| Started | Jul 18 07:40:01 PM PDT 24 |
| Finished | Jul 18 10:21:07 PM PDT 24 |
| Peak memory | 636636 kb |
| Host | smart-e821f266-97f5-42df-ba04-d2431c7c0b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806847619 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.2806847619 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2515057944 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 767374451 ps |
| CPU time | 31.39 seconds |
| Started | Jul 18 07:40:25 PM PDT 24 |
| Finished | Jul 18 07:40:57 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-20747c67-8594-4764-bfa9-57eae4b6c94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515057944 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2515057944 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1127228215 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 13599135066 ps |
| CPU time | 551.54 seconds |
| Started | Jul 18 07:53:45 PM PDT 24 |
| Finished | Jul 18 08:02:58 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-dd078976-e52f-4194-8a23-e3a786ea03a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127228215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1127228215 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1443205049 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 12648802254 ps |
| CPU time | 420.36 seconds |
| Started | Jul 18 07:54:51 PM PDT 24 |
| Finished | Jul 18 08:01:52 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-116f3e86-5fcc-4bf8-92f1-eee8ff956db2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443205049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.1443205049 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4063403769 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 16312293654 ps |
| CPU time | 590.03 seconds |
| Started | Jul 18 07:58:27 PM PDT 24 |
| Finished | Jul 18 08:08:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-470f60d3-c2d2-4913-b3e6-013e6ebc3bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063403769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4063403769 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1852607792 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 299879286 ps |
| CPU time | 22.53 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:01:05 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d6d780f9-8dfc-4d9c-a399-c2137d84d351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852607792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1852607792 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2790493905 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 15763386956 ps |
| CPU time | 587.15 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:10:52 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-b7396c47-d41f-47e9-9769-a5153e8087d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790493905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2790493905 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.544515372 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 7968626173 ps |
| CPU time | 287.2 seconds |
| Started | Jul 18 07:44:55 PM PDT 24 |
| Finished | Jul 18 07:49:43 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-e981e357-c794-4905-9baa-f86047eba3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544515372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.544515372 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2750648170 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 855447061 ps |
| CPU time | 30.19 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-621ae3df-c4de-4639-86ce-0f82e5974efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750648170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2750648170 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2731261265 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 6235331890 ps |
| CPU time | 668.64 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:15:05 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-ce46b13d-5986-4cb8-b963-af819ce9628d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731261265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2731261265 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1073525502 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2324494479 ps |
| CPU time | 219.05 seconds |
| Started | Jul 18 08:25:10 PM PDT 24 |
| Finished | Jul 18 08:28:51 PM PDT 24 |
| Peak memory | 608976 kb |
| Host | smart-69a58d5d-3eff-4aea-b957-8dc5aa57f099 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073525502 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1073525502 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1585601043 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5239745352 ps |
| CPU time | 717.48 seconds |
| Started | Jul 18 08:15:35 PM PDT 24 |
| Finished | Jul 18 08:27:33 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-2868335b-60fe-4c48-ab65-1043a686f422 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15856 01043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1585601043 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2046905841 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 11571020168 ps |
| CPU time | 2161.45 seconds |
| Started | Jul 18 08:21:08 PM PDT 24 |
| Finished | Jul 18 08:57:11 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-eb2f9eb7-7e00-41c8-ba44-5bbf5887400c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2046905841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2046905841 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1035586225 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4933531396 ps |
| CPU time | 270.04 seconds |
| Started | Jul 18 08:43:47 PM PDT 24 |
| Finished | Jul 18 08:48:19 PM PDT 24 |
| Peak memory | 656748 kb |
| Host | smart-c1078d76-8fa1-4b58-8131-004b50dbea8c |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035586225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1035586225 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3328845115 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 2245994074 ps |
| CPU time | 136.68 seconds |
| Started | Jul 18 08:17:07 PM PDT 24 |
| Finished | Jul 18 08:19:25 PM PDT 24 |
| Peak memory | 620468 kb |
| Host | smart-2893aa65-bca0-454a-ba5e-b57513e0a9cd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3328845115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3328845115 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.248843882 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 3531178840 ps |
| CPU time | 629.42 seconds |
| Started | Jul 18 08:14:44 PM PDT 24 |
| Finished | Jul 18 08:25:15 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-196255d6-24f4-4e07-9cbf-cb0b0e3b8c69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248843882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.248843882 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.146978911 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6281105772 ps |
| CPU time | 1527.68 seconds |
| Started | Jul 18 08:18:46 PM PDT 24 |
| Finished | Jul 18 08:44:15 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-27ad6229-75e6-41d4-83c1-33e945f9a05e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=146978911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.146978911 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4076489605 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 9688442120 ps |
| CPU time | 1586.72 seconds |
| Started | Jul 18 08:16:19 PM PDT 24 |
| Finished | Jul 18 08:42:47 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-7dd3229d-69d3-4d22-9504-5267c57cea1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076489605 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4076489605 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1613343246 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2746472540 ps |
| CPU time | 153.36 seconds |
| Started | Jul 18 08:27:35 PM PDT 24 |
| Finished | Jul 18 08:30:09 PM PDT 24 |
| Peak memory | 646208 kb |
| Host | smart-5bafbaa7-dbe2-470c-87ff-967244045128 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613343246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1613343246 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3638622121 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 68796651368 ps |
| CPU time | 9931.89 seconds |
| Started | Jul 18 08:40:16 PM PDT 24 |
| Finished | Jul 18 11:25:50 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-3db02838-d8c9-4138-a3e1-bd2aaf787911 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3638622121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3638622121 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2711790698 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4310489016 ps |
| CPU time | 363.61 seconds |
| Started | Jul 18 08:14:27 PM PDT 24 |
| Finished | Jul 18 08:20:32 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-2d45733c-eb93-418d-b259-f70a1a6d8bef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117 90698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.2711790698 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2549965888 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 24270826984 ps |
| CPU time | 6873.64 seconds |
| Started | Jul 18 08:19:54 PM PDT 24 |
| Finished | Jul 18 10:14:29 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-f56061f8-c39b-4483-b9cd-e5630db465ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2549965888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2549965888 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4124813484 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 5845621000 ps |
| CPU time | 537.22 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:49:00 PM PDT 24 |
| Peak memory | 591624 kb |
| Host | smart-dcde6ad1-da91-4fc5-93e7-73c4697f0dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124813484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.4124813484 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2830775403 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 5550848855 ps |
| CPU time | 416.83 seconds |
| Started | Jul 18 07:40:45 PM PDT 24 |
| Finished | Jul 18 07:47:43 PM PDT 24 |
| Peak memory | 637624 kb |
| Host | smart-c2cbd30a-dabd-4614-96bb-e6eac154c1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830775403 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.2830775403 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.713196181 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 6618165400 ps |
| CPU time | 649.38 seconds |
| Started | Jul 18 07:40:41 PM PDT 24 |
| Finished | Jul 18 07:51:31 PM PDT 24 |
| Peak memory | 598456 kb |
| Host | smart-b72e3f29-09b0-4fb2-bbc5-238750379724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713196181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.713196181 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.128465544 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 4665760808 ps |
| CPU time | 161.04 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:42:44 PM PDT 24 |
| Peak memory | 589916 kb |
| Host | smart-c6b58052-4fd7-4838-84dd-6bc9f5b99b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128465544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .chip_prim_tl_access.128465544 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3201954462 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 13179763558 ps |
| CPU time | 600.99 seconds |
| Started | Jul 18 07:40:04 PM PDT 24 |
| Finished | Jul 18 07:50:05 PM PDT 24 |
| Peak memory | 591240 kb |
| Host | smart-69dc6fce-e013-4380-a407-e8541fc7b161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201954462 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.3201954462 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.521360066 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 14642199020 ps |
| CPU time | 1843.6 seconds |
| Started | Jul 18 07:40:01 PM PDT 24 |
| Finished | Jul 18 08:10:46 PM PDT 24 |
| Peak memory | 593168 kb |
| Host | smart-2edee764-8c08-4e87-a8c9-0831f0aa86cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521360066 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.521360066 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.587675241 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 587342940 ps |
| CPU time | 29.4 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:40:32 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-f43f4792-9911-4149-97a7-58827ce2ea7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587675241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device.587675241 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1510107414 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 2881306168 ps |
| CPU time | 52.06 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:40:55 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-bf780e8c-4a24-4abe-818a-6954f333228b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510107414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.1510107414 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.704267830 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 312616048 ps |
| CPU time | 12.55 seconds |
| Started | Jul 18 07:40:26 PM PDT 24 |
| Finished | Jul 18 07:40:39 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d02a0864-41af-474c-bb58-d9718e355f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704267830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.704267830 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2536022055 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 557266923 ps |
| CPU time | 24.98 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:40:28 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-6fcb602f-b5b3-4add-af93-0403308f08fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536022055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2536022055 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3004069197 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 22900005187 ps |
| CPU time | 272.41 seconds |
| Started | Jul 18 07:40:01 PM PDT 24 |
| Finished | Jul 18 07:44:34 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-fe339ef1-a2f0-4144-9b14-cd346ca93a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004069197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3004069197 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2309051870 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 52304766351 ps |
| CPU time | 849.68 seconds |
| Started | Jul 18 07:40:04 PM PDT 24 |
| Finished | Jul 18 07:54:14 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-3728b37c-93e2-4423-a7c3-63e10c3657e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309051870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.2309051870 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3085937282 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 72694831 ps |
| CPU time | 8.75 seconds |
| Started | Jul 18 07:40:01 PM PDT 24 |
| Finished | Jul 18 07:40:11 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-03e36223-fa3d-415b-83e6-8bf45ee704d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085937282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.3085937282 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.4072877723 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 252580355 ps |
| CPU time | 19.48 seconds |
| Started | Jul 18 07:40:25 PM PDT 24 |
| Finished | Jul 18 07:40:45 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-a8489cbc-5a9c-40e3-abc5-c1e2233a9206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072877723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.4072877723 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.1754710732 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 239707150 ps |
| CPU time | 10.39 seconds |
| Started | Jul 18 07:40:01 PM PDT 24 |
| Finished | Jul 18 07:40:12 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8597d80d-9c81-4c4b-86e3-4498e8d0d61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754710732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.1754710732 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.67800453 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 8961343563 ps |
| CPU time | 93.69 seconds |
| Started | Jul 18 07:40:05 PM PDT 24 |
| Finished | Jul 18 07:41:39 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-f4d7fc9c-d5f4-41ad-83ac-d0273bc7b029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67800453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.67800453 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2721131190 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 6832158497 ps |
| CPU time | 120.04 seconds |
| Started | Jul 18 07:40:02 PM PDT 24 |
| Finished | Jul 18 07:42:03 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-105095f3-9a3f-40e2-839d-5fa1382e0274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721131190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2721131190 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.715719319 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 38187514 ps |
| CPU time | 6.07 seconds |
| Started | Jul 18 07:40:04 PM PDT 24 |
| Finished | Jul 18 07:40:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-165206e7-520a-44c1-9c31-61a142e27fea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715719319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays. 715719319 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.2390547906 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 2562699693 ps |
| CPU time | 258.21 seconds |
| Started | Jul 18 07:40:24 PM PDT 24 |
| Finished | Jul 18 07:44:43 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-dd0e5ee7-7fdc-4d5b-a1be-1e0d50bb9ced |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390547906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.2390547906 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2957678301 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 16325018228 ps |
| CPU time | 654.65 seconds |
| Started | Jul 18 07:40:41 PM PDT 24 |
| Finished | Jul 18 07:51:36 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-ef8b59c4-aae5-4322-a5d5-a95d5da0433d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957678301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2957678301 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.829447281 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 880271530 ps |
| CPU time | 249.93 seconds |
| Started | Jul 18 07:40:43 PM PDT 24 |
| Finished | Jul 18 07:44:54 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-765e0e8c-de8d-48bf-bf1f-1eaea427610b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829447281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.829447281 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3931927019 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 3177014771 ps |
| CPU time | 136.1 seconds |
| Started | Jul 18 07:40:43 PM PDT 24 |
| Finished | Jul 18 07:43:00 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-229b1753-b8b9-446f-a7da-f29a1288adc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931927019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.3931927019 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1484553774 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 1117052877 ps |
| CPU time | 55.71 seconds |
| Started | Jul 18 07:40:24 PM PDT 24 |
| Finished | Jul 18 07:41:20 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-663ca6cb-a159-4d70-8482-8a36437d6ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484553774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.1484553774 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3093372251 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 30745198380 ps |
| CPU time | 4500.12 seconds |
| Started | Jul 18 07:40:47 PM PDT 24 |
| Finished | Jul 18 08:55:48 PM PDT 24 |
| Peak memory | 593444 kb |
| Host | smart-30adab11-e915-4780-996a-71b7763de659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093372251 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3093372251 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.284276308 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 41507529364 ps |
| CPU time | 4331.02 seconds |
| Started | Jul 18 07:40:47 PM PDT 24 |
| Finished | Jul 18 08:52:59 PM PDT 24 |
| Peak memory | 592572 kb |
| Host | smart-9d3ab710-ca36-47e8-af11-e894d43fa7f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284276308 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.284276308 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3601984450 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 11153204166 ps |
| CPU time | 1020.15 seconds |
| Started | Jul 18 07:40:58 PM PDT 24 |
| Finished | Jul 18 07:57:59 PM PDT 24 |
| Peak memory | 645860 kb |
| Host | smart-01744e28-cb14-4800-8571-adf262fc26d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601984450 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3601984450 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.819217531 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 5756555400 ps |
| CPU time | 551.93 seconds |
| Started | Jul 18 07:41:02 PM PDT 24 |
| Finished | Jul 18 07:50:14 PM PDT 24 |
| Peak memory | 598700 kb |
| Host | smart-cc7bf948-e0f7-4b59-9e8e-c319abbbbfbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819217531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.819217531 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2738148596 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 13041815196 ps |
| CPU time | 704.57 seconds |
| Started | Jul 18 07:40:42 PM PDT 24 |
| Finished | Jul 18 07:52:27 PM PDT 24 |
| Peak memory | 589844 kb |
| Host | smart-d4b6083c-194b-43b5-8f2b-633ce5e2f102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738148596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.2738148596 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3118753410 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 7777698096 ps |
| CPU time | 340.76 seconds |
| Started | Jul 18 07:40:43 PM PDT 24 |
| Finished | Jul 18 07:46:25 PM PDT 24 |
| Peak memory | 591248 kb |
| Host | smart-19f9e229-dab5-4276-abab-6f0861ca91d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118753410 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.3118753410 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1844643753 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 15479455032 ps |
| CPU time | 1943.24 seconds |
| Started | Jul 18 07:40:44 PM PDT 24 |
| Finished | Jul 18 08:13:08 PM PDT 24 |
| Peak memory | 592852 kb |
| Host | smart-9d6331bd-feb7-4876-bd86-9ab4b8312add |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844643753 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1844643753 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3841040866 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 4521514458 ps |
| CPU time | 324.2 seconds |
| Started | Jul 18 07:40:40 PM PDT 24 |
| Finished | Jul 18 07:46:05 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-f926b58f-231f-4a85-8e3f-ae23d03e042e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841040866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3841040866 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.607162028 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 983623813 ps |
| CPU time | 62.02 seconds |
| Started | Jul 18 07:40:47 PM PDT 24 |
| Finished | Jul 18 07:41:50 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-e669f91c-c70d-45df-9bf3-cc7f3735a154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607162028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.607162028 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1005790791 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 81285348655 ps |
| CPU time | 1548.29 seconds |
| Started | Jul 18 07:40:54 PM PDT 24 |
| Finished | Jul 18 08:06:43 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-37543b91-c003-48a1-b5d3-913906d97f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005790791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.1005790791 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1248761825 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 202766459 ps |
| CPU time | 12.37 seconds |
| Started | Jul 18 07:40:44 PM PDT 24 |
| Finished | Jul 18 07:40:57 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-667e5824-991d-461a-aa7a-7867c69143c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248761825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1248761825 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.1818005347 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 481001818 ps |
| CPU time | 41.75 seconds |
| Started | Jul 18 07:40:41 PM PDT 24 |
| Finished | Jul 18 07:41:24 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7b50b0c1-151f-4565-96f7-88c66812e196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818005347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.1818005347 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3238559382 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 812439772 ps |
| CPU time | 29.71 seconds |
| Started | Jul 18 07:40:42 PM PDT 24 |
| Finished | Jul 18 07:41:12 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-678782db-0250-4b48-b944-e5a0e298ae88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238559382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3238559382 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3843145348 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 60007909972 ps |
| CPU time | 654.62 seconds |
| Started | Jul 18 07:40:46 PM PDT 24 |
| Finished | Jul 18 07:51:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-226d8d77-59fc-49bc-95cc-f368f76f8c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843145348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.3843145348 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1056182774 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 23441316898 ps |
| CPU time | 424.5 seconds |
| Started | Jul 18 07:40:43 PM PDT 24 |
| Finished | Jul 18 07:47:48 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5bcad920-4de3-4b74-b6ed-c2f3776c09be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056182774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1056182774 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1314190435 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 58417621 ps |
| CPU time | 7.94 seconds |
| Started | Jul 18 07:40:44 PM PDT 24 |
| Finished | Jul 18 07:40:52 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-183cf584-dd75-4da0-a832-82090902ef53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314190435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1314190435 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.1285925900 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 1725159461 ps |
| CPU time | 51.24 seconds |
| Started | Jul 18 07:40:41 PM PDT 24 |
| Finished | Jul 18 07:41:33 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-213d4517-bbf5-454e-9cf7-4a220a3632ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285925900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1285925900 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.4100239413 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 54910613 ps |
| CPU time | 6.59 seconds |
| Started | Jul 18 07:40:46 PM PDT 24 |
| Finished | Jul 18 07:40:54 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d34fbb91-26df-4e47-a82c-8511f85a4094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100239413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.4100239413 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3734528341 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 8832703018 ps |
| CPU time | 106.66 seconds |
| Started | Jul 18 07:40:47 PM PDT 24 |
| Finished | Jul 18 07:42:34 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3b067788-fe51-46c1-b220-08303f315ec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734528341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3734528341 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3494652787 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 4839814769 ps |
| CPU time | 87.39 seconds |
| Started | Jul 18 07:40:43 PM PDT 24 |
| Finished | Jul 18 07:42:11 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-3d4636c7-3567-433c-ba10-42970e193bf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494652787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3494652787 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.835082404 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 49253761 ps |
| CPU time | 6.26 seconds |
| Started | Jul 18 07:40:53 PM PDT 24 |
| Finished | Jul 18 07:41:00 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1c870bb9-7c9a-4207-97ce-60876e4c292d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835082404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 835082404 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.3195403330 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 1666262075 ps |
| CPU time | 64.39 seconds |
| Started | Jul 18 07:40:42 PM PDT 24 |
| Finished | Jul 18 07:41:47 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-edb7b8c4-0c02-4ff9-b0d6-07a862baa7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195403330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.3195403330 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2926127174 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 1294118081 ps |
| CPU time | 93.64 seconds |
| Started | Jul 18 07:40:47 PM PDT 24 |
| Finished | Jul 18 07:42:21 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e2fbfb9a-9960-45f2-8332-4d6cfb032aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926127174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.2926127174 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2235134273 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 274613622 ps |
| CPU time | 118.42 seconds |
| Started | Jul 18 07:40:53 PM PDT 24 |
| Finished | Jul 18 07:42:52 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4196f586-8593-41e8-9412-ed5daf3cf196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235134273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2235134273 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.942435454 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 109492198 ps |
| CPU time | 57.9 seconds |
| Started | Jul 18 07:40:45 PM PDT 24 |
| Finished | Jul 18 07:41:44 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-1a57ad96-4784-4900-a6e0-89b23cbb7d61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942435454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_reset_error.942435454 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1431440258 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 778767371 ps |
| CPU time | 36.76 seconds |
| Started | Jul 18 07:40:53 PM PDT 24 |
| Finished | Jul 18 07:41:30 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-9cfba2ca-19c3-44c5-8214-923306104d29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431440258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.1431440258 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1616730118 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 11653676250 ps |
| CPU time | 776.93 seconds |
| Started | Jul 18 07:45:40 PM PDT 24 |
| Finished | Jul 18 07:58:38 PM PDT 24 |
| Peak memory | 645648 kb |
| Host | smart-1aa1cd54-ae4c-4869-9e83-d58c4d7e15b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616730118 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.1616730118 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3839554980 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 5574496294 ps |
| CPU time | 463.05 seconds |
| Started | Jul 18 07:45:37 PM PDT 24 |
| Finished | Jul 18 07:53:21 PM PDT 24 |
| Peak memory | 597836 kb |
| Host | smart-d8a976d4-f7a7-4926-ade4-00cf14bce973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839554980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3839554980 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3150217352 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 28435499252 ps |
| CPU time | 3745.17 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 08:47:42 PM PDT 24 |
| Peak memory | 593132 kb |
| Host | smart-2b1b59a4-23b5-481a-8988-e0809532cc65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150217352 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3150217352 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.2260096886 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2935577173 ps |
| CPU time | 148.1 seconds |
| Started | Jul 18 07:45:24 PM PDT 24 |
| Finished | Jul 18 07:47:54 PM PDT 24 |
| Peak memory | 599664 kb |
| Host | smart-0ac3e061-0f1d-4ba6-b9ca-7cae8a02fdca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260096886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.2260096886 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.1388805761 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 1453752424 ps |
| CPU time | 59.26 seconds |
| Started | Jul 18 07:45:40 PM PDT 24 |
| Finished | Jul 18 07:46:40 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-0b6d7065-f0d4-49a9-b033-0e63483f8e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388805761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .1388805761 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3796687035 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 51036478341 ps |
| CPU time | 905.9 seconds |
| Started | Jul 18 07:45:51 PM PDT 24 |
| Finished | Jul 18 08:00:58 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-89e48468-d2de-49a8-90d9-b928a3a986ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796687035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.3796687035 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3016081083 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 298654749 ps |
| CPU time | 31.34 seconds |
| Started | Jul 18 07:45:42 PM PDT 24 |
| Finished | Jul 18 07:46:14 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e2e286c9-c632-4b23-8157-e2f069b5c970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016081083 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3016081083 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2525964834 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 2582325492 ps |
| CPU time | 85.46 seconds |
| Started | Jul 18 07:45:41 PM PDT 24 |
| Finished | Jul 18 07:47:07 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-9c1030e4-10d3-451d-a847-79a31bcb6f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525964834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2525964834 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2185713929 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 519242538 ps |
| CPU time | 45.98 seconds |
| Started | Jul 18 07:45:37 PM PDT 24 |
| Finished | Jul 18 07:46:24 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-0d612453-95e5-4c07-ae3b-5d483182983b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185713929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2185713929 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.935080802 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 33817575722 ps |
| CPU time | 385.01 seconds |
| Started | Jul 18 07:45:52 PM PDT 24 |
| Finished | Jul 18 07:52:18 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-879c4956-fe0e-4dba-8aec-d92eaf24bfe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935080802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.935080802 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1761063559 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 61260176872 ps |
| CPU time | 1046.5 seconds |
| Started | Jul 18 07:45:52 PM PDT 24 |
| Finished | Jul 18 08:03:20 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-cf89c86b-6cfa-476d-a88b-ac1644ed7788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761063559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1761063559 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4215488737 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 415447775 ps |
| CPU time | 44.21 seconds |
| Started | Jul 18 07:45:39 PM PDT 24 |
| Finished | Jul 18 07:46:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-792ba70f-0c02-49f1-813a-7a33b535ff22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215488737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.4215488737 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.2185754268 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 444007195 ps |
| CPU time | 15.83 seconds |
| Started | Jul 18 07:45:38 PM PDT 24 |
| Finished | Jul 18 07:45:55 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-f80625de-4ca5-4746-aadf-69bdcb425c92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185754268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.2185754268 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.4120181499 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 187390374 ps |
| CPU time | 8.44 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 07:45:25 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-cb6ffc11-032b-46a9-b28d-2d95eee4fb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120181499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.4120181499 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3218519922 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 7968613414 ps |
| CPU time | 87.36 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 07:46:44 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-0c68b383-da3f-41ae-a286-2114d3dcf39c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218519922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3218519922 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.190580620 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 5156212672 ps |
| CPU time | 97.54 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 07:46:54 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-f9dace44-044b-4983-ba87-0a79dd44fcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190580620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.190580620 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2935998016 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 52253662 ps |
| CPU time | 7 seconds |
| Started | Jul 18 07:45:18 PM PDT 24 |
| Finished | Jul 18 07:45:25 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-1fed9591-8b2a-4d10-b79d-6e5f48d989d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935998016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.2935998016 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.1671359068 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 2198647530 ps |
| CPU time | 76.83 seconds |
| Started | Jul 18 07:45:51 PM PDT 24 |
| Finished | Jul 18 07:47:09 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-568252e4-bf0b-43d8-8e1d-3a5a68ad995b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671359068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.1671359068 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2423648854 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 12836512574 ps |
| CPU time | 471.16 seconds |
| Started | Jul 18 07:45:38 PM PDT 24 |
| Finished | Jul 18 07:53:30 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-42a2c0e6-7d8a-48b0-9a27-b0fb1076ab45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423648854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.2423648854 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2848141253 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 273530961 ps |
| CPU time | 141.65 seconds |
| Started | Jul 18 07:45:52 PM PDT 24 |
| Finished | Jul 18 07:48:15 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-1153b817-2900-4911-befd-101a90dc3d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848141253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2848141253 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1581832565 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 14626885580 ps |
| CPU time | 706.87 seconds |
| Started | Jul 18 07:45:36 PM PDT 24 |
| Finished | Jul 18 07:57:24 PM PDT 24 |
| Peak memory | 582100 kb |
| Host | smart-caaaed2c-fdd7-4303-a9a4-a3f1508e7276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581832565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1581832565 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2200323834 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1380457299 ps |
| CPU time | 61.19 seconds |
| Started | Jul 18 07:45:37 PM PDT 24 |
| Finished | Jul 18 07:46:39 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-7f6e619b-4d9e-4667-b1ab-9e7312cf7563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200323834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.2200323834 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2809553325 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 8958260126 ps |
| CPU time | 693.89 seconds |
| Started | Jul 18 07:46:27 PM PDT 24 |
| Finished | Jul 18 07:58:02 PM PDT 24 |
| Peak memory | 653060 kb |
| Host | smart-09814857-237c-4997-a122-9891b121bb5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809553325 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2809553325 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.3428820316 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 6396576406 ps |
| CPU time | 699.21 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:58:04 PM PDT 24 |
| Peak memory | 598136 kb |
| Host | smart-77f23c65-3c82-46b6-87b6-8b59eeb6335b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428820316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.3428820316 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3076285073 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 29350553786 ps |
| CPU time | 4609.9 seconds |
| Started | Jul 18 07:45:42 PM PDT 24 |
| Finished | Jul 18 09:02:33 PM PDT 24 |
| Peak memory | 593416 kb |
| Host | smart-1ad6320e-7eda-4bec-83e9-98feed68626c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076285073 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3076285073 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.3411118170 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 3432874940 ps |
| CPU time | 198.79 seconds |
| Started | Jul 18 07:46:01 PM PDT 24 |
| Finished | Jul 18 07:49:20 PM PDT 24 |
| Peak memory | 603676 kb |
| Host | smart-6c4dd746-2fca-4cc4-bb93-19e333da1487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411118170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.3411118170 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.216674643 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 2476026328 ps |
| CPU time | 107.3 seconds |
| Started | Jul 18 07:46:07 PM PDT 24 |
| Finished | Jul 18 07:47:55 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0ce8c4e1-71bd-4a75-822c-deffbfbe9d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216674643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device. 216674643 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.984717488 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 11322643062 ps |
| CPU time | 219.22 seconds |
| Started | Jul 18 07:46:03 PM PDT 24 |
| Finished | Jul 18 07:49:43 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-be4b2d5b-6308-4ea4-93b1-0487ec4198f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984717488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_d evice_slow_rsp.984717488 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3296645630 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 1291082606 ps |
| CPU time | 50.8 seconds |
| Started | Jul 18 07:46:02 PM PDT 24 |
| Finished | Jul 18 07:46:54 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-9d128212-3b50-4c2d-a509-ed22ad5b8c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296645630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3296645630 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1828064359 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 457177422 ps |
| CPU time | 36.11 seconds |
| Started | Jul 18 07:46:01 PM PDT 24 |
| Finished | Jul 18 07:46:38 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-cc4ffa1f-cc8c-4f64-a94c-c9bbdad6d092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828064359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1828064359 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1714199184 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 146709364 ps |
| CPU time | 14.58 seconds |
| Started | Jul 18 07:46:02 PM PDT 24 |
| Finished | Jul 18 07:46:17 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-1d4da90b-dc17-4a3e-b376-de7cdc76e69a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714199184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1714199184 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.657410833 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 74771115621 ps |
| CPU time | 828.75 seconds |
| Started | Jul 18 07:46:01 PM PDT 24 |
| Finished | Jul 18 07:59:50 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-8fc77570-8c73-4220-a724-22c43e2a0a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657410833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.657410833 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1258983763 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 21511255228 ps |
| CPU time | 368.9 seconds |
| Started | Jul 18 07:46:06 PM PDT 24 |
| Finished | Jul 18 07:52:16 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c0dd6567-dca8-4e1d-94a9-6099e63e7c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258983763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1258983763 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1941811353 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 311372245 ps |
| CPU time | 32.12 seconds |
| Started | Jul 18 07:46:02 PM PDT 24 |
| Finished | Jul 18 07:46:34 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6399ba73-973d-461b-ac0e-63842164eac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941811353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.1941811353 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.767866266 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 1719793327 ps |
| CPU time | 50.27 seconds |
| Started | Jul 18 07:46:02 PM PDT 24 |
| Finished | Jul 18 07:46:53 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-120e752b-5ec6-4833-9333-55528452721b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767866266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.767866266 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.67093529 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 44976737 ps |
| CPU time | 6.15 seconds |
| Started | Jul 18 07:46:04 PM PDT 24 |
| Finished | Jul 18 07:46:11 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-28e9e769-7566-4d5e-b765-b79b5bbc5a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67093529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.67093529 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.143805724 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 8387517811 ps |
| CPU time | 93.55 seconds |
| Started | Jul 18 07:46:03 PM PDT 24 |
| Finished | Jul 18 07:47:37 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e8502b16-cde6-4a47-8a3a-6e6d1204b153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143805724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.143805724 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.8903729 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 5821525275 ps |
| CPU time | 105.85 seconds |
| Started | Jul 18 07:46:03 PM PDT 24 |
| Finished | Jul 18 07:47:50 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-aaf4e30a-bf0d-4cd0-bcd0-914a115b5d0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8903729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.8903729 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2487552155 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 52743808 ps |
| CPU time | 7.09 seconds |
| Started | Jul 18 07:46:06 PM PDT 24 |
| Finished | Jul 18 07:46:14 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-4845976a-5079-47d3-b101-dc127e6d674a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487552155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.2487552155 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.3879409398 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 8739256758 ps |
| CPU time | 309.98 seconds |
| Started | Jul 18 07:46:06 PM PDT 24 |
| Finished | Jul 18 07:51:17 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-5c860493-b0c0-4786-bded-b0f147c649c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879409398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3879409398 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.640682418 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 2600447958 ps |
| CPU time | 219.43 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:50:06 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-cfc106c4-b9b8-43d0-8fc2-b011182315c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640682418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.640682418 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3100852902 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 548047207 ps |
| CPU time | 332.09 seconds |
| Started | Jul 18 07:46:30 PM PDT 24 |
| Finished | Jul 18 07:52:03 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-d03513de-6f05-43f9-8c43-4fb8db6f5e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100852902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3100852902 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3572259307 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 12376751652 ps |
| CPU time | 471.79 seconds |
| Started | Jul 18 07:46:24 PM PDT 24 |
| Finished | Jul 18 07:54:17 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e2967ee3-9e5e-4bf3-9ed0-d7cccc9dd1cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572259307 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.3572259307 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.949201383 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 211964083 ps |
| CPU time | 26.21 seconds |
| Started | Jul 18 07:46:13 PM PDT 24 |
| Finished | Jul 18 07:46:40 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0951b23e-b7d4-4db6-94cd-8ccaf281b18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949201383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.949201383 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.682080187 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 5857278495 ps |
| CPU time | 433.55 seconds |
| Started | Jul 18 07:46:44 PM PDT 24 |
| Finished | Jul 18 07:53:58 PM PDT 24 |
| Peak memory | 637628 kb |
| Host | smart-0007e107-1759-453c-99b3-cdc73e7096b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682080187 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.682080187 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.4207513969 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 4353024596 ps |
| CPU time | 274.2 seconds |
| Started | Jul 18 07:46:30 PM PDT 24 |
| Finished | Jul 18 07:51:05 PM PDT 24 |
| Peak memory | 598436 kb |
| Host | smart-74b5a17a-5389-45e3-96ff-34211a8eff34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207513969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.4207513969 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2640374261 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 15888925294 ps |
| CPU time | 1494.89 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 08:11:20 PM PDT 24 |
| Peak memory | 593128 kb |
| Host | smart-8c868bfc-35b4-4fed-9945-44cf0a212dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640374261 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2640374261 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.249359723 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4602123057 ps |
| CPU time | 261.2 seconds |
| Started | Jul 18 07:46:30 PM PDT 24 |
| Finished | Jul 18 07:50:52 PM PDT 24 |
| Peak memory | 598532 kb |
| Host | smart-1534b7e2-c59d-4634-b576-42aef5a57269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249359723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.249359723 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.293475333 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 24947939 ps |
| CPU time | 8.65 seconds |
| Started | Jul 18 07:46:28 PM PDT 24 |
| Finished | Jul 18 07:46:37 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-12bab3eb-aa49-49bc-af4c-ca1c717ad7e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293475333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 293475333 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.3580398549 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 466589393 ps |
| CPU time | 20.37 seconds |
| Started | Jul 18 07:46:55 PM PDT 24 |
| Finished | Jul 18 07:47:17 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-70f91c60-d14f-4571-a8c0-1a086785bdf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580398549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.3580398549 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.554446390 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 316884922 ps |
| CPU time | 25.54 seconds |
| Started | Jul 18 07:46:24 PM PDT 24 |
| Finished | Jul 18 07:46:51 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6b4bf40b-7c6b-4503-b8b7-d0367667de88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554446390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.554446390 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1781234829 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 545866094 ps |
| CPU time | 46.89 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:47:13 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-5393c642-12db-4606-97ca-47e3d7ae8ee1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781234829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1781234829 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1559593259 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 15791970565 ps |
| CPU time | 171.98 seconds |
| Started | Jul 18 07:46:27 PM PDT 24 |
| Finished | Jul 18 07:49:20 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-7096a2e5-a310-4887-b166-8ec4aac95808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559593259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1559593259 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.826895889 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 18055197744 ps |
| CPU time | 321.15 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:51:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-9ce6a90c-117c-4029-8422-06b92a370b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826895889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.826895889 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.884589772 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 501058120 ps |
| CPU time | 44.5 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:47:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-653b2d9c-5934-493f-8752-54f51c4ab5d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884589772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.884589772 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.1556188234 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 355259611 ps |
| CPU time | 14.02 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:46:37 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e1f5e015-efe0-42e9-a0a0-f7f9fc31eb33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556188234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.1556188234 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.4207506895 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 144897876 ps |
| CPU time | 7.9 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:46:34 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-7dcd7700-e099-470e-8baa-c0eef82924cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207506895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.4207506895 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2867147988 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 9563198697 ps |
| CPU time | 107.38 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:48:12 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f8299f62-4321-4b86-b754-cc7c34f11a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867147988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2867147988 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2222584607 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 6796659007 ps |
| CPU time | 128.5 seconds |
| Started | Jul 18 07:46:24 PM PDT 24 |
| Finished | Jul 18 07:48:34 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-98e278e1-05a4-4167-bbc6-3d10b38b0f43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222584607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2222584607 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1108179357 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 43954598 ps |
| CPU time | 6.39 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:46:33 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-8c7ee984-e0c2-4ab5-9c0b-d6e488e8c445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108179357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1108179357 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2369957913 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2584346257 ps |
| CPU time | 90.01 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:47:56 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-3c6280ca-34d8-4441-922b-016d4e55f17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369957913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2369957913 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.669029352 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 12792939348 ps |
| CPU time | 458.73 seconds |
| Started | Jul 18 07:46:23 PM PDT 24 |
| Finished | Jul 18 07:54:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-da2c40af-2076-422f-ad2f-cb4395d05eb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669029352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.669029352 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1246264746 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 2286446979 ps |
| CPU time | 368.86 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:52:35 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-922538af-4da5-4538-901b-71ad0acf16d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246264746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1246264746 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.148975128 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 1756217349 ps |
| CPU time | 159.27 seconds |
| Started | Jul 18 07:46:28 PM PDT 24 |
| Finished | Jul 18 07:49:08 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b81f6178-8400-42ae-aa14-134515d3feb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148975128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.148975128 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.494101287 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 146214729 ps |
| CPU time | 9.69 seconds |
| Started | Jul 18 07:46:25 PM PDT 24 |
| Finished | Jul 18 07:46:36 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-f58665c1-fe43-4987-95a1-fa2cb03f809c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494101287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.494101287 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.4218838871 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 5959827660 ps |
| CPU time | 473.68 seconds |
| Started | Jul 18 07:46:57 PM PDT 24 |
| Finished | Jul 18 07:54:53 PM PDT 24 |
| Peak memory | 637632 kb |
| Host | smart-3f02aad4-1649-4c24-af26-2dcc774ee6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218838871 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.4218838871 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.1586276480 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 5948811672 ps |
| CPU time | 602.6 seconds |
| Started | Jul 18 07:47:00 PM PDT 24 |
| Finished | Jul 18 07:57:04 PM PDT 24 |
| Peak memory | 599232 kb |
| Host | smart-709a08d5-8c1f-402c-a0b9-890f23a2f325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586276480 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.1586276480 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.4218045452 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4215864139 ps |
| CPU time | 406.01 seconds |
| Started | Jul 18 07:46:43 PM PDT 24 |
| Finished | Jul 18 07:53:30 PM PDT 24 |
| Peak memory | 599740 kb |
| Host | smart-da86d3af-2b52-4171-a8f3-53678a649626 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218045452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.4218045452 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2748678088 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 2362661562 ps |
| CPU time | 86.25 seconds |
| Started | Jul 18 07:46:44 PM PDT 24 |
| Finished | Jul 18 07:48:11 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9fea5721-23d6-45b9-b50b-956b3a77dc82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748678088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2748678088 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2613797510 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 109794815046 ps |
| CPU time | 2078.96 seconds |
| Started | Jul 18 07:46:39 PM PDT 24 |
| Finished | Jul 18 08:21:20 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-8eeaaf1d-cac2-4856-9015-8c9800762d01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613797510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2613797510 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2061307415 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 880640800 ps |
| CPU time | 30.93 seconds |
| Started | Jul 18 07:46:45 PM PDT 24 |
| Finished | Jul 18 07:47:18 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-206e9099-5e10-43c3-9c09-55132552c3ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061307415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.2061307415 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.382159949 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 1643063460 ps |
| CPU time | 55.94 seconds |
| Started | Jul 18 07:46:39 PM PDT 24 |
| Finished | Jul 18 07:47:37 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-36a6d077-3a0a-42ca-9410-74bb9ba8b2a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382159949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.382159949 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.1141288259 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1732975343 ps |
| CPU time | 58.69 seconds |
| Started | Jul 18 07:46:41 PM PDT 24 |
| Finished | Jul 18 07:47:41 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a8cc7e3d-3586-47c8-82ae-7347728b44ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141288259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.1141288259 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.515581628 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 83479145264 ps |
| CPU time | 883.1 seconds |
| Started | Jul 18 07:46:42 PM PDT 24 |
| Finished | Jul 18 08:01:26 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c7f0d9fe-add1-4bd7-9f25-8b49d953f511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515581628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.515581628 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2239173851 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 33762273647 ps |
| CPU time | 605.57 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 07:56:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-1b991c55-b57a-47ce-9cab-f3647592bf9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239173851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2239173851 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2712528421 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 600331419 ps |
| CPU time | 51.53 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 07:47:33 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-48473786-b0a8-4508-b61f-d94eda0887b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712528421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.2712528421 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.4157881644 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 225026510 ps |
| CPU time | 16.71 seconds |
| Started | Jul 18 07:46:44 PM PDT 24 |
| Finished | Jul 18 07:47:02 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f5cc741d-111a-4c66-a52e-2194e177c092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157881644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4157881644 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.32740824 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 134441761 ps |
| CPU time | 7.02 seconds |
| Started | Jul 18 07:46:46 PM PDT 24 |
| Finished | Jul 18 07:46:54 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-80d8e8e9-5701-4f35-9c05-8cfcd8c2ad89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.32740824 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2923267198 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 10529462689 ps |
| CPU time | 111.49 seconds |
| Started | Jul 18 07:46:44 PM PDT 24 |
| Finished | Jul 18 07:48:36 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-511688d4-8cf6-4181-b15e-b3caf89b27de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923267198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2923267198 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.967270785 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 5910758892 ps |
| CPU time | 100.14 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 07:48:22 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-b88f2acb-46fb-4bb4-8816-214cc86f1681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967270785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.967270785 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4224750286 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 46960206 ps |
| CPU time | 6.55 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 07:46:48 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-7ffe3a23-b256-407e-a98b-1bb1d5252afd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224750286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.4224750286 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3297701042 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 2559958115 ps |
| CPU time | 242.52 seconds |
| Started | Jul 18 07:46:40 PM PDT 24 |
| Finished | Jul 18 07:50:44 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-0ac8563b-b6a9-45ab-8c3d-872297ae40e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297701042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3297701042 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2807121470 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 9412774103 ps |
| CPU time | 307.86 seconds |
| Started | Jul 18 07:46:56 PM PDT 24 |
| Finished | Jul 18 07:52:06 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-b5be92cf-0dea-4846-b5ee-fbb939b3b98b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807121470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2807121470 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.491866785 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 107889053 ps |
| CPU time | 17.93 seconds |
| Started | Jul 18 07:46:58 PM PDT 24 |
| Finished | Jul 18 07:47:18 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-64b2acff-ba05-42da-83da-d42eb349585d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491866785 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.491866785 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.4041672915 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 336980021 ps |
| CPU time | 16.61 seconds |
| Started | Jul 18 07:46:43 PM PDT 24 |
| Finished | Jul 18 07:47:00 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-b1936227-1d92-421d-9eba-ca0fbcf5b625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041672915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.4041672915 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.1717037305 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 4707637824 ps |
| CPU time | 404.29 seconds |
| Started | Jul 18 07:47:15 PM PDT 24 |
| Finished | Jul 18 07:54:01 PM PDT 24 |
| Peak memory | 597704 kb |
| Host | smart-4348e459-dd51-49c9-a75b-952f822806dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717037305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1717037305 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2517614860 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 30310119067 ps |
| CPU time | 4373.77 seconds |
| Started | Jul 18 07:46:57 PM PDT 24 |
| Finished | Jul 18 08:59:53 PM PDT 24 |
| Peak memory | 593500 kb |
| Host | smart-a05af8e4-81e8-4c36-a833-2ffe6bf01b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517614860 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2517614860 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3398611952 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 3024383027 ps |
| CPU time | 117.35 seconds |
| Started | Jul 18 07:47:13 PM PDT 24 |
| Finished | Jul 18 07:49:12 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-61559541-a571-4687-b9de-2afab9c8f0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398611952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3398611952 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2532976937 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 23045331049 ps |
| CPU time | 417.9 seconds |
| Started | Jul 18 07:47:15 PM PDT 24 |
| Finished | Jul 18 07:54:14 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d7c10e21-f53f-4ee6-b929-0598ee7cbcb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532976937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.2532976937 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2761813055 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 170721028 ps |
| CPU time | 20.24 seconds |
| Started | Jul 18 07:47:13 PM PDT 24 |
| Finished | Jul 18 07:47:34 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-922e9f1b-3b80-4901-bb65-cd4108b8b981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761813055 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.2761813055 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.1438316143 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1010758160 ps |
| CPU time | 32.19 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 07:47:48 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-ad72d43f-86e8-43f4-a4c5-3a1c2337d005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438316143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1438316143 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.732150789 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 871529843 ps |
| CPU time | 34.86 seconds |
| Started | Jul 18 07:46:56 PM PDT 24 |
| Finished | Jul 18 07:47:33 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-03943200-5fea-4b55-80f6-cc50df995fd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732150789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.732150789 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.3650546205 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 29294927796 ps |
| CPU time | 331.96 seconds |
| Started | Jul 18 07:46:59 PM PDT 24 |
| Finished | Jul 18 07:52:33 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-33c1a57d-f799-4360-bd8a-d829d816f314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650546205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.3650546205 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.608204429 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 53114705621 ps |
| CPU time | 907.99 seconds |
| Started | Jul 18 07:47:00 PM PDT 24 |
| Finished | Jul 18 08:02:09 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-76085ffa-73df-4a6d-a615-ce10e6017a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608204429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.608204429 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3710605510 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 282338310 ps |
| CPU time | 29.18 seconds |
| Started | Jul 18 07:46:54 PM PDT 24 |
| Finished | Jul 18 07:47:24 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-a06e6a91-61d3-485b-bc96-a99da39ffb2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710605510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3710605510 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.4034229647 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 503299638 ps |
| CPU time | 34.52 seconds |
| Started | Jul 18 07:47:13 PM PDT 24 |
| Finished | Jul 18 07:47:48 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-d0239ce3-ca55-4982-b200-f7359a692bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034229647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.4034229647 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.2005465849 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 55522189 ps |
| CPU time | 6.45 seconds |
| Started | Jul 18 07:46:59 PM PDT 24 |
| Finished | Jul 18 07:47:07 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-40a8b524-1c9a-43a1-a62b-d4f88b8fef70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005465849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.2005465849 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.125778710 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 8054754613 ps |
| CPU time | 88.05 seconds |
| Started | Jul 18 07:46:58 PM PDT 24 |
| Finished | Jul 18 07:48:28 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-1e2afc8b-3a57-4e31-8ca1-fdfa4f01ca58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125778710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.125778710 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3760273948 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 5034342204 ps |
| CPU time | 91.48 seconds |
| Started | Jul 18 07:46:57 PM PDT 24 |
| Finished | Jul 18 07:48:31 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4c27f252-47e1-419e-bd3e-f5526536fb0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760273948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.3760273948 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3401691787 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 51638015 ps |
| CPU time | 6.82 seconds |
| Started | Jul 18 07:46:56 PM PDT 24 |
| Finished | Jul 18 07:47:05 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-48c36ccf-e9e7-4482-8f1e-9a37cffff896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401691787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3401691787 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.781980950 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 1912533976 ps |
| CPU time | 135.34 seconds |
| Started | Jul 18 07:47:13 PM PDT 24 |
| Finished | Jul 18 07:49:29 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-1bc20e97-3546-44e5-ac24-16b83f3ccfff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781980950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.781980950 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2101081516 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 4153385789 ps |
| CPU time | 335.23 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 07:52:50 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-0d012ae3-2db3-4cde-8ff1-2210834ecd59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101081516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2101081516 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3445554099 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 6963948528 ps |
| CPU time | 823.72 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 08:00:59 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ee38f617-7374-4511-849c-c5c7f8a1d11d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445554099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3445554099 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.428516218 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 505483660 ps |
| CPU time | 138.52 seconds |
| Started | Jul 18 07:47:13 PM PDT 24 |
| Finished | Jul 18 07:49:33 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-f12b4aca-f8be-4385-9662-adcce1f966cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428516218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_reset_error.428516218 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2666900180 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 253521387 ps |
| CPU time | 12.63 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 07:47:27 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b6b9f173-18a9-46b5-abb3-966d97636831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666900180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2666900180 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.3625530556 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 10709274568 ps |
| CPU time | 939.46 seconds |
| Started | Jul 18 07:47:49 PM PDT 24 |
| Finished | Jul 18 08:03:30 PM PDT 24 |
| Peak memory | 640644 kb |
| Host | smart-6bd99fba-f3c8-4171-8674-db793fd81ce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625530556 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.3625530556 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1720045221 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 5685752416 ps |
| CPU time | 628.1 seconds |
| Started | Jul 18 07:47:49 PM PDT 24 |
| Finished | Jul 18 07:58:20 PM PDT 24 |
| Peak memory | 598816 kb |
| Host | smart-54a96bc6-da15-4807-bdcf-38bbe0c9f10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720045221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1720045221 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3255492369 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 29008234511 ps |
| CPU time | 3822.43 seconds |
| Started | Jul 18 07:47:14 PM PDT 24 |
| Finished | Jul 18 08:50:58 PM PDT 24 |
| Peak memory | 593148 kb |
| Host | smart-40d764ff-0385-4d07-9eb1-431a638f83c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255492369 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3255492369 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1844124648 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 2733595124 ps |
| CPU time | 104.59 seconds |
| Started | Jul 18 07:47:19 PM PDT 24 |
| Finished | Jul 18 07:49:05 PM PDT 24 |
| Peak memory | 603676 kb |
| Host | smart-c3f703c7-3111-4a1f-91d0-feda58286673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844124648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1844124648 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1505589 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 3568789974 ps |
| CPU time | 151.95 seconds |
| Started | Jul 18 07:47:36 PM PDT 24 |
| Finished | Jul 18 07:50:09 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-c2dafbea-ac51-4b11-a6d7-83c1176d7654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device.1505589 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3932850503 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 109790560533 ps |
| CPU time | 2027.76 seconds |
| Started | Jul 18 07:47:29 PM PDT 24 |
| Finished | Jul 18 08:21:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-b1441c44-3c2f-48bc-8572-87c9afe2bb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932850503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.3932850503 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2188372761 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 120539930 ps |
| CPU time | 14.16 seconds |
| Started | Jul 18 07:47:34 PM PDT 24 |
| Finished | Jul 18 07:47:50 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-82a4d657-d203-410c-8496-de86cce21449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188372761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2188372761 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.4178784949 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 2363723069 ps |
| CPU time | 81.1 seconds |
| Started | Jul 18 07:47:32 PM PDT 24 |
| Finished | Jul 18 07:48:55 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-3d7c3909-56b7-4354-af85-a70aad93fa0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178784949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4178784949 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3900944840 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 372482744 ps |
| CPU time | 36.46 seconds |
| Started | Jul 18 07:47:30 PM PDT 24 |
| Finished | Jul 18 07:48:08 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-42147116-02a5-4ff8-9b75-87dda832032c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900944840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3900944840 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.4145785234 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 23316477847 ps |
| CPU time | 248.27 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:51:41 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-b7053ec1-98ed-49ad-9f74-6912ad54f772 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145785234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.4145785234 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1214851395 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 10162482439 ps |
| CPU time | 176.21 seconds |
| Started | Jul 18 07:47:36 PM PDT 24 |
| Finished | Jul 18 07:50:33 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-dac6b95f-139d-438f-adc0-ebc6b4afe44e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214851395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1214851395 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.716725727 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 146233499 ps |
| CPU time | 14.4 seconds |
| Started | Jul 18 07:47:35 PM PDT 24 |
| Finished | Jul 18 07:47:51 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9faee069-7a6c-4751-90bf-381bad9e4681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716725727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.716725727 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.3562900463 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 601640035 ps |
| CPU time | 19.07 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:47:51 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-14f4820e-fbd3-4865-82fd-e7a872604caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562900463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.3562900463 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1673653619 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 158906321 ps |
| CPU time | 7.44 seconds |
| Started | Jul 18 07:47:15 PM PDT 24 |
| Finished | Jul 18 07:47:24 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-97fa5664-8a30-4cbd-a6b9-cd36f15f232a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673653619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1673653619 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2892027114 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 7219018320 ps |
| CPU time | 75.56 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:48:48 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-dbf48ac6-e0ff-4ba9-9262-4dc88472fc88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892027114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2892027114 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3633053746 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 5288722503 ps |
| CPU time | 91.84 seconds |
| Started | Jul 18 07:47:30 PM PDT 24 |
| Finished | Jul 18 07:49:03 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2c510def-91f0-4b8f-90df-27da867228dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633053746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3633053746 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1303697640 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 43767495 ps |
| CPU time | 6.09 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:47:38 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-fdbe168a-1d97-4a11-b25a-662cce11d09b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303697640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.1303697640 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.3196195877 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 8929408659 ps |
| CPU time | 346.64 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:53:19 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e5ac23d0-4b23-4008-9e67-c3830ae0cf8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196195877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3196195877 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3582558722 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 1474869461 ps |
| CPU time | 129.24 seconds |
| Started | Jul 18 07:47:31 PM PDT 24 |
| Finished | Jul 18 07:49:41 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-be349907-6543-4bf1-befc-b6435909f407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582558722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.3582558722 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2402159023 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 391057714 ps |
| CPU time | 152.75 seconds |
| Started | Jul 18 07:47:36 PM PDT 24 |
| Finished | Jul 18 07:50:10 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-56096cad-8cc7-4623-8364-d8e2177391d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402159023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2402159023 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.2950183286 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 312140261 ps |
| CPU time | 88.4 seconds |
| Started | Jul 18 07:47:32 PM PDT 24 |
| Finished | Jul 18 07:49:02 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-3b9536ee-5414-4df3-b63f-5ba9ef87d1d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950183286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.2950183286 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.4156741984 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1107174135 ps |
| CPU time | 47.2 seconds |
| Started | Jul 18 07:47:35 PM PDT 24 |
| Finished | Jul 18 07:48:24 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-9c300f8e-7c8b-4b96-a2bb-434667466dfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156741984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.4156741984 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.4018960247 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 11041179149 ps |
| CPU time | 881.12 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 08:03:22 PM PDT 24 |
| Peak memory | 646844 kb |
| Host | smart-6a242c0a-8ae1-4349-abd7-7035dda17d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018960247 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.4018960247 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3685035554 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 4632319734 ps |
| CPU time | 384.75 seconds |
| Started | Jul 18 07:48:34 PM PDT 24 |
| Finished | Jul 18 07:54:59 PM PDT 24 |
| Peak memory | 596976 kb |
| Host | smart-5e72bc3d-f146-442f-9af6-7ae289932d9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685035554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3685035554 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2532222610 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 31548158996 ps |
| CPU time | 4482.35 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 09:02:37 PM PDT 24 |
| Peak memory | 593552 kb |
| Host | smart-a5ae17b0-4185-49bb-9607-fc9e721c9ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532222610 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2532222610 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.3844935532 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 3745767354 ps |
| CPU time | 199.68 seconds |
| Started | Jul 18 07:47:53 PM PDT 24 |
| Finished | Jul 18 07:51:14 PM PDT 24 |
| Peak memory | 598640 kb |
| Host | smart-9d85208f-f611-4d80-9130-33a004dc7c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844935532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3844935532 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.3448359085 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 191351084 ps |
| CPU time | 16.23 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 07:48:10 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d1fe511d-7e2e-47a6-b1ca-315120fde4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448359085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .3448359085 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1694532677 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 168663821935 ps |
| CPU time | 3281.99 seconds |
| Started | Jul 18 07:47:51 PM PDT 24 |
| Finished | Jul 18 08:42:36 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-bb460475-0e47-4391-aba0-7b0a4361bc39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694532677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1694532677 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1138632440 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 52964905 ps |
| CPU time | 8.7 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 07:48:03 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-89f9be65-1c28-4ae0-94c3-f332102f4ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138632440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.1138632440 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1051174249 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 598307152 ps |
| CPU time | 47.82 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 07:48:42 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-881f220d-528b-4bee-b3f4-dd7941c29cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051174249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1051174249 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.133127512 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 1773429863 ps |
| CPU time | 62.82 seconds |
| Started | Jul 18 07:47:49 PM PDT 24 |
| Finished | Jul 18 07:48:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7072e2b4-f730-4ae0-8bd1-b28760dcc5d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133127512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.133127512 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.3157018600 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 13616857775 ps |
| CPU time | 149.25 seconds |
| Started | Jul 18 07:47:51 PM PDT 24 |
| Finished | Jul 18 07:50:23 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-d0f63a38-1bd2-42bc-9452-83b20f939104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157018600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.3157018600 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.1902144920 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 16489787308 ps |
| CPU time | 285.05 seconds |
| Started | Jul 18 07:47:50 PM PDT 24 |
| Finished | Jul 18 07:52:37 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-392fb855-ff13-42ee-88a5-708cd7c5f312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902144920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.1902144920 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3952095728 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 111961111 ps |
| CPU time | 10.43 seconds |
| Started | Jul 18 07:47:49 PM PDT 24 |
| Finished | Jul 18 07:48:02 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-1c6e2ed5-4b85-4a66-9da4-e5f989d78ba6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952095728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3952095728 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.720365272 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 2696832613 ps |
| CPU time | 84.29 seconds |
| Started | Jul 18 07:47:50 PM PDT 24 |
| Finished | Jul 18 07:49:17 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-25dc33b7-d596-418e-adc4-e94270a9a20b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720365272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.720365272 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1052577718 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 40647183 ps |
| CPU time | 6.32 seconds |
| Started | Jul 18 07:47:53 PM PDT 24 |
| Finished | Jul 18 07:48:01 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-609d580e-114c-4f45-ad41-91865f1c3e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052577718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1052577718 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1774603245 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 8387290952 ps |
| CPU time | 90.32 seconds |
| Started | Jul 18 07:47:49 PM PDT 24 |
| Finished | Jul 18 07:49:22 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-767b03a3-5e47-4d62-aeca-b6da3d0e3df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774603245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1774603245 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.470187618 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 4567256531 ps |
| CPU time | 79.76 seconds |
| Started | Jul 18 07:47:50 PM PDT 24 |
| Finished | Jul 18 07:49:12 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-34c915e4-fcc4-4d4d-b24c-999bccb93ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470187618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.470187618 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1185379358 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 46513767 ps |
| CPU time | 6.91 seconds |
| Started | Jul 18 07:47:54 PM PDT 24 |
| Finished | Jul 18 07:48:02 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-0335dfc9-47a3-45aa-a176-3dc5c200e1dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185379358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.1185379358 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3910572316 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 6147678176 ps |
| CPU time | 245.83 seconds |
| Started | Jul 18 07:47:53 PM PDT 24 |
| Finished | Jul 18 07:52:00 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-754f5798-57f6-4f1f-9170-63690dba68b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910572316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3910572316 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2525924361 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 5802450 ps |
| CPU time | 3.8 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 07:47:58 PM PDT 24 |
| Peak memory | 565056 kb |
| Host | smart-a0b72dc1-a482-4a25-a5e2-843b99d10703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525924361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.2525924361 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.183181747 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 340330504 ps |
| CPU time | 162.36 seconds |
| Started | Jul 18 07:47:52 PM PDT 24 |
| Finished | Jul 18 07:50:36 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-14450d9c-b9f2-4bf8-b2b5-d84ce1e4534d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183181747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.183181747 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.222831533 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 2121457106 ps |
| CPU time | 175.19 seconds |
| Started | Jul 18 07:48:44 PM PDT 24 |
| Finished | Jul 18 07:51:40 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-fc86d79a-7da1-4485-89ee-2504d2b5ec97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222831533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_reset_error.222831533 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.515259838 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 604416687 ps |
| CPU time | 32.49 seconds |
| Started | Jul 18 07:47:50 PM PDT 24 |
| Finished | Jul 18 07:48:25 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-6c557847-db11-4087-8a06-73ca835cde2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515259838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.515259838 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.327058152 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 10127094952 ps |
| CPU time | 777.41 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 08:01:36 PM PDT 24 |
| Peak memory | 645848 kb |
| Host | smart-e2cb269f-faeb-4561-a3c8-949173b31b17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327058152 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.327058152 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.1322307785 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5564946423 ps |
| CPU time | 578.21 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 07:58:21 PM PDT 24 |
| Peak memory | 598908 kb |
| Host | smart-935ebe13-7dd4-40e9-938b-7a9fe2ba1ce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322307785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.1322307785 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1285216593 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 29142496012 ps |
| CPU time | 3735.05 seconds |
| Started | Jul 18 07:48:43 PM PDT 24 |
| Finished | Jul 18 08:51:00 PM PDT 24 |
| Peak memory | 593400 kb |
| Host | smart-27de03f0-dea8-4fe3-b8e6-6107da452d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285216593 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1285216593 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.3261744752 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3883589668 ps |
| CPU time | 272.44 seconds |
| Started | Jul 18 07:48:45 PM PDT 24 |
| Finished | Jul 18 07:53:18 PM PDT 24 |
| Peak memory | 603672 kb |
| Host | smart-2ab7bf78-ed40-4beb-bcd2-e6a42f138bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261744752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.3261744752 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3411613701 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 996469074 ps |
| CPU time | 70.46 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:49:48 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-8746387c-c5b9-4fa7-abaa-cf94f3d28229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411613701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3411613701 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.945202547 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 19870314610 ps |
| CPU time | 345.88 seconds |
| Started | Jul 18 07:48:44 PM PDT 24 |
| Finished | Jul 18 07:54:31 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-bfda4e2a-eb4f-471c-8d74-50b0193a326e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945202547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.945202547 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2661605583 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 66176716 ps |
| CPU time | 9.91 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 07:48:53 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-7c135263-0753-4994-9a63-51366857f521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661605583 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.2661605583 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3270886356 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 1230832818 ps |
| CPU time | 38.33 seconds |
| Started | Jul 18 07:48:39 PM PDT 24 |
| Finished | Jul 18 07:49:19 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-73f57bb7-c3fa-4b5a-b286-f0199bb1afc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270886356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3270886356 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.1142103246 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 258813532 ps |
| CPU time | 11.91 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 07:48:48 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-fec0a299-85ce-421f-8673-ffc954013c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142103246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.1142103246 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.3572727502 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 43889852934 ps |
| CPU time | 515.61 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 07:57:17 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-67e2d80e-d956-49e7-b9c7-5feb199768a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572727502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.3572727502 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.55203395 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 43249120111 ps |
| CPU time | 733.12 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 08:00:49 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-e09f80e1-0f29-4ff0-8efb-54b89c0226f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55203395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.55203395 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.757938308 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 325965379 ps |
| CPU time | 30.93 seconds |
| Started | Jul 18 07:48:44 PM PDT 24 |
| Finished | Jul 18 07:49:16 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1dc4dd41-2fd4-46a2-8311-21cc55533424 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757938308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.757938308 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3560059055 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 179911193 ps |
| CPU time | 14.56 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:48:53 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-22e23158-85e7-4a5f-8027-b7387cb4f5e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560059055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3560059055 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.561686647 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 49794313 ps |
| CPU time | 6.58 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 07:48:48 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-eca7d42f-6ccf-4671-bbeb-5db9f92045ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561686647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.561686647 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1979746668 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 6911018164 ps |
| CPU time | 73.12 seconds |
| Started | Jul 18 07:48:38 PM PDT 24 |
| Finished | Jul 18 07:49:52 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8b294b6f-66f3-4de5-84ae-969d1d3322f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979746668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1979746668 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.765129892 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 3668597923 ps |
| CPU time | 65.58 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 07:49:42 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-7badfac6-dd40-4a11-a895-e7d4960d185a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765129892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.765129892 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3663106967 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 53574070 ps |
| CPU time | 6.93 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:48:45 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f50a3dc4-bae8-4b1f-b99d-be0db8924b5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663106967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3663106967 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.370155577 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 5936605370 ps |
| CPU time | 237.17 seconds |
| Started | Jul 18 07:48:39 PM PDT 24 |
| Finished | Jul 18 07:52:38 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-cb3b0b0b-31d9-49fb-a9ff-a5fa690fb6d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370155577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.370155577 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.355156179 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 1900229365 ps |
| CPU time | 150.65 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 07:51:14 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-39c49c2b-0cd0-4f37-b255-894a6d5f559f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355156179 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.355156179 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2751442796 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 53463158 ps |
| CPU time | 24.18 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 07:49:05 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-b457b4e7-9b27-4507-aa5e-6e09fa000246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751442796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2751442796 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1349188501 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 1634527728 ps |
| CPU time | 141.52 seconds |
| Started | Jul 18 07:48:44 PM PDT 24 |
| Finished | Jul 18 07:51:06 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-55097f08-0c7b-4928-86f3-5c2db8cd6abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349188501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1349188501 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.119396447 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 818867975 ps |
| CPU time | 30.55 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:49:09 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-09f07c12-56e4-467a-932c-a66779db56b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119396447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.119396447 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2002490255 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 11983635875 ps |
| CPU time | 787.04 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 08:01:50 PM PDT 24 |
| Peak memory | 646872 kb |
| Host | smart-d1b88184-964a-4df0-8b4e-a0d98625cff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002490255 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.2002490255 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.302926380 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 5823129700 ps |
| CPU time | 547.66 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 07:57:51 PM PDT 24 |
| Peak memory | 598516 kb |
| Host | smart-caf98737-96fc-4640-9b89-14985942ace7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302926380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.302926380 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1231553763 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 16119227000 ps |
| CPU time | 2175.83 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 08:24:52 PM PDT 24 |
| Peak memory | 592664 kb |
| Host | smart-78326473-8ba1-4261-a1ed-34ffaa053d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231553763 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1231553763 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.889245735 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 4226241036 ps |
| CPU time | 341.73 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 07:54:18 PM PDT 24 |
| Peak memory | 599856 kb |
| Host | smart-8e155248-eae5-48f4-806c-a3fd96d7edb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889245735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.889245735 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1105407804 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 1714324347 ps |
| CPU time | 68.94 seconds |
| Started | Jul 18 07:48:43 PM PDT 24 |
| Finished | Jul 18 07:49:53 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-7a6e0ec8-9eb2-41d6-a6f9-177d3336abc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105407804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1105407804 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.434704364 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 39798926545 ps |
| CPU time | 676.74 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:59:56 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-09845212-5ed1-4254-ad94-43b3a351ecbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434704364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d evice_slow_rsp.434704364 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2667658737 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 850661462 ps |
| CPU time | 34.22 seconds |
| Started | Jul 18 07:48:43 PM PDT 24 |
| Finished | Jul 18 07:49:19 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-4fdc2e43-6dcc-4ae4-859f-576222a59092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667658737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2667658737 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3565317403 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 518227399 ps |
| CPU time | 42.04 seconds |
| Started | Jul 18 07:48:34 PM PDT 24 |
| Finished | Jul 18 07:49:18 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-c2c8f2eb-9560-417a-80d6-e36c6319b04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565317403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3565317403 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.3202407523 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 505888711 ps |
| CPU time | 16.09 seconds |
| Started | Jul 18 07:48:43 PM PDT 24 |
| Finished | Jul 18 07:49:00 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-7212b3b9-87ce-4143-9de0-192b54add558 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202407523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.3202407523 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.2861865771 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 13901519176 ps |
| CPU time | 164.28 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:51:23 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b268e2f2-f635-4258-962e-2727c739cdc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861865771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.2861865771 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1092879510 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 56974614857 ps |
| CPU time | 1011.42 seconds |
| Started | Jul 18 07:48:35 PM PDT 24 |
| Finished | Jul 18 08:05:27 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-5457df68-b681-4b1e-93aa-18f0d87c0879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092879510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1092879510 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1920400976 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 33386323 ps |
| CPU time | 6.03 seconds |
| Started | Jul 18 07:48:37 PM PDT 24 |
| Finished | Jul 18 07:48:44 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-4f5859cf-647e-4a92-acf4-ef74e1446b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920400976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.1920400976 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.990847480 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 2325845129 ps |
| CPU time | 65.23 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 07:49:47 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-436cd6ec-7e3f-4a9f-9efb-766236356e2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990847480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.990847480 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.2006559045 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 200101822 ps |
| CPU time | 9.41 seconds |
| Started | Jul 18 07:48:44 PM PDT 24 |
| Finished | Jul 18 07:48:54 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-6a0fb84d-d224-40cb-9de2-1da26df999d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006559045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2006559045 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.2820831070 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 6851873178 ps |
| CPU time | 79.68 seconds |
| Started | Jul 18 07:48:45 PM PDT 24 |
| Finished | Jul 18 07:50:06 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-8be2809d-b23a-4d5f-bbdb-5c3c73c76f80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820831070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.2820831070 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.4138656220 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5349502395 ps |
| CPU time | 90.46 seconds |
| Started | Jul 18 07:48:41 PM PDT 24 |
| Finished | Jul 18 07:50:13 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-852f1397-d1c6-450e-a483-ed774ec40b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138656220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4138656220 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.256267206 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 47978962 ps |
| CPU time | 6.71 seconds |
| Started | Jul 18 07:48:34 PM PDT 24 |
| Finished | Jul 18 07:48:41 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f4697f1b-339b-4516-9271-edd8bb8f771b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256267206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .256267206 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.64727416 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 9831508005 ps |
| CPU time | 403.1 seconds |
| Started | Jul 18 07:48:40 PM PDT 24 |
| Finished | Jul 18 07:55:24 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-6cb091b3-46dd-4901-9700-d41ecbaa9acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64727416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.64727416 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2517669058 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 20421861044 ps |
| CPU time | 734.97 seconds |
| Started | Jul 18 07:48:34 PM PDT 24 |
| Finished | Jul 18 08:00:50 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-cfc9dcf8-41fd-4dc7-9246-090fa5b85aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517669058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2517669058 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1360578253 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 238743116 ps |
| CPU time | 138.72 seconds |
| Started | Jul 18 07:48:41 PM PDT 24 |
| Finished | Jul 18 07:51:01 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-0e0792f8-d747-4069-93f7-172874613f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360578253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1360578253 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1927169587 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 653860973 ps |
| CPU time | 213.42 seconds |
| Started | Jul 18 07:48:42 PM PDT 24 |
| Finished | Jul 18 07:52:17 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-0f8100b2-7f1c-4fc5-b2c8-691ea58400fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927169587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1927169587 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.38154880 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 108575281 ps |
| CPU time | 14.4 seconds |
| Started | Jul 18 07:48:43 PM PDT 24 |
| Finished | Jul 18 07:48:59 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-3c629b80-e433-42ca-8270-292f99f07989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38154880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.38154880 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4005849798 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 11996763836 ps |
| CPU time | 957.03 seconds |
| Started | Jul 18 07:49:21 PM PDT 24 |
| Finished | Jul 18 08:05:18 PM PDT 24 |
| Peak memory | 652868 kb |
| Host | smart-8122d5ad-c13b-492b-b6b4-beb89d6b9b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005849798 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.4005849798 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.932043274 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 3922998200 ps |
| CPU time | 329.87 seconds |
| Started | Jul 18 07:49:14 PM PDT 24 |
| Finished | Jul 18 07:54:45 PM PDT 24 |
| Peak memory | 598056 kb |
| Host | smart-484d12cb-540d-4324-84d1-693297195553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932043274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.932043274 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.949014348 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 29360324330 ps |
| CPU time | 3023.35 seconds |
| Started | Jul 18 07:48:58 PM PDT 24 |
| Finished | Jul 18 08:39:22 PM PDT 24 |
| Peak memory | 593480 kb |
| Host | smart-65a03e3e-dc9e-4c50-97a6-5f33786dfef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949014348 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.chip_same_csr_outstanding.949014348 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.2357295582 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2915088878 ps |
| CPU time | 146.42 seconds |
| Started | Jul 18 07:48:59 PM PDT 24 |
| Finished | Jul 18 07:51:26 PM PDT 24 |
| Peak memory | 599652 kb |
| Host | smart-ffed3e64-53c0-4a79-ba79-6d59719f6d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357295582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2357295582 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.961135438 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 281538858 ps |
| CPU time | 33.55 seconds |
| Started | Jul 18 07:48:51 PM PDT 24 |
| Finished | Jul 18 07:49:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0ca88a03-88d6-49b7-b16d-7fb596cf63ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961135438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 961135438 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2876402529 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 39660529427 ps |
| CPU time | 674.57 seconds |
| Started | Jul 18 07:48:55 PM PDT 24 |
| Finished | Jul 18 08:00:11 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-70b97cf1-193e-44bf-a036-04958b05d92b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876402529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.2876402529 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.1148111804 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 213273752 ps |
| CPU time | 11.79 seconds |
| Started | Jul 18 07:48:52 PM PDT 24 |
| Finished | Jul 18 07:49:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-207c665a-d068-4936-bdc9-33e4674e98b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148111804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.1148111804 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.2563776753 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 195246856 ps |
| CPU time | 8.94 seconds |
| Started | Jul 18 07:49:00 PM PDT 24 |
| Finished | Jul 18 07:49:11 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-e56723aa-b57e-42c9-a928-2821f4132026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563776753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.2563776753 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.618289452 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 644011921 ps |
| CPU time | 24.98 seconds |
| Started | Jul 18 07:48:58 PM PDT 24 |
| Finished | Jul 18 07:49:23 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-57637931-1ce0-46f3-9476-fd126be65004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618289452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.618289452 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2115758623 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 92665677947 ps |
| CPU time | 1053.17 seconds |
| Started | Jul 18 07:49:00 PM PDT 24 |
| Finished | Jul 18 08:06:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-93a17b33-7172-4fe2-859d-603992837278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115758623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2115758623 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.476561813 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 12678650046 ps |
| CPU time | 218.35 seconds |
| Started | Jul 18 07:48:59 PM PDT 24 |
| Finished | Jul 18 07:52:39 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-a714bb25-abbf-4abc-9517-188e34f8ff49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476561813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.476561813 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2930927081 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 33329565 ps |
| CPU time | 6.42 seconds |
| Started | Jul 18 07:48:54 PM PDT 24 |
| Finished | Jul 18 07:49:02 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-b625ccf8-7749-449e-bbd5-229c57f40b6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930927081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2930927081 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.1419532300 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 160267107 ps |
| CPU time | 8.65 seconds |
| Started | Jul 18 07:48:56 PM PDT 24 |
| Finished | Jul 18 07:49:05 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-3c48c1ab-5fc1-45b8-b55d-5b91468e1db5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419532300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.1419532300 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.3113940112 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 48619545 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 07:48:56 PM PDT 24 |
| Finished | Jul 18 07:49:03 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-64b04fd4-d482-4bd7-8624-21e4823e570c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113940112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.3113940112 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2724767452 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 9575699341 ps |
| CPU time | 101.68 seconds |
| Started | Jul 18 07:48:56 PM PDT 24 |
| Finished | Jul 18 07:50:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-0fea1490-3ebc-4965-a8b6-c034b72abcb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724767452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2724767452 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.1702283002 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 5926264020 ps |
| CPU time | 106.19 seconds |
| Started | Jul 18 07:48:53 PM PDT 24 |
| Finished | Jul 18 07:50:40 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-19f0d2ca-38b5-4886-9b90-6d209658ea45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702283002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.1702283002 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.1408851899 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 37487481 ps |
| CPU time | 5.67 seconds |
| Started | Jul 18 07:48:53 PM PDT 24 |
| Finished | Jul 18 07:48:59 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-6d958726-c4fa-4399-bd55-d00457becd17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408851899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.1408851899 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1544068823 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 1394990255 ps |
| CPU time | 107.83 seconds |
| Started | Jul 18 07:49:00 PM PDT 24 |
| Finished | Jul 18 07:50:49 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-64d56ad4-992a-450e-89de-cd2a454ac641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544068823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1544068823 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3779713356 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 1133133541 ps |
| CPU time | 73.93 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 07:50:28 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-0cadcb9a-163f-461d-ab02-9fc1dd4a2be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779713356 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3779713356 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1442734207 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 67805633 ps |
| CPU time | 9.65 seconds |
| Started | Jul 18 07:48:53 PM PDT 24 |
| Finished | Jul 18 07:49:03 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-51ca9200-f010-425e-9cbb-dc3fd8561968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442734207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.1442734207 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.870749958 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 3175350618 ps |
| CPU time | 330.32 seconds |
| Started | Jul 18 07:49:14 PM PDT 24 |
| Finished | Jul 18 07:54:45 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c59e4e35-57a2-4bf9-8571-e5598f780a43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870749958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_reset_error.870749958 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2392901048 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 1487415666 ps |
| CPU time | 62.95 seconds |
| Started | Jul 18 07:48:55 PM PDT 24 |
| Finished | Jul 18 07:49:59 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-93c43b02-5ace-425e-a462-ca1460bba468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392901048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2392901048 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1345206737 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 4377018518 ps |
| CPU time | 447.48 seconds |
| Started | Jul 18 07:40:59 PM PDT 24 |
| Finished | Jul 18 07:48:27 PM PDT 24 |
| Peak memory | 590564 kb |
| Host | smart-50974f95-4bba-41ce-a503-74c375dd1acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345206737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1345206737 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.1672819801 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 11977274522 ps |
| CPU time | 873.75 seconds |
| Started | Jul 18 07:41:38 PM PDT 24 |
| Finished | Jul 18 07:56:13 PM PDT 24 |
| Peak memory | 652728 kb |
| Host | smart-4d72dd6e-dacb-48f8-b122-7edf8d6b7808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672819801 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.1672819801 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.497928284 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3814640536 ps |
| CPU time | 262.88 seconds |
| Started | Jul 18 07:41:40 PM PDT 24 |
| Finished | Jul 18 07:46:03 PM PDT 24 |
| Peak memory | 597576 kb |
| Host | smart-d2be71d6-b7fd-4db3-94ef-63a820432180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497928284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.497928284 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2352708068 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 5872760864 ps |
| CPU time | 293.46 seconds |
| Started | Jul 18 07:41:00 PM PDT 24 |
| Finished | Jul 18 07:45:54 PM PDT 24 |
| Peak memory | 590036 kb |
| Host | smart-7e2fb587-80c5-4bb2-b243-832c874f6e7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352708068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2352708068 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1337849869 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 21466071299 ps |
| CPU time | 1057.46 seconds |
| Started | Jul 18 07:41:01 PM PDT 24 |
| Finished | Jul 18 07:58:40 PM PDT 24 |
| Peak memory | 591196 kb |
| Host | smart-2214e769-f9b3-4c3f-981b-0e8ebb12f27a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337849869 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1337849869 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3375494264 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 3830062682 ps |
| CPU time | 250.05 seconds |
| Started | Jul 18 07:40:59 PM PDT 24 |
| Finished | Jul 18 07:45:10 PM PDT 24 |
| Peak memory | 598540 kb |
| Host | smart-bdd633c2-cb9c-451b-8fd9-12934ee4343a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375494264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3375494264 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3538022467 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 3182713998 ps |
| CPU time | 137.93 seconds |
| Started | Jul 18 07:41:16 PM PDT 24 |
| Finished | Jul 18 07:43:34 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-123d5f4e-dcb5-4924-a91c-ca2ec7de0303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538022467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3538022467 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4197746839 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 158382540594 ps |
| CPU time | 2787.57 seconds |
| Started | Jul 18 07:41:15 PM PDT 24 |
| Finished | Jul 18 08:27:44 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1ec4b35c-ef1e-444a-a84a-c97cf61c51b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197746839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.4197746839 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3616989818 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 166958202 ps |
| CPU time | 19.02 seconds |
| Started | Jul 18 07:41:18 PM PDT 24 |
| Finished | Jul 18 07:41:38 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b58927c2-2781-4525-a044-4924d16e93e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616989818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3616989818 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2328880333 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1709938962 ps |
| CPU time | 59.04 seconds |
| Started | Jul 18 07:41:15 PM PDT 24 |
| Finished | Jul 18 07:42:14 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-5008dced-aafe-48c9-acc3-7318ed055cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328880333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2328880333 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.482173105 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 341049898 ps |
| CPU time | 30.34 seconds |
| Started | Jul 18 07:41:02 PM PDT 24 |
| Finished | Jul 18 07:41:33 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-17512154-03fc-4dbd-9530-01ae4d502b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482173105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.482173105 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1514786134 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 85300432029 ps |
| CPU time | 920.89 seconds |
| Started | Jul 18 07:41:15 PM PDT 24 |
| Finished | Jul 18 07:56:36 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-0f67f243-1eb5-46ba-aa4d-6e94f83e2fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514786134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1514786134 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1289715502 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 17266004932 ps |
| CPU time | 286.26 seconds |
| Started | Jul 18 07:41:15 PM PDT 24 |
| Finished | Jul 18 07:46:02 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-87f4099e-91d7-4021-b253-afc3b236a25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289715502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1289715502 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.3728763756 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 463421402 ps |
| CPU time | 44.58 seconds |
| Started | Jul 18 07:40:58 PM PDT 24 |
| Finished | Jul 18 07:41:43 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-9bcfad21-4960-4051-9385-419ed69a074f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728763756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.3728763756 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.2144457216 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 520357101 ps |
| CPU time | 35.76 seconds |
| Started | Jul 18 07:41:18 PM PDT 24 |
| Finished | Jul 18 07:41:54 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-d0370605-162f-4c06-b7c9-3763fac55d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144457216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.2144457216 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.1108898678 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 55485725 ps |
| CPU time | 7.26 seconds |
| Started | Jul 18 07:41:00 PM PDT 24 |
| Finished | Jul 18 07:41:08 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-56dfa1c7-1355-4374-887d-b528e4437f7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108898678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.1108898678 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.1032868523 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 8626109048 ps |
| CPU time | 90.93 seconds |
| Started | Jul 18 07:41:02 PM PDT 24 |
| Finished | Jul 18 07:42:33 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-890aa531-8deb-4a27-bc69-57238dfa8dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032868523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.1032868523 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1639102242 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 5865380434 ps |
| CPU time | 100.35 seconds |
| Started | Jul 18 07:41:48 PM PDT 24 |
| Finished | Jul 18 07:43:29 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7f2aff1b-ff02-4807-9bbc-b59adfadb1bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639102242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1639102242 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3447785592 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 47714473 ps |
| CPU time | 6.48 seconds |
| Started | Jul 18 07:40:59 PM PDT 24 |
| Finished | Jul 18 07:41:07 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-c19ce4ea-30d8-41af-bed7-030838c4e43a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447785592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3447785592 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3115865759 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 8914424055 ps |
| CPU time | 305.62 seconds |
| Started | Jul 18 07:41:15 PM PDT 24 |
| Finished | Jul 18 07:46:21 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-dc768a98-44cc-4cb7-b45e-ddd6bf60a29f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115865759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3115865759 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.2450570860 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 1292759427 ps |
| CPU time | 119.99 seconds |
| Started | Jul 18 07:41:41 PM PDT 24 |
| Finished | Jul 18 07:43:41 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-e7908c63-8f29-4040-9265-27a5d8184ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450570860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.2450570860 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1331351868 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 27495044362 ps |
| CPU time | 1205.63 seconds |
| Started | Jul 18 07:41:16 PM PDT 24 |
| Finished | Jul 18 08:01:22 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-20446f56-9824-4b58-a82d-9ffd321c2402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331351868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1331351868 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2755118194 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 371324377 ps |
| CPU time | 126.13 seconds |
| Started | Jul 18 07:41:39 PM PDT 24 |
| Finished | Jul 18 07:43:46 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d68fe431-7aed-4b6c-b6d9-ac50ca63222d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755118194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2755118194 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.1590130426 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 272958897 ps |
| CPU time | 37.54 seconds |
| Started | Jul 18 07:41:14 PM PDT 24 |
| Finished | Jul 18 07:41:52 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f3469a26-334b-4535-9c60-472bdd5506d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590130426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.1590130426 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1934004640 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 27679650540 ps |
| CPU time | 508.25 seconds |
| Started | Jul 18 07:49:15 PM PDT 24 |
| Finished | Jul 18 07:57:44 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-22e2ed89-282e-445e-ad04-c69dca0485c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934004640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.1934004640 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3345091268 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 354341711 ps |
| CPU time | 17.12 seconds |
| Started | Jul 18 07:49:33 PM PDT 24 |
| Finished | Jul 18 07:49:51 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-31767982-8461-4a29-8798-c43b980bf0fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345091268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3345091268 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2204233152 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 1295243238 ps |
| CPU time | 46.13 seconds |
| Started | Jul 18 07:49:12 PM PDT 24 |
| Finished | Jul 18 07:49:59 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-535fc205-89d1-44b4-90b0-bf3e96e708da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204233152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2204233152 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2352011353 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 380191151 ps |
| CPU time | 18.72 seconds |
| Started | Jul 18 07:49:20 PM PDT 24 |
| Finished | Jul 18 07:49:39 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-aea26e82-73fa-48e5-812c-4e2413e10fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352011353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2352011353 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.4145905718 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 49332235864 ps |
| CPU time | 887.19 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-cdd076cb-a4fa-4557-a881-dff330fb4385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145905718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.4145905718 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.2717835109 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 77293486 ps |
| CPU time | 9.6 seconds |
| Started | Jul 18 07:49:14 PM PDT 24 |
| Finished | Jul 18 07:49:25 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-ab512439-ef67-4a9b-a0c7-26e4b499e49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717835109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.2717835109 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.1755211820 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1697086584 ps |
| CPU time | 49.88 seconds |
| Started | Jul 18 07:49:12 PM PDT 24 |
| Finished | Jul 18 07:50:02 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-a7102109-8d2c-4d64-bd17-ed18a8be9764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755211820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1755211820 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2214719202 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 244285376 ps |
| CPU time | 10.49 seconds |
| Started | Jul 18 07:49:17 PM PDT 24 |
| Finished | Jul 18 07:49:29 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-27b028de-60c4-4904-8395-d74e683ddefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214719202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2214719202 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2284005455 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 9517564389 ps |
| CPU time | 103.16 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 07:50:57 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-a539a88c-34a1-4718-b2e0-8c0aae6d08f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284005455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2284005455 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.498578077 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 5294807850 ps |
| CPU time | 96.43 seconds |
| Started | Jul 18 07:49:13 PM PDT 24 |
| Finished | Jul 18 07:50:50 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-9c83b938-e8b1-48bd-a63c-6d74170035df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498578077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.498578077 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.2739678227 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 41507484 ps |
| CPU time | 6.19 seconds |
| Started | Jul 18 07:49:15 PM PDT 24 |
| Finished | Jul 18 07:49:22 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-92fdacdb-14ec-4be3-98b4-ff73d962b059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739678227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.2739678227 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.993302367 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 1512171489 ps |
| CPU time | 127.51 seconds |
| Started | Jul 18 07:49:35 PM PDT 24 |
| Finished | Jul 18 07:51:43 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-98844c5c-b67d-4d69-b931-fa13f6da9850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993302367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.993302367 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2858132433 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 12344943753 ps |
| CPU time | 475.27 seconds |
| Started | Jul 18 07:49:32 PM PDT 24 |
| Finished | Jul 18 07:57:28 PM PDT 24 |
| Peak memory | 576448 kb |
| Host | smart-0dd60f48-ee25-4578-8a3f-c4341817e003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858132433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2858132433 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1779803570 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 63665335 ps |
| CPU time | 17.29 seconds |
| Started | Jul 18 07:49:34 PM PDT 24 |
| Finished | Jul 18 07:49:52 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-c3e9300d-3cbe-46ee-924b-6990b447a177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779803570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.1779803570 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.259879811 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 64671674 ps |
| CPU time | 50.65 seconds |
| Started | Jul 18 07:49:35 PM PDT 24 |
| Finished | Jul 18 07:50:26 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-b446f66d-d99b-408f-9f2d-d38c0a78fbad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259879811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_reset_error.259879811 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2141475887 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 331933656 ps |
| CPU time | 16.48 seconds |
| Started | Jul 18 07:49:16 PM PDT 24 |
| Finished | Jul 18 07:49:33 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-1e83f44a-8ee3-45c2-b056-1b075f26d2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141475887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.2141475887 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.1724985918 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 4979167290 ps |
| CPU time | 410.52 seconds |
| Started | Jul 18 07:49:46 PM PDT 24 |
| Finished | Jul 18 07:56:38 PM PDT 24 |
| Peak memory | 599680 kb |
| Host | smart-a2354e1d-1072-472d-8bec-0280411a241c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724985918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.1724985918 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2215131758 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 167024996 ps |
| CPU time | 11.21 seconds |
| Started | Jul 18 07:49:45 PM PDT 24 |
| Finished | Jul 18 07:49:57 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-05341e70-145e-4495-b592-e83c8c112ceb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215131758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2215131758 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1859704256 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 43431902999 ps |
| CPU time | 764.4 seconds |
| Started | Jul 18 07:49:33 PM PDT 24 |
| Finished | Jul 18 08:02:18 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-7ec76d8c-a089-4946-9837-54c8502d5aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859704256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1859704256 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3707028294 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 166773375 ps |
| CPU time | 20.02 seconds |
| Started | Jul 18 07:49:50 PM PDT 24 |
| Finished | Jul 18 07:50:12 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-1c7b862b-fdf2-4e82-84c0-a183cc555b34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707028294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.3707028294 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.953761757 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 310974723 ps |
| CPU time | 28.02 seconds |
| Started | Jul 18 07:49:34 PM PDT 24 |
| Finished | Jul 18 07:50:03 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-83143b69-f8c6-446f-b4cd-8c682e5e0dfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953761757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.953761757 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2681110983 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 571612273 ps |
| CPU time | 21.64 seconds |
| Started | Jul 18 07:49:46 PM PDT 24 |
| Finished | Jul 18 07:50:09 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-dbfb12f1-6c49-45fa-b8b8-9a755e3ee7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681110983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2681110983 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.1985146584 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 43006638339 ps |
| CPU time | 483.11 seconds |
| Started | Jul 18 07:49:33 PM PDT 24 |
| Finished | Jul 18 07:57:37 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-126981ea-a260-4fdf-a650-a19e1a902e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985146584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.1985146584 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3531210238 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 7925038277 ps |
| CPU time | 142.83 seconds |
| Started | Jul 18 07:49:34 PM PDT 24 |
| Finished | Jul 18 07:51:57 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-c64089d0-9b91-43c7-bf2c-b810780f876d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531210238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3531210238 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3003036515 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 75233603 ps |
| CPU time | 9.35 seconds |
| Started | Jul 18 07:49:35 PM PDT 24 |
| Finished | Jul 18 07:49:46 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-68dce12d-fbaf-4ee7-a51d-9cfb8eba3600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003036515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3003036515 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.3701518376 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 430549245 ps |
| CPU time | 14.45 seconds |
| Started | Jul 18 07:49:33 PM PDT 24 |
| Finished | Jul 18 07:49:48 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-e6c314dc-a699-4197-a970-d5cb30bae879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701518376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3701518376 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.3633248981 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 213190922 ps |
| CPU time | 8.77 seconds |
| Started | Jul 18 07:49:46 PM PDT 24 |
| Finished | Jul 18 07:49:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-2658e43c-a71c-46c6-8824-6c21c96637db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633248981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.3633248981 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.999786400 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 8619638458 ps |
| CPU time | 90.83 seconds |
| Started | Jul 18 07:49:46 PM PDT 24 |
| Finished | Jul 18 07:51:18 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e41e1b63-1241-40ea-a7f9-ca04eb14e43a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999786400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.999786400 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1914227131 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 3664374486 ps |
| CPU time | 62.97 seconds |
| Started | Jul 18 07:49:46 PM PDT 24 |
| Finished | Jul 18 07:50:50 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-d998d886-ee88-480d-9d00-44891282267f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914227131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1914227131 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.285857573 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 49991267 ps |
| CPU time | 6.54 seconds |
| Started | Jul 18 07:49:37 PM PDT 24 |
| Finished | Jul 18 07:49:44 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-a19bf126-1c4e-458a-acfd-e7200a9aa598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285857573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delays .285857573 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.3549063850 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 66581284 ps |
| CPU time | 7.97 seconds |
| Started | Jul 18 07:49:54 PM PDT 24 |
| Finished | Jul 18 07:50:03 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-6d5cc166-070c-4c4d-abcd-f2918b95dc07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549063850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.3549063850 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1082083079 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 1472484276 ps |
| CPU time | 55.37 seconds |
| Started | Jul 18 07:49:51 PM PDT 24 |
| Finished | Jul 18 07:50:48 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-72c1fd77-5943-4493-ad90-dcfefca0afa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082083079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1082083079 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.203141766 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 10052335847 ps |
| CPU time | 541.21 seconds |
| Started | Jul 18 07:49:51 PM PDT 24 |
| Finished | Jul 18 07:58:54 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-0424094f-ee1e-479f-8caa-260023e0c48c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203141766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_ with_rand_reset.203141766 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2792803822 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6068211053 ps |
| CPU time | 381.98 seconds |
| Started | Jul 18 07:49:51 PM PDT 24 |
| Finished | Jul 18 07:56:15 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-ea3a8a07-87fb-4709-a7e0-c3014390011c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792803822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2792803822 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.824467933 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 1231568217 ps |
| CPU time | 51.91 seconds |
| Started | Jul 18 07:49:52 PM PDT 24 |
| Finished | Jul 18 07:50:45 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a2071234-c620-4e35-97c9-7f30fb208de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824467933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.824467933 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3582580832 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3629502284 ps |
| CPU time | 249.6 seconds |
| Started | Jul 18 07:49:52 PM PDT 24 |
| Finished | Jul 18 07:54:03 PM PDT 24 |
| Peak memory | 599684 kb |
| Host | smart-08e55da8-12fb-4049-8712-6eee4092cccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582580832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3582580832 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.1689371664 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 531471702 ps |
| CPU time | 24.41 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:50:42 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a2fa940c-6e27-4be0-bc16-0677aa901c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689371664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .1689371664 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.2468889136 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 23492192928 ps |
| CPU time | 409.24 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:57:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-9d2683aa-aa9e-48c3-889c-dd1810a04dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468889136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.2468889136 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.3645058551 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 316119951 ps |
| CPU time | 16.1 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:50:32 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-062893f4-1191-4427-9e3e-2bd38b574c3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645058551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.3645058551 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.298952359 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 2201651482 ps |
| CPU time | 85.36 seconds |
| Started | Jul 18 07:50:13 PM PDT 24 |
| Finished | Jul 18 07:51:40 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0b88b4dc-e314-41b0-87de-b9541ef0abed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298952359 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.298952359 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.2406582637 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2110597623 ps |
| CPU time | 80.19 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:51:37 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-71a47ab4-759c-4b6f-81a1-9d7abf1ba46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406582637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.2406582637 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.2466842237 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 64437111597 ps |
| CPU time | 704.45 seconds |
| Started | Jul 18 07:50:16 PM PDT 24 |
| Finished | Jul 18 08:02:03 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-78439c04-ea32-40c7-b5ff-37e54f5edb03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466842237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.2466842237 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.1407032679 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 10715363414 ps |
| CPU time | 181.76 seconds |
| Started | Jul 18 07:50:18 PM PDT 24 |
| Finished | Jul 18 07:53:22 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-f73350b7-957c-43fd-82e4-c78286a1a589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407032679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.1407032679 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.844812098 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 195032230 ps |
| CPU time | 20.44 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:50:38 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-07277281-01bc-483a-8e35-5e21f1d757f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844812098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_dela ys.844812098 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.1945207785 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 2141067382 ps |
| CPU time | 68.5 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:51:24 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-0b753faf-1570-4f7d-8e8a-3fc1393e84ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945207785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1945207785 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3407937005 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 48068057 ps |
| CPU time | 6.71 seconds |
| Started | Jul 18 07:49:51 PM PDT 24 |
| Finished | Jul 18 07:50:00 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-71fdaa30-edcf-47f2-a4fb-6c07cba255eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407937005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3407937005 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.769882159 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 7829688872 ps |
| CPU time | 87.6 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:51:44 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f387b3a0-0d44-48cc-83f3-e2a60d0f104d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769882159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.769882159 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.1276549542 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 5866842431 ps |
| CPU time | 108.85 seconds |
| Started | Jul 18 07:50:16 PM PDT 24 |
| Finished | Jul 18 07:52:07 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-225f014f-65de-415e-ad05-bfcf22b6bfab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276549542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.1276549542 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.2765711935 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 49399666 ps |
| CPU time | 6.58 seconds |
| Started | Jul 18 07:50:17 PM PDT 24 |
| Finished | Jul 18 07:50:26 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-cba714c7-424b-48b0-9f0f-df3528b16a5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765711935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.2765711935 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.2132045591 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 6451617366 ps |
| CPU time | 244.64 seconds |
| Started | Jul 18 07:50:16 PM PDT 24 |
| Finished | Jul 18 07:54:23 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f192b4e6-1aad-42e1-907a-696552baa83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132045591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.2132045591 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.2146409299 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 5042008681 ps |
| CPU time | 164.82 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:53:02 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-caae7dcc-1215-4ad4-bae5-ba3d5fde0db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146409299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.2146409299 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2153000882 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 938973100 ps |
| CPU time | 242.98 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:54:19 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-af633314-4872-4bd3-984c-8553223ef3ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153000882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.2153000882 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.2533975012 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1099591779 ps |
| CPU time | 43.65 seconds |
| Started | Jul 18 07:50:20 PM PDT 24 |
| Finished | Jul 18 07:51:05 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-9fb9dfe7-9d98-4f9a-aea6-37a04e409789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533975012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.2533975012 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.3530202508 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4507273300 ps |
| CPU time | 329.03 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:55:44 PM PDT 24 |
| Peak memory | 599644 kb |
| Host | smart-5025d1af-d6ea-4c0c-9a79-461001fb6a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530202508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.3530202508 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1508645607 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 3657445252 ps |
| CPU time | 161.9 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:52:58 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-e07c485d-769f-4c52-a999-589d5462c5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508645607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1508645607 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1450681662 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 3915575239 ps |
| CPU time | 73.86 seconds |
| Started | Jul 18 07:50:16 PM PDT 24 |
| Finished | Jul 18 07:51:33 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-adac4849-1a0b-4bbd-bdad-78f4180eecb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450681662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1450681662 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3635549226 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 761636017 ps |
| CPU time | 31.12 seconds |
| Started | Jul 18 07:50:43 PM PDT 24 |
| Finished | Jul 18 07:51:15 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-ebfc88bd-b792-421d-ae0b-2d086eb30546 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635549226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3635549226 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.223889766 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 982455570 ps |
| CPU time | 33.98 seconds |
| Started | Jul 18 07:50:18 PM PDT 24 |
| Finished | Jul 18 07:50:54 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-c122643c-e768-427f-a735-52fc98b2438b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223889766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.223889766 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.297897020 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 202968819 ps |
| CPU time | 10.78 seconds |
| Started | Jul 18 07:50:22 PM PDT 24 |
| Finished | Jul 18 07:50:33 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-63db6d31-8e23-4128-95e1-1981d5de9c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297897020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.297897020 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3049326485 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 41118217776 ps |
| CPU time | 457.05 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:57:52 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-46e27066-68d1-40b3-af82-46fbe5a0cb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049326485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3049326485 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1060925476 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 4506620200 ps |
| CPU time | 77.32 seconds |
| Started | Jul 18 07:50:22 PM PDT 24 |
| Finished | Jul 18 07:51:40 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-c6ad383b-33b1-4531-a0b2-0b7984ed4d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060925476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1060925476 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1437175041 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 514762021 ps |
| CPU time | 40.46 seconds |
| Started | Jul 18 07:50:18 PM PDT 24 |
| Finished | Jul 18 07:51:00 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-e46d34c8-bbc0-4137-a65d-f033a873ba4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437175041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1437175041 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.1650153811 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 596187856 ps |
| CPU time | 19.47 seconds |
| Started | Jul 18 07:50:15 PM PDT 24 |
| Finished | Jul 18 07:50:36 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-b86c8ea6-e180-4725-ad06-7b2a139bf809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650153811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.1650153811 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.2982941431 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 148007833 ps |
| CPU time | 7.66 seconds |
| Started | Jul 18 07:50:24 PM PDT 24 |
| Finished | Jul 18 07:50:32 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-7e5745e9-a454-405a-92c5-b173f6bb7816 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982941431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2982941431 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.1294226197 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 9109844812 ps |
| CPU time | 99.73 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:51:56 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-d3161ce3-7dae-4f10-9591-827c0c6c0fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294226197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.1294226197 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3859083961 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 5074507310 ps |
| CPU time | 94.27 seconds |
| Started | Jul 18 07:50:14 PM PDT 24 |
| Finished | Jul 18 07:51:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7c238813-a639-4fdf-88d4-45ee65da4538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859083961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3859083961 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.176286066 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 51689129 ps |
| CPU time | 6.23 seconds |
| Started | Jul 18 07:50:17 PM PDT 24 |
| Finished | Jul 18 07:50:25 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-65caef8e-83f2-43c9-b3ce-5359db5d65a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176286066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delays .176286066 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2936074238 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 996164063 ps |
| CPU time | 100.86 seconds |
| Started | Jul 18 07:50:41 PM PDT 24 |
| Finished | Jul 18 07:52:23 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-01f8e8bf-1ab0-49b4-99c3-d5c2f8cdd4c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936074238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2936074238 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.121850558 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 8444775138 ps |
| CPU time | 365.66 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:56:44 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-58320817-650e-4d90-8255-4383337d057a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121850558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_ with_rand_reset.121850558 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.495318313 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 392393137 ps |
| CPU time | 165.89 seconds |
| Started | Jul 18 07:50:40 PM PDT 24 |
| Finished | Jul 18 07:53:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d9f604ae-1520-4acf-8b0c-9a871b4cea4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495318313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_reset_error.495318313 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2875911069 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 296592827 ps |
| CPU time | 36.32 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:51:15 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-05fcf2c6-cf42-4fb0-b79c-e06ec8eb2a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875911069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2875911069 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.15105973 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 2836802762 ps |
| CPU time | 117.89 seconds |
| Started | Jul 18 07:50:40 PM PDT 24 |
| Finished | Jul 18 07:52:39 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-24720b6a-689f-4b9d-9074-b11a41019b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15105973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device.15105973 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.233629190 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 37184727453 ps |
| CPU time | 633.45 seconds |
| Started | Jul 18 07:50:30 PM PDT 24 |
| Finished | Jul 18 08:01:04 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-677592c5-f2b2-435b-a34a-49bd7b9e2f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233629190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_d evice_slow_rsp.233629190 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1200697018 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 239879826 ps |
| CPU time | 11.28 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 07:50:52 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-05017f74-d998-4938-bf8c-ac0d91f3544f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200697018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1200697018 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.1732294634 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 514036737 ps |
| CPU time | 40.67 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:51:20 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-81f8f132-031e-4ef4-8c80-07e5e803bd86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732294634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.1732294634 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.1088188498 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1909943509 ps |
| CPU time | 80.36 seconds |
| Started | Jul 18 07:50:41 PM PDT 24 |
| Finished | Jul 18 07:52:02 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-aaf34e3e-e7ec-4319-afd8-1a1db44e31e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088188498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1088188498 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3898703293 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 102647189320 ps |
| CPU time | 1224.23 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 08:11:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-8b3347d8-1ba2-4f2d-b7b3-3f7a329f9b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898703293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3898703293 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1986303898 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 46746730008 ps |
| CPU time | 794.07 seconds |
| Started | Jul 18 07:50:38 PM PDT 24 |
| Finished | Jul 18 08:03:54 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-ed1310af-ad29-4e26-9c66-0d2d9a8c5dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986303898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1986303898 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2042512008 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 382673532 ps |
| CPU time | 32.99 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 07:51:14 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-ba52f75c-b009-437a-af43-d55156717bdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042512008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2042512008 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3210133698 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 663452109 ps |
| CPU time | 20.38 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 07:51:01 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-4c390542-506e-4e20-aff5-a32602b7a8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210133698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3210133698 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1964852062 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 191436231 ps |
| CPU time | 9.08 seconds |
| Started | Jul 18 07:50:38 PM PDT 24 |
| Finished | Jul 18 07:50:49 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-d98b75e9-44ae-40d9-b86c-b390cb15442a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964852062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1964852062 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3380669368 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 9381388273 ps |
| CPU time | 109.9 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:52:29 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-eee79332-8225-4fe9-840d-25defd1dcf0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380669368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3380669368 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2860013483 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 4543330360 ps |
| CPU time | 78.15 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 07:51:59 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-9a7ab4d6-d946-472d-9234-c7fba6599a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860013483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2860013483 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.990766243 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 60013997 ps |
| CPU time | 6.94 seconds |
| Started | Jul 18 07:50:38 PM PDT 24 |
| Finished | Jul 18 07:50:46 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e8a54dc1-2592-4d80-bf77-96254451d758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990766243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delays .990766243 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.3999410256 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 7592826945 ps |
| CPU time | 285.48 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:55:25 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-caab9bb5-0a47-474c-8767-cb2497f4481a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999410256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.3999410256 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.1575778397 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 5070998127 ps |
| CPU time | 369.63 seconds |
| Started | Jul 18 07:50:41 PM PDT 24 |
| Finished | Jul 18 07:56:51 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-a156e2ca-0331-49aa-bb04-07b0445689f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575778397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.1575778397 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1783047891 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 11589461296 ps |
| CPU time | 645.26 seconds |
| Started | Jul 18 07:50:39 PM PDT 24 |
| Finished | Jul 18 08:01:26 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-9b09db3b-1995-4933-ab41-a3f218a12e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783047891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1783047891 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.227267888 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 237849809 ps |
| CPU time | 42 seconds |
| Started | Jul 18 07:50:41 PM PDT 24 |
| Finished | Jul 18 07:51:24 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-c6124f97-3f79-47b4-85b0-64cd1d46073a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227267888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.227267888 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1705787215 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 223923734 ps |
| CPU time | 31.91 seconds |
| Started | Jul 18 07:50:36 PM PDT 24 |
| Finished | Jul 18 07:51:10 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-ac20846c-5628-44e8-a427-754f197fe4a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705787215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1705787215 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2394971166 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 4376389176 ps |
| CPU time | 288.04 seconds |
| Started | Jul 18 07:50:40 PM PDT 24 |
| Finished | Jul 18 07:55:29 PM PDT 24 |
| Peak memory | 603748 kb |
| Host | smart-3baf572d-cb4b-4a3a-a2ff-9db4f4d2a42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394971166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2394971166 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.155181846 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 313834431 ps |
| CPU time | 23.58 seconds |
| Started | Jul 18 07:51:03 PM PDT 24 |
| Finished | Jul 18 07:51:27 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-26ab294a-11cf-4758-8d0c-ca1c9aee976f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155181846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 155181846 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2959372204 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 45999533942 ps |
| CPU time | 895.14 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 08:06:00 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-38672d98-146d-4179-adc4-42a170f11ff9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959372204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.2959372204 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.2089761947 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 64646791 ps |
| CPU time | 6.47 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:13 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-faf9f2e5-c07d-4136-bf08-359639886f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089761947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.2089761947 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.445128018 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 940313451 ps |
| CPU time | 32.57 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:39 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-7c72377e-c4ac-456b-91f8-511e560bb566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445128018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.445128018 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1177698137 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 1686692495 ps |
| CPU time | 58.55 seconds |
| Started | Jul 18 07:50:38 PM PDT 24 |
| Finished | Jul 18 07:51:39 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-e4a28f91-afc8-42ee-9dd8-22278c2755df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177698137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1177698137 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3864485770 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 37675044867 ps |
| CPU time | 442.38 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:58:28 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5e4caee2-0a85-449c-9beb-622ed01c9048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864485770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3864485770 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.405265313 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 48499663817 ps |
| CPU time | 779.34 seconds |
| Started | Jul 18 07:51:06 PM PDT 24 |
| Finished | Jul 18 08:04:07 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c8b32d70-90de-4d1b-9a7f-875a6da950ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405265313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.405265313 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1341996802 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 217773593 ps |
| CPU time | 23.94 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:51:03 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-fac5fff5-bf86-4541-82c0-e14e1334362f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341996802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1341996802 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.971915183 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 398904229 ps |
| CPU time | 31.67 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:37 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-96481086-b5fe-4ed9-abf4-c1e07e64c4d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971915183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.971915183 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.3977664195 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 158026915 ps |
| CPU time | 8.34 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:50:48 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-01b576f5-f56e-4ebd-924c-3ac029373a07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977664195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.3977664195 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1809771105 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 7724638404 ps |
| CPU time | 90.17 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:52:10 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-bdb90790-9e99-4f61-a53a-97c4e2b6b4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809771105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1809771105 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1733632199 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 4840368918 ps |
| CPU time | 82 seconds |
| Started | Jul 18 07:50:37 PM PDT 24 |
| Finished | Jul 18 07:52:01 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-3b8aaeb4-45e9-4363-9ab6-c489fa71194c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733632199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1733632199 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.4008704928 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 48675046 ps |
| CPU time | 7.03 seconds |
| Started | Jul 18 07:50:43 PM PDT 24 |
| Finished | Jul 18 07:50:51 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a1072577-3743-45e3-ab6f-ac3a88550895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008704928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.4008704928 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1558507535 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 3159746817 ps |
| CPU time | 230.92 seconds |
| Started | Jul 18 07:51:06 PM PDT 24 |
| Finished | Jul 18 07:54:58 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-423b1b8e-420b-4fa9-938f-26b9378ae175 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558507535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1558507535 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.13572786 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 756512058 ps |
| CPU time | 66.1 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:52:11 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-fe626067-12e0-4f2e-84ed-f3aeb53f85c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.13572786 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2353539132 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 7326142 ps |
| CPU time | 10.82 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:17 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-9523359e-fb1f-42b9-91a7-8e1c8b6b9b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353539132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2353539132 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.34901288 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 101707444 ps |
| CPU time | 13.99 seconds |
| Started | Jul 18 07:51:05 PM PDT 24 |
| Finished | Jul 18 07:51:20 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-257b1f18-7161-4c48-a675-abc82c0f1111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.34901288 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2392476052 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2886716294 ps |
| CPU time | 180.88 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:54:07 PM PDT 24 |
| Peak memory | 603052 kb |
| Host | smart-ff201c10-0a9c-4c00-a6a7-c5754d208c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392476052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2392476052 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.4163634609 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 748641278 ps |
| CPU time | 49.64 seconds |
| Started | Jul 18 07:51:03 PM PDT 24 |
| Finished | Jul 18 07:51:54 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1b6124fd-f216-48f0-ab34-899974dce585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163634609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .4163634609 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2949937294 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 43736290075 ps |
| CPU time | 743.52 seconds |
| Started | Jul 18 07:51:03 PM PDT 24 |
| Finished | Jul 18 08:03:28 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-e344891d-aebc-4cb6-8235-257dae549643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949937294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2949937294 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.142977890 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 663515300 ps |
| CPU time | 24.5 seconds |
| Started | Jul 18 07:51:20 PM PDT 24 |
| Finished | Jul 18 07:51:45 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c981a769-d4e1-4afa-9c4d-92728409503d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142977890 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_addr .142977890 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.4250236552 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 577918511 ps |
| CPU time | 43.62 seconds |
| Started | Jul 18 07:51:22 PM PDT 24 |
| Finished | Jul 18 07:52:06 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e62d0774-91d6-4b36-a5fa-804ca13b1c3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250236552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.4250236552 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.4154810670 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 1614864798 ps |
| CPU time | 57.96 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:52:04 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6838d747-b17c-4cad-87fc-2c1c8f84aaa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154810670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.4154810670 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3866666272 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 103493434904 ps |
| CPU time | 1074.53 seconds |
| Started | Jul 18 07:51:06 PM PDT 24 |
| Finished | Jul 18 08:09:02 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3d893a18-951f-4bba-a630-2a67dfee96a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866666272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3866666272 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.4008343311 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 62105839065 ps |
| CPU time | 1086.95 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 08:09:13 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-855fa3f4-4b94-4072-beb7-1467473ca13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008343311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.4008343311 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3418047506 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 58105201 ps |
| CPU time | 9.18 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:15 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-77f34951-7482-401b-8431-1a946d40224b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418047506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3418047506 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.530588274 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 1815440047 ps |
| CPU time | 52.7 seconds |
| Started | Jul 18 07:51:18 PM PDT 24 |
| Finished | Jul 18 07:52:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-32b74082-ee11-4158-8c46-763168ca8933 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530588274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.530588274 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1815367416 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 184388625 ps |
| CPU time | 9.35 seconds |
| Started | Jul 18 07:51:06 PM PDT 24 |
| Finished | Jul 18 07:51:17 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-4df59a45-bb2c-402c-b628-2776e524e31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815367416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1815367416 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1307589099 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 6907010787 ps |
| CPU time | 76.76 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:52:22 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-d97bdbb4-fff1-4bd5-8c0c-63af85e473a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307589099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1307589099 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3603669449 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 5491000215 ps |
| CPU time | 98.02 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:52:44 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-90e59b3a-1654-48b5-be35-74dd3463803a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603669449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3603669449 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3764347322 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 42019966 ps |
| CPU time | 6.44 seconds |
| Started | Jul 18 07:51:04 PM PDT 24 |
| Finished | Jul 18 07:51:12 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-37ce4b68-b0ad-419d-862a-51d58f2bf44f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764347322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3764347322 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3511366492 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 22313492453 ps |
| CPU time | 841.82 seconds |
| Started | Jul 18 07:51:18 PM PDT 24 |
| Finished | Jul 18 08:05:21 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-89e768b2-2169-47a9-9739-688807606032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511366492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3511366492 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3050424132 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 8428938031 ps |
| CPU time | 294.41 seconds |
| Started | Jul 18 07:51:22 PM PDT 24 |
| Finished | Jul 18 07:56:17 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-5d2d8f06-8c36-4cad-bae6-06ed2646b146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050424132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3050424132 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3357891713 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 115842165 ps |
| CPU time | 31.36 seconds |
| Started | Jul 18 07:51:17 PM PDT 24 |
| Finished | Jul 18 07:51:49 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-a9faafda-a342-48e5-bc70-19d31d9b9b13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357891713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.3357891713 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.1144941130 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 232064612 ps |
| CPU time | 26.25 seconds |
| Started | Jul 18 07:51:21 PM PDT 24 |
| Finished | Jul 18 07:51:48 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-594fe19d-26e0-49b3-ac48-0e4693a4c265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144941130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.1144941130 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.321645739 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 3154290740 ps |
| CPU time | 82.72 seconds |
| Started | Jul 18 07:51:24 PM PDT 24 |
| Finished | Jul 18 07:52:48 PM PDT 24 |
| Peak memory | 592944 kb |
| Host | smart-537f2b85-00dd-4619-bc7a-5972284a578a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321645739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.321645739 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.1568574078 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 1614516519 ps |
| CPU time | 72.85 seconds |
| Started | Jul 18 07:51:24 PM PDT 24 |
| Finished | Jul 18 07:52:38 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-ae0c7c1a-c4a2-4c49-b2c0-f3029975ff9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568574078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .1568574078 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2298634040 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 127320500859 ps |
| CPU time | 2287.71 seconds |
| Started | Jul 18 07:51:21 PM PDT 24 |
| Finished | Jul 18 08:29:29 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-c7bc5949-f965-446b-92f7-e068977e18ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298634040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2298634040 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.1298268236 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 39800767 ps |
| CPU time | 7.92 seconds |
| Started | Jul 18 07:51:22 PM PDT 24 |
| Finished | Jul 18 07:51:31 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-4d699543-68c1-47bf-8768-a7dd91fc385d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298268236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.1298268236 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3407851590 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 293275941 ps |
| CPU time | 26.57 seconds |
| Started | Jul 18 07:51:22 PM PDT 24 |
| Finished | Jul 18 07:51:49 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-8c345de4-3c92-4245-8bc3-d9155e996a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407851590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3407851590 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3211675482 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 1053474533 ps |
| CPU time | 39.2 seconds |
| Started | Jul 18 07:51:21 PM PDT 24 |
| Finished | Jul 18 07:52:01 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-e7522cc7-1fc5-4515-a54c-9b3c4dd7fbb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211675482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3211675482 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2304766608 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 28736631920 ps |
| CPU time | 338.04 seconds |
| Started | Jul 18 07:51:17 PM PDT 24 |
| Finished | Jul 18 07:56:56 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b431a3d0-827e-4335-b5a4-b2602e739a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304766608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2304766608 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.3384074439 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 58269837487 ps |
| CPU time | 1074.71 seconds |
| Started | Jul 18 07:51:20 PM PDT 24 |
| Finished | Jul 18 08:09:16 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-dae98872-ea55-4662-9adb-4e47270f2a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384074439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.3384074439 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3873073141 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 392651755 ps |
| CPU time | 38.76 seconds |
| Started | Jul 18 07:51:17 PM PDT 24 |
| Finished | Jul 18 07:51:57 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-708008aa-d4ed-48c0-ad67-6789f41bb6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873073141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.3873073141 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.172171230 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 2003966689 ps |
| CPU time | 62.39 seconds |
| Started | Jul 18 07:51:20 PM PDT 24 |
| Finished | Jul 18 07:52:23 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-b83df4fb-93ee-464d-8eb5-5406b600549d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172171230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.172171230 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.588333423 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 238860400 ps |
| CPU time | 11.03 seconds |
| Started | Jul 18 07:51:18 PM PDT 24 |
| Finished | Jul 18 07:51:30 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-144fa92c-1b41-4280-ad32-3e529d776e4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588333423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.588333423 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2545004245 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 8218371186 ps |
| CPU time | 98.24 seconds |
| Started | Jul 18 07:51:17 PM PDT 24 |
| Finished | Jul 18 07:52:56 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0b8048c3-653d-4461-b7fc-f13f6ab39b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545004245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2545004245 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.93425344 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 3805770175 ps |
| CPU time | 69.79 seconds |
| Started | Jul 18 07:51:20 PM PDT 24 |
| Finished | Jul 18 07:52:30 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-be6585b4-5faf-4c44-8063-fcd11f833663 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93425344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.93425344 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.333055904 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 53508098 ps |
| CPU time | 6.31 seconds |
| Started | Jul 18 07:51:24 PM PDT 24 |
| Finished | Jul 18 07:51:32 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-0f44b170-86ea-4727-aac7-60cec7b6b238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333055904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delays .333055904 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3963075801 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 11017705025 ps |
| CPU time | 437.66 seconds |
| Started | Jul 18 07:51:17 PM PDT 24 |
| Finished | Jul 18 07:58:36 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-2c332e51-2624-41ad-9628-ba9a406d1441 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963075801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3963075801 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.642987237 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 3156538176 ps |
| CPU time | 113.95 seconds |
| Started | Jul 18 07:51:19 PM PDT 24 |
| Finished | Jul 18 07:53:14 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-0d1a6125-88ae-42bc-8da7-eddd34e366e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642987237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.642987237 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.556254996 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 14840043840 ps |
| CPU time | 760.69 seconds |
| Started | Jul 18 07:51:19 PM PDT 24 |
| Finished | Jul 18 08:04:00 PM PDT 24 |
| Peak memory | 576992 kb |
| Host | smart-2e31a720-6ab1-4d6c-a7b7-af94c0be5601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556254996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_reset_error.556254996 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2897064186 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 382837741 ps |
| CPU time | 19.84 seconds |
| Started | Jul 18 07:51:20 PM PDT 24 |
| Finished | Jul 18 07:51:40 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-83f6f00e-4008-4310-af67-f8681128be4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897064186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2897064186 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2484218893 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 3378553760 ps |
| CPU time | 221.31 seconds |
| Started | Jul 18 07:51:37 PM PDT 24 |
| Finished | Jul 18 07:55:19 PM PDT 24 |
| Peak memory | 598772 kb |
| Host | smart-e9f2701d-da37-416d-a3cf-151d3c35e80c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484218893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2484218893 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.574704338 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 502535783 ps |
| CPU time | 55.23 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:52:31 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-3b4a064f-9222-4cca-a389-5ac1b32c8664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574704338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 574704338 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.4094716071 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 23859680424 ps |
| CPU time | 404.03 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:58:20 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-7bf4140f-ef9d-475e-a460-36b04b3eb9ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094716071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.4094716071 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2160110702 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 594995835 ps |
| CPU time | 25.85 seconds |
| Started | Jul 18 07:51:55 PM PDT 24 |
| Finished | Jul 18 07:52:22 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-75fbf761-ce4a-46c0-a9ea-b8017fefe1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160110702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2160110702 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2191535749 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 541145556 ps |
| CPU time | 46.6 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:52:23 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-e430be11-6c2d-41da-bd29-d7b9a510b080 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191535749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2191535749 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.406064157 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1936102528 ps |
| CPU time | 65.98 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:52:42 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-fb874127-c45e-4463-a4a9-78a95b2aeb0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406064157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.406064157 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3212592281 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 87780632653 ps |
| CPU time | 960.75 seconds |
| Started | Jul 18 07:51:36 PM PDT 24 |
| Finished | Jul 18 08:07:38 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-cee595cc-df9c-4713-bed7-e8e6c29b7fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212592281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3212592281 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.2435942564 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 59903202512 ps |
| CPU time | 1136.96 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 08:10:34 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-b3bfb513-2871-4254-b25a-c1d6a81bb44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435942564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.2435942564 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3498081764 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 577887911 ps |
| CPU time | 52.12 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:52:28 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b74ba69d-7151-4c0c-bf12-f7aeb2988b94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498081764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3498081764 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3876879879 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2240905483 ps |
| CPU time | 68.68 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:52:44 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a25aada3-2fc6-4a81-a670-42828bfa5fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876879879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3876879879 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.178309040 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 225412689 ps |
| CPU time | 10.61 seconds |
| Started | Jul 18 07:51:35 PM PDT 24 |
| Finished | Jul 18 07:51:46 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-fe20bf88-d23f-44e0-b96e-d3904da34185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178309040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.178309040 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.393300621 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 10074031089 ps |
| CPU time | 102.1 seconds |
| Started | Jul 18 07:51:38 PM PDT 24 |
| Finished | Jul 18 07:53:21 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-1af2fcd5-a4b9-4a80-a751-5dfb782788a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393300621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.393300621 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3118694367 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 4840180012 ps |
| CPU time | 80.76 seconds |
| Started | Jul 18 07:51:38 PM PDT 24 |
| Finished | Jul 18 07:53:00 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-80a91863-ac25-43af-aa11-5c993250ddd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118694367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3118694367 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3920642427 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 40450951 ps |
| CPU time | 5.94 seconds |
| Started | Jul 18 07:51:36 PM PDT 24 |
| Finished | Jul 18 07:51:43 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e6a5b1c1-7c3a-472d-9e90-c9907e0a5a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920642427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3920642427 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.1952102023 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3669986900 ps |
| CPU time | 336.47 seconds |
| Started | Jul 18 07:51:53 PM PDT 24 |
| Finished | Jul 18 07:57:30 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f34cb8a2-a604-4569-a950-de4dbb6c8200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952102023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.1952102023 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.322677332 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 2806450086 ps |
| CPU time | 255.03 seconds |
| Started | Jul 18 07:51:53 PM PDT 24 |
| Finished | Jul 18 07:56:09 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-13690654-279b-4425-8eea-0d5897a43179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322677332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.322677332 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.462649663 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 330634508 ps |
| CPU time | 157.76 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 07:54:30 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2b3a1a12-507e-41ae-bf55-36e430a4383a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462649663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_ with_rand_reset.462649663 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1924474738 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 4109570429 ps |
| CPU time | 411.08 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 07:58:44 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-76ce417c-c65b-452d-b559-cbf00b726672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924474738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1924474738 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.596773207 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 1093725253 ps |
| CPU time | 50.62 seconds |
| Started | Jul 18 07:51:36 PM PDT 24 |
| Finished | Jul 18 07:52:28 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-0ec1a2a4-2021-4f66-b6e3-c6272170b4e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596773207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.596773207 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.2667153342 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 2903970669 ps |
| CPU time | 181.44 seconds |
| Started | Jul 18 07:51:53 PM PDT 24 |
| Finished | Jul 18 07:54:56 PM PDT 24 |
| Peak memory | 598572 kb |
| Host | smart-00b16381-eb60-47d8-887a-ac7234757378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667153342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.2667153342 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2531408023 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 407345025 ps |
| CPU time | 36.97 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:52:31 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-9b5fa134-831e-4275-b192-7d948792e176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531408023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2531408023 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1448808122 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 104415961 ps |
| CPU time | 14.09 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 07:52:07 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-f261fd31-2386-4289-b400-209b59c48b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448808122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1448808122 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.2402999428 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 43984065 ps |
| CPU time | 6.04 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:52:01 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-405fdbad-ecf5-4e6d-bb45-ee4b55e29f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402999428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.2402999428 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.3373781021 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 1238298652 ps |
| CPU time | 43.53 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:52:38 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a4f7a400-8008-4044-8f61-0b852c491252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373781021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3373781021 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3416521781 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 102189504609 ps |
| CPU time | 1248.77 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 08:12:42 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-03a4f021-6c0e-4415-91ac-3f5b9807ab08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416521781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3416521781 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.678138560 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 39527981930 ps |
| CPU time | 708.77 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 08:03:42 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-39c167cd-7c2b-4f28-bbb0-0f263ed96732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678138560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.678138560 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2994411954 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 194160535 ps |
| CPU time | 22.25 seconds |
| Started | Jul 18 07:52:14 PM PDT 24 |
| Finished | Jul 18 07:52:37 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-cdd1b466-2bbe-46a6-bf1f-ee47daff813d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994411954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2994411954 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.638909918 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 954278836 ps |
| CPU time | 30.07 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:52:25 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-38f46090-0735-4980-97ac-32234ed77a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638909918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.638909918 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.705754966 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 43816482 ps |
| CPU time | 6.57 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:52:02 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-f563754f-d169-41e7-8dd3-820d14302d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705754966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.705754966 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.207076344 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 5860053422 ps |
| CPU time | 67.8 seconds |
| Started | Jul 18 07:51:54 PM PDT 24 |
| Finished | Jul 18 07:53:03 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-2a1774c6-999b-47a6-b693-069896f7877c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207076344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.207076344 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.962158584 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 5541524756 ps |
| CPU time | 104.34 seconds |
| Started | Jul 18 07:51:51 PM PDT 24 |
| Finished | Jul 18 07:53:37 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5ff3a390-db81-42f1-bb27-bd38f78906fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962158584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.962158584 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3994672126 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 55212633 ps |
| CPU time | 7.5 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 07:52:01 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a05af91e-027d-4298-9924-e1f3c39f8cd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994672126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3994672126 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.1288082286 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 8778584827 ps |
| CPU time | 331.97 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 07:57:42 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-c133516c-27c1-40c3-96a6-07686cc38ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288082286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.1288082286 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1145771780 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 7580085347 ps |
| CPU time | 228.75 seconds |
| Started | Jul 18 07:52:22 PM PDT 24 |
| Finished | Jul 18 07:56:12 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8714ad6d-1dcb-4b9e-a743-bf7b9355e071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145771780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1145771780 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1526991190 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 7797681559 ps |
| CPU time | 429.14 seconds |
| Started | Jul 18 07:52:12 PM PDT 24 |
| Finished | Jul 18 07:59:22 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-a030eda5-20e2-4a73-9a7e-653d26b2891c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526991190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1526991190 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2685748616 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 174660110 ps |
| CPU time | 60.23 seconds |
| Started | Jul 18 07:52:11 PM PDT 24 |
| Finished | Jul 18 07:53:12 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-693d361e-cbeb-4b37-81eb-4d3b30f74f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685748616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2685748616 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.808879216 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 123693840 ps |
| CPU time | 18.18 seconds |
| Started | Jul 18 07:51:52 PM PDT 24 |
| Finished | Jul 18 07:52:11 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b9c3c9d2-a60b-42dd-bd9e-fa0e8fe685dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808879216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.808879216 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3014330447 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 29533552912 ps |
| CPU time | 5447.8 seconds |
| Started | Jul 18 07:41:41 PM PDT 24 |
| Finished | Jul 18 09:12:30 PM PDT 24 |
| Peak memory | 593584 kb |
| Host | smart-70fc116c-ff18-4600-8819-171f27612c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014330447 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3014330447 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.940082394 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 3227865020 ps |
| CPU time | 301.35 seconds |
| Started | Jul 18 07:41:38 PM PDT 24 |
| Finished | Jul 18 07:46:40 PM PDT 24 |
| Peak memory | 593084 kb |
| Host | smart-7dc5e3b1-1245-48b4-a752-493282d6e61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940082394 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.940082394 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2466715928 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4111514961 ps |
| CPU time | 227.11 seconds |
| Started | Jul 18 07:42:18 PM PDT 24 |
| Finished | Jul 18 07:46:05 PM PDT 24 |
| Peak memory | 660340 kb |
| Host | smart-83fe61c0-22b6-455d-8416-c7c35b00a8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466715928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2466715928 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1196682912 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4982838700 ps |
| CPU time | 526.84 seconds |
| Started | Jul 18 07:42:17 PM PDT 24 |
| Finished | Jul 18 07:51:05 PM PDT 24 |
| Peak memory | 640728 kb |
| Host | smart-f6c6a6a5-a8dc-4426-ae61-cf84232a26b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196682912 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.1196682912 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1787667935 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 17102913731 ps |
| CPU time | 1795.88 seconds |
| Started | Jul 18 07:41:40 PM PDT 24 |
| Finished | Jul 18 08:11:37 PM PDT 24 |
| Peak memory | 593132 kb |
| Host | smart-be4f60c5-b25a-444c-9744-819c3dc5216e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787667935 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1787667935 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.53343216 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 231898152 ps |
| CPU time | 25.39 seconds |
| Started | Jul 18 07:41:56 PM PDT 24 |
| Finished | Jul 18 07:42:22 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-a97bfb64-5265-4994-b29b-43f68f4cba8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53343216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.53343216 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.3834430021 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 24240759492 ps |
| CPU time | 441.38 seconds |
| Started | Jul 18 07:41:55 PM PDT 24 |
| Finished | Jul 18 07:49:17 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-98d1ed13-3ae1-4328-bf18-1c191bdac7a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834430021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.3834430021 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.367580752 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 55486358 ps |
| CPU time | 8.67 seconds |
| Started | Jul 18 07:41:57 PM PDT 24 |
| Finished | Jul 18 07:42:07 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c1490845-9bfc-4adc-aef8-21950619e3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367580752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr. 367580752 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3928934103 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 414735575 ps |
| CPU time | 32.34 seconds |
| Started | Jul 18 07:42:03 PM PDT 24 |
| Finished | Jul 18 07:42:35 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c4661956-30e5-4830-a622-33a6fd34a3ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928934103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3928934103 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.878952906 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 131174453 ps |
| CPU time | 14.7 seconds |
| Started | Jul 18 07:41:58 PM PDT 24 |
| Finished | Jul 18 07:42:13 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-6d3631c0-09fa-4553-91d7-dbe868c02fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878952906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.878952906 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.2665277814 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 97583067478 ps |
| CPU time | 1136.45 seconds |
| Started | Jul 18 07:41:58 PM PDT 24 |
| Finished | Jul 18 08:00:56 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b3166a72-ea0c-47d6-a212-454f09620b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665277814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.2665277814 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.4273038658 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 22827398125 ps |
| CPU time | 405.45 seconds |
| Started | Jul 18 07:41:58 PM PDT 24 |
| Finished | Jul 18 07:48:44 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-63e2c77d-aed9-4c10-b034-e9c4dbe21163 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273038658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.4273038658 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.2202706787 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 380143510 ps |
| CPU time | 33.14 seconds |
| Started | Jul 18 07:41:56 PM PDT 24 |
| Finished | Jul 18 07:42:29 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-184cc8b4-c2b4-48ed-9fcc-b66dd9c74045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202706787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.2202706787 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.2238539570 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 401939999 ps |
| CPU time | 30.43 seconds |
| Started | Jul 18 07:41:57 PM PDT 24 |
| Finished | Jul 18 07:42:28 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-ef88ac2d-69d1-40fd-a950-d3eb402b56e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238539570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2238539570 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2710832548 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 212450154 ps |
| CPU time | 9.31 seconds |
| Started | Jul 18 07:41:42 PM PDT 24 |
| Finished | Jul 18 07:41:52 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-b3afdbba-96f4-4f45-b1e8-5bd2d6bb7274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710832548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2710832548 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.1434535608 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 6141232129 ps |
| CPU time | 68.14 seconds |
| Started | Jul 18 07:41:58 PM PDT 24 |
| Finished | Jul 18 07:43:06 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b0193153-0cca-4bfe-9c33-a49f33b45190 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434535608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.1434535608 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4004349534 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 6958654014 ps |
| CPU time | 118.45 seconds |
| Started | Jul 18 07:41:57 PM PDT 24 |
| Finished | Jul 18 07:43:56 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-8097f364-8c9c-4654-93d1-a414970a84ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004349534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4004349534 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.3894425709 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 48314749 ps |
| CPU time | 6.66 seconds |
| Started | Jul 18 07:42:00 PM PDT 24 |
| Finished | Jul 18 07:42:07 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5129fa41-d748-4ce8-9282-cd4611b077fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894425709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .3894425709 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.1077748741 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1313048761 ps |
| CPU time | 52.83 seconds |
| Started | Jul 18 07:41:58 PM PDT 24 |
| Finished | Jul 18 07:42:51 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-9de10d29-8dec-415f-b95a-5733837f37ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077748741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.1077748741 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.2605508650 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 4026057286 ps |
| CPU time | 154.51 seconds |
| Started | Jul 18 07:42:01 PM PDT 24 |
| Finished | Jul 18 07:44:36 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-3731d6d5-bb17-4184-a957-e0d5a8f42f41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605508650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.2605508650 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.792227818 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 3473006933 ps |
| CPU time | 274.72 seconds |
| Started | Jul 18 07:42:01 PM PDT 24 |
| Finished | Jul 18 07:46:36 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-7c929299-c159-435f-890e-3ce08d64d215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792227818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_rand_reset.792227818 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1216918447 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 11299762129 ps |
| CPU time | 530.3 seconds |
| Started | Jul 18 07:42:19 PM PDT 24 |
| Finished | Jul 18 07:51:10 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-71842b48-3428-4c9f-b5cc-6d2fca08a792 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216918447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.1216918447 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2685786629 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 449376345 ps |
| CPU time | 19 seconds |
| Started | Jul 18 07:41:57 PM PDT 24 |
| Finished | Jul 18 07:42:16 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-67959ca0-6d46-47eb-ae84-557740862da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685786629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2685786629 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2731756662 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 2275081306 ps |
| CPU time | 91.78 seconds |
| Started | Jul 18 07:52:23 PM PDT 24 |
| Finished | Jul 18 07:53:55 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-187d444c-4f12-4ed3-9eb7-1000e2ae39a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731756662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .2731756662 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.888373036 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 22514290260 ps |
| CPU time | 396.28 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 07:58:46 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-e356ec76-b60e-4376-96a4-ef44c1f50464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888373036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_d evice_slow_rsp.888373036 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.3406486829 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 245592015 ps |
| CPU time | 28.27 seconds |
| Started | Jul 18 07:52:10 PM PDT 24 |
| Finished | Jul 18 07:52:39 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-3cef89c7-b28a-4272-b208-87c772f00170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406486829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.3406486829 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.3329544357 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 2242988465 ps |
| CPU time | 75.28 seconds |
| Started | Jul 18 07:52:08 PM PDT 24 |
| Finished | Jul 18 07:53:24 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-0ef812a3-e4ce-4a61-b51d-81ebf267a9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329544357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.3329544357 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.242140587 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 1632213232 ps |
| CPU time | 58.26 seconds |
| Started | Jul 18 07:52:11 PM PDT 24 |
| Finished | Jul 18 07:53:10 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-83a9d74a-d2bc-4257-9663-da768f3a5d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242140587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.242140587 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.127265384 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 12113172224 ps |
| CPU time | 144.33 seconds |
| Started | Jul 18 07:52:10 PM PDT 24 |
| Finished | Jul 18 07:54:35 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-41a061e3-224a-478b-8f75-5acc754d3a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127265384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.127265384 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1896589914 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 15201623196 ps |
| CPU time | 248.86 seconds |
| Started | Jul 18 07:52:23 PM PDT 24 |
| Finished | Jul 18 07:56:33 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-c0963fef-4c68-4763-83c7-06e1fbda3dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896589914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1896589914 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.3443540663 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 89908315 ps |
| CPU time | 10.98 seconds |
| Started | Jul 18 07:52:10 PM PDT 24 |
| Finished | Jul 18 07:52:22 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-aed1188b-fbd4-4b78-aea5-0b528816ec7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443540663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.3443540663 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3458138913 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 549485621 ps |
| CPU time | 37.29 seconds |
| Started | Jul 18 07:52:22 PM PDT 24 |
| Finished | Jul 18 07:53:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-449cadb1-403b-406d-8544-633f5dda50cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458138913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3458138913 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.50999684 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 220585033 ps |
| CPU time | 9.66 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 07:52:20 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-d9d455a6-fb78-4197-8ed5-d1068f1fde89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50999684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.50999684 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.3389934270 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7801302221 ps |
| CPU time | 84.19 seconds |
| Started | Jul 18 07:52:21 PM PDT 24 |
| Finished | Jul 18 07:53:46 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-fb04296e-d1a4-4fc6-8f12-e3b3445c96e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389934270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.3389934270 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3614231747 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 5421626071 ps |
| CPU time | 96.63 seconds |
| Started | Jul 18 07:52:13 PM PDT 24 |
| Finished | Jul 18 07:53:50 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-6063498c-fe14-493c-8b66-6894ddb01ac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614231747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3614231747 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.3746375456 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 46745288 ps |
| CPU time | 6.59 seconds |
| Started | Jul 18 07:52:10 PM PDT 24 |
| Finished | Jul 18 07:52:17 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2b626b24-ee18-4965-b7ab-d950644661a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746375456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.3746375456 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3142748106 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 2680368631 ps |
| CPU time | 246.26 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 07:56:17 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-af3c3d0e-850c-40a2-88da-7f3da5251739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142748106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3142748106 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.4060532054 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 2701087969 ps |
| CPU time | 101.87 seconds |
| Started | Jul 18 07:52:22 PM PDT 24 |
| Finished | Jul 18 07:54:05 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-440323e8-a00d-48f5-8d30-eed45b025ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060532054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.4060532054 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.476468348 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 8663434568 ps |
| CPU time | 940.43 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 08:07:50 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-ef84fe83-4426-405d-b887-70db41103b18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476468348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_ with_rand_reset.476468348 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2521250920 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 1128731692 ps |
| CPU time | 209.21 seconds |
| Started | Jul 18 07:52:08 PM PDT 24 |
| Finished | Jul 18 07:55:37 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-e5b5bf7b-b3ec-45b2-af0e-dff1ec45f2d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521250920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2521250920 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.2110933855 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1234711858 ps |
| CPU time | 52.51 seconds |
| Started | Jul 18 07:52:11 PM PDT 24 |
| Finished | Jul 18 07:53:05 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-97c21fdb-947f-41a8-8af1-87f7c74e2194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110933855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.2110933855 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.2550352019 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 403654160 ps |
| CPU time | 22.78 seconds |
| Started | Jul 18 07:52:36 PM PDT 24 |
| Finished | Jul 18 07:52:59 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-78fbd841-c388-4213-a9a8-0600775faed8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550352019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .2550352019 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.1009266580 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 81588554496 ps |
| CPU time | 1545.18 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 08:18:19 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-8684d0e8-3e6f-474b-b168-38de9c075145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009266580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.1009266580 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3713145347 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 1168599815 ps |
| CPU time | 42.65 seconds |
| Started | Jul 18 07:52:38 PM PDT 24 |
| Finished | Jul 18 07:53:21 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-9568f522-fc68-46d6-b781-40a23472be20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713145347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3713145347 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.2845872882 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 650412700 ps |
| CPU time | 27.1 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:53:01 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-d77515d5-43a8-46bf-8ed6-a5f5c6df517b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845872882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2845872882 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.1859063265 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 516304217 ps |
| CPU time | 42.83 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:53:17 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-8a2af6fc-3dbf-46eb-840a-99af9b735dbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859063265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1859063265 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.2625870982 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 60655544150 ps |
| CPU time | 674.55 seconds |
| Started | Jul 18 07:52:36 PM PDT 24 |
| Finished | Jul 18 08:03:52 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-451358ec-e154-44d1-9fde-2100763b2817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625870982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.2625870982 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.333566544 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 51438383534 ps |
| CPU time | 891.75 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 08:07:26 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-182bbf8a-8f67-472d-b0dc-80bed5be0ed1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333566544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.333566544 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.1449111324 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 445414742 ps |
| CPU time | 41.94 seconds |
| Started | Jul 18 07:52:31 PM PDT 24 |
| Finished | Jul 18 07:53:14 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-d34b2958-a316-43f3-b9f4-dd2197b1c276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449111324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.1449111324 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.4118378614 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 1390059985 ps |
| CPU time | 44.32 seconds |
| Started | Jul 18 07:52:33 PM PDT 24 |
| Finished | Jul 18 07:53:18 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-70035ed4-cb78-4f79-853c-18290d7f0f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118378614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4118378614 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.1449018553 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 141320062 ps |
| CPU time | 8.04 seconds |
| Started | Jul 18 07:52:09 PM PDT 24 |
| Finished | Jul 18 07:52:18 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-9521481f-06a1-4174-a4a6-b8c10c43d9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449018553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.1449018553 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3736956673 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 6813885919 ps |
| CPU time | 81.7 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:53:55 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6090c955-72a2-4582-b756-f9d632f6842d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736956673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3736956673 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.542369891 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 5771996472 ps |
| CPU time | 100.77 seconds |
| Started | Jul 18 07:52:38 PM PDT 24 |
| Finished | Jul 18 07:54:19 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-fbf1d705-e953-452e-bba3-9d0474d34950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542369891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.542369891 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1105499004 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 50097873 ps |
| CPU time | 7.2 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:52:40 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-96f33f0e-1f77-424a-b604-0fcc9e6ff643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105499004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1105499004 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.350789644 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 4283684708 ps |
| CPU time | 400.77 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:59:14 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-8d74704c-c413-4830-99c0-2da32d3a94d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350789644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.350789644 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3613756170 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 9275847102 ps |
| CPU time | 360.11 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:58:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-77143ade-c7a4-4de3-8634-20a57c20bf6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613756170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3613756170 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.459977059 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 2786377804 ps |
| CPU time | 353.69 seconds |
| Started | Jul 18 07:52:35 PM PDT 24 |
| Finished | Jul 18 07:58:30 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-f6df1547-7dcf-4e63-9c26-66d0871e341e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459977059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.459977059 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.811982330 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 7138736501 ps |
| CPU time | 334.35 seconds |
| Started | Jul 18 07:52:33 PM PDT 24 |
| Finished | Jul 18 07:58:09 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-0332c37f-2c5e-4640-a3d8-744493cf12bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811982330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_reset_error.811982330 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.919418884 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 87301640 ps |
| CPU time | 12.09 seconds |
| Started | Jul 18 07:52:33 PM PDT 24 |
| Finished | Jul 18 07:52:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0634c0e5-14b5-4775-8bb8-350841d1058d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919418884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.919418884 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3319075667 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 1311249834 ps |
| CPU time | 54.04 seconds |
| Started | Jul 18 07:52:50 PM PDT 24 |
| Finished | Jul 18 07:53:45 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-1f9e7bff-5f37-47ee-9b73-1b0ae0ea942e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319075667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3319075667 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.415173742 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 28795341102 ps |
| CPU time | 506.67 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 08:01:21 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-a3781671-c08a-4bae-b3eb-5a1219122df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415173742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.415173742 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1352987068 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 202006271 ps |
| CPU time | 12.25 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:53:05 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e617c247-80ef-4745-96f2-8ddfa8888cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352987068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.1352987068 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.346911363 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 1683047544 ps |
| CPU time | 56.23 seconds |
| Started | Jul 18 07:52:50 PM PDT 24 |
| Finished | Jul 18 07:53:48 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-066f9652-f89e-459f-93cc-eb53915f0b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346911363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.346911363 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3994054149 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 420119192 ps |
| CPU time | 18.8 seconds |
| Started | Jul 18 07:52:36 PM PDT 24 |
| Finished | Jul 18 07:52:55 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-bc6e7fff-9756-40e0-9326-c7caece90508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994054149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3994054149 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2180874256 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 110288966915 ps |
| CPU time | 1333.73 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 08:15:04 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-6708a40c-44be-41bc-970c-10a7359d0d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180874256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2180874256 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2667305457 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 48981038080 ps |
| CPU time | 885.18 seconds |
| Started | Jul 18 07:52:50 PM PDT 24 |
| Finished | Jul 18 08:07:37 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-a627bbea-9cd7-4042-a9b1-ac760ea2064a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667305457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.2667305457 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.318108106 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 120317672 ps |
| CPU time | 12.09 seconds |
| Started | Jul 18 07:52:34 PM PDT 24 |
| Finished | Jul 18 07:52:47 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-e3f4b6fd-7d3f-40ba-a03e-6ddf2e6f0b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318108106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.318108106 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3816348253 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 2003887935 ps |
| CPU time | 57.86 seconds |
| Started | Jul 18 07:52:50 PM PDT 24 |
| Finished | Jul 18 07:53:49 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-9a2116d1-fc68-40b1-8da5-4f5d13aee7cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816348253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3816348253 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2865499363 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 43606181 ps |
| CPU time | 6.2 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:52:40 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-8782584f-8587-4020-af43-cb9d2bdf90d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865499363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2865499363 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.691765381 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 5629391286 ps |
| CPU time | 60.09 seconds |
| Started | Jul 18 07:52:34 PM PDT 24 |
| Finished | Jul 18 07:53:35 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-51025485-a7bd-480c-8f55-aefc7e56f7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691765381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.691765381 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.1678218259 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 3849379969 ps |
| CPU time | 67.02 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:53:41 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-891cf766-6421-4ab4-b3be-038bd7b9c16f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678218259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.1678218259 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.2690699366 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 50973730 ps |
| CPU time | 6.24 seconds |
| Started | Jul 18 07:52:32 PM PDT 24 |
| Finished | Jul 18 07:52:39 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-7953b5a6-f678-4fdc-bae1-5372a4209cde |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690699366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.2690699366 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.560868965 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 6417136297 ps |
| CPU time | 196.26 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:56:09 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-5a0845ee-1402-42ea-afe7-3f1eaae7f322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560868965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.560868965 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.2369655960 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 7682652054 ps |
| CPU time | 254.29 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:57:07 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-27ee3cd3-a781-4ba7-a56b-a767cf3cdcde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369655960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.2369655960 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.539741360 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 11311866430 ps |
| CPU time | 598.62 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 08:02:53 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-cd102c9f-df9a-430d-af51-b00a16fbb0c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539741360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.539741360 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3141863096 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 14525510300 ps |
| CPU time | 661.32 seconds |
| Started | Jul 18 07:52:52 PM PDT 24 |
| Finished | Jul 18 08:03:55 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-eab42cab-5a3b-473f-8327-817bde4c6f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141863096 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3141863096 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1770476003 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 742577588 ps |
| CPU time | 33.6 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:53:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e750de78-cc7c-45c6-8d85-32a1a67c1b39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770476003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1770476003 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2323155430 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 272805280 ps |
| CPU time | 20.36 seconds |
| Started | Jul 18 07:52:55 PM PDT 24 |
| Finished | Jul 18 07:53:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-70a5ce3a-c156-4f71-8b0e-d3bd3ac0af8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323155430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2323155430 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1273818193 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 26713463801 ps |
| CPU time | 494.81 seconds |
| Started | Jul 18 07:52:54 PM PDT 24 |
| Finished | Jul 18 08:01:10 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-dcc4afe5-5b0f-4d0e-a48d-268fac0f414a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273818193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1273818193 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1491444652 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 314417984 ps |
| CPU time | 31.58 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 07:53:22 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f50d6b7d-f92d-4c2c-810e-9847e383226f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491444652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1491444652 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3588920545 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 460925449 ps |
| CPU time | 32.75 seconds |
| Started | Jul 18 07:52:52 PM PDT 24 |
| Finished | Jul 18 07:53:26 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-f8861f1f-bc39-4939-b7ea-a7088b5d958f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588920545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3588920545 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1813245458 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 464009783 ps |
| CPU time | 37.78 seconds |
| Started | Jul 18 07:52:52 PM PDT 24 |
| Finished | Jul 18 07:53:31 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-92284f94-ec1c-45da-99c3-3181e904569f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813245458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1813245458 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.429043667 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 4880583688 ps |
| CPU time | 56.06 seconds |
| Started | Jul 18 07:52:54 PM PDT 24 |
| Finished | Jul 18 07:53:51 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-bebaea1a-a7a5-4e7c-a094-acb38d8b5c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429043667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.429043667 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.1733220362 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 6234155763 ps |
| CPU time | 115.22 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 07:54:49 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-27d75d35-563f-4f45-9138-d6db43f2fede |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733220362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.1733220362 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2764968375 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 140443406 ps |
| CPU time | 15.07 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 07:53:06 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-62d6bbab-bd75-4914-a694-87e76acf7972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764968375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2764968375 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3276244907 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 219092393 ps |
| CPU time | 18.37 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:53:11 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-30fcb6d1-f816-4e1e-b426-cb916c7920fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276244907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3276244907 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2594632403 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 41682284 ps |
| CPU time | 6.07 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 07:53:00 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-65c09761-500a-4ce8-8634-679ab5f3aeda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594632403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2594632403 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2771209532 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 7686100303 ps |
| CPU time | 85.65 seconds |
| Started | Jul 18 07:52:50 PM PDT 24 |
| Finished | Jul 18 07:54:18 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c10e09e8-6811-4454-afc1-14d75ab4af33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771209532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2771209532 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3426311611 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 5029184353 ps |
| CPU time | 91.08 seconds |
| Started | Jul 18 07:52:55 PM PDT 24 |
| Finished | Jul 18 07:54:27 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-f436e516-234a-4dfa-bb04-228db63ad762 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426311611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3426311611 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.236121373 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 35523121 ps |
| CPU time | 5.26 seconds |
| Started | Jul 18 07:52:52 PM PDT 24 |
| Finished | Jul 18 07:52:59 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d81ddb83-bd04-4626-a9f5-e72cbf6f6e73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236121373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delays .236121373 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2786559319 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 3285874991 ps |
| CPU time | 292.81 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 07:57:43 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-9d7e4bc6-e46c-410e-b032-9e6dd31b6250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786559319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2786559319 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.76401877 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 982135515 ps |
| CPU time | 115.74 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 07:54:50 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d2e9f2b2-e4f5-4864-a497-b05b7115d366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76401877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_w ith_rand_reset.76401877 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3197584419 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 4890539862 ps |
| CPU time | 485.88 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 08:00:57 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-6ae44d6f-bba4-4c90-a8df-752b907f04c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197584419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3197584419 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.2426553016 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 946272573 ps |
| CPU time | 40.06 seconds |
| Started | Jul 18 07:52:53 PM PDT 24 |
| Finished | Jul 18 07:53:34 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-8bc05749-9fda-487f-ae77-6dabfe476800 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426553016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.2426553016 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3231689798 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 101972646 ps |
| CPU time | 9.24 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:53:17 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-25c41a7f-5549-4be4-a76e-e141a856d2d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231689798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3231689798 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.535455784 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 105855342276 ps |
| CPU time | 1979.1 seconds |
| Started | Jul 18 07:53:08 PM PDT 24 |
| Finished | Jul 18 08:26:09 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-e052e8a8-ef5a-4d3a-a67b-240db97ed6eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535455784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.535455784 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1626684525 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 1098076777 ps |
| CPU time | 39.02 seconds |
| Started | Jul 18 07:53:10 PM PDT 24 |
| Finished | Jul 18 07:53:50 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-80ab3692-9e79-4ca4-a2ae-119dc0c7d2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626684525 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1626684525 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3067927666 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 141677771 ps |
| CPU time | 12.41 seconds |
| Started | Jul 18 07:53:08 PM PDT 24 |
| Finished | Jul 18 07:53:21 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-6593fab4-31e6-4467-97db-f52140acdff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067927666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3067927666 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2490636449 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 2410317781 ps |
| CPU time | 89.85 seconds |
| Started | Jul 18 07:53:10 PM PDT 24 |
| Finished | Jul 18 07:54:41 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-550d515c-f198-4a7e-b338-e61263b332b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490636449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2490636449 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1145693103 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 18982835129 ps |
| CPU time | 202.1 seconds |
| Started | Jul 18 07:53:10 PM PDT 24 |
| Finished | Jul 18 07:56:33 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-fab810b8-0516-4220-b69d-fa62cd55d86e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145693103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1145693103 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3296655759 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 42293508416 ps |
| CPU time | 741.74 seconds |
| Started | Jul 18 07:53:08 PM PDT 24 |
| Finished | Jul 18 08:05:31 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-24caace3-4bbf-4bc2-8622-b426355f2652 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296655759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3296655759 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.3412108815 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 502958035 ps |
| CPU time | 41.24 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:53:50 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-44ce4757-e9c7-477f-a01b-02398a8e76be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412108815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.3412108815 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1533263391 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 1078912747 ps |
| CPU time | 36.5 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:53:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5a74d7f7-c313-4dbf-9e52-5be2d420537e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533263391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1533263391 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.2966997084 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 39946151 ps |
| CPU time | 5.78 seconds |
| Started | Jul 18 07:52:51 PM PDT 24 |
| Finished | Jul 18 07:52:59 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-ae33d674-55ce-47ce-841a-1c7291fdb02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966997084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.2966997084 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.970764881 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 5561634525 ps |
| CPU time | 60.59 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 07:53:51 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-a35e61de-f683-4c84-a905-170db7962612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970764881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.970764881 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2092574131 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 5494003658 ps |
| CPU time | 92.27 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:54:41 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a5cea82e-97f0-4955-85b5-8e1f11c4c045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092574131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2092574131 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1863695685 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 54524540 ps |
| CPU time | 6.76 seconds |
| Started | Jul 18 07:52:49 PM PDT 24 |
| Finished | Jul 18 07:52:56 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-a8768d46-cfb2-4f42-9ff7-3ca882619076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863695685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1863695685 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1569979084 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 916378772 ps |
| CPU time | 79.4 seconds |
| Started | Jul 18 07:53:11 PM PDT 24 |
| Finished | Jul 18 07:54:32 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2699a9b7-8105-479a-a3b4-4157175fd516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569979084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1569979084 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.3305339717 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 1549210119 ps |
| CPU time | 97.03 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:54:45 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-2e30124a-0a74-4660-869b-de12f6a780fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305339717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.3305339717 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4055612452 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 101426376 ps |
| CPU time | 82.55 seconds |
| Started | Jul 18 07:53:07 PM PDT 24 |
| Finished | Jul 18 07:54:31 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-48869fd2-0813-4bfa-a971-37c2b624aa79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055612452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.4055612452 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.822871657 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 690650523 ps |
| CPU time | 29.51 seconds |
| Started | Jul 18 07:53:12 PM PDT 24 |
| Finished | Jul 18 07:53:42 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-da639842-4f18-492d-a465-d335d1a6180b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822871657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.822871657 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3227780019 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 908956871 ps |
| CPU time | 74.71 seconds |
| Started | Jul 18 07:53:28 PM PDT 24 |
| Finished | Jul 18 07:54:45 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-66390e61-bc3c-4d1b-844a-4c68a715bb6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227780019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3227780019 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.300809068 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 48981973185 ps |
| CPU time | 821.88 seconds |
| Started | Jul 18 07:53:25 PM PDT 24 |
| Finished | Jul 18 08:07:08 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-beb50169-615a-4905-a2ae-c0a10cd44784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300809068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.300809068 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2888883835 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 272796295 ps |
| CPU time | 31.82 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 07:54:00 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-7c46d03f-054d-49cc-87e2-50b03c5974d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888883835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.2888883835 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2022114871 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 1036508820 ps |
| CPU time | 33.28 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 07:54:01 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-eb72ec58-7078-43b6-aefd-2f6e6b72ab54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022114871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2022114871 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.275595815 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 1964726431 ps |
| CPU time | 74.92 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 07:54:43 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-4511bf41-b445-4531-975d-a97d14562041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275595815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.275595815 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.83482926 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 66855162732 ps |
| CPU time | 730.63 seconds |
| Started | Jul 18 07:53:25 PM PDT 24 |
| Finished | Jul 18 08:05:37 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-5604ea03-424b-4ec3-9d2a-acf8de1551e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83482926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.83482926 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.440548612 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 45763873493 ps |
| CPU time | 796.44 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 08:06:46 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-78ec8c30-13e1-4b98-83de-6ddb2b40537f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440548612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.440548612 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.1501957774 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 262386443 ps |
| CPU time | 23.55 seconds |
| Started | Jul 18 07:53:30 PM PDT 24 |
| Finished | Jul 18 07:53:56 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ce8d3ab2-b933-4e80-a96b-f2008d5c14ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501957774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.1501957774 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.3156042938 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 898205030 ps |
| CPU time | 29.58 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 07:53:58 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-76e26baf-d4e9-4fa9-b797-d9196c5c023c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156042938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.3156042938 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2694101565 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 42734889 ps |
| CPU time | 6.37 seconds |
| Started | Jul 18 07:53:12 PM PDT 24 |
| Finished | Jul 18 07:53:20 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-04ed3614-a81e-4651-8597-1e011485b8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694101565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2694101565 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1123606021 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 7878440529 ps |
| CPU time | 93.09 seconds |
| Started | Jul 18 07:53:09 PM PDT 24 |
| Finished | Jul 18 07:54:43 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d893dc99-2be4-4d83-a4ef-e64404806d3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123606021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1123606021 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2336615325 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 4293172126 ps |
| CPU time | 81.99 seconds |
| Started | Jul 18 07:53:26 PM PDT 24 |
| Finished | Jul 18 07:54:50 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-bc29b156-806c-4e80-bdb1-b2a328574665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336615325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2336615325 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.1229532765 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 44982865 ps |
| CPU time | 7.11 seconds |
| Started | Jul 18 07:53:08 PM PDT 24 |
| Finished | Jul 18 07:53:16 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1dace53e-8669-4260-ab6b-229dc7bb2bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229532765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.1229532765 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1555805929 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 3691051907 ps |
| CPU time | 138 seconds |
| Started | Jul 18 07:53:25 PM PDT 24 |
| Finished | Jul 18 07:55:44 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-fbd22700-d7a7-4200-8045-6dba0cf4cce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555805929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1555805929 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2120199142 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 3925730512 ps |
| CPU time | 121.87 seconds |
| Started | Jul 18 07:53:26 PM PDT 24 |
| Finished | Jul 18 07:55:29 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-fd11779c-5cb4-4c50-8a71-c1f55ce4f690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120199142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2120199142 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.895743838 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 120665436 ps |
| CPU time | 37.29 seconds |
| Started | Jul 18 07:53:26 PM PDT 24 |
| Finished | Jul 18 07:54:05 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-261cdec1-5a17-4cba-8fc4-4c758584ba5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895743838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.895743838 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3581880671 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 18373625 ps |
| CPU time | 25.3 seconds |
| Started | Jul 18 07:53:26 PM PDT 24 |
| Finished | Jul 18 07:53:53 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-f4df1099-8bbe-4328-a6f9-ad4fa60aba9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581880671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3581880671 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.2026539234 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 326864721 ps |
| CPU time | 43.57 seconds |
| Started | Jul 18 07:53:27 PM PDT 24 |
| Finished | Jul 18 07:54:11 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-a6247c56-57d3-4e0d-b5e3-52e0d9cdd2a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026539234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.2026539234 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1141562268 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 3216018264 ps |
| CPU time | 130.94 seconds |
| Started | Jul 18 07:53:51 PM PDT 24 |
| Finished | Jul 18 07:56:03 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-2bea2489-62f5-4132-8ce4-8d86309f1bce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141562268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .1141562268 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2256648792 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 42655801080 ps |
| CPU time | 742.79 seconds |
| Started | Jul 18 07:53:45 PM PDT 24 |
| Finished | Jul 18 08:06:09 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7b815ba8-deec-4701-9ab4-68074e1e7442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256648792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2256648792 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2973652219 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 295076286 ps |
| CPU time | 34.57 seconds |
| Started | Jul 18 07:53:49 PM PDT 24 |
| Finished | Jul 18 07:54:25 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-5fa15a71-e1f0-4635-994c-776bdc06284a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973652219 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.2973652219 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.180370930 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 1050641994 ps |
| CPU time | 34.69 seconds |
| Started | Jul 18 07:53:46 PM PDT 24 |
| Finished | Jul 18 07:54:21 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a888604d-623b-4c26-8fd0-19113818cc4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180370930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.180370930 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.405465459 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 135701504 ps |
| CPU time | 14.47 seconds |
| Started | Jul 18 07:53:28 PM PDT 24 |
| Finished | Jul 18 07:53:44 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d2def30d-abc3-4bb7-a68a-41c61f29eeaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405465459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.405465459 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2631486076 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 6604504271 ps |
| CPU time | 73.67 seconds |
| Started | Jul 18 07:53:45 PM PDT 24 |
| Finished | Jul 18 07:55:00 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-d82776f8-2980-4658-9f65-3aa08516a366 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631486076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2631486076 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.4294398150 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 54756834443 ps |
| CPU time | 1043.05 seconds |
| Started | Jul 18 07:53:46 PM PDT 24 |
| Finished | Jul 18 08:11:10 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0ac787f9-3aea-4cfd-a4bc-88f57d41c4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294398150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.4294398150 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.1292628514 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 114863312 ps |
| CPU time | 11.89 seconds |
| Started | Jul 18 07:53:28 PM PDT 24 |
| Finished | Jul 18 07:53:42 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-c63581be-37ba-4971-b6b0-28b809470dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292628514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.1292628514 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.2382400316 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 205098935 ps |
| CPU time | 16.76 seconds |
| Started | Jul 18 07:53:46 PM PDT 24 |
| Finished | Jul 18 07:54:04 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-172a1f52-1f80-40e5-9666-caa2552f8a04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382400316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2382400316 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.1926885645 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 37158321 ps |
| CPU time | 5.9 seconds |
| Started | Jul 18 07:53:29 PM PDT 24 |
| Finished | Jul 18 07:53:37 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-a61b5ceb-fe7a-4761-9114-24aa95b022c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926885645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.1926885645 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3953709555 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 4533785887 ps |
| CPU time | 52.39 seconds |
| Started | Jul 18 07:53:25 PM PDT 24 |
| Finished | Jul 18 07:54:18 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-e0e9d3b2-1a3e-40f8-945e-030d75e9633b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953709555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3953709555 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.342773192 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 3579030527 ps |
| CPU time | 63.51 seconds |
| Started | Jul 18 07:53:31 PM PDT 24 |
| Finished | Jul 18 07:54:36 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-75bc51b7-225e-4a0c-a8a9-35c4a4000f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342773192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.342773192 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.4065853150 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 45408188 ps |
| CPU time | 6.13 seconds |
| Started | Jul 18 07:53:30 PM PDT 24 |
| Finished | Jul 18 07:53:38 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-7a585131-3263-4d99-aee1-9b319a20f09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065853150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.4065853150 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3830211938 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 7475938452 ps |
| CPU time | 254.14 seconds |
| Started | Jul 18 07:53:50 PM PDT 24 |
| Finished | Jul 18 07:58:05 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-f0f8ebe0-0ee1-4d72-af14-4edc5ea1079e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830211938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3830211938 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.485208107 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 10211529113 ps |
| CPU time | 333.2 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:59:18 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-0ffb9060-4b17-4489-8aa5-e55a1333e81e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485208107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.485208107 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.847906761 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 7871353728 ps |
| CPU time | 440.9 seconds |
| Started | Jul 18 07:53:51 PM PDT 24 |
| Finished | Jul 18 08:01:13 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-2a05588f-96ad-45f9-8a57-7f970d0fd2ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847906761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.847906761 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.2786957348 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 571103807 ps |
| CPU time | 192.76 seconds |
| Started | Jul 18 07:53:48 PM PDT 24 |
| Finished | Jul 18 07:57:02 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-2cb7cf48-afc8-40fc-b0ac-513328b5c0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786957348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.2786957348 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.755505799 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 1328267236 ps |
| CPU time | 54.71 seconds |
| Started | Jul 18 07:53:43 PM PDT 24 |
| Finished | Jul 18 07:54:39 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-b12f2a22-d3ac-401e-a34d-4aed5927e470 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755505799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.755505799 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.4109460989 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 39749464 ps |
| CPU time | 11.98 seconds |
| Started | Jul 18 07:53:50 PM PDT 24 |
| Finished | Jul 18 07:54:03 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d0bf1868-5647-49fe-b7c7-d0ed31754669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109460989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .4109460989 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.439251383 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 4152046196 ps |
| CPU time | 76.39 seconds |
| Started | Jul 18 07:53:46 PM PDT 24 |
| Finished | Jul 18 07:55:03 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-4b5c21a4-df14-40da-8d3c-180ec85c0782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439251383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.439251383 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.758115584 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 1018969426 ps |
| CPU time | 38.47 seconds |
| Started | Jul 18 07:53:51 PM PDT 24 |
| Finished | Jul 18 07:54:30 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-96030563-7165-4758-be63-6eaea77bfaec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758115584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_addr .758115584 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.3956741823 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 406290535 ps |
| CPU time | 35.86 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:54:21 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-68efd097-7b05-46d0-bde3-2c33e181c2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956741823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.3956741823 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.4123222490 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 807286964 ps |
| CPU time | 32.72 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:54:17 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-d339ce10-6e95-4e7a-aebe-ecead13498e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123222490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.4123222490 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4165405360 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 88107100105 ps |
| CPU time | 1045.63 seconds |
| Started | Jul 18 07:53:47 PM PDT 24 |
| Finished | Jul 18 08:11:14 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-fc046c6f-1d3a-41b3-8ce1-82c3e237c085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165405360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4165405360 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3071161715 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 22351944145 ps |
| CPU time | 341.32 seconds |
| Started | Jul 18 07:53:47 PM PDT 24 |
| Finished | Jul 18 07:59:29 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-50b673a7-764e-4516-aebb-3c4f7486b261 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071161715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3071161715 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.2270007163 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 121587392 ps |
| CPU time | 13.13 seconds |
| Started | Jul 18 07:53:49 PM PDT 24 |
| Finished | Jul 18 07:54:03 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-5f6377ae-e097-46cd-9599-cc4b56774f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270007163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.2270007163 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.1110472562 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1317050916 ps |
| CPU time | 41.46 seconds |
| Started | Jul 18 07:53:45 PM PDT 24 |
| Finished | Jul 18 07:54:28 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-2823e32a-7855-4fc1-9cb0-3435aebc448a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110472562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.1110472562 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.3016831478 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 50526889 ps |
| CPU time | 6.73 seconds |
| Started | Jul 18 07:53:45 PM PDT 24 |
| Finished | Jul 18 07:53:53 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-0d7f08ea-8c98-4937-a20f-4af584c64300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016831478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3016831478 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3664993675 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 8154269647 ps |
| CPU time | 83.89 seconds |
| Started | Jul 18 07:53:47 PM PDT 24 |
| Finished | Jul 18 07:55:11 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-18030b42-d076-4dfd-8368-844dedb4aef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664993675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3664993675 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2608269191 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 5263345926 ps |
| CPU time | 87.55 seconds |
| Started | Jul 18 07:53:46 PM PDT 24 |
| Finished | Jul 18 07:55:14 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-444323b4-1f87-41d9-9431-2a40f647b9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608269191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2608269191 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3033579413 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 49657039 ps |
| CPU time | 6.27 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:53:51 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-8ffa151c-7a62-41a8-92cf-deaff11b3240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033579413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.3033579413 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.916027404 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 9884291291 ps |
| CPU time | 312.68 seconds |
| Started | Jul 18 07:53:44 PM PDT 24 |
| Finished | Jul 18 07:58:57 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-cb80dff6-7b1d-4df4-a512-2980596d3200 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916027404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.916027404 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.980363410 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 626081337 ps |
| CPU time | 235.69 seconds |
| Started | Jul 18 07:53:48 PM PDT 24 |
| Finished | Jul 18 07:57:45 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-616e3212-dc0c-44c9-bc30-2a69264f3259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980363410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_ with_rand_reset.980363410 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1358170390 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 277014122 ps |
| CPU time | 33.11 seconds |
| Started | Jul 18 07:53:51 PM PDT 24 |
| Finished | Jul 18 07:54:25 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-1d5aee60-c749-476c-8333-08c61ac6d217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358170390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1358170390 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1799224457 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 706752982 ps |
| CPU time | 64.43 seconds |
| Started | Jul 18 07:54:10 PM PDT 24 |
| Finished | Jul 18 07:55:14 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-265feaed-fd34-49b8-b796-4ebf99282cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799224457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1799224457 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.156546297 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 21015493722 ps |
| CPU time | 359.01 seconds |
| Started | Jul 18 07:54:09 PM PDT 24 |
| Finished | Jul 18 08:00:08 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-b778946e-3157-424f-b827-1676b02e0519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156546297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.156546297 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.1049008886 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 161198105 ps |
| CPU time | 18.23 seconds |
| Started | Jul 18 07:54:09 PM PDT 24 |
| Finished | Jul 18 07:54:28 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-06bb3bf5-097f-4ee2-a327-771a4d5194bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049008886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.1049008886 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.3732789855 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 1402528625 ps |
| CPU time | 43.4 seconds |
| Started | Jul 18 07:54:16 PM PDT 24 |
| Finished | Jul 18 07:55:00 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-f513ee8b-e560-42a6-8d34-fe4a364d8612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732789855 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.3732789855 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.4279685433 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 414394057 ps |
| CPU time | 36.23 seconds |
| Started | Jul 18 07:54:08 PM PDT 24 |
| Finished | Jul 18 07:54:45 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-f053dea3-8db5-4dbf-a5f0-6e549b39e709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279685433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.4279685433 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.621708965 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 110040101725 ps |
| CPU time | 1190.81 seconds |
| Started | Jul 18 07:54:08 PM PDT 24 |
| Finished | Jul 18 08:13:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-6f1c46c6-39c7-4d35-b9b3-3709b6ed6f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621708965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.621708965 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.1595670003 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 43300473650 ps |
| CPU time | 761.92 seconds |
| Started | Jul 18 07:54:07 PM PDT 24 |
| Finished | Jul 18 08:06:50 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-9f1216f2-e113-4734-88ac-483dec754b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595670003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.1595670003 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3786890827 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 416684603 ps |
| CPU time | 39.7 seconds |
| Started | Jul 18 07:54:05 PM PDT 24 |
| Finished | Jul 18 07:54:46 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-5c6c06c3-176c-459e-b8f4-20e1318fc1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786890827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3786890827 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3099410921 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 1788988797 ps |
| CPU time | 53.3 seconds |
| Started | Jul 18 07:54:10 PM PDT 24 |
| Finished | Jul 18 07:55:04 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d96246d0-a7df-4aa0-904b-726844f5faa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099410921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3099410921 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.1918658346 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 200137894 ps |
| CPU time | 8.63 seconds |
| Started | Jul 18 07:53:47 PM PDT 24 |
| Finished | Jul 18 07:53:57 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-48871aee-8b82-4721-888f-a5d8e5245a3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918658346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.1918658346 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2481317684 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 9380453835 ps |
| CPU time | 104.3 seconds |
| Started | Jul 18 07:54:06 PM PDT 24 |
| Finished | Jul 18 07:55:51 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-01b0020b-a9de-4ba2-9652-c2daab2d16cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481317684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2481317684 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2633935993 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 4033081396 ps |
| CPU time | 63.81 seconds |
| Started | Jul 18 07:54:05 PM PDT 24 |
| Finished | Jul 18 07:55:10 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-2bcedff3-da88-4396-b1a1-b5675bda3bf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633935993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2633935993 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.3547189447 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 48744836 ps |
| CPU time | 6.74 seconds |
| Started | Jul 18 07:54:16 PM PDT 24 |
| Finished | Jul 18 07:54:24 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6eaa7d6c-b0aa-44a6-81ac-4cf02841278e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547189447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.3547189447 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.2357637306 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 10475382310 ps |
| CPU time | 370.46 seconds |
| Started | Jul 18 07:54:05 PM PDT 24 |
| Finished | Jul 18 08:00:17 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-5f997659-d8ad-49fa-ac78-1ec9c63fa395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357637306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2357637306 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3863792130 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 2680363190 ps |
| CPU time | 192.43 seconds |
| Started | Jul 18 07:54:04 PM PDT 24 |
| Finished | Jul 18 07:57:18 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-c79a1063-f76a-45db-975a-15407f025e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863792130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3863792130 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.4209081470 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3334028058 ps |
| CPU time | 332.3 seconds |
| Started | Jul 18 07:54:06 PM PDT 24 |
| Finished | Jul 18 07:59:40 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9093cf7a-03e0-4f5d-a295-5e0d81d92692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209081470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.4209081470 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2040786341 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 2868622070 ps |
| CPU time | 285.61 seconds |
| Started | Jul 18 07:54:05 PM PDT 24 |
| Finished | Jul 18 07:58:52 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-4bf836d8-e5d1-486c-9fad-1d11ce83a2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040786341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2040786341 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.253473967 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 194840119 ps |
| CPU time | 23.35 seconds |
| Started | Jul 18 07:54:16 PM PDT 24 |
| Finished | Jul 18 07:54:40 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-53588328-4bcf-4a53-a6b2-6a824f4aadae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253473967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.253473967 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.1679972965 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 63541682 ps |
| CPU time | 7.98 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:54:32 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-06661651-620b-4b1d-9854-fdfd2223b3df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679972965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .1679972965 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3242673536 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 44572524552 ps |
| CPU time | 788.86 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 08:07:32 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-cdbebebf-f2f5-44b8-8e6c-003aac72d8e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242673536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.3242673536 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.1212906095 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 991192128 ps |
| CPU time | 38.64 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:55:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e2597c42-db51-4403-9cf7-7bb80b995bca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212906095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.1212906095 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.3893865561 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 1806193614 ps |
| CPU time | 61.29 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:55:26 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-d1a171a1-6f21-463f-abe1-91407250ec0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893865561 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3893865561 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2282235505 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 124732517 ps |
| CPU time | 12.93 seconds |
| Started | Jul 18 07:54:08 PM PDT 24 |
| Finished | Jul 18 07:54:21 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-40ff69a1-5112-4e22-9171-3d16e8149d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282235505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2282235505 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2595275578 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 86737649606 ps |
| CPU time | 933.72 seconds |
| Started | Jul 18 07:54:15 PM PDT 24 |
| Finished | Jul 18 08:09:50 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-751f5549-72ab-4012-8c0b-8fbe7ce31ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595275578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2595275578 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3100398408 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 67800388502 ps |
| CPU time | 1229.61 seconds |
| Started | Jul 18 07:54:06 PM PDT 24 |
| Finished | Jul 18 08:14:37 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-4faaaa92-5e65-44bd-a9df-a3cd4bc8986a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100398408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3100398408 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.975765735 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 223232162 ps |
| CPU time | 20.02 seconds |
| Started | Jul 18 07:54:05 PM PDT 24 |
| Finished | Jul 18 07:54:26 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-aeb2459a-32e7-4265-a4fa-7152e0d6fc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975765735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.975765735 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3242889816 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 321306057 ps |
| CPU time | 23.03 seconds |
| Started | Jul 18 07:54:28 PM PDT 24 |
| Finished | Jul 18 07:54:52 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-3593bb28-c4d2-4e50-bd1a-de53639a6d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242889816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3242889816 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.2467054947 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 50821339 ps |
| CPU time | 6.87 seconds |
| Started | Jul 18 07:54:06 PM PDT 24 |
| Finished | Jul 18 07:54:14 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-7222e7b6-ade5-4ca7-b065-ba855c58ad3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467054947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.2467054947 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3607089711 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 8057572671 ps |
| CPU time | 95.28 seconds |
| Started | Jul 18 07:54:15 PM PDT 24 |
| Finished | Jul 18 07:55:51 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-afb98de8-7c77-4454-84c1-d69d601b90d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607089711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3607089711 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3470806554 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 5432263893 ps |
| CPU time | 91.41 seconds |
| Started | Jul 18 07:54:10 PM PDT 24 |
| Finished | Jul 18 07:55:42 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-e4469208-3430-46a7-9af4-edb6b8a781f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470806554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3470806554 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.121275283 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 42272157 ps |
| CPU time | 5.76 seconds |
| Started | Jul 18 07:54:08 PM PDT 24 |
| Finished | Jul 18 07:54:15 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-08e6de11-a759-49bc-a3ab-f7306774dd38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121275283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .121275283 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.86807270 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 4137803225 ps |
| CPU time | 151.28 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:56:56 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-c18437a2-0578-40b2-a4fe-f02889fc4ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86807270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.86807270 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.314320040 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 6615551850 ps |
| CPU time | 248.97 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:58:34 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-1f2313ac-0d49-4ef7-94bc-cb2aa8ba630c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314320040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.314320040 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3321125344 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3291962604 ps |
| CPU time | 236.2 seconds |
| Started | Jul 18 07:54:25 PM PDT 24 |
| Finished | Jul 18 07:58:23 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-51ab9cde-f9e0-46a0-b551-a96f55e955bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321125344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3321125344 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.2225627660 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 6226246670 ps |
| CPU time | 395.43 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 08:01:00 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-597d0be6-457e-4829-bdcb-31b4ca0f2e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225627660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.2225627660 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1619581591 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 742699142 ps |
| CPU time | 36.31 seconds |
| Started | Jul 18 07:54:27 PM PDT 24 |
| Finished | Jul 18 07:55:04 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-879f62ef-5240-449b-becd-fd0c4e229c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619581591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1619581591 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2679614680 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 57636352357 ps |
| CPU time | 10368.7 seconds |
| Started | Jul 18 07:42:17 PM PDT 24 |
| Finished | Jul 18 10:35:07 PM PDT 24 |
| Peak memory | 638368 kb |
| Host | smart-039e1c76-3f31-4e41-8517-0d1868870221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679614680 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2679614680 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.232902436 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 47458536404 ps |
| CPU time | 5797.62 seconds |
| Started | Jul 18 07:42:17 PM PDT 24 |
| Finished | Jul 18 09:18:56 PM PDT 24 |
| Peak memory | 593784 kb |
| Host | smart-c157edaf-80a4-42c6-b87e-6b92b873bced |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232902436 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.232902436 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.3867938522 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4442278488 ps |
| CPU time | 268.19 seconds |
| Started | Jul 18 07:42:51 PM PDT 24 |
| Finished | Jul 18 07:47:19 PM PDT 24 |
| Peak memory | 663812 kb |
| Host | smart-5cc6fe85-c40b-4552-81ba-3323637182e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867938522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.3867938522 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.1603478164 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 9986785630 ps |
| CPU time | 710.55 seconds |
| Started | Jul 18 07:42:51 PM PDT 24 |
| Finished | Jul 18 07:54:42 PM PDT 24 |
| Peak memory | 652880 kb |
| Host | smart-ba7ca00e-4bc3-4a22-b308-7cd18eca6578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603478164 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.1603478164 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.1080888426 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 4798599675 ps |
| CPU time | 396.38 seconds |
| Started | Jul 18 07:42:52 PM PDT 24 |
| Finished | Jul 18 07:49:29 PM PDT 24 |
| Peak memory | 596756 kb |
| Host | smart-dc7bd39b-3a99-4dfc-b947-2451cdd8738b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080888426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.1080888426 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.377402874 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 30000823322 ps |
| CPU time | 4247.96 seconds |
| Started | Jul 18 07:42:25 PM PDT 24 |
| Finished | Jul 18 08:53:14 PM PDT 24 |
| Peak memory | 593576 kb |
| Host | smart-da18d8f0-f638-4eff-b20d-3c68c7454f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377402874 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.377402874 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.520858843 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 562304433 ps |
| CPU time | 32.75 seconds |
| Started | Jul 18 07:42:33 PM PDT 24 |
| Finished | Jul 18 07:43:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-d8a3dacb-4705-4173-bed9-62cc761a6354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520858843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.520858843 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.2583776296 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 36648486 ps |
| CPU time | 6.95 seconds |
| Started | Jul 18 07:42:35 PM PDT 24 |
| Finished | Jul 18 07:42:42 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-f037ec00-9857-45f5-9011-1c6cdf401567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583776296 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .2583776296 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.590966657 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 24575103 ps |
| CPU time | 5.3 seconds |
| Started | Jul 18 07:42:34 PM PDT 24 |
| Finished | Jul 18 07:42:39 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-0241b756-7f76-4d44-8823-bbd5b1365be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590966657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.590966657 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.3024649589 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 513541653 ps |
| CPU time | 21.45 seconds |
| Started | Jul 18 07:42:35 PM PDT 24 |
| Finished | Jul 18 07:42:57 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-552f1bf2-8942-410d-bb1a-24537af0622f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024649589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.3024649589 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2333044975 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 3423988981 ps |
| CPU time | 58.62 seconds |
| Started | Jul 18 07:42:40 PM PDT 24 |
| Finished | Jul 18 07:43:39 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-88d415e4-59c6-4fd9-a3d2-96906e2ca069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333044975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2333044975 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.2650343072 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 506257042 ps |
| CPU time | 44.48 seconds |
| Started | Jul 18 07:42:40 PM PDT 24 |
| Finished | Jul 18 07:43:25 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-ba97bfcd-fcdd-4ad4-9f32-2f924c49ba28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650343072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.2650343072 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.1590939556 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 331740950 ps |
| CPU time | 28.69 seconds |
| Started | Jul 18 07:42:31 PM PDT 24 |
| Finished | Jul 18 07:43:00 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-91660093-e0ae-4090-b433-dff98b96f7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590939556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.1590939556 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2975229499 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 179333692 ps |
| CPU time | 8.26 seconds |
| Started | Jul 18 07:42:16 PM PDT 24 |
| Finished | Jul 18 07:42:24 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-6c509158-cd36-43c7-8993-887911b8c109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975229499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2975229499 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1750479392 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 6344266426 ps |
| CPU time | 73.11 seconds |
| Started | Jul 18 07:42:24 PM PDT 24 |
| Finished | Jul 18 07:43:37 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-6fb8fe2b-bbb9-4113-bedb-903c25050741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750479392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1750479392 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.481756984 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 4802590239 ps |
| CPU time | 80.05 seconds |
| Started | Jul 18 07:42:35 PM PDT 24 |
| Finished | Jul 18 07:43:56 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-1efa9af0-6ab9-4de5-8892-bc21029f0121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481756984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.481756984 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2335599928 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 56680481 ps |
| CPU time | 6.77 seconds |
| Started | Jul 18 07:42:24 PM PDT 24 |
| Finished | Jul 18 07:42:32 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-fda00a12-43b2-4ffb-91d4-a41bdde68a88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335599928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2335599928 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.1523906775 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 3037066412 ps |
| CPU time | 112.49 seconds |
| Started | Jul 18 07:42:40 PM PDT 24 |
| Finished | Jul 18 07:44:33 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-d5964942-0581-4cd3-a00b-f041ff021964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523906775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.1523906775 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3921822564 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 2276080808 ps |
| CPU time | 69.16 seconds |
| Started | Jul 18 07:42:52 PM PDT 24 |
| Finished | Jul 18 07:44:02 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-86ba2e41-2ac3-449f-96d9-adcdc3c06da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921822564 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3921822564 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3598776851 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 26081561079 ps |
| CPU time | 1321.91 seconds |
| Started | Jul 18 07:42:51 PM PDT 24 |
| Finished | Jul 18 08:04:54 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-295b62df-a61a-4eb6-b815-03cf1be0de59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598776851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.3598776851 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.623605243 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 5457393384 ps |
| CPU time | 229.76 seconds |
| Started | Jul 18 07:42:50 PM PDT 24 |
| Finished | Jul 18 07:46:40 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-98fd927f-f9f6-4e1e-965c-9a993de86cd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623605243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_reset_error.623605243 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.1827860950 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 235052548 ps |
| CPU time | 23.62 seconds |
| Started | Jul 18 07:42:34 PM PDT 24 |
| Finished | Jul 18 07:42:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-72600720-76ee-47c1-9671-001c43fb6a2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827860950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.1827860950 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3461734540 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 106031614 ps |
| CPU time | 13.18 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:54:39 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-16d973d5-e868-48ea-a5cf-c76fb03dd302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461734540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3461734540 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3546907803 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 79926654674 ps |
| CPU time | 1519.72 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 08:19:46 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6d54de52-9eab-447a-9397-b7f3bc141b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546907803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3546907803 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.4102705963 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 751176246 ps |
| CPU time | 32.5 seconds |
| Started | Jul 18 07:54:29 PM PDT 24 |
| Finished | Jul 18 07:55:02 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-224dd3ca-8c64-4d6a-b87f-74e1ee98a883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102705963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.4102705963 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.2147753038 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 41507781 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 07:54:25 PM PDT 24 |
| Finished | Jul 18 07:54:33 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-29b34e31-ba63-488e-a204-f3b13d42a55d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147753038 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.2147753038 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.211915771 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 302204050 ps |
| CPU time | 14.09 seconds |
| Started | Jul 18 07:54:22 PM PDT 24 |
| Finished | Jul 18 07:54:37 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e1492d43-83eb-4820-a3a2-3aabd4a257e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211915771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.211915771 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.3370898481 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 56762630489 ps |
| CPU time | 585.02 seconds |
| Started | Jul 18 07:54:28 PM PDT 24 |
| Finished | Jul 18 08:04:14 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-8bb9eedc-1dac-43f5-a83c-7b15fd65fe23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370898481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.3370898481 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.3191264228 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 27329965538 ps |
| CPU time | 476.76 seconds |
| Started | Jul 18 07:54:25 PM PDT 24 |
| Finished | Jul 18 08:02:23 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-672b6f52-9a24-4997-a88f-02bf4a9cd87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191264228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3191264228 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2248210235 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 285392449 ps |
| CPU time | 25.15 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:54:51 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-a83a956b-02ab-4f9e-8d75-d32d4af885bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248210235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2248210235 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.3083516885 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 106484731 ps |
| CPU time | 10.15 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:54:33 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-659cebf0-592b-41bf-88b7-2fedadc5e2d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083516885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.3083516885 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.2421127020 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 200828807 ps |
| CPU time | 9.53 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:54:34 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-9770b18f-e447-4415-b8e0-bab98696938a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421127020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.2421127020 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1515758114 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 8586814194 ps |
| CPU time | 87.7 seconds |
| Started | Jul 18 07:54:25 PM PDT 24 |
| Finished | Jul 18 07:55:54 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-676e3ca1-7e41-4b2e-8850-8e1ec56a9911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515758114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1515758114 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.2625240070 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 5497947890 ps |
| CPU time | 89.75 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:55:55 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f18d11f0-9d62-4e61-9b18-77c17c6dae6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625240070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.2625240070 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.1176682238 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 47282687 ps |
| CPU time | 6.41 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:54:31 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-622c79b5-75e5-42dd-b098-421e24215f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176682238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.1176682238 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2268992897 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5847576716 ps |
| CPU time | 223.88 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:58:09 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-cd2ad960-86d1-4dfb-977a-4c1d57ee54c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268992897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2268992897 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1923176758 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 2359400606 ps |
| CPU time | 198.73 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:58:09 PM PDT 24 |
| Peak memory | 576016 kb |
| Host | smart-0685d88f-4733-405f-ac24-1cac22258cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923176758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1923176758 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.263696626 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 1858737676 ps |
| CPU time | 189.04 seconds |
| Started | Jul 18 07:54:23 PM PDT 24 |
| Finished | Jul 18 07:57:34 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-4df0f104-3cf1-4f7d-b770-42288c4c054e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263696626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.263696626 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.242069072 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 344436900 ps |
| CPU time | 58.35 seconds |
| Started | Jul 18 07:54:47 PM PDT 24 |
| Finished | Jul 18 07:55:47 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-89265c14-2a5c-48ff-845c-8ccdcbae1465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242069072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_reset_error.242069072 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2916592232 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 1160739281 ps |
| CPU time | 43.34 seconds |
| Started | Jul 18 07:54:24 PM PDT 24 |
| Finished | Jul 18 07:55:09 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b064caa1-ddd6-47e7-8b0d-162fa666f8a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916592232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2916592232 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.906757145 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 1200192754 ps |
| CPU time | 92.44 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 07:56:23 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-b3fd870a-abb6-48c7-be99-6ad7a0988cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906757145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device. 906757145 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1618810033 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 90790306285 ps |
| CPU time | 1630.68 seconds |
| Started | Jul 18 07:54:50 PM PDT 24 |
| Finished | Jul 18 08:22:02 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-8f7d950d-78e7-4ce5-b9a3-efc52905ccbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618810033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1618810033 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2342842195 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 62166174 ps |
| CPU time | 8.2 seconds |
| Started | Jul 18 07:54:53 PM PDT 24 |
| Finished | Jul 18 07:55:02 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-a2903a25-8519-4024-9c77-96fdccbe618f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342842195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.2342842195 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1809503599 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 102103924 ps |
| CPU time | 10.05 seconds |
| Started | Jul 18 07:54:47 PM PDT 24 |
| Finished | Jul 18 07:54:58 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-5b61e43c-aca3-4f9d-9e9a-e2ea3588b24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809503599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1809503599 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.793982821 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1198706056 ps |
| CPU time | 38.42 seconds |
| Started | Jul 18 07:54:52 PM PDT 24 |
| Finished | Jul 18 07:55:31 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-51281f5f-35c5-4dc7-9da1-95250dc887c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793982821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.793982821 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1217423170 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 10021749616 ps |
| CPU time | 109.08 seconds |
| Started | Jul 18 07:54:50 PM PDT 24 |
| Finished | Jul 18 07:56:40 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-660b1bdc-cf0c-4b9c-a82f-209f286488d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217423170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1217423170 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.3259239720 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 46967496157 ps |
| CPU time | 832.24 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 08:08:43 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-c2e4a338-565e-4b29-863e-5b2efeec8070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259239720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.3259239720 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2339398114 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 366568114 ps |
| CPU time | 33.47 seconds |
| Started | Jul 18 07:54:47 PM PDT 24 |
| Finished | Jul 18 07:55:22 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-3450fa5a-28d9-4a20-9efa-838310fb13f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339398114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2339398114 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.4010809739 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 253809541 ps |
| CPU time | 9.78 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 07:55:00 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-bb532032-c4de-4a38-a198-ebe19c4c45ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010809739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.4010809739 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1084454943 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 241562325 ps |
| CPU time | 10.24 seconds |
| Started | Jul 18 07:54:51 PM PDT 24 |
| Finished | Jul 18 07:55:02 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-5d469103-b995-4920-a007-303ca0a82627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084454943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1084454943 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.2321592478 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 7857003453 ps |
| CPU time | 86.76 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:56:16 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-2bf1ae08-30b5-4735-94dd-7829771250a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321592478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.2321592478 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1072695706 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 5892692866 ps |
| CPU time | 101.79 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:56:31 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-9cb0ca5a-ddb6-4a49-a0c0-e3552bbc156b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072695706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1072695706 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.774935185 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 43608361 ps |
| CPU time | 6.15 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:54:56 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-2aac3a56-7b44-41f1-8a21-67b325bef35a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774935185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delays .774935185 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.60369374 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 410011454 ps |
| CPU time | 28.39 seconds |
| Started | Jul 18 07:54:53 PM PDT 24 |
| Finished | Jul 18 07:55:22 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-cba5f066-b22c-4020-aeaa-b5e9a6e1d21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60369374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.60369374 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.4247416293 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 526986687 ps |
| CPU time | 47.91 seconds |
| Started | Jul 18 07:54:51 PM PDT 24 |
| Finished | Jul 18 07:55:40 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a840cdfc-c67d-452a-a020-d13b31697ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247416293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.4247416293 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3127458958 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2526418256 ps |
| CPU time | 141.47 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 07:57:12 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-4772d5fc-127f-4fdd-8eda-dddcf51d5bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127458958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.3127458958 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.576162385 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 891452771 ps |
| CPU time | 42.43 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:55:32 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-1bcbbaf5-677a-467e-811f-cdc8adf2349e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576162385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.576162385 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3495383865 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 803451246 ps |
| CPU time | 41.3 seconds |
| Started | Jul 18 07:54:47 PM PDT 24 |
| Finished | Jul 18 07:55:29 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-1db0bbbf-ea45-4bf2-ac76-6730dd80fe3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495383865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3495383865 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1264444940 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 60191045711 ps |
| CPU time | 1127.13 seconds |
| Started | Jul 18 07:55:16 PM PDT 24 |
| Finished | Jul 18 08:14:05 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-000765a1-59eb-4041-8532-3ccebe4988bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264444940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.1264444940 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1863648948 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 692111876 ps |
| CPU time | 26.53 seconds |
| Started | Jul 18 07:55:16 PM PDT 24 |
| Finished | Jul 18 07:55:43 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-46fda9e5-1e5b-48c6-aa79-73245b47115f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863648948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.1863648948 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1900625539 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 1248609059 ps |
| CPU time | 38.23 seconds |
| Started | Jul 18 07:55:10 PM PDT 24 |
| Finished | Jul 18 07:55:50 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-d1423482-5aa4-4fcb-99de-80262f48fbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900625539 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1900625539 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.560170391 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 2196775197 ps |
| CPU time | 86.33 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 07:56:17 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3702935c-ceaf-4b4c-9637-beb7dc3a5a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560170391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.560170391 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.565149337 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 24370897068 ps |
| CPU time | 275.73 seconds |
| Started | Jul 18 07:54:52 PM PDT 24 |
| Finished | Jul 18 07:59:28 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-9bbd5fa8-1d8c-4872-8f02-045f55af9701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565149337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.565149337 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2833480620 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 60037844094 ps |
| CPU time | 1086.66 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 08:12:57 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-7aef6388-b353-465f-bdfe-07b9eb5a5578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833480620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2833480620 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.76490038 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 110989499 ps |
| CPU time | 12.33 seconds |
| Started | Jul 18 07:54:49 PM PDT 24 |
| Finished | Jul 18 07:55:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-4276e38f-c3f9-4bee-a3e1-edb417722b1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76490038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_delay s.76490038 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2007216855 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 164097548 ps |
| CPU time | 14.26 seconds |
| Started | Jul 18 07:55:10 PM PDT 24 |
| Finished | Jul 18 07:55:25 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-677b7390-93a9-4c92-b397-8722a2b4f8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007216855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2007216855 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3604377032 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 50303700 ps |
| CPU time | 6.57 seconds |
| Started | Jul 18 07:54:50 PM PDT 24 |
| Finished | Jul 18 07:54:58 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-9d9c7402-e217-432e-98f5-735d783393b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604377032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3604377032 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1603115247 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 7949954849 ps |
| CPU time | 92.98 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:56:23 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-c5de2236-4a87-472d-8557-67af38247e0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603115247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1603115247 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1287478811 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 4751470664 ps |
| CPU time | 82.91 seconds |
| Started | Jul 18 07:54:50 PM PDT 24 |
| Finished | Jul 18 07:56:14 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3cadce42-640b-4779-93a4-8cbe5861d8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287478811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1287478811 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.539434233 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 42569196 ps |
| CPU time | 6.56 seconds |
| Started | Jul 18 07:54:48 PM PDT 24 |
| Finished | Jul 18 07:54:56 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-bf9d8a5c-7dda-4476-915a-75537b311bc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539434233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .539434233 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3363985761 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 1266354294 ps |
| CPU time | 92.6 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:56:43 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f80acabc-3edc-47ad-8821-38eba1fe2d79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363985761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3363985761 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.265945614 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 7941762267 ps |
| CPU time | 286.36 seconds |
| Started | Jul 18 07:55:08 PM PDT 24 |
| Finished | Jul 18 07:59:56 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-e1336455-e362-4d77-ad4e-bf393421647e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265945614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.265945614 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3378066681 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 108664285 ps |
| CPU time | 57.66 seconds |
| Started | Jul 18 07:55:16 PM PDT 24 |
| Finished | Jul 18 07:56:15 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-110f74b2-6e91-405d-ab15-d8da667b92da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378066681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3378066681 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.957011256 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 1699544721 ps |
| CPU time | 218.74 seconds |
| Started | Jul 18 07:55:08 PM PDT 24 |
| Finished | Jul 18 07:58:48 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-4074ce36-50e7-432d-820e-60d85ebe4edb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957011256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.957011256 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.120918123 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 318309664 ps |
| CPU time | 16.82 seconds |
| Started | Jul 18 07:55:15 PM PDT 24 |
| Finished | Jul 18 07:55:32 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-1690c3cc-a58e-4e81-a2e0-4030974da9d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120918123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.120918123 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.2450647788 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 699633126 ps |
| CPU time | 56.63 seconds |
| Started | Jul 18 07:55:16 PM PDT 24 |
| Finished | Jul 18 07:56:14 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-f2bd9de6-4cfa-4b50-9a8a-916b776ab806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450647788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .2450647788 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3110640925 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 5867986526 ps |
| CPU time | 101.7 seconds |
| Started | Jul 18 07:55:10 PM PDT 24 |
| Finished | Jul 18 07:56:53 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-14536694-a47f-45c9-a372-9dd21cec9823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110640925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.3110640925 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2710071437 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 293798954 ps |
| CPU time | 28.64 seconds |
| Started | Jul 18 07:55:11 PM PDT 24 |
| Finished | Jul 18 07:55:40 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-85d2e570-2000-4a05-84d6-a6661444e2a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710071437 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2710071437 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.762459042 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 296343352 ps |
| CPU time | 13.59 seconds |
| Started | Jul 18 07:55:08 PM PDT 24 |
| Finished | Jul 18 07:55:23 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-4e820474-77d0-467c-b3d6-f5a7b6e728a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762459042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.762459042 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1655634950 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1994211484 ps |
| CPU time | 70.38 seconds |
| Started | Jul 18 07:55:15 PM PDT 24 |
| Finished | Jul 18 07:56:26 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-02a56acf-30c3-4103-8bc3-8dd0b197238a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655634950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1655634950 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3543922337 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 93799588175 ps |
| CPU time | 1142.52 seconds |
| Started | Jul 18 07:55:13 PM PDT 24 |
| Finished | Jul 18 08:14:16 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-3ab802b0-abef-4916-880a-4c36d9d0d5ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543922337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3543922337 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.676971763 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 52456944784 ps |
| CPU time | 925.76 seconds |
| Started | Jul 18 07:55:22 PM PDT 24 |
| Finished | Jul 18 08:10:49 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-6950e17c-9611-46ae-aecd-86894fccb7b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676971763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.676971763 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3564557301 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 613911876 ps |
| CPU time | 58 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:56:08 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-2e1261b2-e4ea-47b6-9030-a6bc96ac4b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564557301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3564557301 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.1748856128 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 401146408 ps |
| CPU time | 14.6 seconds |
| Started | Jul 18 07:55:22 PM PDT 24 |
| Finished | Jul 18 07:55:38 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-dc9da8df-8995-486f-97f7-a8a1bf11ca8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748856128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1748856128 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.698651300 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 55467312 ps |
| CPU time | 6.92 seconds |
| Started | Jul 18 07:55:22 PM PDT 24 |
| Finished | Jul 18 07:55:30 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-1c197b2d-42c9-40a8-9adc-042ebd0f169f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698651300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.698651300 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3906476343 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 9927291291 ps |
| CPU time | 108.46 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:56:58 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-473117e1-ce26-49b3-9835-0b5b729798d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906476343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3906476343 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3598314022 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 4917112818 ps |
| CPU time | 87.71 seconds |
| Started | Jul 18 07:55:11 PM PDT 24 |
| Finished | Jul 18 07:56:39 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-eba9869d-9e1c-47a7-806e-cc64286ccfbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598314022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3598314022 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3619214507 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 47914366 ps |
| CPU time | 6.41 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:55:16 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-86cfd4c5-d1fe-4239-b7e0-617d1ded643d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619214507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3619214507 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2517720586 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 9949183802 ps |
| CPU time | 365.41 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 08:01:16 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-2a1b15c5-a676-42e2-94b0-e75e81716ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517720586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2517720586 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1608003164 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 2305379334 ps |
| CPU time | 158.43 seconds |
| Started | Jul 18 07:55:11 PM PDT 24 |
| Finished | Jul 18 07:57:50 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c21c7d7e-1ef8-4ae1-94fe-e13d4fb785fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608003164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1608003164 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2971365543 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 108451493 ps |
| CPU time | 41.97 seconds |
| Started | Jul 18 07:55:10 PM PDT 24 |
| Finished | Jul 18 07:55:53 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a8ff5ee6-44e6-4609-b162-ddcc696454ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971365543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2971365543 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.95582378 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 56527091 ps |
| CPU time | 17.59 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:55:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-608a541d-dd61-4116-8ab3-f11098ff284d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95582378 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_ with_reset_error.95582378 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.3639697781 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 83609833 ps |
| CPU time | 6.49 seconds |
| Started | Jul 18 07:55:10 PM PDT 24 |
| Finished | Jul 18 07:55:17 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-bf3e1d7f-82c8-4286-891e-69a822fd3b02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639697781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.3639697781 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.2597189937 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 667491581 ps |
| CPU time | 45.37 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 07:56:16 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-8de5da0c-e558-40ac-97c8-768e2f183760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597189937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .2597189937 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.3473329195 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 31443892925 ps |
| CPU time | 564.63 seconds |
| Started | Jul 18 07:55:31 PM PDT 24 |
| Finished | Jul 18 08:04:56 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-66235cfd-4839-4385-80cc-7e4c8434f4b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473329195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.3473329195 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1458256156 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 115935683 ps |
| CPU time | 14.94 seconds |
| Started | Jul 18 07:55:39 PM PDT 24 |
| Finished | Jul 18 07:55:55 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-e935b3d8-643e-4190-bb71-20966b1c4ca8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458256156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1458256156 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.2922902960 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 620471853 ps |
| CPU time | 47.37 seconds |
| Started | Jul 18 07:55:39 PM PDT 24 |
| Finished | Jul 18 07:56:27 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e5fb0444-fd5f-4f4d-b40f-6250d496e582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922902960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.2922902960 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1595984806 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 2060527386 ps |
| CPU time | 76.6 seconds |
| Started | Jul 18 07:55:22 PM PDT 24 |
| Finished | Jul 18 07:56:39 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0dcfaac8-9b86-4e4c-a948-6851d37f3f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595984806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1595984806 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.473489830 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 63533610646 ps |
| CPU time | 672.11 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 08:06:43 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f37214f5-c25d-4553-a0ae-2fb3545fdc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473489830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.473489830 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.714568400 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 31473171573 ps |
| CPU time | 567.17 seconds |
| Started | Jul 18 07:55:32 PM PDT 24 |
| Finished | Jul 18 08:05:00 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-41ed3c34-d059-4061-9a69-12c15b9a100f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714568400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.714568400 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.876602825 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 164111326 ps |
| CPU time | 17.59 seconds |
| Started | Jul 18 07:55:09 PM PDT 24 |
| Finished | Jul 18 07:55:28 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-0ad4daa1-a671-44d8-8eea-f893dd71ad85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876602825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_dela ys.876602825 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3448997548 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 1859407378 ps |
| CPU time | 57.88 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 07:56:29 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8e840e4e-e0b8-4031-8309-99a3cea5dca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448997548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3448997548 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.875241082 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 49464991 ps |
| CPU time | 5.8 seconds |
| Started | Jul 18 07:55:22 PM PDT 24 |
| Finished | Jul 18 07:55:28 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8015eece-3176-4a68-b409-c5e06cb08b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875241082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.875241082 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.2310846496 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 9876643655 ps |
| CPU time | 112.8 seconds |
| Started | Jul 18 07:55:11 PM PDT 24 |
| Finished | Jul 18 07:57:05 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-6cc920f2-3cc9-44cf-beb5-852d2ad8ceb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310846496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.2310846496 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.703761989 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 4696172693 ps |
| CPU time | 84.99 seconds |
| Started | Jul 18 07:55:12 PM PDT 24 |
| Finished | Jul 18 07:56:38 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-945aca4b-d010-416c-b2b8-ee96ee322bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703761989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.703761989 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1130570970 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 41137513 ps |
| CPU time | 5.9 seconds |
| Started | Jul 18 07:55:11 PM PDT 24 |
| Finished | Jul 18 07:55:18 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-992f5b49-eda4-45bf-a986-876bc2403e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130570970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1130570970 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.1480425318 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 6186972730 ps |
| CPU time | 202.85 seconds |
| Started | Jul 18 07:55:29 PM PDT 24 |
| Finished | Jul 18 07:58:53 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ebd8ec38-e4c1-47b8-8644-bd904f2ab14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480425318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.1480425318 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.2362672687 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 2907328383 ps |
| CPU time | 97.8 seconds |
| Started | Jul 18 07:55:31 PM PDT 24 |
| Finished | Jul 18 07:57:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-123f31c3-0e39-4ea0-af88-39fb3052e7a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362672687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.2362672687 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3528435820 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 803438663 ps |
| CPU time | 289.39 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 08:00:21 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-6215920f-2542-4e26-ab1d-ebcceb482ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528435820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3528435820 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.172435533 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 1609412274 ps |
| CPU time | 272.18 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 08:00:03 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f5b92bb3-4969-4cd0-a96d-7fa8b4a3389d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172435533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_reset_error.172435533 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2676222382 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 1224415665 ps |
| CPU time | 56.24 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 07:56:27 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-255e4b06-3d94-4832-90ff-de87a7992249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676222382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2676222382 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3294158909 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 1044650400 ps |
| CPU time | 47.56 seconds |
| Started | Jul 18 07:55:29 PM PDT 24 |
| Finished | Jul 18 07:56:17 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-aaabff48-cb58-4888-a85b-0a6b543c606e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294158909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3294158909 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.2844340380 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 67475315170 ps |
| CPU time | 1309.21 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 08:17:20 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-53de3797-39ec-4a74-becd-151a74aea5b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844340380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.2844340380 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.2727378061 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 276683555 ps |
| CPU time | 32.3 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:28 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-4cd5855b-f07f-4a10-830a-602b04aff744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727378061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.2727378061 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.1238360149 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 805243397 ps |
| CPU time | 30.14 seconds |
| Started | Jul 18 07:55:58 PM PDT 24 |
| Finished | Jul 18 07:56:29 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-9e743e9f-30f7-46cf-8cc5-21d2c2dba2b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238360149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.1238360149 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.265238813 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 246100866 ps |
| CPU time | 11.29 seconds |
| Started | Jul 18 07:55:32 PM PDT 24 |
| Finished | Jul 18 07:55:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e66838b8-2306-4cac-a3ea-d2290f4693ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265238813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.265238813 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2856752853 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 76851562980 ps |
| CPU time | 909.66 seconds |
| Started | Jul 18 07:55:36 PM PDT 24 |
| Finished | Jul 18 08:10:47 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-fa71d58b-f5a5-461c-ad53-fd83b22064ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856752853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2856752853 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.1366410529 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 34526897104 ps |
| CPU time | 587.01 seconds |
| Started | Jul 18 07:55:32 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-c6eb1fe7-e30e-4b9a-b97c-2deb821fee25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366410529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.1366410529 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1471115556 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 513257790 ps |
| CPU time | 43.27 seconds |
| Started | Jul 18 07:55:29 PM PDT 24 |
| Finished | Jul 18 07:56:13 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-d8c3c669-b095-48f5-857b-cf875c8b1a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471115556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1471115556 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1564989111 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 1207732793 ps |
| CPU time | 39.81 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 07:56:10 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6bf39ce4-4e2f-400a-928a-33ba40b8a7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564989111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1564989111 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.713282064 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 52455535 ps |
| CPU time | 6.89 seconds |
| Started | Jul 18 07:55:31 PM PDT 24 |
| Finished | Jul 18 07:55:39 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-97cb1756-e9d1-4fe1-b8be-41284ca5bdba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713282064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.713282064 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2851398158 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 9410799650 ps |
| CPU time | 104.03 seconds |
| Started | Jul 18 07:55:31 PM PDT 24 |
| Finished | Jul 18 07:57:16 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-2994c660-e620-4c08-a22c-b843bedc710d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851398158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2851398158 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1881645897 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 3059517393 ps |
| CPU time | 55.94 seconds |
| Started | Jul 18 07:55:30 PM PDT 24 |
| Finished | Jul 18 07:56:27 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ee6a983b-faa5-49d2-bee2-00e797d5dfd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881645897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1881645897 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.669659285 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 43822845 ps |
| CPU time | 6.1 seconds |
| Started | Jul 18 07:55:32 PM PDT 24 |
| Finished | Jul 18 07:55:39 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-069319a7-6e18-4471-be3d-85c25dc4a56f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669659285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .669659285 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3195444559 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 11935936305 ps |
| CPU time | 476.2 seconds |
| Started | Jul 18 07:55:58 PM PDT 24 |
| Finished | Jul 18 08:03:56 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-142c88d9-0f5b-46bd-8a45-dc80e40817d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195444559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3195444559 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.621734250 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 12155224873 ps |
| CPU time | 421.03 seconds |
| Started | Jul 18 07:55:56 PM PDT 24 |
| Finished | Jul 18 08:02:58 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-fa8b1c7e-7b9e-455c-91e9-93c97fc9348f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621734250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.621734250 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1234487144 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 181640840 ps |
| CPU time | 98.94 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:57:34 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-9e679a06-e27a-44f2-b405-a0a44258c68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234487144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1234487144 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.2225628689 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 9689016918 ps |
| CPU time | 519.48 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 08:04:35 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-76e43620-9a69-4182-a36d-832acc5ca1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225628689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.2225628689 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3482647546 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 603458643 ps |
| CPU time | 26.84 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:22 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-1db53d2d-3e58-442e-a3d3-7520c1cbc3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482647546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3482647546 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.2566532524 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 765384180 ps |
| CPU time | 50.25 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 07:56:44 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-fd010e29-5926-4e5f-a16f-b0a18a6078e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566532524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .2566532524 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.1642176421 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 64438132389 ps |
| CPU time | 1113.29 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 08:14:27 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-0da6dd7b-2a85-4d6d-a8c1-8907fc7ea8c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642176421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.1642176421 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.523455090 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 1150278315 ps |
| CPU time | 44.58 seconds |
| Started | Jul 18 07:55:57 PM PDT 24 |
| Finished | Jul 18 07:56:42 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-d4473394-7d62-41a7-a17a-b0b1c2c56e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523455090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr .523455090 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.3618076117 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 387148847 ps |
| CPU time | 30.52 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:26 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-da9add3f-62e7-4712-a46e-67682073b8ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618076117 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.3618076117 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2157918857 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 2286632152 ps |
| CPU time | 72.92 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 07:57:07 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-506c0170-c014-4d10-9932-c42ccfc18e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157918857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2157918857 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.3246396388 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 55626793421 ps |
| CPU time | 586.7 seconds |
| Started | Jul 18 07:55:59 PM PDT 24 |
| Finished | Jul 18 08:05:47 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-2eeea5f2-3b14-4769-a79b-0a9c47507b80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246396388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.3246396388 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1322753617 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 34858960000 ps |
| CPU time | 591.49 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 08:05:46 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-82311982-64da-4e05-ae22-d35a0e516f8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322753617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1322753617 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1420937891 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 563050236 ps |
| CPU time | 52.38 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:48 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-9ab9331b-76f5-4865-ad1c-2843e1ee6a94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420937891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1420937891 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.4127095777 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 560711809 ps |
| CPU time | 41.59 seconds |
| Started | Jul 18 07:55:55 PM PDT 24 |
| Finished | Jul 18 07:56:37 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-e2c9d62e-e7a8-4297-ae81-1c334573fcd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127095777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.4127095777 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4147154181 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 175163317 ps |
| CPU time | 8.1 seconds |
| Started | Jul 18 07:55:56 PM PDT 24 |
| Finished | Jul 18 07:56:05 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-84aab900-6d18-45db-a74b-e0f6c36d3331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147154181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4147154181 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3705417030 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 7364057312 ps |
| CPU time | 80.05 seconds |
| Started | Jul 18 07:55:51 PM PDT 24 |
| Finished | Jul 18 07:57:12 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-4d5bb499-0452-482b-9452-ff56e00cc7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705417030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3705417030 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.2684896966 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 5726357950 ps |
| CPU time | 95.82 seconds |
| Started | Jul 18 07:55:57 PM PDT 24 |
| Finished | Jul 18 07:57:34 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-b79a686c-2aea-43a9-a094-29226c7e8b92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684896966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.2684896966 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1370374198 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 47588724 ps |
| CPU time | 6.74 seconds |
| Started | Jul 18 07:55:56 PM PDT 24 |
| Finished | Jul 18 07:56:04 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-f64771d6-8c76-480f-b746-e17d64d8c304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370374198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1370374198 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.2325355542 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 3384392268 ps |
| CPU time | 307.52 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 08:01:03 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-c003ad4e-c8f2-4209-bbc5-50ad8120364d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325355542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.2325355542 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2997614949 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 8519697848 ps |
| CPU time | 266.82 seconds |
| Started | Jul 18 07:55:58 PM PDT 24 |
| Finished | Jul 18 08:00:25 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-e928dd67-5f99-452c-9ada-7eb9792638a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997614949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2997614949 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.825270410 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 3333717769 ps |
| CPU time | 340.97 seconds |
| Started | Jul 18 07:55:56 PM PDT 24 |
| Finished | Jul 18 08:01:38 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-c67e6015-6f3a-408a-bf12-a39ae404a695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825270410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_ with_rand_reset.825270410 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.652113336 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 4083934100 ps |
| CPU time | 284.12 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 08:00:39 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-7f985ad2-57c2-4373-a1b6-8ef066e9f2b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652113336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_reset_error.652113336 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.4075610716 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 334783566 ps |
| CPU time | 37.54 seconds |
| Started | Jul 18 07:55:57 PM PDT 24 |
| Finished | Jul 18 07:56:35 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-645e81e9-5c27-4539-9a7a-07f1291d34cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075610716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.4075610716 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2653715493 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 263057013 ps |
| CPU time | 18.03 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 07:56:12 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-55c2c9e9-383a-4c37-bd64-dace7db0023a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653715493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2653715493 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1465169523 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 137914878 ps |
| CPU time | 15.03 seconds |
| Started | Jul 18 07:56:14 PM PDT 24 |
| Finished | Jul 18 07:56:30 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-ab78d53b-c8d6-434b-a133-42dca6de9597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465169523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.1465169523 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.3324650293 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 2218246320 ps |
| CPU time | 82.09 seconds |
| Started | Jul 18 07:56:00 PM PDT 24 |
| Finished | Jul 18 07:57:23 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d1b5fa8b-9e37-448f-ad6d-5d4b82216222 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324650293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.3324650293 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.2986870638 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 430578347 ps |
| CPU time | 35.58 seconds |
| Started | Jul 18 07:55:58 PM PDT 24 |
| Finished | Jul 18 07:56:34 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-80905068-1295-4392-898c-db6c9cbd5cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986870638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2986870638 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.598413909 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 55334261381 ps |
| CPU time | 584.84 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 08:05:40 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-ba609712-f0e1-4a55-b463-51c6c6bac34e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598413909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.598413909 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.177960559 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 42828711130 ps |
| CPU time | 754.23 seconds |
| Started | Jul 18 07:55:53 PM PDT 24 |
| Finished | Jul 18 08:08:29 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-df86f784-55d7-4637-b807-7c09c7d2504c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177960559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.177960559 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1944791706 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 65320245 ps |
| CPU time | 8.99 seconds |
| Started | Jul 18 07:55:55 PM PDT 24 |
| Finished | Jul 18 07:56:05 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-71a1d524-9841-4376-b62d-f9d516a8f0f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944791706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1944791706 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.1522637409 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 558567203 ps |
| CPU time | 39.31 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:34 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f3fd9e60-e97d-489b-9722-f4804088a039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522637409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.1522637409 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.597783479 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 53860898 ps |
| CPU time | 6.61 seconds |
| Started | Jul 18 07:55:59 PM PDT 24 |
| Finished | Jul 18 07:56:06 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-0670efd1-b93c-47b4-8a55-bdb94bafc9bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597783479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.597783479 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2897726677 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 8497817151 ps |
| CPU time | 99.75 seconds |
| Started | Jul 18 07:55:59 PM PDT 24 |
| Finished | Jul 18 07:57:40 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-d9fd9e1b-0aa5-45bc-939b-580a0d20b91e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897726677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2897726677 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.935509300 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 5198345954 ps |
| CPU time | 89.05 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:57:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-89809fba-2668-4f0c-864d-71d2d88eebe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935509300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.935509300 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.1688512940 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 48357602 ps |
| CPU time | 6.93 seconds |
| Started | Jul 18 07:55:54 PM PDT 24 |
| Finished | Jul 18 07:56:02 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-ed39aa55-fa51-4031-9593-c93629267980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688512940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.1688512940 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.4163075607 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 1239503412 ps |
| CPU time | 107.11 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:58:09 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-b449ba16-ef2a-4806-aece-a4b61c54203c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163075607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.4163075607 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1293723548 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 2331598001 ps |
| CPU time | 77.02 seconds |
| Started | Jul 18 07:56:22 PM PDT 24 |
| Finished | Jul 18 07:57:40 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-61f8cbe4-6f1d-418c-9156-1d256f3e160e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293723548 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.1293723548 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3229263703 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 379762041 ps |
| CPU time | 100.96 seconds |
| Started | Jul 18 07:56:14 PM PDT 24 |
| Finished | Jul 18 07:57:56 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-4d23ba9d-0714-4ea7-b723-64a0c52e163f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229263703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3229263703 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2534163309 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 5019915950 ps |
| CPU time | 249.78 seconds |
| Started | Jul 18 07:56:19 PM PDT 24 |
| Finished | Jul 18 08:00:30 PM PDT 24 |
| Peak memory | 576552 kb |
| Host | smart-082764d2-e293-4cdc-b9ba-3cd3d60f27f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534163309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.2534163309 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.2311810638 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 135753858 ps |
| CPU time | 17.76 seconds |
| Started | Jul 18 07:56:16 PM PDT 24 |
| Finished | Jul 18 07:56:35 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-cffc9a90-7566-4a51-b4c1-a30bda45f013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311810638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.2311810638 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3863318478 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 63517509 ps |
| CPU time | 7.08 seconds |
| Started | Jul 18 07:56:16 PM PDT 24 |
| Finished | Jul 18 07:56:25 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-e9b9e590-771a-4073-8d50-8a527a8478bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863318478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3863318478 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.772070946 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 48897737823 ps |
| CPU time | 905.39 seconds |
| Started | Jul 18 07:56:14 PM PDT 24 |
| Finished | Jul 18 08:11:20 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-53d04fa7-4e34-47fc-9715-17f4b62ea9d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772070946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_d evice_slow_rsp.772070946 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.2222067592 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 144825610 ps |
| CPU time | 16.5 seconds |
| Started | Jul 18 07:56:20 PM PDT 24 |
| Finished | Jul 18 07:56:37 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-763defb8-8403-4448-b184-3fd5301c9e8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222067592 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.2222067592 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.4155896107 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 1308722383 ps |
| CPU time | 41.46 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 07:56:57 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-753f5d8f-bf0f-4dcd-8dee-993deede9843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155896107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4155896107 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.452087846 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 326786234 ps |
| CPU time | 31.34 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 07:56:48 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-c2e43868-72be-46d8-a10e-f6ca14a37d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452087846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.452087846 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.4239898312 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 65777203417 ps |
| CPU time | 752.33 seconds |
| Started | Jul 18 07:56:19 PM PDT 24 |
| Finished | Jul 18 08:08:53 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f826ec51-9cd0-4b28-8bdc-8836a7861ebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239898312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.4239898312 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3953187947 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 51113028307 ps |
| CPU time | 952.09 seconds |
| Started | Jul 18 07:56:20 PM PDT 24 |
| Finished | Jul 18 08:12:13 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-8dd92261-0784-46b3-b7c0-06e1a8f640db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953187947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3953187947 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.2457515188 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 129433836 ps |
| CPU time | 13.46 seconds |
| Started | Jul 18 07:56:43 PM PDT 24 |
| Finished | Jul 18 07:56:57 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-5d6f90b9-dd25-4d29-bd06-23f8a0d1f6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457515188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.2457515188 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1640262711 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 381170783 ps |
| CPU time | 28.06 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:56:50 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-127f0749-357d-4828-b4e4-af36c7be14b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640262711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1640262711 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2497338031 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 43615730 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 07:56:17 PM PDT 24 |
| Finished | Jul 18 07:56:24 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-ff056fa2-4864-4f46-ae2c-c4cc8f218eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497338031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2497338031 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.963620438 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 8807699188 ps |
| CPU time | 95.39 seconds |
| Started | Jul 18 07:56:17 PM PDT 24 |
| Finished | Jul 18 07:57:53 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-9ed2f3f1-c25c-4fca-adaa-f7227bf62463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963620438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.963620438 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2784871629 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 5782858803 ps |
| CPU time | 103.83 seconds |
| Started | Jul 18 07:56:13 PM PDT 24 |
| Finished | Jul 18 07:57:58 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6c602efd-1427-4259-8bbf-3b78cc5bd071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784871629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2784871629 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.2404315133 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 42742004 ps |
| CPU time | 6.42 seconds |
| Started | Jul 18 07:56:19 PM PDT 24 |
| Finished | Jul 18 07:56:26 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-b9660629-eef4-40b6-917c-0a7f29fc04f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404315133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.2404315133 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.3678834471 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 10562331256 ps |
| CPU time | 401.5 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 08:02:58 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5c2daba7-56d8-4944-95ee-eae6977251da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678834471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.3678834471 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1679584009 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 2811822605 ps |
| CPU time | 115.63 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-2074eddb-a9cb-4954-9a73-ab3239d8db74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679584009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1679584009 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1634018459 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 629004763 ps |
| CPU time | 131.28 seconds |
| Started | Jul 18 07:56:19 PM PDT 24 |
| Finished | Jul 18 07:58:31 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-4fcc4f1f-4e55-44d6-9a2b-357c29555a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634018459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1634018459 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1195028199 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 8501060132 ps |
| CPU time | 427.95 seconds |
| Started | Jul 18 07:56:17 PM PDT 24 |
| Finished | Jul 18 08:03:26 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-8fa9c615-cf35-4d3e-b707-5cd68047002e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195028199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1195028199 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.3087790684 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 752348772 ps |
| CPU time | 31.95 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 07:56:48 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-7ed28e9d-9330-4748-8dc7-c24b39ade783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087790684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.3087790684 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2262491953 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 2485929748 ps |
| CPU time | 100.18 seconds |
| Started | Jul 18 07:56:16 PM PDT 24 |
| Finished | Jul 18 07:57:57 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c9aad356-a63a-4c96-a339-cdda71611ed5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262491953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2262491953 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3769046397 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 98442009637 ps |
| CPU time | 1882.57 seconds |
| Started | Jul 18 07:56:19 PM PDT 24 |
| Finished | Jul 18 08:27:42 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-5993d81f-8c2b-48f8-ae6a-d555e9eb0f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769046397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3769046397 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.2112050240 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 225776802 ps |
| CPU time | 12.18 seconds |
| Started | Jul 18 07:56:36 PM PDT 24 |
| Finished | Jul 18 07:56:49 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-f3c95ff1-337c-490b-bf0f-1996b50d9d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112050240 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.2112050240 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.2375030852 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 1757519068 ps |
| CPU time | 61.45 seconds |
| Started | Jul 18 07:56:20 PM PDT 24 |
| Finished | Jul 18 07:57:22 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-33a8cea8-c0f7-46d2-a058-33ff4f76e264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375030852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2375030852 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.25084479 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 28550025 ps |
| CPU time | 6.29 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 07:56:22 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-6cf791c5-4636-4e98-8746-9207e46e9235 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25084479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.25084479 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.4007617416 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 67492791531 ps |
| CPU time | 790.44 seconds |
| Started | Jul 18 07:56:20 PM PDT 24 |
| Finished | Jul 18 08:09:32 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-f7ee5afb-ae1b-4b1b-bb63-e59124386f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007617416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.4007617416 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.2282206828 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 3438099190 ps |
| CPU time | 57 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:57:18 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-3ca754a0-ca3d-44b2-994e-186cec2af854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282206828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.2282206828 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2465285189 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 311350032 ps |
| CPU time | 26.64 seconds |
| Started | Jul 18 07:56:14 PM PDT 24 |
| Finished | Jul 18 07:56:41 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-dcb6ab6b-abb3-4548-accb-10156c15f8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465285189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2465285189 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.3050720966 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 1981963452 ps |
| CPU time | 59.43 seconds |
| Started | Jul 18 07:56:17 PM PDT 24 |
| Finished | Jul 18 07:57:17 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e3d3bdf1-503e-4ad7-abdc-6d9ef9bc0f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050720966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.3050720966 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.2767037108 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 53159740 ps |
| CPU time | 6.78 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:56:28 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-e493a6fd-ce6e-46d7-8626-53afa24bdabe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767037108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2767037108 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1172005239 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 7426149624 ps |
| CPU time | 85.32 seconds |
| Started | Jul 18 07:56:22 PM PDT 24 |
| Finished | Jul 18 07:57:48 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-9ec32c42-8839-4128-8645-b651382eb43b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172005239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1172005239 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2141080500 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 5483750872 ps |
| CPU time | 90.49 seconds |
| Started | Jul 18 07:56:21 PM PDT 24 |
| Finished | Jul 18 07:57:52 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-af1104f5-43fa-409d-8aa2-932a6b054bf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141080500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2141080500 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.2237182619 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 40799677 ps |
| CPU time | 6.09 seconds |
| Started | Jul 18 07:56:15 PM PDT 24 |
| Finished | Jul 18 07:56:22 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-43927ba1-8726-4f7a-9601-5c8908270282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237182619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.2237182619 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.494017836 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 295071016 ps |
| CPU time | 27.81 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:57:03 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-6fd7b776-15f9-4d17-9580-4e9ed56b6a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494017836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.494017836 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1956100781 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 209206584 ps |
| CPU time | 14.72 seconds |
| Started | Jul 18 07:56:32 PM PDT 24 |
| Finished | Jul 18 07:56:48 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-f4669097-5832-4844-81a1-3c17cdf6a57b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956100781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1956100781 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.2689964241 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 5319819355 ps |
| CPU time | 367.67 seconds |
| Started | Jul 18 07:56:39 PM PDT 24 |
| Finished | Jul 18 08:02:47 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-cdaa24a1-cd79-46ff-8e4f-2e4613e40730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689964241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.2689964241 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1146594382 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 92730135 ps |
| CPU time | 22.83 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:56:58 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a83b97cc-32ba-4ebe-a5c8-742385ef37b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146594382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1146594382 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.2361611167 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 1230788426 ps |
| CPU time | 54.35 seconds |
| Started | Jul 18 07:56:16 PM PDT 24 |
| Finished | Jul 18 07:57:12 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5972f740-613a-47d4-bd42-e5ef39901ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361611167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.2361611167 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3083069113 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 8126950116 ps |
| CPU time | 599.12 seconds |
| Started | Jul 18 07:43:28 PM PDT 24 |
| Finished | Jul 18 07:53:29 PM PDT 24 |
| Peak memory | 639172 kb |
| Host | smart-eed4c4ea-83a4-46c1-add7-c14065f5e6ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083069113 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.3083069113 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3730035458 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 5834045662 ps |
| CPU time | 677.49 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:54:46 PM PDT 24 |
| Peak memory | 598900 kb |
| Host | smart-20acc07f-32ab-423b-8c06-ee944ed6f91e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730035458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3730035458 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2730833246 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 16907437560 ps |
| CPU time | 2770.8 seconds |
| Started | Jul 18 07:42:52 PM PDT 24 |
| Finished | Jul 18 08:29:04 PM PDT 24 |
| Peak memory | 593116 kb |
| Host | smart-a8d5ed68-5b2c-4abb-93cc-7863279b5545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730833246 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2730833246 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1872247449 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 3734853560 ps |
| CPU time | 300.62 seconds |
| Started | Jul 18 07:42:50 PM PDT 24 |
| Finished | Jul 18 07:47:51 PM PDT 24 |
| Peak memory | 603680 kb |
| Host | smart-4f14fbea-e8f7-48e5-adbb-168f32669ef9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872247449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1872247449 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3794609949 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 2091251964 ps |
| CPU time | 81.52 seconds |
| Started | Jul 18 07:43:09 PM PDT 24 |
| Finished | Jul 18 07:44:31 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-75490230-a62f-483a-a25a-92c52974bd1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794609949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3794609949 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2908162802 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 2516498616 ps |
| CPU time | 48.53 seconds |
| Started | Jul 18 07:43:12 PM PDT 24 |
| Finished | Jul 18 07:44:02 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-8a453add-d2b3-42b2-b3c2-8126c7c5e404 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908162802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.2908162802 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1392763854 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1278767570 ps |
| CPU time | 59.76 seconds |
| Started | Jul 18 07:43:09 PM PDT 24 |
| Finished | Jul 18 07:44:10 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-8c8435a6-609f-49da-8ac8-bb701e0bbab6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392763854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1392763854 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.913995916 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 213013702 ps |
| CPU time | 20.8 seconds |
| Started | Jul 18 07:43:10 PM PDT 24 |
| Finished | Jul 18 07:43:32 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-55c77bdd-fa85-4e1b-af33-86eb543cf899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913995916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.913995916 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.2169342560 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 443882222 ps |
| CPU time | 47.65 seconds |
| Started | Jul 18 07:43:09 PM PDT 24 |
| Finished | Jul 18 07:43:57 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-62d08952-7ac5-4439-8dd1-565f5ce91dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169342560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.2169342560 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2157668524 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 73608026493 ps |
| CPU time | 842.28 seconds |
| Started | Jul 18 07:43:12 PM PDT 24 |
| Finished | Jul 18 07:57:15 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-e5162bc3-2112-4832-90c2-c49f2b66c92f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157668524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2157668524 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3528981054 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 47164694052 ps |
| CPU time | 851.44 seconds |
| Started | Jul 18 07:43:10 PM PDT 24 |
| Finished | Jul 18 07:57:23 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-feb22135-eae8-4094-9237-74ac5968cf8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528981054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3528981054 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2349377103 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 319173496 ps |
| CPU time | 31.24 seconds |
| Started | Jul 18 07:43:10 PM PDT 24 |
| Finished | Jul 18 07:43:42 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-94b54418-8246-4f5b-85c5-f45ad72f9ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349377103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2349377103 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2956392862 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 1126655169 ps |
| CPU time | 32.02 seconds |
| Started | Jul 18 07:43:12 PM PDT 24 |
| Finished | Jul 18 07:43:44 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-95463434-9b19-4c2b-ba78-5805acab6f20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956392862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2956392862 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.1974909598 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 47487238 ps |
| CPU time | 6.28 seconds |
| Started | Jul 18 07:42:51 PM PDT 24 |
| Finished | Jul 18 07:42:58 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-81fd5d29-6655-47b9-aed4-b3bb21032af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974909598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.1974909598 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.945163542 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 7688690134 ps |
| CPU time | 87.44 seconds |
| Started | Jul 18 07:43:14 PM PDT 24 |
| Finished | Jul 18 07:44:43 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-940b014d-0f83-4c19-8086-2a2f157a3665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945163542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.945163542 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.1088195412 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 3192507361 ps |
| CPU time | 55.74 seconds |
| Started | Jul 18 07:43:10 PM PDT 24 |
| Finished | Jul 18 07:44:06 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-34fe394f-0d16-470d-97f4-268aa66acc35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088195412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.1088195412 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4155496140 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 51362443 ps |
| CPU time | 6.84 seconds |
| Started | Jul 18 07:43:14 PM PDT 24 |
| Finished | Jul 18 07:43:21 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-b7dfa7b2-570e-4849-864f-0a4862406f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155496140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .4155496140 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1061755953 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 6313794776 ps |
| CPU time | 232.91 seconds |
| Started | Jul 18 07:43:13 PM PDT 24 |
| Finished | Jul 18 07:47:06 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6254e22c-d04e-46fd-8055-56d091fdb026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061755953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1061755953 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.462734841 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 660676393 ps |
| CPU time | 45.21 seconds |
| Started | Jul 18 07:43:12 PM PDT 24 |
| Finished | Jul 18 07:43:57 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3bc0244c-c40b-4f99-a21c-31c8f22a055a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462734841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.462734841 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2963186073 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 378400605 ps |
| CPU time | 151.6 seconds |
| Started | Jul 18 07:43:31 PM PDT 24 |
| Finished | Jul 18 07:46:04 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-394d7fe3-5c13-4a39-89f2-09dda200dd53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963186073 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2963186073 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3490949685 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 65999462 ps |
| CPU time | 6.14 seconds |
| Started | Jul 18 07:43:12 PM PDT 24 |
| Finished | Jul 18 07:43:18 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-fd7621a1-9991-4b9e-9599-b7e10b2e1d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490949685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3490949685 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.3700723331 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 2516055057 ps |
| CPU time | 95.84 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:58:12 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-9f25fbc4-12ce-416a-a048-485fe578e455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700723331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .3700723331 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.1349992253 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 77902902948 ps |
| CPU time | 1431.02 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 08:20:26 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-e1c04619-eead-489e-9589-835eb3775fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349992253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.1349992253 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.146567130 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 377182274 ps |
| CPU time | 15.43 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:56:49 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d77e6db3-1852-45dd-85a7-65f73037a3d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146567130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_addr .146567130 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.2730211987 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 372139100 ps |
| CPU time | 32.05 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:57:07 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-19d33120-3a51-4423-8c64-88fd116e245e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730211987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.2730211987 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3062615753 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 78764141 ps |
| CPU time | 10.21 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:56:44 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-86833a2c-95d4-4147-900b-5d4ab0a40b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062615753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3062615753 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3297335615 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 105441945493 ps |
| CPU time | 1338.98 seconds |
| Started | Jul 18 07:56:38 PM PDT 24 |
| Finished | Jul 18 08:18:57 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-af6e7d16-0895-4aa8-98ec-52f7afbda736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297335615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3297335615 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.1679141326 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 38536785795 ps |
| CPU time | 683.76 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 08:07:58 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-1b1a2ed9-ddd3-4d2c-93b5-b28813b583d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679141326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.1679141326 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.3988888399 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 371326899 ps |
| CPU time | 32.23 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:57:07 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-e2c282bf-84c1-4ade-973c-6b53c28186a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988888399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.3988888399 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1723966091 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 229090567 ps |
| CPU time | 16.48 seconds |
| Started | Jul 18 07:56:38 PM PDT 24 |
| Finished | Jul 18 07:56:55 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f52ab544-0193-4e7d-af34-029491e02239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723966091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1723966091 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.944744596 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 54987846 ps |
| CPU time | 6.46 seconds |
| Started | Jul 18 07:56:37 PM PDT 24 |
| Finished | Jul 18 07:56:44 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-795870ee-f754-46cd-97fc-54f926e3ce34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944744596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.944744596 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2993482071 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 8889911986 ps |
| CPU time | 99.67 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:58:14 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-eed2885c-c32d-4f13-980b-0a79bfb71b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993482071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2993482071 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1282492522 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 6821281124 ps |
| CPU time | 115.84 seconds |
| Started | Jul 18 07:56:33 PM PDT 24 |
| Finished | Jul 18 07:58:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-d0dccb33-df2f-4cc1-b2ed-4f7609e81c74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282492522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1282492522 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3430695112 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 37198259 ps |
| CPU time | 5.54 seconds |
| Started | Jul 18 07:56:39 PM PDT 24 |
| Finished | Jul 18 07:56:45 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-6746d627-ebe5-4027-bd2f-fb10c10b490a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430695112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3430695112 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2867318906 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 8315422679 ps |
| CPU time | 302.49 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 08:01:38 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-e866d6b8-edd4-4cee-a974-b3224823ff3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867318906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2867318906 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.710950193 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 2655334063 ps |
| CPU time | 115.14 seconds |
| Started | Jul 18 07:56:36 PM PDT 24 |
| Finished | Jul 18 07:58:32 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-62e09a2e-6691-464b-9849-f06ea317420c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710950193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.710950193 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3226078776 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 6644515530 ps |
| CPU time | 374.28 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 08:02:49 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-6a67c42d-bf02-44e6-be2b-3e0620aca13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226078776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3226078776 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.2860987912 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 6743041916 ps |
| CPU time | 414.17 seconds |
| Started | Jul 18 07:56:35 PM PDT 24 |
| Finished | Jul 18 08:03:30 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-b0f2cf82-5867-4ff4-88a1-443c27b1f690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860987912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.2860987912 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2281835769 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 920807519 ps |
| CPU time | 41.96 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:57:17 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-21cc371b-0d53-4b2a-a560-b59c9bd36a7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281835769 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2281835769 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2042908916 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 460689544 ps |
| CPU time | 47.95 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 07:57:47 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-fdc35b79-48ac-4637-a447-5adb25ca2699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042908916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2042908916 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2701662257 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 1423724561 ps |
| CPU time | 54.1 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 07:57:53 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-a06227be-fb37-4cf4-bb79-01bd9d1d00c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701662257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2701662257 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.3466087551 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 801324706 ps |
| CPU time | 28.62 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:57:30 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-874bf600-f2aa-4316-ad05-9b57315d2105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466087551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3466087551 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.4219466122 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 1791906859 ps |
| CPU time | 65.86 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:58:07 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-614a1855-ad1d-4288-bcd2-98dae6598d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219466122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.4219466122 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3795505724 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 61476228519 ps |
| CPU time | 662.91 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 08:08:02 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-10802c33-ac16-49eb-81cf-de107136a28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795505724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.3795505724 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2425777076 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 23886694992 ps |
| CPU time | 443.44 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 08:04:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1a3360f9-eea8-498f-ab3b-d03a0fc019fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425777076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2425777076 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.317702863 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 360109135 ps |
| CPU time | 32.36 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:57:33 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-1a0bbcf7-9749-4d05-a5c0-f20e2c54b034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317702863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.317702863 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.3477675078 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 1898926889 ps |
| CPU time | 55.72 seconds |
| Started | Jul 18 07:56:55 PM PDT 24 |
| Finished | Jul 18 07:57:54 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-3dacb2af-79d8-441e-9448-7b0eb5a1b555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477675078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.3477675078 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.479342797 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 46952031 ps |
| CPU time | 6.01 seconds |
| Started | Jul 18 07:56:35 PM PDT 24 |
| Finished | Jul 18 07:56:42 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-4841e25c-c0d2-4721-b846-2d225605ae82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479342797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.479342797 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1288410105 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 8112305905 ps |
| CPU time | 90.22 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:58:05 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1b743200-19b5-49e7-a297-093d6930b585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288410105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1288410105 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.680465088 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 3923615629 ps |
| CPU time | 75.16 seconds |
| Started | Jul 18 07:56:58 PM PDT 24 |
| Finished | Jul 18 07:58:15 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-7e6fc7a2-d078-4d23-910b-e7e7ec90f2c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680465088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.680465088 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3236169709 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 48658050 ps |
| CPU time | 6.25 seconds |
| Started | Jul 18 07:56:34 PM PDT 24 |
| Finished | Jul 18 07:56:42 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-2a425040-8912-40bc-ba73-f8969195fd1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236169709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3236169709 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2720133047 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 725412685 ps |
| CPU time | 47.36 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:57:49 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-45ad029e-c007-4b97-8439-83d8f5d444d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720133047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2720133047 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3988376232 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 813532943 ps |
| CPU time | 297.3 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 08:01:58 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-a72828b7-1441-4107-8d90-ca8d2f1d4f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988376232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.3988376232 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.229683350 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 8521555867 ps |
| CPU time | 473.17 seconds |
| Started | Jul 18 07:56:57 PM PDT 24 |
| Finished | Jul 18 08:04:53 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-a1bee76e-a9f0-4274-8afc-53afc6f3b4e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229683350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.229683350 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.3018823153 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 1131866459 ps |
| CPU time | 53.63 seconds |
| Started | Jul 18 07:56:56 PM PDT 24 |
| Finished | Jul 18 07:57:52 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-89ded704-a4e7-45a4-8b9d-0805f6691b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018823153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.3018823153 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1632568062 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 812652149 ps |
| CPU time | 41.12 seconds |
| Started | Jul 18 07:56:55 PM PDT 24 |
| Finished | Jul 18 07:57:39 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-7ca6b7ed-e555-4ce8-90fa-2dde8d090096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632568062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1632568062 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.26972195 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 4685555624 ps |
| CPU time | 90.99 seconds |
| Started | Jul 18 07:56:57 PM PDT 24 |
| Finished | Jul 18 07:58:30 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-ba6c3d22-2930-471e-ba6d-67336947718f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26972195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_de vice_slow_rsp.26972195 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2248480738 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 571597584 ps |
| CPU time | 22.6 seconds |
| Started | Jul 18 07:57:24 PM PDT 24 |
| Finished | Jul 18 07:57:48 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-34bf228c-b095-4824-8fff-64271c6dfc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248480738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2248480738 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.1643949959 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 281569794 ps |
| CPU time | 13.01 seconds |
| Started | Jul 18 07:56:57 PM PDT 24 |
| Finished | Jul 18 07:57:12 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-8ac44213-bcbb-4184-bc55-bfabdcfc7251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643949959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.1643949959 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2633429058 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 1942972834 ps |
| CPU time | 77.7 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:58:18 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-0ae0d09c-e6dc-47c3-9c93-dcc788f9fab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633429058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2633429058 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.445601250 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 87247516160 ps |
| CPU time | 1014.92 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 08:13:56 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a268aaf9-d7ce-4f0b-8943-7674f3419b4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445601250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.445601250 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.1078354861 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 66442117218 ps |
| CPU time | 1254.58 seconds |
| Started | Jul 18 07:57:01 PM PDT 24 |
| Finished | Jul 18 08:17:56 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b9612c5b-e726-4f73-807a-5e3c19bfdcb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078354861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.1078354861 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3740726140 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 336454026 ps |
| CPU time | 29.73 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:57:31 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-2a02beeb-ab5d-4cef-970f-dbfae986f6f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740726140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3740726140 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.839366732 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 1431207608 ps |
| CPU time | 48.28 seconds |
| Started | Jul 18 07:56:57 PM PDT 24 |
| Finished | Jul 18 07:57:48 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-dbe4fae6-c6f3-43c9-ae11-9562529538b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839366732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.839366732 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.1930869251 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 197709536 ps |
| CPU time | 9.5 seconds |
| Started | Jul 18 07:56:59 PM PDT 24 |
| Finished | Jul 18 07:57:10 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-94377465-55d9-46c0-842c-eaa7ee4865b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930869251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.1930869251 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2612611906 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 8347504479 ps |
| CPU time | 92.15 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:58:34 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c2d83700-4f60-4598-9bcd-654a64681f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612611906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2612611906 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.883530374 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 6513271424 ps |
| CPU time | 108.66 seconds |
| Started | Jul 18 07:57:00 PM PDT 24 |
| Finished | Jul 18 07:58:50 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-74f29c0f-5be4-41cd-9bc8-5a44bfcd762f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883530374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.883530374 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.2259863526 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 42765115 ps |
| CPU time | 6.2 seconds |
| Started | Jul 18 07:56:57 PM PDT 24 |
| Finished | Jul 18 07:57:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-5a4ee4a6-530a-4494-b1be-1f57566ce9d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259863526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.2259863526 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.347652542 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 5633382103 ps |
| CPU time | 213.6 seconds |
| Started | Jul 18 07:57:15 PM PDT 24 |
| Finished | Jul 18 08:00:50 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0a67e2fd-173d-457f-a019-71336876ef3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347652542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.347652542 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.460328457 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 11226960249 ps |
| CPU time | 411.72 seconds |
| Started | Jul 18 07:57:16 PM PDT 24 |
| Finished | Jul 18 08:04:09 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3a26fcd6-9d2f-49cc-9674-b85459860d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460328457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.460328457 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.1013308780 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 161231319 ps |
| CPU time | 52.42 seconds |
| Started | Jul 18 07:57:23 PM PDT 24 |
| Finished | Jul 18 07:58:16 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d4ecea9c-b0f7-43d0-82a0-bfb10fb0f254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013308780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.1013308780 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1308379230 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 1313460549 ps |
| CPU time | 56.53 seconds |
| Started | Jul 18 07:57:25 PM PDT 24 |
| Finished | Jul 18 07:58:22 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-2567a053-cc35-4978-bfac-69ea86e92acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308379230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1308379230 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1317207076 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 285993958 ps |
| CPU time | 20.27 seconds |
| Started | Jul 18 07:57:25 PM PDT 24 |
| Finished | Jul 18 07:57:46 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-efbce56d-543f-4993-afe5-b1420ff5c7e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317207076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .1317207076 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.4236114249 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 50744771617 ps |
| CPU time | 869.83 seconds |
| Started | Jul 18 07:57:18 PM PDT 24 |
| Finished | Jul 18 08:11:49 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-e7376018-8115-4cdf-9d89-b76de84fecd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236114249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.4236114249 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.842252771 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1418615641 ps |
| CPU time | 57.72 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 07:58:16 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-0503fc81-a70b-4ec7-8725-292974d7bbd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842252771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr .842252771 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.2137796831 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 562548954 ps |
| CPU time | 46.78 seconds |
| Started | Jul 18 07:57:22 PM PDT 24 |
| Finished | Jul 18 07:58:10 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-b8bac71a-9016-462d-8cca-9317de9f0ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137796831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2137796831 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1952589683 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 297060799 ps |
| CPU time | 28.08 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 07:57:46 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2a0960b4-692f-4661-b0f6-fea86683a13a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952589683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1952589683 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.1112122090 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 110541633349 ps |
| CPU time | 1324.14 seconds |
| Started | Jul 18 07:57:22 PM PDT 24 |
| Finished | Jul 18 08:19:27 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-7a24beb3-9412-4805-872a-026c97e5264a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112122090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1112122090 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.615644133 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 30214961954 ps |
| CPU time | 541.1 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 08:06:20 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-5d25a48a-3b90-4407-afcc-91368edda54e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615644133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.615644133 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1258493640 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 620109824 ps |
| CPU time | 55.52 seconds |
| Started | Jul 18 07:57:18 PM PDT 24 |
| Finished | Jul 18 07:58:14 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-541415bd-e9d8-4af9-90ba-f276d557b879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258493640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.1258493640 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.422023014 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 359727956 ps |
| CPU time | 29.96 seconds |
| Started | Jul 18 07:57:14 PM PDT 24 |
| Finished | Jul 18 07:57:45 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-5272a190-2779-49b2-ab9d-2740f8be94a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422023014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.422023014 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.4286110885 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 54986696 ps |
| CPU time | 6.51 seconds |
| Started | Jul 18 07:57:25 PM PDT 24 |
| Finished | Jul 18 07:57:32 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-810fc058-1cdb-4b0b-a072-cceea82d6e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286110885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.4286110885 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.40468650 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 8679715747 ps |
| CPU time | 101.63 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 07:59:00 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-9a5be7fd-9085-4bfc-8124-2ef60a6f5dab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40468650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.40468650 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.2907626051 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 5719373960 ps |
| CPU time | 98.37 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 07:58:57 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-060ab488-b10f-43c5-b933-9018afa87373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907626051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.2907626051 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2787837188 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 56416540 ps |
| CPU time | 6.18 seconds |
| Started | Jul 18 07:57:22 PM PDT 24 |
| Finished | Jul 18 07:57:28 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-c83600fb-2140-4519-a2bd-e7215385cf21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787837188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2787837188 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1445341857 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 11248075389 ps |
| CPU time | 368.86 seconds |
| Started | Jul 18 07:57:17 PM PDT 24 |
| Finished | Jul 18 08:03:27 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-4a1f3c7c-631b-4ff2-8697-e39dcf080ddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445341857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1445341857 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1313466949 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 1303640591 ps |
| CPU time | 110.92 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:59:30 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a3450377-456d-4410-86da-36d23d8a9b57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313466949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1313466949 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1489823208 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 326689889 ps |
| CPU time | 127.54 seconds |
| Started | Jul 18 07:57:21 PM PDT 24 |
| Finished | Jul 18 07:59:29 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d64cfee5-6448-4ec2-a103-f011c81e4ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489823208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1489823208 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.701052529 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 4015966039 ps |
| CPU time | 362.52 seconds |
| Started | Jul 18 07:57:41 PM PDT 24 |
| Finished | Jul 18 08:03:44 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-e70bd9a4-bbac-4487-b836-1060e08dc052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701052529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.701052529 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.3598806571 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 170825771 ps |
| CPU time | 23.87 seconds |
| Started | Jul 18 07:57:16 PM PDT 24 |
| Finished | Jul 18 07:57:41 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-f9f60375-d733-458c-9e1e-3d8ef1e361b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598806571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.3598806571 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3212091565 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 1018960863 ps |
| CPU time | 78.43 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:58:58 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-4fe6e3db-cb70-4edc-9436-e9676aeef161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212091565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3212091565 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2281339999 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 68683586613 ps |
| CPU time | 1126.18 seconds |
| Started | Jul 18 07:57:35 PM PDT 24 |
| Finished | Jul 18 08:16:22 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-aaf12090-9ec1-44ef-b21f-d02a1612bbf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281339999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2281339999 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.1078641824 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 125493313 ps |
| CPU time | 15.14 seconds |
| Started | Jul 18 07:57:41 PM PDT 24 |
| Finished | Jul 18 07:57:56 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-cc5d4669-3217-46bb-819c-30e64aef708d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078641824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.1078641824 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.3942304510 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 1894093706 ps |
| CPU time | 57.55 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:58:37 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-ce0c12a2-dc5a-45c0-bc7c-07f7f577664c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942304510 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.3942304510 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3796529692 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 273125234 ps |
| CPU time | 24 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 07:57:59 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-095b5cb5-0927-4eea-b223-6b4603cc5ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796529692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3796529692 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2845920838 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 86444835230 ps |
| CPU time | 992.38 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 08:14:07 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5f49ad90-fd52-4e2c-a4de-53c3949090f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845920838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2845920838 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.777525079 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 50773347243 ps |
| CPU time | 846.18 seconds |
| Started | Jul 18 07:57:40 PM PDT 24 |
| Finished | Jul 18 08:11:47 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-f61a65f6-4a6b-4880-8b55-90e0ecc01cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777525079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.777525079 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.3273188888 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 43647434 ps |
| CPU time | 6.91 seconds |
| Started | Jul 18 07:57:36 PM PDT 24 |
| Finished | Jul 18 07:57:44 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-705438ea-ba7c-4099-886c-c548d5e8a64d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273188888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.3273188888 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.2914062157 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 1429095971 ps |
| CPU time | 47.09 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 07:58:22 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-067c6f36-6875-48aa-9888-78b5f2d75af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914062157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.2914062157 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.2109046126 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 244981277 ps |
| CPU time | 10.86 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:57:50 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8f432f1c-867d-41b3-a9e6-5d8384dbea12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109046126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2109046126 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1591463198 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 7109768241 ps |
| CPU time | 85.61 seconds |
| Started | Jul 18 07:57:38 PM PDT 24 |
| Finished | Jul 18 07:59:04 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8a98f0aa-cb63-4563-aa87-232526a7e5cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591463198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.1591463198 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3430293099 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 6571654301 ps |
| CPU time | 109.89 seconds |
| Started | Jul 18 07:57:35 PM PDT 24 |
| Finished | Jul 18 07:59:26 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-239d27f1-7763-482f-83ba-71863168f4ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430293099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3430293099 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.727377072 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 49767424 ps |
| CPU time | 6.84 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 07:57:41 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-2cdd6386-e615-4bb8-ae45-6588cbe9362b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727377072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .727377072 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.4007987641 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 2680353201 ps |
| CPU time | 86.82 seconds |
| Started | Jul 18 07:57:41 PM PDT 24 |
| Finished | Jul 18 07:59:08 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-0197448c-0359-4c9c-91ea-2b5f6912be25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007987641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.4007987641 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.968562533 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2538561425 ps |
| CPU time | 187.98 seconds |
| Started | Jul 18 07:57:40 PM PDT 24 |
| Finished | Jul 18 08:00:49 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-7cbdbfcb-af0b-4a54-b845-8850710d0426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968562533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.968562533 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.1742190721 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 452871281 ps |
| CPU time | 129.08 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 07:59:44 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-fc70f8ac-b2a3-463e-a1ce-ce56b10787b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742190721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.1742190721 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1176985309 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 258428335 ps |
| CPU time | 73.49 seconds |
| Started | Jul 18 07:57:34 PM PDT 24 |
| Finished | Jul 18 07:58:48 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-64c5b5ec-50d5-4d02-bada-fc0936b74964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176985309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1176985309 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3897650127 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 215989033 ps |
| CPU time | 26.26 seconds |
| Started | Jul 18 07:57:36 PM PDT 24 |
| Finished | Jul 18 07:58:03 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-1e2d8f4b-0461-48ff-a1c0-d943fcb504e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897650127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3897650127 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.3939005556 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 289206126 ps |
| CPU time | 13.27 seconds |
| Started | Jul 18 07:57:42 PM PDT 24 |
| Finished | Jul 18 07:57:56 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-07a7d36a-73bb-4657-ab26-09504ada4901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939005556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .3939005556 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3550934217 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 138984263667 ps |
| CPU time | 2582.37 seconds |
| Started | Jul 18 07:57:55 PM PDT 24 |
| Finished | Jul 18 08:40:59 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-080f5b8b-8f24-4f90-929e-5909529b02dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550934217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3550934217 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.18683907 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 168242409 ps |
| CPU time | 18.55 seconds |
| Started | Jul 18 07:57:51 PM PDT 24 |
| Finished | Jul 18 07:58:11 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7c39408a-662f-4d3a-9296-d39761d2ba3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr.18683907 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1489122671 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 224734506 ps |
| CPU time | 19.39 seconds |
| Started | Jul 18 07:58:00 PM PDT 24 |
| Finished | Jul 18 07:58:20 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e209ec1e-283d-47ca-aff6-c9bcac10d022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489122671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1489122671 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.3652571658 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 489651050 ps |
| CPU time | 44.74 seconds |
| Started | Jul 18 07:57:32 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-d527466b-0546-4563-a659-49a4e9f3ee48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652571658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.3652571658 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.4291229820 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 116092537730 ps |
| CPU time | 1331.52 seconds |
| Started | Jul 18 07:57:37 PM PDT 24 |
| Finished | Jul 18 08:19:49 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-2bfd5718-9e5c-4dbe-961a-c5121b74386f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291229820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.4291229820 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.69609594 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 38445669482 ps |
| CPU time | 622.82 seconds |
| Started | Jul 18 07:57:35 PM PDT 24 |
| Finished | Jul 18 08:07:59 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e75724b0-7578-44cb-b064-be70d5246e0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69609594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.69609594 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3408529545 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 255147768 ps |
| CPU time | 20.85 seconds |
| Started | Jul 18 07:57:36 PM PDT 24 |
| Finished | Jul 18 07:57:57 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-f8b1cb3e-17ee-4a80-9e7e-37469c4b7748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408529545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3408529545 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1650284702 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 354209712 ps |
| CPU time | 25.74 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 07:58:21 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-19fedf6f-64e4-49cf-a648-e7495931b533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650284702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1650284702 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.4225933833 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 145620770 ps |
| CPU time | 7.77 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:57:48 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-5745d0ff-2ba7-4ea0-aec8-27fbc08cdd57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225933833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.4225933833 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2637467822 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 8833510677 ps |
| CPU time | 92.8 seconds |
| Started | Jul 18 07:57:39 PM PDT 24 |
| Finished | Jul 18 07:59:12 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-4ca11d97-691b-4514-9a46-98082d36c789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637467822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2637467822 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.1458752519 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 5624053302 ps |
| CPU time | 102.32 seconds |
| Started | Jul 18 07:57:36 PM PDT 24 |
| Finished | Jul 18 07:59:19 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-149f9f4d-4c39-4d1c-ba66-94e8015695d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458752519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.1458752519 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.737123073 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 44191031 ps |
| CPU time | 6.15 seconds |
| Started | Jul 18 07:57:36 PM PDT 24 |
| Finished | Jul 18 07:57:43 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-4df4d551-3e7a-4207-8382-88a14c89a055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737123073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .737123073 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3859575904 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 1042952130 ps |
| CPU time | 92.69 seconds |
| Started | Jul 18 07:57:52 PM PDT 24 |
| Finished | Jul 18 07:59:26 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-00f22744-6c1c-4d77-8301-a1de48420c45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859575904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3859575904 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.2584530036 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 7287458613 ps |
| CPU time | 246.85 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 08:02:02 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-ab4dae8f-bea3-4a03-a6ff-c1e353c88a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584530036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.2584530036 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2781786141 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 8984795228 ps |
| CPU time | 448.35 seconds |
| Started | Jul 18 08:00:28 PM PDT 24 |
| Finished | Jul 18 08:07:58 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1bc5802b-9114-4b30-bc38-69b855bdb4e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781786141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2781786141 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.10071046 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 360728656 ps |
| CPU time | 17.05 seconds |
| Started | Jul 18 07:57:57 PM PDT 24 |
| Finished | Jul 18 07:58:15 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-87d86043-528c-4fb1-a594-ecf4108d838b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10071046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.10071046 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1957261641 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 894896360 ps |
| CPU time | 72.07 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 07:59:07 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-ea22e0a2-3c65-4129-a8c2-0505733e8056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957261641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1957261641 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.142509151 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 34198701043 ps |
| CPU time | 611.51 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 08:08:06 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-bbfe93ea-43e5-4b16-b55f-e9f2849f00f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142509151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_d evice_slow_rsp.142509151 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3072843342 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 1309303996 ps |
| CPU time | 46.54 seconds |
| Started | Jul 18 07:57:52 PM PDT 24 |
| Finished | Jul 18 07:58:40 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3227db76-bd97-4270-bfa0-fdf3814e6ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072843342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3072843342 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4078852368 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 235695941 ps |
| CPU time | 20.25 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-fe69b175-2810-4b8b-99a4-1eda14fe7e4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078852368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4078852368 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3611199242 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 1298229877 ps |
| CPU time | 42.41 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 07:58:37 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-b4b00481-e625-427f-b507-712f20045b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611199242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3611199242 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3329749221 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 55467482798 ps |
| CPU time | 554.58 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 08:07:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a60beed6-5277-4217-8c8c-da3dd4fb2f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329749221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3329749221 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.2346025064 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 51548304392 ps |
| CPU time | 946.18 seconds |
| Started | Jul 18 07:58:00 PM PDT 24 |
| Finished | Jul 18 08:13:47 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6f1abfb3-0bbf-4ea1-abc0-d85e1fd6631d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346025064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.2346025064 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3446851556 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 190469373 ps |
| CPU time | 17.81 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:15 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-9c936699-673d-4232-a358-e99438098dab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446851556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3446851556 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.547214034 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1332667667 ps |
| CPU time | 40.47 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:37 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-206039b8-b2cc-4271-9fbb-30b4176b8573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547214034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.547214034 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3646459959 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 43511228 ps |
| CPU time | 6.13 seconds |
| Started | Jul 18 07:58:04 PM PDT 24 |
| Finished | Jul 18 07:58:11 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-08fac79d-224c-444a-b55c-5d34831782a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646459959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3646459959 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2825981438 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 8983350309 ps |
| CPU time | 99.84 seconds |
| Started | Jul 18 07:57:57 PM PDT 24 |
| Finished | Jul 18 07:59:38 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-22a0f107-17ba-4882-b468-47c964a0f3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825981438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2825981438 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.3892445862 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 4510418378 ps |
| CPU time | 81.79 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 07:59:16 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-fec118f8-0b0e-4d7a-af70-ef29d77a02ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892445862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.3892445862 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.449544720 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 50127773 ps |
| CPU time | 6.58 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 07:58:01 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-72b83bf5-d306-4da1-8bcd-40a6bcca3ded |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449544720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delays .449544720 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.1162679116 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 4240093633 ps |
| CPU time | 366.56 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 08:04:02 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-20fd80a8-3565-47d0-84c3-e6b6a35b50f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162679116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.1162679116 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.3405883151 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 8853515008 ps |
| CPU time | 287.41 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 08:02:42 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-2dcbd28a-e5ef-4495-ad20-f4f7ba33985a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405883151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.3405883151 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3599278659 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 86116597 ps |
| CPU time | 24.53 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:21 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-01efd49a-e5f2-48df-8f55-c6cee0ec1258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599278659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3599278659 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3834221858 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 120881526 ps |
| CPU time | 8.83 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:06 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-01bc7280-0b42-48fb-80e7-f48cf2cc4900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834221858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3834221858 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.2143360756 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 1110598403 ps |
| CPU time | 71.69 seconds |
| Started | Jul 18 07:57:51 PM PDT 24 |
| Finished | Jul 18 07:59:03 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-6fcf5e79-a743-4389-a4ea-cec3285e4e7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143360756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .2143360756 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.4104206767 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 44531152366 ps |
| CPU time | 786.11 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 08:11:04 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-8001a369-8d05-495b-af8f-03f4c525f152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104206767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.4104206767 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.2357757149 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 571277443 ps |
| CPU time | 26.26 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:24 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-1b0f28f9-f64e-4aaa-8f5b-5ad3a9fb2cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357757149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.2357757149 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.266014724 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 57824700 ps |
| CPU time | 7.89 seconds |
| Started | Jul 18 07:57:52 PM PDT 24 |
| Finished | Jul 18 07:58:02 PM PDT 24 |
| Peak memory | 573396 kb |
| Host | smart-a8512561-cee6-48bc-b5c5-a26e639854f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266014724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.266014724 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.2108791945 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 548919387 ps |
| CPU time | 45.39 seconds |
| Started | Jul 18 07:58:00 PM PDT 24 |
| Finished | Jul 18 07:58:46 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-82a85b1d-9184-449c-9846-c0b2760dc216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108791945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.2108791945 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.643964352 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 74521861296 ps |
| CPU time | 833.86 seconds |
| Started | Jul 18 07:57:55 PM PDT 24 |
| Finished | Jul 18 08:11:50 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-75f186ba-dd57-4afd-bc17-372327a7ba83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643964352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.643964352 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.135077319 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 17650036161 ps |
| CPU time | 301.63 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 08:02:56 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-cb4239c4-d634-4a4e-b8cf-56e834d25e61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135077319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.135077319 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.684460418 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 570800134 ps |
| CPU time | 42.51 seconds |
| Started | Jul 18 07:57:52 PM PDT 24 |
| Finished | Jul 18 07:58:36 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-124501e5-e995-485d-84fd-65d0f439e52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684460418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.684460418 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3689611833 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 559194059 ps |
| CPU time | 37.82 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:35 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-270a4bb8-f929-43ad-bb92-4e5caa799902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689611833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3689611833 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.2091906177 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 225892042 ps |
| CPU time | 10.15 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 07:58:05 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-5658c5f5-1fa1-4656-8a35-76c022be7f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091906177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.2091906177 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.552354986 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 9464724131 ps |
| CPU time | 105.79 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 07:59:40 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-95d40abe-7e8e-4f81-9118-53af89fd346e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552354986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.552354986 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2673475763 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 4147579483 ps |
| CPU time | 69.4 seconds |
| Started | Jul 18 07:57:54 PM PDT 24 |
| Finished | Jul 18 07:59:05 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-7f5bc326-f121-4241-951a-0072c6d21219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673475763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2673475763 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1646175326 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 39877384 ps |
| CPU time | 5.99 seconds |
| Started | Jul 18 07:57:56 PM PDT 24 |
| Finished | Jul 18 07:58:03 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-a463f8f0-20ad-4b9d-81b4-3557c06ba0b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646175326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.1646175326 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3142031755 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 2868553998 ps |
| CPU time | 244.15 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 08:02:15 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a6eeaada-041f-4e00-b54b-68d8be9f7bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142031755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3142031755 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.4220306308 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 2246980835 ps |
| CPU time | 63.96 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 07:59:15 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-38b76ed4-40ad-4297-910d-b904202b51ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220306308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.4220306308 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1885155848 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 179534918 ps |
| CPU time | 101.95 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 07:59:53 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-eb729833-5989-446b-a834-4192bf642751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885155848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1885155848 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1417794157 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3019821143 ps |
| CPU time | 450.16 seconds |
| Started | Jul 18 07:58:11 PM PDT 24 |
| Finished | Jul 18 08:05:43 PM PDT 24 |
| Peak memory | 577732 kb |
| Host | smart-bfacfb8b-10d5-4d1c-addc-c01cab472b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417794157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1417794157 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.1945783978 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 310119819 ps |
| CPU time | 39.7 seconds |
| Started | Jul 18 07:57:53 PM PDT 24 |
| Finished | Jul 18 07:58:34 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-24dcf28a-6d00-4cdb-8b23-4980a2ad278d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945783978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.1945783978 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3697252731 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 462540445 ps |
| CPU time | 55.02 seconds |
| Started | Jul 18 07:58:11 PM PDT 24 |
| Finished | Jul 18 07:59:07 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-b03fe2f5-59fd-4518-9b9a-7932e32c9e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697252731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3697252731 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2735824825 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 8225843922 ps |
| CPU time | 138.33 seconds |
| Started | Jul 18 07:58:12 PM PDT 24 |
| Finished | Jul 18 08:00:31 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-67bf59b1-181a-47b8-885c-449f6c2b7847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735824825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.2735824825 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.2596470794 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 1209012633 ps |
| CPU time | 50.09 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 07:59:01 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-93cd4288-96a2-477e-beac-85af881dbeaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596470794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.2596470794 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.3180145858 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 449830664 ps |
| CPU time | 32.52 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 07:58:44 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-30771273-5488-4b21-b195-7cf24c08ebb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180145858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.3180145858 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.3400644900 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 2190793659 ps |
| CPU time | 74.21 seconds |
| Started | Jul 18 07:58:09 PM PDT 24 |
| Finished | Jul 18 07:59:24 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-3a196824-0aff-4d30-9a75-2a11a56c48de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400644900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.3400644900 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3348498068 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 86038938028 ps |
| CPU time | 974.99 seconds |
| Started | Jul 18 07:58:08 PM PDT 24 |
| Finished | Jul 18 08:14:24 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c6fe37cb-aa96-4bc9-8338-26e14538a17c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348498068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3348498068 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.4185895583 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 12510984025 ps |
| CPU time | 219.87 seconds |
| Started | Jul 18 07:58:11 PM PDT 24 |
| Finished | Jul 18 08:01:52 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-93fc4245-2eac-401b-b59d-e49179314f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185895583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.4185895583 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3373446107 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 99702424 ps |
| CPU time | 11.2 seconds |
| Started | Jul 18 07:58:09 PM PDT 24 |
| Finished | Jul 18 07:58:21 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-eef60dbf-573f-4d20-bbc7-c8c51d3083cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373446107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3373446107 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.124273964 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 1037393175 ps |
| CPU time | 31.61 seconds |
| Started | Jul 18 07:58:12 PM PDT 24 |
| Finished | Jul 18 07:58:44 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-6d2e251a-ccc4-4538-a777-ca604ba841a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124273964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.124273964 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.3114143544 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 53546690 ps |
| CPU time | 6.85 seconds |
| Started | Jul 18 07:58:09 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-d6ea44c0-6c94-4ddf-9bc8-572e3fd48a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114143544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.3114143544 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2011194486 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 9242587515 ps |
| CPU time | 105.01 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 08:00:01 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-13daa83c-fbe2-4836-8df0-2277dde11099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011194486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2011194486 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1942398879 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 6475511588 ps |
| CPU time | 119.6 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 08:00:10 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-9c56c848-164a-40e7-9d8c-09599b1deb97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942398879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1942398879 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2196687550 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 51220740 ps |
| CPU time | 6.29 seconds |
| Started | Jul 18 07:58:10 PM PDT 24 |
| Finished | Jul 18 07:58:17 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-6447bf3e-4e98-49cc-aad7-97d766852d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196687550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2196687550 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.804858343 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 4854913437 ps |
| CPU time | 186.83 seconds |
| Started | Jul 18 07:58:13 PM PDT 24 |
| Finished | Jul 18 08:01:21 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-1911e0af-e373-4f3c-8512-a27fe3f795a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804858343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.804858343 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1751421647 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 965718147 ps |
| CPU time | 79.86 seconds |
| Started | Jul 18 07:58:13 PM PDT 24 |
| Finished | Jul 18 07:59:33 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-1b439254-65e7-41a6-8b8b-f4b4e985174d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751421647 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1751421647 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3701223324 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 8113168 ps |
| CPU time | 16.51 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 07:58:32 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-fb6c19bb-772b-4a8f-986b-c05a83ebc7c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701223324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3701223324 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.744574992 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 7540841860 ps |
| CPU time | 361.35 seconds |
| Started | Jul 18 07:58:13 PM PDT 24 |
| Finished | Jul 18 08:04:15 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-1e514270-1745-480e-b7d0-afc64e1d1a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744574992 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_reset_error.744574992 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.3985422496 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 46417255 ps |
| CPU time | 8.18 seconds |
| Started | Jul 18 07:58:11 PM PDT 24 |
| Finished | Jul 18 07:58:20 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-8bddd780-a9c2-4507-bf57-83b3d4196ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985422496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.3985422496 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2853688613 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 213097259 ps |
| CPU time | 18.65 seconds |
| Started | Jul 18 07:58:17 PM PDT 24 |
| Finished | Jul 18 07:58:36 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-d9698dc2-79e8-458e-a6ea-d6138b817a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853688613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2853688613 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.1332946440 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 109903087888 ps |
| CPU time | 2061.08 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 08:32:37 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-99fe9baf-e126-4a0c-8dab-c3ecd9ca64c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332946440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.1332946440 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3491577756 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 1308662906 ps |
| CPU time | 45.77 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 07:59:21 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-ac615155-245c-4219-a894-d4aaaca50541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491577756 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3491577756 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.2098130486 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 2192642190 ps |
| CPU time | 81.59 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 07:59:37 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-49836524-ab84-4e00-a1b7-526075385699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098130486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.2098130486 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2513784729 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 351058482 ps |
| CPU time | 14.97 seconds |
| Started | Jul 18 07:58:12 PM PDT 24 |
| Finished | Jul 18 07:58:28 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-f30efb28-d72d-44a5-b42d-d51aea14d2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513784729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2513784729 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.2139539158 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 51746138563 ps |
| CPU time | 536.99 seconds |
| Started | Jul 18 07:58:17 PM PDT 24 |
| Finished | Jul 18 08:07:15 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-e2e7ffa0-8285-4fba-9755-acea6756b459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139539158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.2139539158 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.1014591680 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 11585989497 ps |
| CPU time | 187.52 seconds |
| Started | Jul 18 07:58:17 PM PDT 24 |
| Finished | Jul 18 08:01:25 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-a17bb3bd-812b-48be-b6fb-ebd2a2396461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014591680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.1014591680 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.674763301 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 359929344 ps |
| CPU time | 34.34 seconds |
| Started | Jul 18 07:58:11 PM PDT 24 |
| Finished | Jul 18 07:58:47 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-4a08f158-d04b-4129-8c41-e7edcad7ff0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674763301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.674763301 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.2341015974 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 2503281694 ps |
| CPU time | 76.94 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 07:59:33 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-0d26dc9c-ba47-400b-9aa9-cc11f0d0e5da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341015974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2341015974 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.221526363 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 212385860 ps |
| CPU time | 9.64 seconds |
| Started | Jul 18 07:58:13 PM PDT 24 |
| Finished | Jul 18 07:58:23 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-2445fb24-4e5f-4c62-8717-85077880b0d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221526363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.221526363 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.707592162 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 7699964690 ps |
| CPU time | 85.43 seconds |
| Started | Jul 18 07:58:17 PM PDT 24 |
| Finished | Jul 18 07:59:44 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-af8bd89a-16b7-4f3d-a521-c22d68440e09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707592162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.707592162 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.1111277767 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 4794097174 ps |
| CPU time | 78.11 seconds |
| Started | Jul 18 07:58:16 PM PDT 24 |
| Finished | Jul 18 07:59:35 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-fa37192b-1012-431d-bad0-b4ebaa5e0d0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111277767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.1111277767 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.3915277812 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 60244595 ps |
| CPU time | 7.03 seconds |
| Started | Jul 18 07:58:17 PM PDT 24 |
| Finished | Jul 18 07:58:25 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-86bc5ef4-4e42-404e-a92f-6f7a972d8b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915277812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.3915277812 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1227390762 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 3174502285 ps |
| CPU time | 113.35 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 08:00:29 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d0fa251d-81f8-4111-b759-548d06af401a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227390762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1227390762 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.109794448 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 3074914517 ps |
| CPU time | 340.26 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 08:04:16 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-fdcc89d6-fa7d-4e72-8043-b41af3e62cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109794448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.109794448 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2584592994 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 268487357 ps |
| CPU time | 89.22 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 08:00:04 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-7a45d095-a243-4493-af47-1a87e8965f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584592994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2584592994 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3265902158 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 732999962 ps |
| CPU time | 33.54 seconds |
| Started | Jul 18 07:58:15 PM PDT 24 |
| Finished | Jul 18 07:58:49 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5c74f835-9547-4df6-b812-34c1f848879e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265902158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3265902158 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2531573973 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 10378413998 ps |
| CPU time | 776.49 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:57:10 PM PDT 24 |
| Peak memory | 645792 kb |
| Host | smart-fc318752-594b-44ca-be76-e494905a8a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531573973 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2531573973 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3615537500 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 5427755337 ps |
| CPU time | 511.63 seconds |
| Started | Jul 18 07:44:13 PM PDT 24 |
| Finished | Jul 18 07:52:46 PM PDT 24 |
| Peak memory | 599328 kb |
| Host | smart-ed66061e-4cde-41ca-b675-6cba5ef5b7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615537500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3615537500 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.1065141538 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 29667588134 ps |
| CPU time | 3750.65 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 08:45:59 PM PDT 24 |
| Peak memory | 593260 kb |
| Host | smart-1c756a23-f040-47ea-8543-ed03bda9a631 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065141538 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.1065141538 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.3366583596 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 3159372784 ps |
| CPU time | 213.14 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:47:01 PM PDT 24 |
| Peak memory | 598648 kb |
| Host | smart-0d29079c-e153-4fc1-9dc8-11003df9382f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366583596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3366583596 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3481318101 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 111417991942 ps |
| CPU time | 2106.52 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 08:18:36 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-00609b96-0431-4431-93f2-153cc417290d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481318101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.3481318101 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2169184791 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 194057899 ps |
| CPU time | 20.75 seconds |
| Started | Jul 18 07:44:17 PM PDT 24 |
| Finished | Jul 18 07:44:39 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d218a903-f8e8-404e-a7e6-58401ea9811d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169184791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2169184791 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.71337245 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 1626036515 ps |
| CPU time | 52.69 seconds |
| Started | Jul 18 07:44:13 PM PDT 24 |
| Finished | Jul 18 07:45:07 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-beff4bfd-b3a8-48da-b645-3f871e7cdc99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71337245 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.71337245 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.3199758220 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 132118463 ps |
| CPU time | 14.55 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:43:43 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-4323edcb-2d6c-413f-9b7f-bf2a7aaedb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199758220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.3199758220 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1877586639 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 103484158096 ps |
| CPU time | 1173.24 seconds |
| Started | Jul 18 07:43:28 PM PDT 24 |
| Finished | Jul 18 08:03:03 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-9d0475ca-0f0f-46d0-9352-af2b549ad393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877586639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1877586639 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.4197861437 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 62977184081 ps |
| CPU time | 1134.86 seconds |
| Started | Jul 18 07:43:32 PM PDT 24 |
| Finished | Jul 18 08:02:27 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-a0dafc69-4e43-4514-8cbd-ed022aa4b532 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197861437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.4197861437 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2647616821 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 411839981 ps |
| CPU time | 36.22 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:44:04 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-7114a4eb-e2a2-4109-8426-864b92822d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647616821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2647616821 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.579243539 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 1984966730 ps |
| CPU time | 54.01 seconds |
| Started | Jul 18 07:44:13 PM PDT 24 |
| Finished | Jul 18 07:45:08 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-0e2e2056-0112-4970-a9d5-aa4d430b0a20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579243539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.579243539 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.2053987078 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 50230613 ps |
| CPU time | 6.01 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:43:35 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-bcdbc013-5378-4499-80f2-fd7d5b72c72d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053987078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.2053987078 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.323455923 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 9214801057 ps |
| CPU time | 105.37 seconds |
| Started | Jul 18 07:43:28 PM PDT 24 |
| Finished | Jul 18 07:45:15 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-92b2e6ee-f2de-475b-a554-83e88e753d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323455923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.323455923 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1343206987 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 6886237770 ps |
| CPU time | 115.9 seconds |
| Started | Jul 18 07:43:32 PM PDT 24 |
| Finished | Jul 18 07:45:28 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9def63f0-504a-4ad5-98d9-c033b59b7b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343206987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1343206987 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.4215932919 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 38327533 ps |
| CPU time | 5.95 seconds |
| Started | Jul 18 07:43:27 PM PDT 24 |
| Finished | Jul 18 07:43:35 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-5078c3a3-6c6e-46f1-b758-9526d1ed0340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215932919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .4215932919 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.2303933875 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 2864454781 ps |
| CPU time | 266.35 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:48:44 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-0dd49e24-42b2-4f96-a06d-0f8113ae4867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303933875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.2303933875 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.671882010 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 796103275 ps |
| CPU time | 63.46 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:45:21 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-4264e10c-e881-45d7-b764-86a7d9168340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671882010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.671882010 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.233851048 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 180387989 ps |
| CPU time | 61.18 seconds |
| Started | Jul 18 07:44:15 PM PDT 24 |
| Finished | Jul 18 07:45:17 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-66c7f6ce-d7fc-46c2-bc5d-dc4e105a0703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233851048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.233851048 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.287546575 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 855002581 ps |
| CPU time | 40.73 seconds |
| Started | Jul 18 07:44:14 PM PDT 24 |
| Finished | Jul 18 07:44:55 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-a7b1b630-a2be-40c6-9f04-3bf8f357a519 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287546575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.287546575 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.2128384449 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 284978717 ps |
| CPU time | 25.67 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:54 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-1e04cb5f-5c43-460a-b68c-33190959f9d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128384449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .2128384449 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.428265042 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 86244171335 ps |
| CPU time | 1563.89 seconds |
| Started | Jul 18 07:58:29 PM PDT 24 |
| Finished | Jul 18 08:24:34 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-abc8d6a5-b019-4e02-ad3b-8fcd7458f170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428265042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_d evice_slow_rsp.428265042 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.4036242523 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 699196624 ps |
| CPU time | 29.32 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:58 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-7be4ff54-8787-4199-bf54-84c9bddac15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036242523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.4036242523 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.1234687809 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 366914729 ps |
| CPU time | 13.54 seconds |
| Started | Jul 18 07:58:38 PM PDT 24 |
| Finished | Jul 18 07:58:52 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-e83b2e3e-3a4b-430b-a750-ddde6aaa797b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234687809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.1234687809 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.2103886189 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 1461471437 ps |
| CPU time | 46.54 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:59:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-0695070b-d844-472c-a21e-3d0cf40a972f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103886189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.2103886189 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.3917545538 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 104821867004 ps |
| CPU time | 1229.93 seconds |
| Started | Jul 18 07:58:27 PM PDT 24 |
| Finished | Jul 18 08:18:58 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-5abebe2a-3bae-4d31-a853-b0089e10e390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917545538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.3917545538 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1401245575 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 51965363378 ps |
| CPU time | 836.87 seconds |
| Started | Jul 18 07:58:38 PM PDT 24 |
| Finished | Jul 18 08:12:36 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-ea3026e2-acc7-41d0-82f8-0b76d945b65c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401245575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1401245575 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3071132605 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 69762341 ps |
| CPU time | 9.79 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:39 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-fd57fbe9-f1ab-4f2b-8dfe-c4288dd73be3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071132605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3071132605 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1763724391 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 797906863 ps |
| CPU time | 25.3 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 07:59:01 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-b9fe29cc-32e2-4407-a3e1-51bfa90198e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763724391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1763724391 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.3150147492 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 49591476 ps |
| CPU time | 6.31 seconds |
| Started | Jul 18 07:58:30 PM PDT 24 |
| Finished | Jul 18 07:58:37 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-46e1f20c-f07a-4837-93a5-7898acf97871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150147492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.3150147492 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.420883896 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 9672030701 ps |
| CPU time | 111.91 seconds |
| Started | Jul 18 07:58:31 PM PDT 24 |
| Finished | Jul 18 08:00:23 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-f29576c6-0a44-45f2-88b0-3386904b90fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420883896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.420883896 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.1438486346 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 5803192542 ps |
| CPU time | 103.51 seconds |
| Started | Jul 18 07:58:27 PM PDT 24 |
| Finished | Jul 18 08:00:11 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-46282703-9a80-4469-a8aa-f22dd48a227e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438486346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.1438486346 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2607322881 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 44231160 ps |
| CPU time | 6.29 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:36 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-351afcdb-9c61-4db7-bc0b-f5ae792a9d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607322881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2607322881 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.918442710 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 1512935024 ps |
| CPU time | 112.98 seconds |
| Started | Jul 18 07:58:27 PM PDT 24 |
| Finished | Jul 18 08:00:21 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-14d68a1e-174a-4bbd-83da-c521ccf8abd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918442710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.918442710 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.4103112724 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 1883850738 ps |
| CPU time | 120.93 seconds |
| Started | Jul 18 07:58:29 PM PDT 24 |
| Finished | Jul 18 08:00:31 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-fd8011ab-4e1a-4293-adc1-d48bb92b0f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103112724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.4103112724 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.182009122 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 1115342511 ps |
| CPU time | 161.35 seconds |
| Started | Jul 18 07:58:30 PM PDT 24 |
| Finished | Jul 18 08:01:12 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-58db0f2e-9dd5-4ec6-8ce1-df95e35ef58a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182009122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.182009122 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1351101078 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 8323982962 ps |
| CPU time | 422.23 seconds |
| Started | Jul 18 07:58:31 PM PDT 24 |
| Finished | Jul 18 08:05:34 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-28fbcd6c-06e5-4547-b0e6-59732b9c0dfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351101078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1351101078 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.4176847942 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 105039229 ps |
| CPU time | 7.4 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:37 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-29f90e65-fc19-44b3-b173-77680848956b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176847942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.4176847942 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1989685442 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1396800113 ps |
| CPU time | 58.18 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 07:59:50 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-db55bb91-e120-4632-a3ed-12740077d21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989685442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .1989685442 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1792160384 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 125813917746 ps |
| CPU time | 2298.24 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 08:37:11 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1b6293f2-5835-4445-aae6-985e9256a54e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792160384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1792160384 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.908131764 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 178414114 ps |
| CPU time | 18.26 seconds |
| Started | Jul 18 07:58:54 PM PDT 24 |
| Finished | Jul 18 07:59:13 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-e311de20-a987-40e4-91b7-dcbf68746e72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908131764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .908131764 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.4287399249 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 1435527060 ps |
| CPU time | 50.78 seconds |
| Started | Jul 18 07:58:53 PM PDT 24 |
| Finished | Jul 18 07:59:45 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-88226d27-4980-47e1-889a-fa279c2d6cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287399249 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.4287399249 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.828965174 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 422786225 ps |
| CPU time | 17.23 seconds |
| Started | Jul 18 07:58:38 PM PDT 24 |
| Finished | Jul 18 07:58:56 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-127d5c68-4542-4dc3-8cc3-c55eae37d21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828965174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.828965174 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.3311089691 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 40117352691 ps |
| CPU time | 432.45 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 08:05:42 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-fc211ce1-2601-410e-80e3-1b41841b18a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311089691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.3311089691 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.2360349837 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 31263519534 ps |
| CPU time | 516.46 seconds |
| Started | Jul 18 07:58:38 PM PDT 24 |
| Finished | Jul 18 08:07:16 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-ebbf9d2f-522e-45b5-8525-0c4d47149c06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360349837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.2360349837 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.1518846988 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 356921324 ps |
| CPU time | 34.58 seconds |
| Started | Jul 18 07:58:29 PM PDT 24 |
| Finished | Jul 18 07:59:05 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-196813ca-113a-4d69-be58-14c70fa35496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518846988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.1518846988 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.462116035 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 1051956291 ps |
| CPU time | 36.71 seconds |
| Started | Jul 18 07:58:53 PM PDT 24 |
| Finished | Jul 18 07:59:31 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-53447b1b-c648-473e-8910-0c40f2c1eae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462116035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.462116035 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.3635594040 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 49066345 ps |
| CPU time | 6.46 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:35 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-67fbc818-d260-4181-a0c5-f61b48a02a6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635594040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.3635594040 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.992071690 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 6819603270 ps |
| CPU time | 77.91 seconds |
| Started | Jul 18 07:58:34 PM PDT 24 |
| Finished | Jul 18 07:59:54 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-2a83d69b-c334-4946-900f-5e6786fe0b96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992071690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.992071690 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3157264184 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 5767609167 ps |
| CPU time | 98.89 seconds |
| Started | Jul 18 07:58:30 PM PDT 24 |
| Finished | Jul 18 08:00:10 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-3f69b123-0242-49f4-8b7d-bf3e90a6c80b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157264184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3157264184 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.2903067861 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 48386695 ps |
| CPU time | 6.6 seconds |
| Started | Jul 18 07:58:28 PM PDT 24 |
| Finished | Jul 18 07:58:35 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-45059eff-04a1-4e25-b65c-215e39de3aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903067861 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.2903067861 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.3181665359 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 5983506870 ps |
| CPU time | 234.4 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 08:02:47 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-46c953d2-69bb-4dbd-a67e-f2fb326ff090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181665359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3181665359 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1914977782 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5488342583 ps |
| CPU time | 193.78 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 08:02:04 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-64bb38f9-f6f4-437d-b09a-946d57505a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914977782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1914977782 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.2162125177 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 360290559 ps |
| CPU time | 118.71 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 08:00:51 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-c0f3aae6-c6f9-4856-8323-6218533d4437 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162125177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.2162125177 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.672423504 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 180395640 ps |
| CPU time | 20.3 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 07:59:12 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-da04270e-3d77-438f-a270-2593d3c5c00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672423504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.672423504 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.2164500993 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 671928597 ps |
| CPU time | 25.98 seconds |
| Started | Jul 18 07:58:53 PM PDT 24 |
| Finished | Jul 18 07:59:20 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-37c32140-6c8f-44ed-905c-9f788a8b96d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164500993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .2164500993 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1224972313 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 64697623033 ps |
| CPU time | 1287.85 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 08:20:20 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-33e74f81-301c-4c4a-ab64-57ea4134a4dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224972313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1224972313 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.725827872 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 160757444 ps |
| CPU time | 18.11 seconds |
| Started | Jul 18 07:58:52 PM PDT 24 |
| Finished | Jul 18 07:59:12 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-0c49a478-668a-47c0-b408-8c7a6cc54507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725827872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .725827872 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.866845127 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 238899949 ps |
| CPU time | 23.3 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 07:59:15 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-debe6037-3ee7-4174-a409-2e051dec4d20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866845127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.866845127 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.4170185656 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 309812403 ps |
| CPU time | 28.51 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 07:59:21 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-d5e49cf9-8c7d-45ae-b836-823653a22560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170185656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.4170185656 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3182965172 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 62586500635 ps |
| CPU time | 683.72 seconds |
| Started | Jul 18 07:58:53 PM PDT 24 |
| Finished | Jul 18 08:10:18 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-65de70e9-cc36-4111-8842-cac2c1a84a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182965172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3182965172 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.4180124910 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 19577440806 ps |
| CPU time | 353.56 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 08:04:46 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-850af929-8c11-4f16-bc8c-31b489aa5591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180124910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.4180124910 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2689996289 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 325181068 ps |
| CPU time | 32.86 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 07:59:24 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-5c91a44d-5b02-4d58-8dab-c34d2574a5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689996289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2689996289 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.3722281099 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 209667134 ps |
| CPU time | 17.43 seconds |
| Started | Jul 18 07:58:52 PM PDT 24 |
| Finished | Jul 18 07:59:11 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b01b6e9b-7124-4c5b-952b-8af23f235565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722281099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.3722281099 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.3022722066 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 42577991 ps |
| CPU time | 6.81 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 07:58:59 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-41fa9c1e-94c4-45d6-9d50-edcd4ea3ac9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022722066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.3022722066 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.3648752842 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 5029245485 ps |
| CPU time | 57.25 seconds |
| Started | Jul 18 07:58:51 PM PDT 24 |
| Finished | Jul 18 07:59:50 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-8e49607e-6c1d-427b-b651-dc82aa9887da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648752842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.3648752842 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.3848638248 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 4659306388 ps |
| CPU time | 82.64 seconds |
| Started | Jul 18 07:58:52 PM PDT 24 |
| Finished | Jul 18 08:00:17 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-fb573ef5-6385-41b0-a012-95fbb6ae037f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848638248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.3848638248 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.939755024 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 36155720 ps |
| CPU time | 5.98 seconds |
| Started | Jul 18 07:58:53 PM PDT 24 |
| Finished | Jul 18 07:59:00 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-cd306d4e-6a97-4847-9906-3f4cb1a04629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939755024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delays .939755024 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1413454841 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 3630877732 ps |
| CPU time | 272.66 seconds |
| Started | Jul 18 07:59:25 PM PDT 24 |
| Finished | Jul 18 08:03:58 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-912ae2fa-7774-432a-a10f-6efa4c9c610b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413454841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1413454841 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.1086327952 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 2571402013 ps |
| CPU time | 76.84 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 08:00:40 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-caf112e8-9e86-4888-8b63-6f131f6323e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086327952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.1086327952 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3906992394 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 776855068 ps |
| CPU time | 227.34 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 08:03:09 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-5be8d87b-40a6-476e-a181-ea23b28aaf66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906992394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3906992394 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2891051949 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 489378471 ps |
| CPU time | 114.78 seconds |
| Started | Jul 18 07:59:17 PM PDT 24 |
| Finished | Jul 18 08:01:14 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-331d3b1d-72e0-4a46-a0db-98f4c94af8da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891051949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2891051949 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.2056981891 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 179937737 ps |
| CPU time | 23.38 seconds |
| Started | Jul 18 07:58:50 PM PDT 24 |
| Finished | Jul 18 07:59:15 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-dac2bcf1-6daf-4f75-9c00-b4cb7cfe501e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056981891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.2056981891 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.4153515088 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 2082026870 ps |
| CPU time | 78.94 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 08:00:42 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-0981fd31-ba5c-434f-9484-2eed2a06db3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153515088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .4153515088 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1408619503 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 13052853362 ps |
| CPU time | 245.85 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 08:03:26 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-034f1813-0484-4af8-8a93-4dc4370e661f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408619503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1408619503 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1346253451 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 1090305993 ps |
| CPU time | 44.4 seconds |
| Started | Jul 18 07:59:23 PM PDT 24 |
| Finished | Jul 18 08:00:09 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-69729a97-8346-4f37-9d16-04553315cd18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346253451 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1346253451 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.4117510549 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 321220567 ps |
| CPU time | 27.37 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 07:59:48 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-b1bc1531-2885-465f-b2e7-f9aab4095971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117510549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.4117510549 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.3660340824 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1434145724 ps |
| CPU time | 52.91 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 08:00:13 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b52d010a-89ab-4ab1-91cf-f0fa31f40372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660340824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.3660340824 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.2208338727 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 79314915230 ps |
| CPU time | 991.43 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 08:15:51 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-affe77e5-8bdf-4a05-b1a3-a35ff57930c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208338727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.2208338727 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1989290239 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 68449265060 ps |
| CPU time | 1296.35 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 08:20:58 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-d377d426-b412-4f07-93fc-cc75a9fea79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989290239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1989290239 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1193987882 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 349900158 ps |
| CPU time | 32.47 seconds |
| Started | Jul 18 07:59:17 PM PDT 24 |
| Finished | Jul 18 07:59:52 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-e46432bd-7be4-4b7e-adb3-90972c11679a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193987882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1193987882 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2601433179 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 1726778443 ps |
| CPU time | 51.32 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 08:00:13 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-a6432b79-9313-4156-8591-8fab557aad02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601433179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2601433179 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.3183822531 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 211060170 ps |
| CPU time | 9.14 seconds |
| Started | Jul 18 07:59:17 PM PDT 24 |
| Finished | Jul 18 07:59:28 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-eed5cf06-d8d8-41ff-bf22-8109e750e105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183822531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3183822531 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.283923170 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 8982661379 ps |
| CPU time | 101.21 seconds |
| Started | Jul 18 07:59:22 PM PDT 24 |
| Finished | Jul 18 08:01:05 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-fabbe167-d907-4ca3-bf83-824b9c7e538b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283923170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.283923170 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.3941403105 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 6882531306 ps |
| CPU time | 122.28 seconds |
| Started | Jul 18 07:59:16 PM PDT 24 |
| Finished | Jul 18 08:01:20 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-332e1ffc-e331-428e-960c-8f19ed51b826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941403105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.3941403105 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.882276418 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 47748098 ps |
| CPU time | 6.23 seconds |
| Started | Jul 18 07:59:16 PM PDT 24 |
| Finished | Jul 18 07:59:24 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e524ee37-cb61-479d-8b28-5052a79529e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882276418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .882276418 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2612636078 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 2518238426 ps |
| CPU time | 98.91 seconds |
| Started | Jul 18 07:59:16 PM PDT 24 |
| Finished | Jul 18 08:00:57 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-573b7473-13b0-49ac-b326-eac228f74a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612636078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2612636078 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.3649715755 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 8655269198 ps |
| CPU time | 332.49 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 08:04:56 PM PDT 24 |
| Peak memory | 576216 kb |
| Host | smart-d04dc10e-e8e5-4b4c-9ebb-6bca2a0a9a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649715755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.3649715755 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4276875900 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 3609758662 ps |
| CPU time | 183.18 seconds |
| Started | Jul 18 07:59:17 PM PDT 24 |
| Finished | Jul 18 08:02:22 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6e830457-c374-435e-9e89-858ee56ff85b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276875900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4276875900 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3439873887 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 15409905 ps |
| CPU time | 10.5 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 07:59:32 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-196d9a30-6aee-4b2a-ae37-810c0a9f53fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439873887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3439873887 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.4024015923 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 377400894 ps |
| CPU time | 18.78 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 07:59:39 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-64825b44-0611-4643-808f-8fc3ab20c548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024015923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.4024015923 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2561394092 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 1752954285 ps |
| CPU time | 78.6 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 08:00:42 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-2a60b080-a50d-47ca-a13f-21da992d902e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561394092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2561394092 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.2897257175 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 49562272507 ps |
| CPU time | 926.69 seconds |
| Started | Jul 18 07:59:22 PM PDT 24 |
| Finished | Jul 18 08:14:51 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-9dd4f6e6-0b0e-48cf-ab35-c8b77ba6d0b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897257175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.2897257175 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3425789329 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 298423204 ps |
| CPU time | 32.51 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 07:59:55 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-6245de11-5f0c-46aa-9725-d302adb3b1ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425789329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3425789329 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.4081577254 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 283833500 ps |
| CPU time | 11.25 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 07:59:35 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-cd9e54af-6dc8-4ee4-a638-851bfd8595ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081577254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.4081577254 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1613228417 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 391549270 ps |
| CPU time | 34.18 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 07:59:54 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-4abddace-e5e4-415c-97fa-f885b1868c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613228417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1613228417 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.868282959 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 34687891403 ps |
| CPU time | 359.79 seconds |
| Started | Jul 18 07:59:18 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-c7f84926-9437-4df9-9a57-cef9207beb5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868282959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.868282959 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.824415466 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 43050384158 ps |
| CPU time | 756.04 seconds |
| Started | Jul 18 07:59:22 PM PDT 24 |
| Finished | Jul 18 08:12:00 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c27f61bb-ab28-417d-b582-9ab6a5e3b259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824415466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.824415466 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1566278759 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 65046536 ps |
| CPU time | 8.07 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 07:59:29 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-177279e1-58ab-4a0d-8492-6c235397e6ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566278759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.1566278759 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.236272650 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 470460588 ps |
| CPU time | 35 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 07:59:57 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-4d32cc2e-3862-4584-87a1-ff3ea9107910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236272650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.236272650 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3915928287 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 41700587 ps |
| CPU time | 6.12 seconds |
| Started | Jul 18 07:59:20 PM PDT 24 |
| Finished | Jul 18 07:59:29 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-261ebb4d-3318-497e-9ef4-daa977698678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915928287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3915928287 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.549819130 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 9178228162 ps |
| CPU time | 107.35 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 08:01:09 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-38d7afdf-fd68-4513-a3f2-6211f1edfd88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549819130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.549819130 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.3085473013 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 3307124850 ps |
| CPU time | 56.51 seconds |
| Started | Jul 18 07:59:17 PM PDT 24 |
| Finished | Jul 18 08:00:16 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-4c78c4fb-8706-4272-a212-61f59a36f2cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085473013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.3085473013 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1141582630 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 38329344 ps |
| CPU time | 5.94 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 07:59:27 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-078ed8fc-1ce8-4d0e-8f9b-3de4a432c052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141582630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1141582630 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.1783898527 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 9105981909 ps |
| CPU time | 353.97 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 08:05:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-512f2048-87b2-4002-b101-3aef7cbd7229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783898527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.1783898527 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1917590469 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 5347239094 ps |
| CPU time | 199.09 seconds |
| Started | Jul 18 07:59:22 PM PDT 24 |
| Finished | Jul 18 08:02:43 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-1626bcc1-229e-46a0-b445-95cf835285b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917590469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1917590469 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1096822152 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2633690982 ps |
| CPU time | 296.73 seconds |
| Started | Jul 18 07:59:19 PM PDT 24 |
| Finished | Jul 18 08:04:18 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-917a2fe0-0b9d-47a7-9b3c-e4368dc609cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096822152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_al l_with_reset_error.1096822152 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2322549236 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 248008203 ps |
| CPU time | 27.65 seconds |
| Started | Jul 18 07:59:21 PM PDT 24 |
| Finished | Jul 18 07:59:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-44c9fdcf-eb31-47d1-919e-1810cb270b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322549236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.2322549236 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.1357020603 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 224410156 ps |
| CPU time | 16.59 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 07:59:56 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c013fa14-d736-45a1-97a3-dde14d0985bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357020603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .1357020603 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3355296954 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 73743215654 ps |
| CPU time | 1342.92 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 08:22:06 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d934b779-4da4-4ea1-b27b-73d04ebb57cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355296954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3355296954 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.2842688744 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 855725629 ps |
| CPU time | 35.8 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 08:00:18 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-1a7b040c-0a59-4248-b549-93844beac57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842688744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.2842688744 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.3174954997 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 539581082 ps |
| CPU time | 44.31 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:00:29 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-36d84dd6-3760-4a2f-82c0-6cc0303124e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174954997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3174954997 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2193574508 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 507436404 ps |
| CPU time | 20.02 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 07:59:59 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-4c0c61c6-0df7-49e2-a0b8-649dfd138bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193574508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2193574508 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2504337317 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 96104765114 ps |
| CPU time | 1079.17 seconds |
| Started | Jul 18 07:59:41 PM PDT 24 |
| Finished | Jul 18 08:17:41 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-5d2fb2b3-72ea-4052-a704-f68bd881809f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504337317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2504337317 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2659490245 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 60722583257 ps |
| CPU time | 1096.5 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 08:17:55 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-52806e08-3f33-432f-b519-3f10c3b5eac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659490245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2659490245 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.913431678 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 309754454 ps |
| CPU time | 28.54 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:00:13 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a97deca0-8055-4015-8864-e89aa533f048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913431678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_dela ys.913431678 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.3052590574 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 731684917 ps |
| CPU time | 23.75 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 08:00:06 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-2f8f6e26-5d3c-47a5-abcf-7b6e6d60e3b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052590574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3052590574 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.2589711576 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 42408522 ps |
| CPU time | 6.16 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 07:59:48 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-cbde304a-8784-48c6-8447-fc9b741267c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589711576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.2589711576 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.3350482015 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 6609168614 ps |
| CPU time | 71.98 seconds |
| Started | Jul 18 07:59:39 PM PDT 24 |
| Finished | Jul 18 08:00:52 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-70ed2bbc-3dbe-47b0-92e7-76c408b4aa61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350482015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.3350482015 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3476943671 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 3218580850 ps |
| CPU time | 56.1 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:00:37 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-cf0a9926-e970-42a2-81ed-b0bfe0464881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476943671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3476943671 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3885619203 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 50544330 ps |
| CPU time | 6.34 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 07:59:47 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-1ffa13da-dc1c-4758-9d70-f683d0135b10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885619203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.3885619203 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.1046472108 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 8626322104 ps |
| CPU time | 339.66 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 08:05:22 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-8f9526a3-adf9-4365-ba35-af3aa4cb7846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046472108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1046472108 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.74130078 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 579802006 ps |
| CPU time | 43.61 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:00:25 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-47c7bc11-ada3-4268-ae3a-838c8b5e9b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74130078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.74130078 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1870527409 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 19530844 ps |
| CPU time | 18.69 seconds |
| Started | Jul 18 07:59:51 PM PDT 24 |
| Finished | Jul 18 08:00:10 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-1816df03-32cf-42af-9fbd-6b339171e01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870527409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.1870527409 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.1057283048 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 3745771259 ps |
| CPU time | 460.83 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 08:07:19 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-41b4d258-dd80-41b7-be0c-70308d2272c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057283048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.1057283048 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1259600186 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 427558965 ps |
| CPU time | 21.73 seconds |
| Started | Jul 18 07:59:46 PM PDT 24 |
| Finished | Jul 18 08:00:08 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-114d0179-5452-41a9-bc1b-b1fd00ada9f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259600186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1259600186 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.3609234558 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2152097636 ps |
| CPU time | 82.85 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:01:04 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-bd376fa1-0295-49b1-8f4d-3d061146627c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609234558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .3609234558 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1344423940 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 83092298720 ps |
| CPU time | 1534.56 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:25:16 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-50583a04-8a57-4d77-8c15-b49da973e310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344423940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1344423940 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.1673663238 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 95406170 ps |
| CPU time | 12.81 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 07:59:56 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-938a7b24-4857-4501-97a0-074f706dab5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673663238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.1673663238 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.3600993938 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 361609465 ps |
| CPU time | 28.24 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:00:10 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-658db593-3538-4f86-bbc9-1c2d8770ba65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600993938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.3600993938 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1926680381 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 921070609 ps |
| CPU time | 34.87 seconds |
| Started | Jul 18 07:59:43 PM PDT 24 |
| Finished | Jul 18 08:00:19 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-8ee2a31b-09c6-4748-a385-58051cdd73c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926680381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1926680381 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3214021592 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 31899222480 ps |
| CPU time | 388.76 seconds |
| Started | Jul 18 07:59:43 PM PDT 24 |
| Finished | Jul 18 08:06:12 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-09c45381-6489-444d-8759-d7b5cb3b1376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214021592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3214021592 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1784949423 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 60456303990 ps |
| CPU time | 1137.31 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 08:18:36 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-c0478585-6a6a-4840-bb4b-8b19d98ecd97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784949423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1784949423 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.2202103393 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 395633786 ps |
| CPU time | 35.25 seconds |
| Started | Jul 18 07:59:41 PM PDT 24 |
| Finished | Jul 18 08:00:17 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-3e366c56-8f83-4388-ab32-1797f376807e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202103393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.2202103393 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.4116710042 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 2325954705 ps |
| CPU time | 79.22 seconds |
| Started | Jul 18 07:59:39 PM PDT 24 |
| Finished | Jul 18 08:00:59 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-541f0c20-99bd-4ccf-853d-ce576ce8bf37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116710042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.4116710042 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.901916236 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 36964593 ps |
| CPU time | 5.86 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 07:59:47 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-65834240-7113-425f-871f-0443263e72dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901916236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.901916236 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1255457957 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 8696806413 ps |
| CPU time | 98.37 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:01:23 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-375343e6-acd6-4907-8a6d-44a49337ec91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255457957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1255457957 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.484893467 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 6360317659 ps |
| CPU time | 107.9 seconds |
| Started | Jul 18 07:59:41 PM PDT 24 |
| Finished | Jul 18 08:01:30 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8038c326-5896-4e2c-8caa-f4f6fe31f1e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484893467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.484893467 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.1405260754 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 48006846 ps |
| CPU time | 5.98 seconds |
| Started | Jul 18 07:59:43 PM PDT 24 |
| Finished | Jul 18 07:59:49 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-d9592f83-8325-4cb5-9eed-361c1de29793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405260754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.1405260754 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2566101240 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 820281990 ps |
| CPU time | 65.58 seconds |
| Started | Jul 18 07:59:39 PM PDT 24 |
| Finished | Jul 18 08:00:46 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-83e77463-3a0b-4695-a2a5-e4797021eb8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566101240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2566101240 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2053052143 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 16120306848 ps |
| CPU time | 597.47 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:09:38 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-8644d0c4-b62e-48bc-a403-a4a07f15030e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053052143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.2053052143 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.3459595216 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 528090700 ps |
| CPU time | 186.71 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:02:48 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-4859d041-0577-436d-93e0-024f98c6de99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459595216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.3459595216 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1671068769 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 293100906 ps |
| CPU time | 125.26 seconds |
| Started | Jul 18 07:59:39 PM PDT 24 |
| Finished | Jul 18 08:01:46 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-1fa8dfdb-6e22-46ad-98a9-28359c6891d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671068769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1671068769 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.4260079695 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 700424286 ps |
| CPU time | 33.54 seconds |
| Started | Jul 18 07:59:51 PM PDT 24 |
| Finished | Jul 18 08:00:26 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-c630cf8c-4f73-4cdd-8edc-25559d55050e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260079695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.4260079695 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1045984471 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 1181769246 ps |
| CPU time | 86.79 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:01:11 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-cf3bebb2-5efc-4fc8-a614-175dd30c0158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045984471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1045984471 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.925159532 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 159297030371 ps |
| CPU time | 3028.32 seconds |
| Started | Jul 18 07:59:45 PM PDT 24 |
| Finished | Jul 18 08:50:14 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-3760c63b-e59e-4316-b213-59d370eec73c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925159532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_d evice_slow_rsp.925159532 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2660048913 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 671473396 ps |
| CPU time | 32.24 seconds |
| Started | Jul 18 07:59:47 PM PDT 24 |
| Finished | Jul 18 08:00:20 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-4c19cd15-aeda-413e-9917-bba6eae6f742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660048913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2660048913 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.3206388680 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 413259169 ps |
| CPU time | 36.26 seconds |
| Started | Jul 18 07:59:47 PM PDT 24 |
| Finished | Jul 18 08:00:24 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-5136f7dc-4e72-48c6-9997-3900d9f63eb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206388680 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.3206388680 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.807311039 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 347840060 ps |
| CPU time | 31.81 seconds |
| Started | Jul 18 07:59:43 PM PDT 24 |
| Finished | Jul 18 08:00:16 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-56896612-d4c9-477a-9b15-66b3af53cdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807311039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.807311039 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3427340886 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 103767526348 ps |
| CPU time | 1285.5 seconds |
| Started | Jul 18 07:59:38 PM PDT 24 |
| Finished | Jul 18 08:21:05 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-67c22fff-b917-4cd5-a96c-24d2a98bd152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427340886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3427340886 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3069437162 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 20943461031 ps |
| CPU time | 379.8 seconds |
| Started | Jul 18 07:59:42 PM PDT 24 |
| Finished | Jul 18 08:06:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-ab1ffe8b-fc3d-4ba6-a055-a9d8067a241d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069437162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3069437162 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.3682115737 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 478393689 ps |
| CPU time | 39.49 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:00:21 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-ae309869-53ed-48db-bca8-3c5acd6a98f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682115737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.3682115737 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.1096377390 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 2131720073 ps |
| CPU time | 66.08 seconds |
| Started | Jul 18 07:59:50 PM PDT 24 |
| Finished | Jul 18 08:00:57 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-dbf5eddc-3fd4-4c77-b55c-4f86cb52cfeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096377390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1096377390 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.1544053420 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 180464227 ps |
| CPU time | 8.93 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 07:59:53 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-c5c164a7-be9f-4cfa-a5cf-6ecc8c93f46c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544053420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1544053420 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.864782370 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 8415420734 ps |
| CPU time | 94.48 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:01:19 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-0782becf-2709-4d4c-b26a-8b07cf5ae18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864782370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.864782370 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1130445489 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 4501869247 ps |
| CPU time | 79.26 seconds |
| Started | Jul 18 07:59:44 PM PDT 24 |
| Finished | Jul 18 08:01:04 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-ab0af02d-9ee1-4ee7-a4f1-1f6bfc28eb78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130445489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1130445489 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.2164771500 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 56486706 ps |
| CPU time | 7.43 seconds |
| Started | Jul 18 07:59:47 PM PDT 24 |
| Finished | Jul 18 07:59:55 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-04f8e4ba-633a-426e-ade3-974cd040c813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164771500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.2164771500 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2279232221 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 188633767 ps |
| CPU time | 16.34 seconds |
| Started | Jul 18 07:59:47 PM PDT 24 |
| Finished | Jul 18 08:00:04 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-82b9c47c-c5f0-4a37-b745-78ba7cd6bc08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279232221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2279232221 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3032225217 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 16037660300 ps |
| CPU time | 590.18 seconds |
| Started | Jul 18 07:59:48 PM PDT 24 |
| Finished | Jul 18 08:09:39 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-f0020a71-b1b5-4e0a-adcb-5d63301d0b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032225217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3032225217 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.306468866 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 6284853217 ps |
| CPU time | 711.9 seconds |
| Started | Jul 18 07:59:48 PM PDT 24 |
| Finished | Jul 18 08:11:41 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ec1bc485-807b-4e31-9c75-05aa2a9c926c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306468866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_ with_rand_reset.306468866 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2419031554 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 112071041 ps |
| CPU time | 34.71 seconds |
| Started | Jul 18 07:59:48 PM PDT 24 |
| Finished | Jul 18 08:00:24 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-9284a745-2249-4605-982c-7b61f13c832f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419031554 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2419031554 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.215492860 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 831084948 ps |
| CPU time | 35.37 seconds |
| Started | Jul 18 07:59:47 PM PDT 24 |
| Finished | Jul 18 08:00:23 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e7946411-6647-4012-b70d-67f0abb21cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215492860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.215492860 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.262452954 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 608429944 ps |
| CPU time | 50.43 seconds |
| Started | Jul 18 08:00:14 PM PDT 24 |
| Finished | Jul 18 08:01:05 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-fa0a8d70-4ca9-4ae2-95d1-ad0f189e51e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262452954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device. 262452954 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3106809080 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 143835331096 ps |
| CPU time | 2695.78 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:44:54 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c8395cbc-0b16-42c6-92df-723ab2ebacc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106809080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3106809080 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.649181516 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 176667366 ps |
| CPU time | 21.07 seconds |
| Started | Jul 18 07:59:59 PM PDT 24 |
| Finished | Jul 18 08:00:21 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-4a0ec97c-b207-4191-895f-2b4947df8fd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649181516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .649181516 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.562189281 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 1697265336 ps |
| CPU time | 53.61 seconds |
| Started | Jul 18 08:00:02 PM PDT 24 |
| Finished | Jul 18 08:00:56 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-a6f1e9a2-c5a6-49cc-b180-eb8f6da628a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562189281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.562189281 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.3185025036 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2458075411 ps |
| CPU time | 93.57 seconds |
| Started | Jul 18 08:00:07 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-58bad3bc-68ed-40a2-96c5-891f1a59e040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185025036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.3185025036 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.469707671 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 60979879180 ps |
| CPU time | 666.91 seconds |
| Started | Jul 18 07:59:59 PM PDT 24 |
| Finished | Jul 18 08:11:06 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-ce3ff416-0c2d-4a3e-9d76-e524d6c66ec0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469707671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.469707671 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.4020889066 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 2293963504 ps |
| CPU time | 38.26 seconds |
| Started | Jul 18 08:00:13 PM PDT 24 |
| Finished | Jul 18 08:00:52 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-780cb3ab-bc0e-493d-97fe-1aa190a836d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020889066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.4020889066 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1046208464 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 63686555 ps |
| CPU time | 7.97 seconds |
| Started | Jul 18 08:00:14 PM PDT 24 |
| Finished | Jul 18 08:00:23 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-77cf8a8e-58ea-456b-8ae1-3df70fcfa80c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046208464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.1046208464 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.743760653 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 484183721 ps |
| CPU time | 33.83 seconds |
| Started | Jul 18 07:59:58 PM PDT 24 |
| Finished | Jul 18 08:00:33 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-508004e0-cc7a-44e1-adcc-d8298c797a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743760653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.743760653 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.303966105 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 176636320 ps |
| CPU time | 8.11 seconds |
| Started | Jul 18 07:59:48 PM PDT 24 |
| Finished | Jul 18 07:59:57 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-b74216b7-25e7-4837-b796-4cdddb4067a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303966105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.303966105 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2026699143 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 11196053623 ps |
| CPU time | 125.65 seconds |
| Started | Jul 18 07:59:40 PM PDT 24 |
| Finished | Jul 18 08:01:47 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d0a0c1f3-70e9-405b-a7ad-69d220ec06d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026699143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2026699143 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2165789071 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 4691212243 ps |
| CPU time | 84.19 seconds |
| Started | Jul 18 07:59:58 PM PDT 24 |
| Finished | Jul 18 08:01:23 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a2614dc0-e9a8-48a8-be48-0275f0d4764e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165789071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2165789071 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.414568708 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 55970680 ps |
| CPU time | 6.6 seconds |
| Started | Jul 18 07:59:48 PM PDT 24 |
| Finished | Jul 18 07:59:56 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-cfdc97dc-d20b-44db-87ec-cd949782d4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414568708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .414568708 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.3384180253 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 2394109942 ps |
| CPU time | 114.35 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:01:52 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-cd82722a-5994-48c8-8a78-2efda0047678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384180253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3384180253 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.100708287 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 2640265679 ps |
| CPU time | 180.97 seconds |
| Started | Jul 18 08:00:13 PM PDT 24 |
| Finished | Jul 18 08:03:15 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-fcbf0667-5ea2-4d45-b610-afdb2bb39fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100708287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.100708287 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.88803733 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 8016040168 ps |
| CPU time | 446.22 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:07:25 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-f73f9dc0-701a-430f-8a31-1ac456c310a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88803733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_ with_reset_error.88803733 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.1122875237 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 767708480 ps |
| CPU time | 28.25 seconds |
| Started | Jul 18 07:59:56 PM PDT 24 |
| Finished | Jul 18 08:00:26 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-cb2b106b-2ada-4110-bd3c-3c1ad4c93fa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122875237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.1122875237 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.384015187 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 780795436 ps |
| CPU time | 39.19 seconds |
| Started | Jul 18 08:00:00 PM PDT 24 |
| Finished | Jul 18 08:00:40 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-baa254bb-77ec-445c-9c15-81e2a68a17a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384015187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device. 384015187 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3518313584 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 29997641196 ps |
| CPU time | 558.73 seconds |
| Started | Jul 18 07:59:59 PM PDT 24 |
| Finished | Jul 18 08:09:19 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-c8cd5bf1-a685-4a00-95ca-9233ec5f978b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518313584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3518313584 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2661446104 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 432491122 ps |
| CPU time | 18.17 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:00:16 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a61a234d-4504-45f8-96bc-7a2a0a01ea1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661446104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.2661446104 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1661711656 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 1842147809 ps |
| CPU time | 60.86 seconds |
| Started | Jul 18 07:59:58 PM PDT 24 |
| Finished | Jul 18 08:01:00 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-fdc60e6d-4a87-4708-8dcc-d66e0c89be1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661711656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1661711656 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.3048926836 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 222707995 ps |
| CPU time | 22.7 seconds |
| Started | Jul 18 08:00:01 PM PDT 24 |
| Finished | Jul 18 08:00:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-333e6188-cf0b-4b8a-845c-664c340d7773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048926836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.3048926836 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.1522719661 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 58378303112 ps |
| CPU time | 664.99 seconds |
| Started | Jul 18 08:00:02 PM PDT 24 |
| Finished | Jul 18 08:11:08 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-f828462a-a73e-46d1-aa6b-d9bb5695cb33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522719661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.1522719661 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.1370059293 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 45606138276 ps |
| CPU time | 859.76 seconds |
| Started | Jul 18 08:00:13 PM PDT 24 |
| Finished | Jul 18 08:14:35 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-ae56fed1-ed97-4d20-a23d-eb03ad8bd582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370059293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.1370059293 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1907525222 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 290960597 ps |
| CPU time | 27.75 seconds |
| Started | Jul 18 07:59:56 PM PDT 24 |
| Finished | Jul 18 08:00:25 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-bba3e48e-51fd-425e-bf49-c37c2e3cd5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907525222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.1907525222 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3694560448 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 394223305 ps |
| CPU time | 13.74 seconds |
| Started | Jul 18 08:00:02 PM PDT 24 |
| Finished | Jul 18 08:00:16 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-082771df-648b-4317-82f3-16a99c04c896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694560448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3694560448 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.2954550957 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 164180085 ps |
| CPU time | 8.11 seconds |
| Started | Jul 18 08:00:13 PM PDT 24 |
| Finished | Jul 18 08:00:22 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-9059ce71-482b-40c8-8183-bc1c23dacdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954550957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.2954550957 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.2632167745 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 6607228222 ps |
| CPU time | 76.2 seconds |
| Started | Jul 18 07:59:58 PM PDT 24 |
| Finished | Jul 18 08:01:15 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-8afc086c-6779-492f-be1c-67d7e3f00b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632167745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.2632167745 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.342815225 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 4550591108 ps |
| CPU time | 72.68 seconds |
| Started | Jul 18 07:59:59 PM PDT 24 |
| Finished | Jul 18 08:01:13 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-dc4265ca-cbc6-4966-ae43-459a447087c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342815225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.342815225 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2991850031 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 47465180 ps |
| CPU time | 6.21 seconds |
| Started | Jul 18 08:00:01 PM PDT 24 |
| Finished | Jul 18 08:00:08 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7ea914f7-e80f-41aa-a7f4-fc602c5f989d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991850031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2991850031 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.395835238 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 5654972420 ps |
| CPU time | 208.77 seconds |
| Started | Jul 18 08:00:07 PM PDT 24 |
| Finished | Jul 18 08:03:36 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-980cc5d7-a824-4405-a109-38707354993c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395835238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.395835238 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1757996533 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 14908704134 ps |
| CPU time | 621.76 seconds |
| Started | Jul 18 07:59:58 PM PDT 24 |
| Finished | Jul 18 08:10:21 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-04a63dc4-cf66-4210-8cd2-d680366655f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757996533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1757996533 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.4106356731 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 7718358048 ps |
| CPU time | 324.98 seconds |
| Started | Jul 18 08:00:02 PM PDT 24 |
| Finished | Jul 18 08:05:27 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-107ee938-e338-4435-9aff-c85bd62b59f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106356731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.4106356731 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1203301789 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 3844121622 ps |
| CPU time | 307.08 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:05:05 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-75254296-0b26-4a2b-99e3-c51d7213a027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203301789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.1203301789 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.728932348 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 244960857 ps |
| CPU time | 27.6 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:00:25 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f2876bb0-bb3b-49be-b2e5-2b9c6525d75a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728932348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.728932348 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3531555839 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 7476767257 ps |
| CPU time | 441.66 seconds |
| Started | Jul 18 07:44:14 PM PDT 24 |
| Finished | Jul 18 07:51:37 PM PDT 24 |
| Peak memory | 636540 kb |
| Host | smart-7f84a1cf-4417-4186-9327-4d6caf08050a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531555839 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.3531555839 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.3145965288 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 5799866114 ps |
| CPU time | 548.99 seconds |
| Started | Jul 18 07:44:11 PM PDT 24 |
| Finished | Jul 18 07:53:21 PM PDT 24 |
| Peak memory | 599412 kb |
| Host | smart-557be0d9-b9ba-4e24-a415-9e049a2a2468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145965288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.3145965288 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3516575563 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 31161690536 ps |
| CPU time | 3871.16 seconds |
| Started | Jul 18 07:44:13 PM PDT 24 |
| Finished | Jul 18 08:48:46 PM PDT 24 |
| Peak memory | 593564 kb |
| Host | smart-67c3f981-b5a8-4997-b27c-71e2c0127093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516575563 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3516575563 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.704414905 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4314214228 ps |
| CPU time | 299.38 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:49:12 PM PDT 24 |
| Peak memory | 603712 kb |
| Host | smart-c18b0c2a-d06f-4420-abd2-9a03220291a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704414905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.704414905 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.3653224792 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 750543182 ps |
| CPU time | 28.95 seconds |
| Started | Jul 18 07:44:17 PM PDT 24 |
| Finished | Jul 18 07:44:47 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-6f9875bd-9076-42f6-95ac-3dcc14edd8fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653224792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 3653224792 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.84557485 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 115896388437 ps |
| CPU time | 2204.82 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 08:21:02 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0df2f500-7a1d-400b-ab17-e39354c0ed1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84557485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_dev ice_slow_rsp.84557485 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1661838920 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 222390779 ps |
| CPU time | 11.64 seconds |
| Started | Jul 18 07:44:17 PM PDT 24 |
| Finished | Jul 18 07:44:30 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d8631178-8eba-4856-9c64-9f60ae2208ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661838920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1661838920 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1893322402 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 160620891 ps |
| CPU time | 16.01 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:44:33 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-fdef210a-8510-4ad7-863a-469c3fc886d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893322402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1893322402 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.3713919080 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 1356039407 ps |
| CPU time | 56.3 seconds |
| Started | Jul 18 07:44:14 PM PDT 24 |
| Finished | Jul 18 07:45:11 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-0033fc02-dc76-425a-9021-55030122c98a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713919080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.3713919080 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.2164453579 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 49828714686 ps |
| CPU time | 539.91 seconds |
| Started | Jul 18 07:44:15 PM PDT 24 |
| Finished | Jul 18 07:53:16 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-43caac48-cfe9-4bac-8281-7385b01d9a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164453579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.2164453579 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3301818982 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 12346180743 ps |
| CPU time | 205.13 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:47:42 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-7e38a433-eabf-4266-9307-0a61007577a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301818982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3301818982 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1575243041 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 421495730 ps |
| CPU time | 36.97 seconds |
| Started | Jul 18 07:44:15 PM PDT 24 |
| Finished | Jul 18 07:44:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-3b334f96-0197-4f6f-a743-c381bfdaaead |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575243041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.1575243041 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.3739997501 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1739062364 ps |
| CPU time | 59.75 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:45:17 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-41098c7f-0bb7-4e05-bf46-c90ebc4256c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739997501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.3739997501 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3267555561 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 199561730 ps |
| CPU time | 9.22 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:44:23 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-57327666-c231-4ca9-90a6-d95a143d9182 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267555561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3267555561 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.407030467 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 4742077836 ps |
| CPU time | 54.03 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:45:07 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3690eb9e-66f2-4d0e-a576-a5edbdbbd179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407030467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.407030467 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.351036621 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 5285309571 ps |
| CPU time | 98.19 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:45:51 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-6cf28ce2-cba9-4e12-bc58-81dd49510f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351036621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.351036621 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.647226370 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 41628776 ps |
| CPU time | 6.32 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:44:20 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-4b401e07-ab9b-43e2-a119-b2ad1ff461ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647226370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 647226370 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.4218155543 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 2434693272 ps |
| CPU time | 71.53 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:45:29 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e0fcf687-5c77-4482-a96f-2d4b61a605ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218155543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4218155543 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.4085840000 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 25493104870 ps |
| CPU time | 881.1 seconds |
| Started | Jul 18 07:44:16 PM PDT 24 |
| Finished | Jul 18 07:58:58 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-eccbcbe5-10f5-4d3c-b700-6c3c183a4c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085840000 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.4085840000 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.926834890 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 289473942 ps |
| CPU time | 82.25 seconds |
| Started | Jul 18 07:44:15 PM PDT 24 |
| Finished | Jul 18 07:45:38 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-f8f163a2-fdd3-4be2-a6a6-e08c92c5a399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926834890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.926834890 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.4071328483 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 266207078 ps |
| CPU time | 92.14 seconds |
| Started | Jul 18 07:44:12 PM PDT 24 |
| Finished | Jul 18 07:45:46 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-53786556-eaf5-47c7-ae70-6c518c458375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071328483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.4071328483 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1545551565 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 75731411 ps |
| CPU time | 6.6 seconds |
| Started | Jul 18 07:44:17 PM PDT 24 |
| Finished | Jul 18 07:44:25 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d43823fd-af9d-4ca1-8abd-a7065131d21b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545551565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1545551565 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2324719118 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2400918903 ps |
| CPU time | 109.67 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:02:11 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a37a31f8-dab3-49ef-a036-84b5d857a64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324719118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2324719118 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3216371608 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 91268969904 ps |
| CPU time | 1795.31 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:30:17 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-5c79aaf0-eb5f-454d-a044-8fd64e169d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216371608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.3216371608 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.313808014 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 303525341 ps |
| CPU time | 33.38 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:00:54 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-1e3cbbc2-9cd0-4585-bf8d-9da9a74ef065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313808014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .313808014 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.874106099 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 1998733052 ps |
| CPU time | 77.72 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:01:39 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-fd0400de-c7fd-4b4d-8681-565942da7cdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874106099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.874106099 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2852210309 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 423008796 ps |
| CPU time | 37.24 seconds |
| Started | Jul 18 08:00:31 PM PDT 24 |
| Finished | Jul 18 08:01:09 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-1be894f6-0826-4454-9584-8fdebfc5614d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852210309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2852210309 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.176539148 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 17767455725 ps |
| CPU time | 206.72 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:03:48 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-8d6c7bf9-3b28-495c-9ffb-925767322c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176539148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.176539148 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2593507120 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 48341258459 ps |
| CPU time | 863.08 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:14:42 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-a33c55a2-712a-48c5-91f3-78dd12a87a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593507120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2593507120 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.4121182602 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 433171259 ps |
| CPU time | 38.39 seconds |
| Started | Jul 18 08:00:23 PM PDT 24 |
| Finished | Jul 18 08:01:02 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-a1fc8236-e367-41be-952c-e8076ef86b33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121182602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.4121182602 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.3995608295 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 492542256 ps |
| CPU time | 16.65 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:00:38 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-762b0fa1-ab5c-44a4-8167-5b85add54b79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995608295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3995608295 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.669007197 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 53108691 ps |
| CPU time | 6.75 seconds |
| Started | Jul 18 07:59:59 PM PDT 24 |
| Finished | Jul 18 08:00:07 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-646bfe85-55c8-450f-b0d5-f7e6516f084d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669007197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.669007197 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.577476973 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 8864850680 ps |
| CPU time | 98.18 seconds |
| Started | Jul 18 08:00:07 PM PDT 24 |
| Finished | Jul 18 08:01:46 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-724708b3-1881-4b51-8b52-c5858866a926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577476973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.577476973 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1423562532 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 5455324326 ps |
| CPU time | 96.9 seconds |
| Started | Jul 18 07:59:57 PM PDT 24 |
| Finished | Jul 18 08:01:35 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-9fbb885a-cd3d-4113-8961-8b3c57fe6d70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423562532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1423562532 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.1917884416 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 40018258 ps |
| CPU time | 5.77 seconds |
| Started | Jul 18 08:00:13 PM PDT 24 |
| Finished | Jul 18 08:00:19 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-ae27ad3b-6995-47c3-9f3a-a736094a5840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917884416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.1917884416 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.382237021 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 657702199 ps |
| CPU time | 49.98 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:01:10 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-3cddf9a0-ca80-4729-8bd0-4dd3ab36d0f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382237021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.382237021 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.2722292752 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 10449278902 ps |
| CPU time | 323.05 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:05:44 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-6f2d8a45-42e6-4a7b-8088-e5f79bfb8401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722292752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.2722292752 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.3758736671 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 16336950 ps |
| CPU time | 12.11 seconds |
| Started | Jul 18 08:00:22 PM PDT 24 |
| Finished | Jul 18 08:00:36 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6eb2345f-63c4-4b92-8242-b840cd6d9beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758736671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.3758736671 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.3693027021 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 871331788 ps |
| CPU time | 198.44 seconds |
| Started | Jul 18 08:00:21 PM PDT 24 |
| Finished | Jul 18 08:03:41 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d81fbe81-0be0-4d20-8563-73ffdc5d40f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693027021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.3693027021 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2873602105 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 359597728 ps |
| CPU time | 17.46 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:00:39 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-51939f07-e217-4192-a36d-d01adb7a7dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873602105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2873602105 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.300122889 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 345524550 ps |
| CPU time | 31.3 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:00:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6120ba7d-193e-4562-85ed-e55867a0f654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300122889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device. 300122889 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2940909773 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 14797303430 ps |
| CPU time | 264.44 seconds |
| Started | Jul 18 08:00:22 PM PDT 24 |
| Finished | Jul 18 08:04:47 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-bfbc1a52-623c-4fce-8d93-4c87e252f51a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940909773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2940909773 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2302000892 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 380106176 ps |
| CPU time | 15.43 seconds |
| Started | Jul 18 08:00:21 PM PDT 24 |
| Finished | Jul 18 08:00:38 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-940797bd-1b3e-43e8-8226-ca62f62b9ad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302000892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2302000892 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.2211987704 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 38928485 ps |
| CPU time | 6.58 seconds |
| Started | Jul 18 08:00:24 PM PDT 24 |
| Finished | Jul 18 08:00:31 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-7c0df422-bc9e-4937-be78-26d69c399f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211987704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.2211987704 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.4099672836 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 301359086 ps |
| CPU time | 26.5 seconds |
| Started | Jul 18 08:00:21 PM PDT 24 |
| Finished | Jul 18 08:00:49 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-27db3ef8-ea76-4a2a-94ad-b68705b1a201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099672836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.4099672836 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.301058545 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 90299533432 ps |
| CPU time | 1103.53 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:18:46 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-8263d81d-b832-4083-a10f-c77270a2fbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301058545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.301058545 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.4093622661 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 62510410760 ps |
| CPU time | 1185.31 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:20:06 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-ba56c9dc-0481-4013-bc3b-ff49207e0c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093622661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.4093622661 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1672685681 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 182723638 ps |
| CPU time | 19.59 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:00:41 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-2fee6b68-839a-434f-aeee-22c75e156638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672685681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1672685681 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.4005926134 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 700504609 ps |
| CPU time | 22.7 seconds |
| Started | Jul 18 08:00:22 PM PDT 24 |
| Finished | Jul 18 08:00:46 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-3103bd57-440e-4a59-b09a-cd738c753485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005926134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.4005926134 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3085118661 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 218285870 ps |
| CPU time | 9.61 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:00:31 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-c6193a79-bd44-48ef-9f1d-0a13dbd37e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085118661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3085118661 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.4116717430 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 10149444833 ps |
| CPU time | 112.08 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:02:13 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-96326d9e-a933-48e8-99a9-1bcf71d5bf1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116717430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.4116717430 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1895027740 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 5570084200 ps |
| CPU time | 96.02 seconds |
| Started | Jul 18 08:00:23 PM PDT 24 |
| Finished | Jul 18 08:02:00 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1df893d2-9861-431e-9ec0-467c7b02c2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895027740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1895027740 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.2325732948 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 40582049 ps |
| CPU time | 5.83 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:00:28 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-0dde0ed7-bcbd-4caa-9e15-8651e877a893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325732948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.2325732948 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.3322497937 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 3904592387 ps |
| CPU time | 320.29 seconds |
| Started | Jul 18 08:00:19 PM PDT 24 |
| Finished | Jul 18 08:05:41 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5d087eb4-bd63-40b3-bc49-f7c2c1a31224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322497937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3322497937 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.262157006 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 5515708179 ps |
| CPU time | 233.07 seconds |
| Started | Jul 18 08:00:43 PM PDT 24 |
| Finished | Jul 18 08:04:37 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-806eace3-f36c-40ae-a0a3-1e85ec3b0803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262157006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.262157006 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2947394783 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 154181858 ps |
| CPU time | 52.08 seconds |
| Started | Jul 18 08:00:20 PM PDT 24 |
| Finished | Jul 18 08:01:14 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1b2c40d5-750f-4271-9d1a-38b41e25f4a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947394783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2947394783 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3038795305 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 6493196567 ps |
| CPU time | 440.44 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:08:01 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a07c0af3-a595-417d-a8ae-568efc27c1f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038795305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3038795305 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.618888221 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 326101160 ps |
| CPU time | 16.86 seconds |
| Started | Jul 18 08:00:22 PM PDT 24 |
| Finished | Jul 18 08:00:40 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-588b251a-5e29-41ea-8429-9626e2420515 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618888221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.618888221 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.365698149 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 541680526 ps |
| CPU time | 19.46 seconds |
| Started | Jul 18 08:00:51 PM PDT 24 |
| Finished | Jul 18 08:01:11 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-67118c54-5d84-4a86-8905-e400a63c1571 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365698149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 365698149 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2440037006 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 92830974879 ps |
| CPU time | 1763.12 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:30:05 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-e1c6207b-7ae1-4494-bf08-c04a1293f158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440037006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.2440037006 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2805141533 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 411238982 ps |
| CPU time | 17.57 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:01:00 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-0aa2340a-86d9-4036-9957-b2a9150726b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805141533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2805141533 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.3858513724 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 135281040 ps |
| CPU time | 14.38 seconds |
| Started | Jul 18 08:00:44 PM PDT 24 |
| Finished | Jul 18 08:00:58 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-cd30ad1b-3e30-4e8e-bf66-d3183df5e03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858513724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.3858513724 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2095213946 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 43572879009 ps |
| CPU time | 483.28 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:08:45 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0b03d12f-d091-42a2-82f4-5f9d74213733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095213946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2095213946 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3929397051 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 16342576880 ps |
| CPU time | 280.97 seconds |
| Started | Jul 18 08:00:39 PM PDT 24 |
| Finished | Jul 18 08:05:21 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-711b3b4b-62bb-46a9-8d1d-fb5705948503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929397051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3929397051 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.245833178 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 116129114 ps |
| CPU time | 13.78 seconds |
| Started | Jul 18 08:00:51 PM PDT 24 |
| Finished | Jul 18 08:01:05 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-2c516987-5871-4fc5-a68c-a41a9f8f6267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245833178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_dela ys.245833178 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.3096815008 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 529572142 ps |
| CPU time | 37.73 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:01:21 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e05a8e58-3b12-4281-a065-16db798738cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096815008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.3096815008 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1423555687 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 218093240 ps |
| CPU time | 9.31 seconds |
| Started | Jul 18 08:00:51 PM PDT 24 |
| Finished | Jul 18 08:01:01 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-6652118c-7194-41b8-a19e-efd613ead81a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423555687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1423555687 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.682566500 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 4550780053 ps |
| CPU time | 79.7 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:02:02 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-5ee01f07-1e94-4aea-9251-52c85815a159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682566500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.682566500 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2282050601 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 51541165 ps |
| CPU time | 6.7 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:00:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-c6564b07-9220-474f-a75e-e5b68d60c08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282050601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.2282050601 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3916762555 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 5036296090 ps |
| CPU time | 199.87 seconds |
| Started | Jul 18 08:00:43 PM PDT 24 |
| Finished | Jul 18 08:04:04 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3f3421db-732b-46dd-a56b-b6f03086472d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916762555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3916762555 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2704344167 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 1975502794 ps |
| CPU time | 72.8 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:01:55 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f4b23412-0622-49c2-8019-39bb6178f37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704344167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2704344167 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.4092779648 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 9434911219 ps |
| CPU time | 596.19 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:10:39 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-e9da0f6c-d58c-46a2-b702-16e1339f2f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092779648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.4092779648 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3855588750 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 6606401766 ps |
| CPU time | 617.55 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:11:01 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-991ccbba-1ae8-4027-9e73-759799cbba73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855588750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3855588750 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.4012829607 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 1372664212 ps |
| CPU time | 62.56 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:01:45 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-74b8f63a-c40b-424d-a737-8ad408101462 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012829607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.4012829607 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2685644399 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 577023865 ps |
| CPU time | 49.07 seconds |
| Started | Jul 18 08:00:39 PM PDT 24 |
| Finished | Jul 18 08:01:29 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-aa69051e-dc89-4fd0-9182-a982efa9667f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685644399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2685644399 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3659520192 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 81662470117 ps |
| CPU time | 1547.49 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:26:31 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-fa33fdea-f755-492b-b44c-beb4831a76cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659520192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3659520192 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.627185758 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 245219218 ps |
| CPU time | 29.54 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:01:12 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-00dd0f31-c1b6-4fea-83a6-9ff1c9013f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627185758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .627185758 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.2609910800 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 87091922 ps |
| CPU time | 10.34 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:00:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f949fd07-ad1a-48e2-a6f9-4ced4a3d928a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609910800 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.2609910800 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.920104682 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 42638254 ps |
| CPU time | 6.37 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:00:47 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-07d12ee0-472e-4a32-b6ee-ac3547566918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920104682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.920104682 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.2746371324 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 14093360640 ps |
| CPU time | 153.94 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:03:17 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-71aef28e-70bb-4a1c-a836-550b4b4e73b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746371324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.2746371324 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.837759158 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 9291828356 ps |
| CPU time | 172.11 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:03:35 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-6e7e5e28-2674-4f3c-a094-b7eb79d0317b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837759158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.837759158 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1800598127 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 379459797 ps |
| CPU time | 30.36 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:01:14 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-eaeb10bf-495f-4eb3-81df-0c7e7b55b08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800598127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1800598127 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.1232955205 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 2465389498 ps |
| CPU time | 68.35 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:01:50 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-a8273346-896f-42fa-9732-52a5bd6d9b62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232955205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.1232955205 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.1068204805 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 221530084 ps |
| CPU time | 9.56 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:00:53 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-43b20882-674b-416b-a7fb-979061e38578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068204805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.1068204805 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.3106804557 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 5000255156 ps |
| CPU time | 53.82 seconds |
| Started | Jul 18 08:00:51 PM PDT 24 |
| Finished | Jul 18 08:01:45 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-e47ba928-b763-4ae6-a803-6d1b4036e7e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106804557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.3106804557 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.666975721 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 5367161879 ps |
| CPU time | 95.88 seconds |
| Started | Jul 18 08:00:44 PM PDT 24 |
| Finished | Jul 18 08:02:20 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-2ac36b26-38df-4ba9-8b03-c15daec444f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666975721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.666975721 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.463922500 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 46949257 ps |
| CPU time | 6.11 seconds |
| Started | Jul 18 08:00:42 PM PDT 24 |
| Finished | Jul 18 08:00:49 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-856d83cb-6482-4627-beab-6c3aba1a9a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463922500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delays .463922500 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.2582694376 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 3379163828 ps |
| CPU time | 147.19 seconds |
| Started | Jul 18 08:00:41 PM PDT 24 |
| Finished | Jul 18 08:03:10 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1ad3ca83-ac4c-49d1-9f1b-e411b126ac15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582694376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.2582694376 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2290745827 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 2677817981 ps |
| CPU time | 93.44 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:02:37 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-f576503d-4701-4776-a180-df147c67f257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290745827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2290745827 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.408486074 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 784184419 ps |
| CPU time | 339.34 seconds |
| Started | Jul 18 08:00:40 PM PDT 24 |
| Finished | Jul 18 08:06:20 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-c1fe4046-b809-492b-ad63-68cffa91c6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408486074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.408486074 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3537767186 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 1351738905 ps |
| CPU time | 224.81 seconds |
| Started | Jul 18 08:01:04 PM PDT 24 |
| Finished | Jul 18 08:04:52 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-224c7c1c-da4f-4d52-ba9a-c0a956a5d0be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537767186 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3537767186 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1782066994 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 189157368 ps |
| CPU time | 22.47 seconds |
| Started | Jul 18 08:00:45 PM PDT 24 |
| Finished | Jul 18 08:01:08 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-9bf647e5-cb33-471b-9ba1-a61bb36a7b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782066994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1782066994 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1535671276 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 995855693 ps |
| CPU time | 67.58 seconds |
| Started | Jul 18 08:01:05 PM PDT 24 |
| Finished | Jul 18 08:02:15 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-5c1e125f-5651-43f7-9c9a-3aca35750be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535671276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1535671276 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.3123024915 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 53943423742 ps |
| CPU time | 1018.08 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:18:02 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-5f505600-c44d-4a47-a65a-0c27f3b46f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123024915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.3123024915 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2920306694 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 233416409 ps |
| CPU time | 25.67 seconds |
| Started | Jul 18 08:01:06 PM PDT 24 |
| Finished | Jul 18 08:01:33 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-88d5b50c-c0fd-4d46-a865-a1c297f56da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920306694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2920306694 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.2676230295 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 1511721213 ps |
| CPU time | 48.97 seconds |
| Started | Jul 18 08:01:04 PM PDT 24 |
| Finished | Jul 18 08:01:55 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-c38749ff-0ebe-45a0-839d-5ed27c77464b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676230295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2676230295 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.801085683 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 1542276967 ps |
| CPU time | 56.42 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:02:00 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-9f938b3a-f095-4e0c-9eb6-719b461fac7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801085683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.801085683 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.3853134232 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 108765648498 ps |
| CPU time | 1238.16 seconds |
| Started | Jul 18 08:01:06 PM PDT 24 |
| Finished | Jul 18 08:21:46 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e2f3f82e-9bf9-462f-bc44-1798d730a34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853134232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3853134232 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.905783932 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 14299332759 ps |
| CPU time | 251.73 seconds |
| Started | Jul 18 08:01:03 PM PDT 24 |
| Finished | Jul 18 08:05:17 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-9e638558-9803-497c-891c-148576328cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905783932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.905783932 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2984315014 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 417012177 ps |
| CPU time | 37.35 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f56ca477-31c3-4f83-b62f-cd45b2570a73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984315014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2984315014 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1154885366 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 1759625302 ps |
| CPU time | 51.51 seconds |
| Started | Jul 18 08:01:03 PM PDT 24 |
| Finished | Jul 18 08:01:57 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-182ace42-d3b6-4013-b9df-33d4ce6e290e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154885366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1154885366 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.4087351307 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 46880851 ps |
| CPU time | 5.9 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:01:11 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-4fcce74a-20b6-4401-b537-21df17554703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087351307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.4087351307 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.917718420 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 5988548793 ps |
| CPU time | 68.9 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:02:13 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-2fdd3c38-ea88-48c7-be2a-b0a1f645fa37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917718420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.917718420 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.375318838 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 4541839446 ps |
| CPU time | 76.74 seconds |
| Started | Jul 18 08:01:05 PM PDT 24 |
| Finished | Jul 18 08:02:24 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-aa1ef731-a916-4189-8504-da8d3a4b7876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375318838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.375318838 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.668046458 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 41845693 ps |
| CPU time | 5.95 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:01:10 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-4f1ccb7b-4a4d-4925-8d7c-7862fd833a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668046458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delays .668046458 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2674224985 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 6800302968 ps |
| CPU time | 243.19 seconds |
| Started | Jul 18 08:01:04 PM PDT 24 |
| Finished | Jul 18 08:05:10 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-da5a2a88-dcd8-4964-ac17-d92288bed158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674224985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2674224985 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1675464012 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 6677354784 ps |
| CPU time | 353.36 seconds |
| Started | Jul 18 08:01:04 PM PDT 24 |
| Finished | Jul 18 08:07:00 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-4a1fd543-8a70-47d2-901c-db04afa0dfb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675464012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1675464012 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.173820593 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 9989201610 ps |
| CPU time | 407.74 seconds |
| Started | Jul 18 08:01:30 PM PDT 24 |
| Finished | Jul 18 08:08:20 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-6887391e-58b6-46eb-9d70-9cd93307fd66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173820593 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_reset_error.173820593 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2734278697 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 22807465 ps |
| CPU time | 5.31 seconds |
| Started | Jul 18 08:01:03 PM PDT 24 |
| Finished | Jul 18 08:01:11 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-13f8a767-1efe-45d4-9611-c3574e9374cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734278697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2734278697 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.333987175 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 542534615 ps |
| CPU time | 46.1 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:02:15 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-85992755-7852-4379-bc1c-3105b3254bb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333987175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 333987175 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.415005518 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 70681714692 ps |
| CPU time | 1343.66 seconds |
| Started | Jul 18 08:01:26 PM PDT 24 |
| Finished | Jul 18 08:23:51 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7c47910b-f78b-4659-a0af-ea3733fba77a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415005518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_d evice_slow_rsp.415005518 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2546882156 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 146500609 ps |
| CPU time | 18.35 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:01:46 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-728290de-e49f-4801-a4b9-c7b9eec36845 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546882156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2546882156 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2865195724 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 775694088 ps |
| CPU time | 27.92 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:01:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-0fce00b0-af75-46f1-96c7-6818b05de08e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865195724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2865195724 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.487499113 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 2310915393 ps |
| CPU time | 81.93 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:02:26 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-176334b5-006f-4a52-bdf0-0926b4726494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487499113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.487499113 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.270911979 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 29693653014 ps |
| CPU time | 330.2 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:06:59 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6e19a93f-a1b2-4c27-8fc5-34488dcc7b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270911979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.270911979 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3270487415 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 20547149600 ps |
| CPU time | 371.28 seconds |
| Started | Jul 18 08:01:30 PM PDT 24 |
| Finished | Jul 18 08:07:44 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b324d616-a0b7-4770-b5d8-691411069c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270487415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3270487415 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1831176821 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 241636763 ps |
| CPU time | 22.41 seconds |
| Started | Jul 18 08:01:02 PM PDT 24 |
| Finished | Jul 18 08:01:26 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-3a04390c-6393-43fe-b1ae-d6ba5172d725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831176821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1831176821 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.3219908546 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 252197211 ps |
| CPU time | 18.68 seconds |
| Started | Jul 18 08:01:34 PM PDT 24 |
| Finished | Jul 18 08:01:54 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-385af808-7621-496b-87aa-3bac6dc1cacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219908546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.3219908546 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3313988662 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 178134897 ps |
| CPU time | 8.99 seconds |
| Started | Jul 18 08:01:01 PM PDT 24 |
| Finished | Jul 18 08:01:11 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-5bba7307-5137-44c7-8001-db150c4d8463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313988662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3313988662 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2608389692 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 7834911246 ps |
| CPU time | 87.57 seconds |
| Started | Jul 18 08:01:04 PM PDT 24 |
| Finished | Jul 18 08:02:34 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-71a4a454-a34a-429c-ab19-c658688a523d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608389692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2608389692 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3227574340 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 4997098220 ps |
| CPU time | 86.91 seconds |
| Started | Jul 18 08:01:08 PM PDT 24 |
| Finished | Jul 18 08:02:35 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-1747774b-124d-499e-a59d-175126772514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227574340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3227574340 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.93227552 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 31953906 ps |
| CPU time | 5.94 seconds |
| Started | Jul 18 08:01:01 PM PDT 24 |
| Finished | Jul 18 08:01:09 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-82c68a62-68ce-45af-901a-f69a0c0a93b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93227552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delays.93227552 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2717939496 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 256703503 ps |
| CPU time | 19.61 seconds |
| Started | Jul 18 08:01:28 PM PDT 24 |
| Finished | Jul 18 08:01:48 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-f91dd53b-358f-4d86-abe9-b702763383f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717939496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2717939496 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.4086710930 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 223053764 ps |
| CPU time | 93.58 seconds |
| Started | Jul 18 08:01:28 PM PDT 24 |
| Finished | Jul 18 08:03:04 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-7eb5247a-20c0-499a-8371-7ccb60e816ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086710930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.4086710930 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.148031826 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 5419210307 ps |
| CPU time | 236.17 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:05:28 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-31d03410-5f72-47c6-9e79-68f2feacbb4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148031826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_reset_error.148031826 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.705091075 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 509061633 ps |
| CPU time | 23.48 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:01:55 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-65ac5eda-cb07-44f2-ad2f-1d1f9787836c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705091075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.705091075 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1340837597 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2418588312 ps |
| CPU time | 119.78 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:03:29 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-7d941fa9-7520-4a83-a220-83cb7c440b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340837597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1340837597 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3633815052 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 11911560409 ps |
| CPU time | 212.68 seconds |
| Started | Jul 18 08:01:30 PM PDT 24 |
| Finished | Jul 18 08:05:06 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-d1f04c42-c74c-40f3-b6ca-03597d853137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633815052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3633815052 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.536831376 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 102996056 ps |
| CPU time | 11.41 seconds |
| Started | Jul 18 08:01:28 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-4984342c-b06e-47f8-90b3-7e25d0069c3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536831376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr .536831376 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.1651609993 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 159927395 ps |
| CPU time | 9.59 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-19738e5e-6872-4607-957c-e4e97a36a240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651609993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1651609993 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2659718324 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 696708094 ps |
| CPU time | 27.82 seconds |
| Started | Jul 18 08:01:26 PM PDT 24 |
| Finished | Jul 18 08:01:55 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-7f349b10-de5b-4485-9f0e-1d909b6bbe74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659718324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2659718324 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.1276080694 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 21538245083 ps |
| CPU time | 238.97 seconds |
| Started | Jul 18 08:01:32 PM PDT 24 |
| Finished | Jul 18 08:05:32 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-d6e1bccc-86b0-434e-a90b-4dff29907a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276080694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.1276080694 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.609131485 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 40540000310 ps |
| CPU time | 725.74 seconds |
| Started | Jul 18 08:01:30 PM PDT 24 |
| Finished | Jul 18 08:13:38 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-c036167a-11d5-4820-8998-35188b6dbf91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609131485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.609131485 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3381283873 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 444809916 ps |
| CPU time | 36.86 seconds |
| Started | Jul 18 08:01:35 PM PDT 24 |
| Finished | Jul 18 08:02:12 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-fc912ab2-7d2b-4996-9cef-95bd215d71b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381283873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.3381283873 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.2185612999 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 573298348 ps |
| CPU time | 42.33 seconds |
| Started | Jul 18 08:01:39 PM PDT 24 |
| Finished | Jul 18 08:02:22 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-22fbb6d8-7a12-48d6-9740-570d701eb89c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185612999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2185612999 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2938476254 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 231632575 ps |
| CPU time | 9.81 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-e9228ade-5e30-477f-9773-787b6f40ed11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938476254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2938476254 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1059176576 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 10374590348 ps |
| CPU time | 117.16 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:03:29 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-98ccf48b-c91c-4e7c-8e83-a7926a7074c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059176576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1059176576 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.826012202 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 6322847851 ps |
| CPU time | 112.86 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:03:21 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-ff558cfc-3d39-481b-baaa-9c2e0cefee2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826012202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.826012202 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1757159145 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 51951134 ps |
| CPU time | 6.62 seconds |
| Started | Jul 18 08:01:30 PM PDT 24 |
| Finished | Jul 18 08:01:39 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-8d65633a-9d07-4009-8549-863a9d92ffb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757159145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1757159145 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1541421308 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2735442287 ps |
| CPU time | 259.7 seconds |
| Started | Jul 18 08:01:28 PM PDT 24 |
| Finished | Jul 18 08:05:49 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-cd276d09-ab1b-486a-86eb-3b1d2599452e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541421308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1541421308 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.3395728198 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 1716582098 ps |
| CPU time | 141.01 seconds |
| Started | Jul 18 08:01:29 PM PDT 24 |
| Finished | Jul 18 08:03:53 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-c8a7f8b3-560a-4e13-aaca-06e88b757074 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395728198 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.3395728198 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2691321222 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 5215324653 ps |
| CPU time | 526.25 seconds |
| Started | Jul 18 08:01:32 PM PDT 24 |
| Finished | Jul 18 08:10:20 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-5b5f57bc-8cc8-4592-ad22-53225df07dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691321222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2691321222 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1175764423 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 1912361814 ps |
| CPU time | 170.64 seconds |
| Started | Jul 18 08:01:31 PM PDT 24 |
| Finished | Jul 18 08:04:24 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-b549f837-12e1-4e42-9e94-b19ea3881fb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175764423 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1175764423 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.619246102 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 139215321 ps |
| CPU time | 16.88 seconds |
| Started | Jul 18 08:01:27 PM PDT 24 |
| Finished | Jul 18 08:01:45 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-00f88128-c967-4ce7-b2cd-eeb1510d10a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619246102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.619246102 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.4177283002 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 437827357 ps |
| CPU time | 42.38 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:02:35 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-cac23a80-e0d6-415d-8f01-5a55b934cf60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177283002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .4177283002 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.2470997653 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4119070615 ps |
| CPU time | 76.15 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:03:09 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-35f87d8a-310d-45eb-801c-b4664e4f7f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470997653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.2470997653 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.987503789 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 964449821 ps |
| CPU time | 36.05 seconds |
| Started | Jul 18 08:01:50 PM PDT 24 |
| Finished | Jul 18 08:02:27 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-f5d0f387-1b75-44a1-945e-d62ff0544eae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987503789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr .987503789 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.636250535 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 1541474782 ps |
| CPU time | 53.75 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:02:54 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-8e519c17-c8f2-4ef6-bdcf-81ace22b31cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636250535 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.636250535 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2339459553 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2113828588 ps |
| CPU time | 69.38 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:03:02 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-1a2ce623-428c-4fb6-a068-1c4a1019f91d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339459553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2339459553 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1651476125 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 46191237397 ps |
| CPU time | 508.61 seconds |
| Started | Jul 18 08:01:53 PM PDT 24 |
| Finished | Jul 18 08:10:23 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-eb569616-3878-4c2b-8a41-3c77baa47234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651476125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1651476125 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.370480444 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 23334878811 ps |
| CPU time | 404.5 seconds |
| Started | Jul 18 08:01:48 PM PDT 24 |
| Finished | Jul 18 08:08:34 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-d503c213-ccf1-4771-9294-1855622673c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370480444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.370480444 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3085596571 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 595634505 ps |
| CPU time | 52.18 seconds |
| Started | Jul 18 08:01:54 PM PDT 24 |
| Finished | Jul 18 08:02:48 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-d620f39e-8c09-4b4b-8c27-27b5191b145e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085596571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3085596571 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.1204441489 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 2143095336 ps |
| CPU time | 64.86 seconds |
| Started | Jul 18 08:01:53 PM PDT 24 |
| Finished | Jul 18 08:02:58 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-89112ec3-1c0d-463a-b0e1-f867d2096f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204441489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.1204441489 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.3864994364 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 165806245 ps |
| CPU time | 8.09 seconds |
| Started | Jul 18 08:01:34 PM PDT 24 |
| Finished | Jul 18 08:01:43 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-f8600cf5-854e-49fa-b4dd-cc7401b8fd66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864994364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.3864994364 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1182677779 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 5276260528 ps |
| CPU time | 59.34 seconds |
| Started | Jul 18 08:01:33 PM PDT 24 |
| Finished | Jul 18 08:02:34 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-ab8c48e2-b648-48d7-a286-79d496c66ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182677779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1182677779 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3565374979 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 5010849964 ps |
| CPU time | 90.44 seconds |
| Started | Jul 18 08:01:31 PM PDT 24 |
| Finished | Jul 18 08:03:04 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-c9bed29d-f013-4f18-b22f-3d54b038be93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565374979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3565374979 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.768032969 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 47010818 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 08:01:34 PM PDT 24 |
| Finished | Jul 18 08:01:41 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-12a19269-ea11-4d83-bf01-cad5a9b0cb66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768032969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .768032969 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1468515262 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 3322662846 ps |
| CPU time | 270.55 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:06:24 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ece5338a-aa34-46d4-b63b-2786aa7a50e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468515262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1468515262 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.970231362 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 4004487686 ps |
| CPU time | 147.24 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:04:21 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2afa4e50-853b-49a1-8ef5-89ddbe7a09d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970231362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.970231362 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.1047552241 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 337751123 ps |
| CPU time | 140.37 seconds |
| Started | Jul 18 08:01:49 PM PDT 24 |
| Finished | Jul 18 08:04:11 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-27bc0184-3148-4166-8499-7c695fb73e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047552241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.1047552241 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3563654479 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 1465965264 ps |
| CPU time | 60.55 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:03:01 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-db6208d6-b24f-4372-ade3-2cd4afd4cdb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563654479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3563654479 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.3436231026 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 1960959135 ps |
| CPU time | 76.73 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:03:17 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-945558c4-2e28-4374-a50d-118742a9b68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436231026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .3436231026 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2982556485 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 61211650500 ps |
| CPU time | 1172.99 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:21:25 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-e29b2134-da5c-468a-8724-80dcab32c839 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982556485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2982556485 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1202618801 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 1242989274 ps |
| CPU time | 44.71 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:02:37 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-007d34bf-ff16-4f01-9c94-52a23666937f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202618801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.1202618801 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.39276396 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 480647515 ps |
| CPU time | 40.33 seconds |
| Started | Jul 18 08:01:50 PM PDT 24 |
| Finished | Jul 18 08:02:31 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3aa5f4b5-dd40-4e1a-b157-30b67f372cd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39276396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.39276396 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2605303082 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 257493847 ps |
| CPU time | 25.75 seconds |
| Started | Jul 18 08:01:53 PM PDT 24 |
| Finished | Jul 18 08:02:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-fbc09cc8-bd83-46aa-8670-1f641734bba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605303082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2605303082 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3140001358 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 64214395433 ps |
| CPU time | 768.8 seconds |
| Started | Jul 18 08:01:50 PM PDT 24 |
| Finished | Jul 18 08:14:40 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-17f94504-290b-4e4f-b083-5884b24be370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140001358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3140001358 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3723407396 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 38836842418 ps |
| CPU time | 709.93 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:13:43 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b82b9dac-0540-4122-b609-04423d4eb73a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723407396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3723407396 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1929847089 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 289668320 ps |
| CPU time | 26.57 seconds |
| Started | Jul 18 08:01:49 PM PDT 24 |
| Finished | Jul 18 08:02:16 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-232a4755-7ecc-4420-9ab7-878bc74e8f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929847089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1929847089 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3343187086 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 2459367443 ps |
| CPU time | 78.77 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:03:11 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-8e9fdac5-85c8-4173-a0de-e28dcec1779c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343187086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3343187086 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.1472393232 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 241727700 ps |
| CPU time | 10.25 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:02:03 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-28ed343c-c2c7-4654-b05a-68e2fbc2db60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472393232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.1472393232 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2122261697 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 6682001200 ps |
| CPU time | 71.38 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:03:03 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ebb56e09-bd91-4e01-8765-6069c672b362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122261697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2122261697 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.1822713708 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 5839266081 ps |
| CPU time | 107.05 seconds |
| Started | Jul 18 08:01:49 PM PDT 24 |
| Finished | Jul 18 08:03:37 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-e5877d2a-0447-420d-a909-67d25322030d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822713708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.1822713708 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1486500306 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 40581922 ps |
| CPU time | 6 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:02:05 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-e3f8f171-1cfa-41e5-9cb4-168e774e9578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486500306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1486500306 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.1720025635 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 2812864219 ps |
| CPU time | 241.54 seconds |
| Started | Jul 18 08:01:57 PM PDT 24 |
| Finished | Jul 18 08:06:00 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-6b81d271-8b72-406a-9a65-9b3502068655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720025635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.1720025635 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2312781842 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 4100746888 ps |
| CPU time | 130.41 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:04:11 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-10ead3f5-d6b2-46ec-9b8b-e5495189f4b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312781842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2312781842 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2927115179 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 2145897922 ps |
| CPU time | 392.22 seconds |
| Started | Jul 18 08:01:57 PM PDT 24 |
| Finished | Jul 18 08:08:31 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-b158d2be-5fdd-487b-9eab-365dc6c60768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927115179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2927115179 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.675985491 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 7464262 ps |
| CPU time | 8.67 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:02:07 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-e1f54f46-8966-4f92-bcd2-7422e3a85fec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675985491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_reset_error.675985491 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2420932930 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 184016056 ps |
| CPU time | 24.67 seconds |
| Started | Jul 18 08:01:59 PM PDT 24 |
| Finished | Jul 18 08:02:25 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-5fc8e491-814a-4f69-8f75-ca5cff561651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420932930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2420932930 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.1192109843 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 778961656 ps |
| CPU time | 34.61 seconds |
| Started | Jul 18 08:01:53 PM PDT 24 |
| Finished | Jul 18 08:02:29 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-e70a2aaf-0aa0-467f-a825-f3f413cf5941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192109843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .1192109843 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.699970980 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 118087501195 ps |
| CPU time | 2231.88 seconds |
| Started | Jul 18 08:01:54 PM PDT 24 |
| Finished | Jul 18 08:39:07 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-ef269c8d-5048-4119-a00a-48ca5214c2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699970980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.699970980 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1656379611 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 899135910 ps |
| CPU time | 29.16 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:02:43 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-ecb0459a-a233-4778-b36e-7d3fa057bd17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656379611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.1656379611 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.669658383 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 587831717 ps |
| CPU time | 46.48 seconds |
| Started | Jul 18 08:01:55 PM PDT 24 |
| Finished | Jul 18 08:02:43 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-6615a4fe-ca2a-4a55-a752-dcda62f69786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669658383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.669658383 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.2139177341 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 1132810864 ps |
| CPU time | 38.9 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:02:39 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-bd910079-3a2f-4488-a1f4-499160dfd684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139177341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.2139177341 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3713151734 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 72965970961 ps |
| CPU time | 845.91 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:16:06 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-1ba0ec70-8bcd-47a0-b9cb-946583c6c5f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713151734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3713151734 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3253644512 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 26849665909 ps |
| CPU time | 454.54 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:09:35 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-91544320-bbb5-4152-b086-3c506618e98c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253644512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3253644512 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2880523664 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 322808399 ps |
| CPU time | 26.85 seconds |
| Started | Jul 18 08:01:59 PM PDT 24 |
| Finished | Jul 18 08:02:27 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-250d57c6-4d88-44f8-9a63-0d7d14ec2f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880523664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.2880523664 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.218963231 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 385354689 ps |
| CPU time | 27.68 seconds |
| Started | Jul 18 08:01:59 PM PDT 24 |
| Finished | Jul 18 08:02:28 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e4d10560-d21c-42c3-8339-959a25a891af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218963231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.218963231 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.4123512802 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 204364686 ps |
| CPU time | 9.35 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:02:08 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-98147da5-2612-4fc3-9a62-512adefd7bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123512802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.4123512802 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.1419721428 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 4997545716 ps |
| CPU time | 55.6 seconds |
| Started | Jul 18 08:01:51 PM PDT 24 |
| Finished | Jul 18 08:02:47 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-c06b3401-cdd2-4392-9ffb-d5127c5606eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419721428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.1419721428 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1412842293 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 5514881397 ps |
| CPU time | 96.66 seconds |
| Started | Jul 18 08:01:57 PM PDT 24 |
| Finished | Jul 18 08:03:35 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a48f590d-efae-4244-9f32-339b50e7ff96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412842293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1412842293 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.4055081141 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 48576817 ps |
| CPU time | 6.61 seconds |
| Started | Jul 18 08:01:56 PM PDT 24 |
| Finished | Jul 18 08:02:04 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b7c94269-83f2-4f27-ae6a-69106a1d6706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055081141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.4055081141 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.523976521 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 6974274350 ps |
| CPU time | 239.48 seconds |
| Started | Jul 18 08:01:57 PM PDT 24 |
| Finished | Jul 18 08:05:57 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-88d79440-b2c1-4792-a7ed-ac7c7e1168b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523976521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.523976521 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.2652364231 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 2442241286 ps |
| CPU time | 64.29 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:03:17 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c3a6e676-39fd-4374-bc9a-8b703fc96101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652364231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.2652364231 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2014778913 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1903368289 ps |
| CPU time | 427.07 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:09:20 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-7d0aedad-592e-4d29-a36f-1ac5fd542f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014778913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.2014778913 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.2568814865 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 160149821 ps |
| CPU time | 43.6 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:02:57 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-71daacaf-71d1-4516-bd43-c15cefeaa282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568814865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.2568814865 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.2437599138 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 221393409 ps |
| CPU time | 25.91 seconds |
| Started | Jul 18 08:01:56 PM PDT 24 |
| Finished | Jul 18 08:02:23 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-8c744bd3-543d-43d8-ae4b-e75d8eb3f08a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437599138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.2437599138 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1813224564 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 6573535041 ps |
| CPU time | 536.68 seconds |
| Started | Jul 18 07:44:53 PM PDT 24 |
| Finished | Jul 18 07:53:51 PM PDT 24 |
| Peak memory | 637484 kb |
| Host | smart-5d2182e5-0bcd-4d91-9a8f-456bac67e886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813224564 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.1813224564 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1134666145 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 4413129340 ps |
| CPU time | 309.91 seconds |
| Started | Jul 18 07:44:53 PM PDT 24 |
| Finished | Jul 18 07:50:04 PM PDT 24 |
| Peak memory | 598248 kb |
| Host | smart-e1ad9877-c49a-4aa3-a4b9-5d338780a373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134666145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1134666145 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.2979071447 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 15432894382 ps |
| CPU time | 2004.69 seconds |
| Started | Jul 18 07:44:35 PM PDT 24 |
| Finished | Jul 18 08:18:01 PM PDT 24 |
| Peak memory | 592040 kb |
| Host | smart-9825324d-92ad-4c4d-a84c-52b219b596a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979071447 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.2979071447 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3904337289 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 2157685749 ps |
| CPU time | 85.74 seconds |
| Started | Jul 18 07:44:34 PM PDT 24 |
| Finished | Jul 18 07:46:01 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-e8e1a8f5-c655-49d8-bced-65c7fbccb489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904337289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3904337289 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4103993304 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 19443866736 ps |
| CPU time | 333.88 seconds |
| Started | Jul 18 07:44:35 PM PDT 24 |
| Finished | Jul 18 07:50:11 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-ccd80b55-e386-419c-91d1-3293f5d4b8c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103993304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.4103993304 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.625544199 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1215360567 ps |
| CPU time | 44.76 seconds |
| Started | Jul 18 07:45:00 PM PDT 24 |
| Finished | Jul 18 07:45:45 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-27a23247-6465-4190-92ae-4121040cc9de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625544199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr. 625544199 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.599460669 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 310661079 ps |
| CPU time | 13.11 seconds |
| Started | Jul 18 07:44:52 PM PDT 24 |
| Finished | Jul 18 07:45:06 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-9d16cdbf-0342-4060-a12a-9d80173c8d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599460669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.599460669 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.1402857994 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 340689736 ps |
| CPU time | 30.19 seconds |
| Started | Jul 18 07:44:34 PM PDT 24 |
| Finished | Jul 18 07:45:05 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4b6c6fcd-3124-49e7-ae53-fd2c30cd3a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402857994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1402857994 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.1010892642 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 37279892108 ps |
| CPU time | 424.15 seconds |
| Started | Jul 18 07:44:34 PM PDT 24 |
| Finished | Jul 18 07:51:38 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-83496854-112b-4b38-b5c4-a1e50b0b15c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010892642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.1010892642 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2024421126 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 2188082112 ps |
| CPU time | 37.75 seconds |
| Started | Jul 18 07:44:34 PM PDT 24 |
| Finished | Jul 18 07:45:13 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ba30d762-5052-4605-a19c-f4c370d584bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024421126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2024421126 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3935144242 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 448400886 ps |
| CPU time | 41.07 seconds |
| Started | Jul 18 07:44:37 PM PDT 24 |
| Finished | Jul 18 07:45:19 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-9560fffa-e6f7-4c2c-b3b4-0f55934fa6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935144242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3935144242 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3718596734 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 1509527778 ps |
| CPU time | 47.8 seconds |
| Started | Jul 18 07:44:56 PM PDT 24 |
| Finished | Jul 18 07:45:44 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-9b867d61-e9f1-4d4b-91e2-f2d3af1789cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718596734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3718596734 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.2072417400 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 41628065 ps |
| CPU time | 6.35 seconds |
| Started | Jul 18 07:44:35 PM PDT 24 |
| Finished | Jul 18 07:44:42 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-fcd56296-b2ef-4e48-b3b3-20059ce9ee61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072417400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.2072417400 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2721037084 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 7735399669 ps |
| CPU time | 79.19 seconds |
| Started | Jul 18 07:44:34 PM PDT 24 |
| Finished | Jul 18 07:45:54 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a411c0fe-e231-4dd4-8bfc-f2a4a9e987be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721037084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2721037084 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3881689406 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 5125687342 ps |
| CPU time | 91.76 seconds |
| Started | Jul 18 07:44:36 PM PDT 24 |
| Finished | Jul 18 07:46:09 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-929d5b52-0ef3-4e32-bea0-afd95108b671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881689406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3881689406 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.111825078 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 49910674 ps |
| CPU time | 6.35 seconds |
| Started | Jul 18 07:44:36 PM PDT 24 |
| Finished | Jul 18 07:44:43 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-05b9d3ac-bb9a-4fc0-a7dc-4d6ba6c7a1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111825078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays. 111825078 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.3526613189 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1430063801 ps |
| CPU time | 69.25 seconds |
| Started | Jul 18 07:44:57 PM PDT 24 |
| Finished | Jul 18 07:46:06 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-adf5951f-be9a-4c65-9346-91b56b730640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526613189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3526613189 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.238582353 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 1934154174 ps |
| CPU time | 142.07 seconds |
| Started | Jul 18 07:44:55 PM PDT 24 |
| Finished | Jul 18 07:47:18 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-9f84db80-0a3d-4211-bbe5-9a85553772d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238582353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.238582353 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3849487192 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 484133169 ps |
| CPU time | 136.4 seconds |
| Started | Jul 18 07:44:53 PM PDT 24 |
| Finished | Jul 18 07:47:10 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-07261aca-f587-4ba2-9b32-87f308bd03e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849487192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3849487192 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.38902697 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 88037755 ps |
| CPU time | 7.01 seconds |
| Started | Jul 18 07:44:59 PM PDT 24 |
| Finished | Jul 18 07:45:07 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c935205d-961b-4695-b583-0cc1703d6910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.38902697 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.167665536 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 1301254513 ps |
| CPU time | 60.93 seconds |
| Started | Jul 18 08:01:55 PM PDT 24 |
| Finished | Jul 18 08:02:57 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-dea4375f-0327-4b80-a8be-79df66f47721 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167665536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device. 167665536 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1290357786 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 149371446128 ps |
| CPU time | 2677.84 seconds |
| Started | Jul 18 08:01:54 PM PDT 24 |
| Finished | Jul 18 08:46:34 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-17567b4d-126d-4a51-9da3-5ca3d33f2852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290357786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1290357786 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2950767114 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 1237638744 ps |
| CPU time | 43.21 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:03:27 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-a25093e6-201c-4b6a-a7bc-b9c614513dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950767114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2950767114 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3137792477 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 320036923 ps |
| CPU time | 26.99 seconds |
| Started | Jul 18 08:01:52 PM PDT 24 |
| Finished | Jul 18 08:02:20 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-488add12-1754-496a-aa58-b7b902252656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137792477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3137792477 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.377257482 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 1927745728 ps |
| CPU time | 61.56 seconds |
| Started | Jul 18 08:02:13 PM PDT 24 |
| Finished | Jul 18 08:03:16 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-60da5985-722d-442f-8967-0a9f0a5a286d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377257482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.377257482 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2027031207 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 80275447633 ps |
| CPU time | 887.56 seconds |
| Started | Jul 18 08:01:56 PM PDT 24 |
| Finished | Jul 18 08:16:45 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-96e73e87-5511-43e0-8764-fd55c5fc1837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027031207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2027031207 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.429824313 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 38025209901 ps |
| CPU time | 680.82 seconds |
| Started | Jul 18 08:01:58 PM PDT 24 |
| Finished | Jul 18 08:13:20 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-8c0efbc8-ebbd-49de-93e1-f815932160be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429824313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.429824313 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.4290129666 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 233825182 ps |
| CPU time | 21.3 seconds |
| Started | Jul 18 08:01:56 PM PDT 24 |
| Finished | Jul 18 08:02:19 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-d6a699f7-f7d7-4f47-b03b-47cf128995f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290129666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.4290129666 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.2695256126 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 415816276 ps |
| CPU time | 30.24 seconds |
| Started | Jul 18 08:02:05 PM PDT 24 |
| Finished | Jul 18 08:02:35 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-ab16ec4a-b0d7-4ce5-97b4-1118c2a47c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695256126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.2695256126 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1595640599 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 179038612 ps |
| CPU time | 8.21 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:02:23 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-6eac1f06-9a30-42fa-aec7-92b9f94a5ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595640599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1595640599 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2042623186 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 8082099901 ps |
| CPU time | 85.44 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:03:39 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-997dbd18-8a4b-43a3-834f-a229f3af236f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042623186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2042623186 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1024484225 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 5714117101 ps |
| CPU time | 90.81 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:03:45 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a7a7f32b-25b4-4700-9099-00e0a59bdee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024484225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1024484225 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.449917057 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 44878542 ps |
| CPU time | 6.09 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:02:21 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-93deaef6-9c55-49ab-9164-f5f750c3f564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449917057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delays .449917057 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.3942534792 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 6040545039 ps |
| CPU time | 214.58 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:05:47 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a551b918-e2e4-4e26-9591-9f683ec684f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942534792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.3942534792 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3035994789 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 5138570036 ps |
| CPU time | 173.68 seconds |
| Started | Jul 18 08:02:07 PM PDT 24 |
| Finished | Jul 18 08:05:02 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-b3e77332-5ea0-4dab-bc24-0a5bfac5ee43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035994789 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.3035994789 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.618768973 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 4522714857 ps |
| CPU time | 505.85 seconds |
| Started | Jul 18 08:02:16 PM PDT 24 |
| Finished | Jul 18 08:10:43 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8b19ebc6-cc00-462d-bae6-864742f63f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618768973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.618768973 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.2884952782 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 850613997 ps |
| CPU time | 137.54 seconds |
| Started | Jul 18 08:02:10 PM PDT 24 |
| Finished | Jul 18 08:04:30 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-6cf3b220-3132-46d8-a611-4ca6b626a5b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884952782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.2884952782 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2668268986 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 235407112 ps |
| CPU time | 13.63 seconds |
| Started | Jul 18 08:02:07 PM PDT 24 |
| Finished | Jul 18 08:02:22 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-7a5ddc71-82b0-46a7-9f24-090f9c384a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668268986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2668268986 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.3872667165 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1302201344 ps |
| CPU time | 107.25 seconds |
| Started | Jul 18 08:02:06 PM PDT 24 |
| Finished | Jul 18 08:03:54 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-7677b4de-1ecf-45b9-9ca7-3c926d3efa51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872667165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .3872667165 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.2673855035 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 113391138257 ps |
| CPU time | 2160.62 seconds |
| Started | Jul 18 08:02:08 PM PDT 24 |
| Finished | Jul 18 08:38:10 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-e55f7f65-8469-4281-bc14-16f0c2137eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673855035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.2673855035 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.3846817454 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 1379481669 ps |
| CPU time | 50.36 seconds |
| Started | Jul 18 08:02:10 PM PDT 24 |
| Finished | Jul 18 08:03:02 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-3961ec18-4136-4ec3-9503-19b885b856fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846817454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.3846817454 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1865464966 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 123764946 ps |
| CPU time | 12.22 seconds |
| Started | Jul 18 08:02:08 PM PDT 24 |
| Finished | Jul 18 08:02:22 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-c3233eb8-2da7-434c-ae4e-c5c3750c5b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865464966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1865464966 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.3100899097 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 1950756005 ps |
| CPU time | 65.74 seconds |
| Started | Jul 18 08:02:13 PM PDT 24 |
| Finished | Jul 18 08:03:21 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-7b68d2ff-2111-4446-bfcf-ebfe394d3699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100899097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3100899097 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2288552652 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 80478481391 ps |
| CPU time | 1019.6 seconds |
| Started | Jul 18 08:02:08 PM PDT 24 |
| Finished | Jul 18 08:19:08 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-44f8344d-e0a9-4057-b314-b1ce0679dbae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288552652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2288552652 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.253692512 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 37446141601 ps |
| CPU time | 715.2 seconds |
| Started | Jul 18 08:02:08 PM PDT 24 |
| Finished | Jul 18 08:14:05 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-ba84096f-db90-4d97-9b1d-66e1c1c611d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253692512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.253692512 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.1303445059 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 300767098 ps |
| CPU time | 24.59 seconds |
| Started | Jul 18 08:02:14 PM PDT 24 |
| Finished | Jul 18 08:02:40 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-0061f3bf-17d3-4ba0-aaed-744ffd08738a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303445059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.1303445059 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1971659446 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 199328008 ps |
| CPU time | 15.12 seconds |
| Started | Jul 18 08:02:15 PM PDT 24 |
| Finished | Jul 18 08:02:31 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-debc13b6-30d0-4ed1-9410-4dbcefc79243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971659446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1971659446 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.537948916 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 38818420 ps |
| CPU time | 6.38 seconds |
| Started | Jul 18 08:02:10 PM PDT 24 |
| Finished | Jul 18 08:02:17 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-faaca28f-c01c-40ec-9b8f-92a54f65f9f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537948916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.537948916 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.781787016 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 5469492542 ps |
| CPU time | 63.02 seconds |
| Started | Jul 18 08:02:10 PM PDT 24 |
| Finished | Jul 18 08:03:15 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-2996845b-8e97-41fe-8df4-8d862d561c63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781787016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.781787016 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.3193549294 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 5411596772 ps |
| CPU time | 96.18 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:03:51 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-5fb5b200-bb1f-4120-bf74-89b681cbfd28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193549294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.3193549294 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1204968646 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 46719291 ps |
| CPU time | 6.48 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:02:21 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-2aff1781-5d8c-406a-831c-31b5044f3a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204968646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.1204968646 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.3734673109 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 1729669381 ps |
| CPU time | 69.32 seconds |
| Started | Jul 18 08:02:08 PM PDT 24 |
| Finished | Jul 18 08:03:19 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-dda7e4fa-552d-43a0-8a15-b7a7a81cbaae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734673109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.3734673109 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.706186298 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 4250657069 ps |
| CPU time | 128.91 seconds |
| Started | Jul 18 08:02:09 PM PDT 24 |
| Finished | Jul 18 08:04:20 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-ec41490b-748c-4131-bb87-ef16000411df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706186298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.706186298 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3049562654 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 7159938537 ps |
| CPU time | 419.5 seconds |
| Started | Jul 18 08:02:07 PM PDT 24 |
| Finished | Jul 18 08:09:07 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-20a6d657-5736-461b-bd82-afbae72f5d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049562654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3049562654 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1173120364 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 52522178 ps |
| CPU time | 14.78 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:02:27 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-63cd959e-4d61-4697-9cbf-8022c0a54ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173120364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1173120364 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3535662455 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 22147452 ps |
| CPU time | 5.33 seconds |
| Started | Jul 18 08:02:16 PM PDT 24 |
| Finished | Jul 18 08:02:22 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-9af0e8f7-46a3-4ae6-b364-d3a8ee30a7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535662455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3535662455 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1726595966 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 3520097898 ps |
| CPU time | 139.37 seconds |
| Started | Jul 18 08:02:15 PM PDT 24 |
| Finished | Jul 18 08:04:36 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-56e483b9-96c5-4ca1-addf-1361df00dd6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726595966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1726595966 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2632683031 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 5321455497 ps |
| CPU time | 87.01 seconds |
| Started | Jul 18 08:02:15 PM PDT 24 |
| Finished | Jul 18 08:03:43 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-f44fb356-512f-4c7f-9709-868d777ae1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632683031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2632683031 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3602732107 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 757729581 ps |
| CPU time | 29.23 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:03:03 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-23b2916c-ede2-43a2-a5c6-df4988c15e5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602732107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3602732107 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3566995531 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 491080353 ps |
| CPU time | 41.19 seconds |
| Started | Jul 18 08:02:32 PM PDT 24 |
| Finished | Jul 18 08:03:14 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-fe54e002-9337-4e8e-9ec0-493dd9b4d77d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566995531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3566995531 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.3191628060 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 1453171593 ps |
| CPU time | 50.91 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:03:05 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-b2ee300a-1f47-483a-a64d-cf9d657dfda2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191628060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.3191628060 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.588118040 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 51589436415 ps |
| CPU time | 579.91 seconds |
| Started | Jul 18 08:02:09 PM PDT 24 |
| Finished | Jul 18 08:11:50 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-230e396a-eef0-4d5d-9c16-f9ef87aa8c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588118040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.588118040 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.4255153270 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 64888185204 ps |
| CPU time | 1206.16 seconds |
| Started | Jul 18 08:02:16 PM PDT 24 |
| Finished | Jul 18 08:22:23 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-9ab4c8eb-5c5d-420b-a0ef-68410061d70c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255153270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.4255153270 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1040306843 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 544120478 ps |
| CPU time | 49.61 seconds |
| Started | Jul 18 08:02:12 PM PDT 24 |
| Finished | Jul 18 08:03:04 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-183b7152-d788-4b98-85a3-5b45a25c7f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040306843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1040306843 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1824556996 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 759912606 ps |
| CPU time | 23.56 seconds |
| Started | Jul 18 08:02:09 PM PDT 24 |
| Finished | Jul 18 08:02:34 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-5188206e-e50b-428d-868e-4b0d91046997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824556996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1824556996 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.996976458 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 57714725 ps |
| CPU time | 7.67 seconds |
| Started | Jul 18 08:02:10 PM PDT 24 |
| Finished | Jul 18 08:02:19 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-aec496fd-5ab2-4c06-96ce-454524a24f02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996976458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.996976458 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.4214061424 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 6745732508 ps |
| CPU time | 76.72 seconds |
| Started | Jul 18 08:02:16 PM PDT 24 |
| Finished | Jul 18 08:03:33 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-db3a31a3-3427-4aba-bbd4-21b1d9455167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214061424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.4214061424 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1483231431 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 3985611930 ps |
| CPU time | 72.97 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:03:26 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-206b948c-26e7-4c9f-9076-0efe07f041fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483231431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1483231431 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2922006857 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 43464726 ps |
| CPU time | 6.17 seconds |
| Started | Jul 18 08:02:11 PM PDT 24 |
| Finished | Jul 18 08:02:20 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-e4fba623-a5d2-41a1-88d2-2136cbcb47f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922006857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.2922006857 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2258262601 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 2107236929 ps |
| CPU time | 184.54 seconds |
| Started | Jul 18 08:02:28 PM PDT 24 |
| Finished | Jul 18 08:05:34 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-0ce3bdeb-dc22-4b0b-aed2-206dc5a310d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258262601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2258262601 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1320520798 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 17517453526 ps |
| CPU time | 569.44 seconds |
| Started | Jul 18 08:02:25 PM PDT 24 |
| Finished | Jul 18 08:11:55 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-893e9c86-d3d7-491b-876e-43f0ce509b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320520798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1320520798 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1966263015 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 4771494005 ps |
| CPU time | 400.36 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:09:09 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-0851c271-142a-49d6-9734-dce63743b29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966263015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.1966263015 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.3514436666 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 352015001 ps |
| CPU time | 112.08 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:04:26 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c15641ee-afb9-43f2-a00d-902c5ca58e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514436666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.3514436666 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1708012454 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 61274826 ps |
| CPU time | 8.82 seconds |
| Started | Jul 18 08:02:24 PM PDT 24 |
| Finished | Jul 18 08:02:34 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-ec75d300-d28a-44d1-80e5-278d4f15e115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708012454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1708012454 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.2807546657 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 2416227275 ps |
| CPU time | 92.54 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:04:07 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-53d50cb8-804c-478a-9810-0f533ce77780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807546657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .2807546657 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2793294630 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 118263528194 ps |
| CPU time | 2250.69 seconds |
| Started | Jul 18 08:02:34 PM PDT 24 |
| Finished | Jul 18 08:40:06 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-bde4b3c6-2b71-4c05-a5ee-a1462ae6c539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793294630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2793294630 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.4253239018 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 592885832 ps |
| CPU time | 24.5 seconds |
| Started | Jul 18 08:02:30 PM PDT 24 |
| Finished | Jul 18 08:02:56 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1850de24-649b-4e0e-a32c-818f73a1db23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253239018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.4253239018 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2715921563 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 1193374836 ps |
| CPU time | 45.99 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:03:14 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-980b5cc4-5039-47d9-8ff4-2ad12b640db6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715921563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2715921563 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.3488082219 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1757772023 ps |
| CPU time | 69.53 seconds |
| Started | Jul 18 08:02:31 PM PDT 24 |
| Finished | Jul 18 08:03:42 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-2d8e8774-6502-4ce9-b2ac-f1a6f51d51cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488082219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3488082219 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.312036166 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 88432152219 ps |
| CPU time | 983.79 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:18:54 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-ec4ea309-b42c-478c-86e1-edc595efc04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312036166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.312036166 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.2362976735 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 58002212727 ps |
| CPU time | 1124.87 seconds |
| Started | Jul 18 08:02:35 PM PDT 24 |
| Finished | Jul 18 08:21:21 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-df5e6a3a-9c87-4d42-8419-236b31b99bde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362976735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.2362976735 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.2444769531 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 595913379 ps |
| CPU time | 47.99 seconds |
| Started | Jul 18 08:02:28 PM PDT 24 |
| Finished | Jul 18 08:03:17 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-cc1e706e-2cb8-4155-8d62-3d3f04958ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444769531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.2444769531 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.2123583906 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 713505615 ps |
| CPU time | 22.28 seconds |
| Started | Jul 18 08:02:31 PM PDT 24 |
| Finished | Jul 18 08:02:54 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-3d3a056a-2893-483f-bf3a-df28d860099e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123583906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2123583906 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1613376943 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 201602916 ps |
| CPU time | 9.06 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:02:39 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-c3fe04c0-6293-46d4-af55-1f765a753f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613376943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1613376943 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2304587176 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 9869013047 ps |
| CPU time | 104.29 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:04:12 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-7d211cc1-c4cd-4d38-ab85-e2a755b7f6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304587176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2304587176 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.4272012896 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 5783353890 ps |
| CPU time | 99.42 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:04:10 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2b301935-7235-4157-9db9-67037df61e73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272012896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.4272012896 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.4264885714 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 45082805 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:02:41 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8000677b-73d4-4454-81d4-47f87ac49ef4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264885714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.4264885714 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3753536914 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 4408005767 ps |
| CPU time | 349.67 seconds |
| Started | Jul 18 08:02:25 PM PDT 24 |
| Finished | Jul 18 08:08:16 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-b7c38748-0f14-427a-bdd8-1f2fa5ede1fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753536914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3753536914 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.2344266471 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 5941620067 ps |
| CPU time | 179.45 seconds |
| Started | Jul 18 08:02:34 PM PDT 24 |
| Finished | Jul 18 08:05:35 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-0baa6967-c9a3-4200-8a7d-173ebc2ee34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344266471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.2344266471 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.344378174 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 270806530 ps |
| CPU time | 134.55 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:04:49 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-84fabcb9-f13a-41d7-aa54-08b283e7b3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344378174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.344378174 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2389227752 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 1596841833 ps |
| CPU time | 361.72 seconds |
| Started | Jul 18 08:02:34 PM PDT 24 |
| Finished | Jul 18 08:08:37 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-73841e19-cd1e-4f45-89e0-f696f2f806b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389227752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.2389227752 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.249327281 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 277850126 ps |
| CPU time | 31.31 seconds |
| Started | Jul 18 08:02:26 PM PDT 24 |
| Finished | Jul 18 08:02:58 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-3dd77091-917f-410d-a14e-ea84b257c2cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249327281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.249327281 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.3342003706 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2495695392 ps |
| CPU time | 103.1 seconds |
| Started | Jul 18 08:02:31 PM PDT 24 |
| Finished | Jul 18 08:04:15 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-4c6e79f5-7a7c-4ed3-9c70-3a5667340554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342003706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .3342003706 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.424658308 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 19740291328 ps |
| CPU time | 358.78 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:08:30 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-207a8fa8-ecc9-42cc-b8ba-5027bc15df52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424658308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.424658308 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3180305141 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 756820660 ps |
| CPU time | 32.86 seconds |
| Started | Jul 18 08:02:28 PM PDT 24 |
| Finished | Jul 18 08:03:02 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-e38a6f4e-dacd-41f8-84d5-ee0f06947dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180305141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3180305141 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.331136651 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 68608218 ps |
| CPU time | 9.1 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:02:37 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-89ea02c8-fc5c-4593-b062-8bfa07e960fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331136651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.331136651 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1866993643 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 630039177 ps |
| CPU time | 55.6 seconds |
| Started | Jul 18 08:02:36 PM PDT 24 |
| Finished | Jul 18 08:03:33 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-b1b11d92-31f1-4ad0-8c1e-f81a28aaf076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866993643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1866993643 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.223891325 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 19112932986 ps |
| CPU time | 214.54 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:06:04 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f7a9d81d-6a75-43f7-98cb-80f38ceecfef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223891325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.223891325 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3408682950 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 10747578605 ps |
| CPU time | 187.29 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:05:37 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-17911fde-4398-4e11-b2be-2352e5868a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408682950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3408682950 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3991379312 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 63789707 ps |
| CPU time | 8.4 seconds |
| Started | Jul 18 08:02:26 PM PDT 24 |
| Finished | Jul 18 08:02:35 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-27d917fa-7808-40cd-a62d-8fd5a8555ba5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991379312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3991379312 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2074931812 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 59555506 ps |
| CPU time | 6.99 seconds |
| Started | Jul 18 08:02:24 PM PDT 24 |
| Finished | Jul 18 08:02:32 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-2e19813d-1d3d-45b2-bff1-feb9767e011d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074931812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2074931812 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.2924250701 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 203981568 ps |
| CPU time | 8.88 seconds |
| Started | Jul 18 08:02:33 PM PDT 24 |
| Finished | Jul 18 08:02:44 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-e48568e6-8d2d-402e-b457-9cd52e55af1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924250701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.2924250701 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2821966683 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 4385231475 ps |
| CPU time | 51.66 seconds |
| Started | Jul 18 08:02:25 PM PDT 24 |
| Finished | Jul 18 08:03:17 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-e369ef3f-2131-4d47-acd2-e6cbba2d5302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821966683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2821966683 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.302566221 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 5780393165 ps |
| CPU time | 99.59 seconds |
| Started | Jul 18 08:02:26 PM PDT 24 |
| Finished | Jul 18 08:04:07 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-d6d399ba-c82b-4287-86da-f9e2459273d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302566221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.302566221 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.728876067 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 45814391 ps |
| CPU time | 6.24 seconds |
| Started | Jul 18 08:02:27 PM PDT 24 |
| Finished | Jul 18 08:02:34 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-c2cddbed-5661-416f-8aeb-c2b1a33f7407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728876067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .728876067 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.53107358 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 689542156 ps |
| CPU time | 60.69 seconds |
| Started | Jul 18 08:03:27 PM PDT 24 |
| Finished | Jul 18 08:04:28 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-df4b62e6-b7f9-4bfa-b83f-0b415f8ecfa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53107358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.53107358 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.4229412152 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 12341537111 ps |
| CPU time | 494.21 seconds |
| Started | Jul 18 08:02:30 PM PDT 24 |
| Finished | Jul 18 08:10:46 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-054988c2-22bb-459a-82d0-4bcc20110cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229412152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.4229412152 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2746188753 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 9290023238 ps |
| CPU time | 622.46 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:12:53 PM PDT 24 |
| Peak memory | 576556 kb |
| Host | smart-fce95f66-b9dd-4749-a674-971354e5a856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746188753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2746188753 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1807906046 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 496231671 ps |
| CPU time | 23.09 seconds |
| Started | Jul 18 08:02:28 PM PDT 24 |
| Finished | Jul 18 08:02:52 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-39d7b9a1-f2d9-4442-8888-db4f001f12c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807906046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1807906046 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.944428575 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 82126033211 ps |
| CPU time | 1590 seconds |
| Started | Jul 18 08:02:44 PM PDT 24 |
| Finished | Jul 18 08:29:16 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-9bf26485-33e8-4b3c-bf94-f2a2ed5c0a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944428575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_d evice_slow_rsp.944428575 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4131797475 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 190693307 ps |
| CPU time | 23.2 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:03:07 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-ecc4ada0-7e7e-4d39-ab37-eba6139105d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131797475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.4131797475 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2717694347 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 310048997 ps |
| CPU time | 25.89 seconds |
| Started | Jul 18 08:02:44 PM PDT 24 |
| Finished | Jul 18 08:03:10 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-42fa9a2c-3ff2-471f-839a-7a9393a3d94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717694347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2717694347 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.3234881059 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 865746384 ps |
| CPU time | 28.75 seconds |
| Started | Jul 18 08:02:41 PM PDT 24 |
| Finished | Jul 18 08:03:10 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-191208fb-4b6b-4f36-a903-283cdfe0e655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234881059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3234881059 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.274610728 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 7738233178 ps |
| CPU time | 93.4 seconds |
| Started | Jul 18 08:02:47 PM PDT 24 |
| Finished | Jul 18 08:04:21 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-455ea0b8-9e22-41e7-931b-e89a0368cbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274610728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.274610728 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2418843845 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 61482918858 ps |
| CPU time | 1184.16 seconds |
| Started | Jul 18 08:02:46 PM PDT 24 |
| Finished | Jul 18 08:22:31 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-8667095f-41c4-4df9-bf00-fde471190fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418843845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2418843845 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.255324167 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 244249140 ps |
| CPU time | 23.68 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:03:08 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-b941b688-8934-4014-a08a-ea3d3d1893a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255324167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.255324167 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.441577960 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 1246791761 ps |
| CPU time | 38.59 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:03:22 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-c7e941f9-6223-4e9e-818a-e41bd5f159c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441577960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.441577960 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.2920629049 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 41002573 ps |
| CPU time | 6.03 seconds |
| Started | Jul 18 08:02:30 PM PDT 24 |
| Finished | Jul 18 08:02:36 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-a66a7b13-6215-4eaa-823d-413f9cb34eaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920629049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2920629049 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1133561312 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 8986879575 ps |
| CPU time | 99.87 seconds |
| Started | Jul 18 08:02:41 PM PDT 24 |
| Finished | Jul 18 08:04:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-3b89c016-fb6a-4889-8097-808234a55f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133561312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1133561312 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.876083139 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 4678038946 ps |
| CPU time | 80.94 seconds |
| Started | Jul 18 08:02:44 PM PDT 24 |
| Finished | Jul 18 08:04:06 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-07267f47-04e9-4f99-b103-b8857f0bbad5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876083139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.876083139 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.4118555687 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 40228297 ps |
| CPU time | 5.91 seconds |
| Started | Jul 18 08:02:29 PM PDT 24 |
| Finished | Jul 18 08:02:36 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-77915fd1-174b-45a5-8346-483aaaaaf3d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118555687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.4118555687 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1814197773 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1210554479 ps |
| CPU time | 112.14 seconds |
| Started | Jul 18 08:02:46 PM PDT 24 |
| Finished | Jul 18 08:04:38 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-2bab0eb1-2253-48b6-ad00-e27c1c175e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814197773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1814197773 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3716229616 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 2757895575 ps |
| CPU time | 209.93 seconds |
| Started | Jul 18 08:02:47 PM PDT 24 |
| Finished | Jul 18 08:06:18 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-78614987-c655-434c-a0b0-9ed157d2f162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716229616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3716229616 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.557885081 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 246852657 ps |
| CPU time | 53.69 seconds |
| Started | Jul 18 08:02:46 PM PDT 24 |
| Finished | Jul 18 08:03:40 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-edf887e0-8c35-48cb-a5ab-efde5a205270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557885081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_ with_rand_reset.557885081 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.288032588 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 223871139 ps |
| CPU time | 53.97 seconds |
| Started | Jul 18 08:02:41 PM PDT 24 |
| Finished | Jul 18 08:03:36 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-b31715fa-4991-42f4-a356-403a10b0c224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288032588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.288032588 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.1102517817 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 1084313564 ps |
| CPU time | 40.87 seconds |
| Started | Jul 18 08:02:43 PM PDT 24 |
| Finished | Jul 18 08:03:25 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-830b8cde-f217-48ae-9e93-3ddc5446634d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102517817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.1102517817 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.3898578897 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 267964249 ps |
| CPU time | 20.13 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-61ccfb06-83ca-4400-adeb-633ad12d9fdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898578897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .3898578897 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1315047269 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 48753080159 ps |
| CPU time | 991.28 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:19:33 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-087e5e21-2955-4836-925b-4d0e1b5e0559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315047269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1315047269 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3366489004 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 1339241468 ps |
| CPU time | 54.37 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:56 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-10b1fb1c-107a-4cb5-b49a-da323ef2c84c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366489004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3366489004 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.2365391123 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 106150188 ps |
| CPU time | 6.99 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:03:08 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-c86f1ecb-4d05-4cd2-b80a-9b384e64ea81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365391123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.2365391123 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.1853721837 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 402316578 ps |
| CPU time | 33.54 seconds |
| Started | Jul 18 08:03:04 PM PDT 24 |
| Finished | Jul 18 08:03:38 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-2499e0c4-5fe7-4116-b877-5e31d54847bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853721837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.1853721837 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.217215387 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 42523022116 ps |
| CPU time | 477.32 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:10:56 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5f40f397-b9d5-46f3-9240-dcbeac4f2ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217215387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.217215387 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2830459865 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 8049706796 ps |
| CPU time | 140.78 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:05:23 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-a16aab4d-5148-4616-a1fa-a8dcf78a8d87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830459865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.2830459865 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1753043679 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 160454171 ps |
| CPU time | 15.72 seconds |
| Started | Jul 18 08:03:04 PM PDT 24 |
| Finished | Jul 18 08:03:20 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-55b34e8d-0996-489f-b700-4268602d09e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753043679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1753043679 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1424840949 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 1469703054 ps |
| CPU time | 47.39 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:03:47 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-91052782-360b-46f6-b6de-21ffbd51bd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424840949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1424840949 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.1786633367 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 207980396 ps |
| CPU time | 9.54 seconds |
| Started | Jul 18 08:02:44 PM PDT 24 |
| Finished | Jul 18 08:02:54 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c5670140-ded3-4bcb-b8d6-c723ec4c95c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786633367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.1786633367 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.3409775075 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 5620346408 ps |
| CPU time | 63.12 seconds |
| Started | Jul 18 08:03:02 PM PDT 24 |
| Finished | Jul 18 08:04:06 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-123853de-27f8-4f94-bb44-625d8cbc3c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409775075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.3409775075 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1895621790 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 5577929940 ps |
| CPU time | 99.21 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:04:39 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-b1c2cb98-bd5c-44d0-8d91-dab52aa9a79d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895621790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1895621790 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.3334046298 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 50955807 ps |
| CPU time | 6.58 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:08 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-90e775bf-72b1-4d0b-abca-cc17263ccf78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334046298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.3334046298 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2096414993 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1633916508 ps |
| CPU time | 133.72 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:05:16 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-734e8d63-735f-4c45-b3c8-8f5c7427d928 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096414993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2096414993 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1107125297 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 15964389965 ps |
| CPU time | 645.4 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:13:48 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-137649be-e772-4a34-bfeb-835178e38dd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107125297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1107125297 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2308966972 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 5058225719 ps |
| CPU time | 394.75 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:09:36 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6c314df8-c458-4104-b6b3-4f28e5f9a4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308966972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2308966972 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2010927645 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 5481456609 ps |
| CPU time | 484.04 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:11:06 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3078f73c-376b-46fa-a422-6718feef8319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010927645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2010927645 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3699972531 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 495245620 ps |
| CPU time | 21.92 seconds |
| Started | Jul 18 08:03:01 PM PDT 24 |
| Finished | Jul 18 08:03:24 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-cf984259-ea94-45f3-bf44-bddbcc2009cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699972531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3699972531 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.2139270157 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 237764246 ps |
| CPU time | 17.8 seconds |
| Started | Jul 18 08:03:04 PM PDT 24 |
| Finished | Jul 18 08:03:22 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-499feb80-0128-4953-8854-b1d423254625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139270157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .2139270157 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1914009572 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 107082234058 ps |
| CPU time | 2144.25 seconds |
| Started | Jul 18 08:03:01 PM PDT 24 |
| Finished | Jul 18 08:38:47 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-f5c17865-2fa9-4067-952e-937a11fe1872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914009572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1914009572 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1295326072 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 411628309 ps |
| CPU time | 17.6 seconds |
| Started | Jul 18 08:03:27 PM PDT 24 |
| Finished | Jul 18 08:03:46 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-d3ff866f-1105-49a9-b08d-0491619370d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295326072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1295326072 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.534659394 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1230586996 ps |
| CPU time | 47.03 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:49 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-9ebb9647-1714-4443-b35e-0672c5de3c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534659394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.534659394 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.4271494703 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 63205994139 ps |
| CPU time | 781.15 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:16:03 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-281d6728-80bb-4dd9-8406-c988ebbc44a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271494703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.4271494703 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2438073860 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 15621521905 ps |
| CPU time | 288.67 seconds |
| Started | Jul 18 08:03:03 PM PDT 24 |
| Finished | Jul 18 08:07:52 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-e51cd7bb-3957-4541-b47d-82194629b542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438073860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2438073860 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2890023419 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 504755442 ps |
| CPU time | 48 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:03:49 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-3043940a-86c6-4505-86e5-c93349eb75df |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890023419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2890023419 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.1646133928 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2543832625 ps |
| CPU time | 75.38 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:04:47 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-b7b64ed0-cbbf-4b46-9a38-e2187c427134 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646133928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.1646133928 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2032640347 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 40423814 ps |
| CPU time | 6.06 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:08 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-4d9fbb3e-2c14-4122-8216-7315364c0dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032640347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2032640347 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.303408742 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 8342255629 ps |
| CPU time | 93.05 seconds |
| Started | Jul 18 08:02:59 PM PDT 24 |
| Finished | Jul 18 08:04:34 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b8d0de01-4f37-46a7-96ae-b291634d5126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303408742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.303408742 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2455808453 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 5884313711 ps |
| CPU time | 102.76 seconds |
| Started | Jul 18 08:03:02 PM PDT 24 |
| Finished | Jul 18 08:04:46 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-79177481-3369-4b55-bccc-4ff8701cced0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455808453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2455808453 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.263868190 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 38610978 ps |
| CPU time | 6.11 seconds |
| Started | Jul 18 08:03:00 PM PDT 24 |
| Finished | Jul 18 08:03:08 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-3461044e-bc32-4e01-9f3f-68a98c505ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263868190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delays .263868190 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.4021059491 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 5838150142 ps |
| CPU time | 225.39 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:07:16 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-772b92a1-2aad-495d-bb23-f11c07882636 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021059491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.4021059491 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1867443225 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 1707058917 ps |
| CPU time | 59.8 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:04:30 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-4ed39b17-4441-403d-a553-95490a72c488 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867443225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1867443225 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3031872127 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 10707131387 ps |
| CPU time | 652.53 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:14:24 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-90f9c1ea-a66a-4ffa-8d48-0dbab137caaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031872127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3031872127 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.134917415 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 272130646 ps |
| CPU time | 84.89 seconds |
| Started | Jul 18 08:03:31 PM PDT 24 |
| Finished | Jul 18 08:04:57 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-57edc702-845e-488f-982c-1768ed52685b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134917415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.134917415 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.977852065 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 646008995 ps |
| CPU time | 29.73 seconds |
| Started | Jul 18 08:03:31 PM PDT 24 |
| Finished | Jul 18 08:04:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-f97ccbe3-b41e-4325-af1a-8bad76486d8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977852065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.977852065 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.1378114457 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 248632281 ps |
| CPU time | 12.29 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:03:44 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-1a2be65f-8e8d-4068-bcf9-66f3b8214757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378114457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .1378114457 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.2982765340 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 289282426 ps |
| CPU time | 32.11 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:04:04 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-0fefa7c6-9be1-4b18-a47d-4d79d8eb95d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982765340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.2982765340 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.260721046 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 2215952281 ps |
| CPU time | 68.06 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:04:39 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b498c6ee-98be-42b1-aae9-b1ebced7fb23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260721046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.260721046 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.295327259 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 578519675 ps |
| CPU time | 52.6 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:04:25 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-a50ffe4f-7a1f-4074-a58b-dc59e8827058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295327259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.295327259 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.711640793 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 84962531313 ps |
| CPU time | 1054.53 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:21:05 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-301cb082-1ddf-4bd7-b621-72b97f315849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711640793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.711640793 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.117174875 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 26543839198 ps |
| CPU time | 493.64 seconds |
| Started | Jul 18 08:03:32 PM PDT 24 |
| Finished | Jul 18 08:11:47 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-aac4f028-0459-43cb-8167-bb7c7b070e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117174875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.117174875 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.284065434 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 236997398 ps |
| CPU time | 23.76 seconds |
| Started | Jul 18 08:03:33 PM PDT 24 |
| Finished | Jul 18 08:03:57 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-ab8f3cd7-9d8a-4377-902b-c9a56cec5211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284065434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.284065434 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1024363542 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 444640391 ps |
| CPU time | 31.53 seconds |
| Started | Jul 18 08:03:28 PM PDT 24 |
| Finished | Jul 18 08:04:00 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-4a0910c8-e89e-44b0-a8ca-b2bf24e595f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024363542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1024363542 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.3994151135 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 173260751 ps |
| CPU time | 8.89 seconds |
| Started | Jul 18 08:03:30 PM PDT 24 |
| Finished | Jul 18 08:03:40 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-d13cd65a-3c0d-4388-a72a-080d9252172c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994151135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.3994151135 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.1144433111 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 9519132623 ps |
| CPU time | 107.48 seconds |
| Started | Jul 18 08:03:32 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8156b791-c118-40f0-95a8-e3f2e6272770 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144433111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.1144433111 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3569444386 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 4455974662 ps |
| CPU time | 79.04 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:04:49 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-86485c59-2da9-4b4c-9b62-b334589de205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569444386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3569444386 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3268836463 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 48549147 ps |
| CPU time | 6.05 seconds |
| Started | Jul 18 08:03:31 PM PDT 24 |
| Finished | Jul 18 08:03:39 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ff75a61b-4c8a-4ca1-964b-559133ebd3a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268836463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.3268836463 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.4207669344 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 9062489269 ps |
| CPU time | 334.32 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:09:05 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-e46a07ea-888e-4e51-8cf9-2795618a6489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207669344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.4207669344 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.350623443 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 1031066347 ps |
| CPU time | 41.4 seconds |
| Started | Jul 18 08:03:49 PM PDT 24 |
| Finished | Jul 18 08:04:33 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b28a9768-7397-423b-9ebb-3a9c35a0067e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350623443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.350623443 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.2697718347 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 7495191 ps |
| CPU time | 31.48 seconds |
| Started | Jul 18 08:03:56 PM PDT 24 |
| Finished | Jul 18 08:04:29 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-84a1f55f-be21-4590-a628-0f4b3fa1bd14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697718347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.2697718347 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.48461223 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 324174096 ps |
| CPU time | 16.96 seconds |
| Started | Jul 18 08:03:29 PM PDT 24 |
| Finished | Jul 18 08:03:47 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-919da40e-e95a-4014-846f-737800f408a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48461223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.48461223 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.560715281 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 3149158142 ps |
| CPU time | 117.49 seconds |
| Started | Jul 18 08:03:55 PM PDT 24 |
| Finished | Jul 18 08:05:54 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-7bca4223-46d5-4df2-8b76-ddc0a681ca29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560715281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 560715281 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3893537820 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 66697372176 ps |
| CPU time | 1206.08 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:24:00 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-190a974b-ddf4-4cc5-a506-9b84250cb180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893537820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3893537820 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2434510243 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 381154455 ps |
| CPU time | 17.33 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:04:09 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-820da77b-369a-42a3-8e43-d5f3cf0d4f62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434510243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2434510243 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.571457095 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 1832401976 ps |
| CPU time | 66.92 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:05:02 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2df12c40-92ef-4de0-b295-342e63197bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571457095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.571457095 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1724755803 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 505391167 ps |
| CPU time | 48.08 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:04:42 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-a6ab92a0-ba9f-4721-be36-43cffb376853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724755803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1724755803 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3210717734 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 60785367288 ps |
| CPU time | 678.05 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:15:10 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-e0f67706-1594-4c21-8afb-373d880de843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210717734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3210717734 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3964643220 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 37437271532 ps |
| CPU time | 665.85 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:14:58 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d2ed9580-1c35-475a-b80f-bb40385a8b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964643220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3964643220 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3965313855 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 430308820 ps |
| CPU time | 36.74 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:04:29 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-57d793fe-021a-4699-b199-b813449548e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965313855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3965313855 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.3434682161 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 2420001168 ps |
| CPU time | 68.91 seconds |
| Started | Jul 18 08:03:55 PM PDT 24 |
| Finished | Jul 18 08:05:06 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-bcc7bc8c-091b-4743-88f1-e3147e5289a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434682161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3434682161 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.2025263520 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 219127847 ps |
| CPU time | 9.3 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-fe041320-d231-46e0-9a9a-2edca183937b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025263520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.2025263520 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.1912903025 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 9257544473 ps |
| CPU time | 108.74 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:05:41 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-83a55f2a-6a9d-4537-a0e1-1f36c4f98f3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912903025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.1912903025 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2907632532 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 5071270064 ps |
| CPU time | 90.21 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:05:25 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-e4fdf47c-9114-4c7f-a85f-fa95dd622a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907632532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2907632532 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1129809541 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 48315730 ps |
| CPU time | 6.03 seconds |
| Started | Jul 18 08:03:51 PM PDT 24 |
| Finished | Jul 18 08:03:59 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-1a453e52-075e-4c64-a8dd-957239b18402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129809541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1129809541 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3676379014 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 3496872085 ps |
| CPU time | 262.38 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:08:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a5c3d756-32ee-4858-b56a-35e24ed79c43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676379014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3676379014 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.3047454566 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 8723137465 ps |
| CPU time | 308.78 seconds |
| Started | Jul 18 08:03:54 PM PDT 24 |
| Finished | Jul 18 08:09:05 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-20da39dd-e489-436d-8735-e2c97d05a2f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047454566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.3047454566 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.1217400651 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 2560270138 ps |
| CPU time | 268.69 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:08:23 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-cfe8e0e7-3b55-49f4-a524-d18dd87db15b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217400651 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.1217400651 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.2811761994 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 3440943601 ps |
| CPU time | 263.44 seconds |
| Started | Jul 18 08:03:56 PM PDT 24 |
| Finished | Jul 18 08:08:21 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-b3fc1beb-9af5-487b-a38a-a6b3de9bf8e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811761994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.2811761994 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1189512439 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 191842983 ps |
| CPU time | 12.14 seconds |
| Started | Jul 18 08:03:48 PM PDT 24 |
| Finished | Jul 18 08:04:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-0e4e4913-9d1c-4d80-9150-068b4389719a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189512439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1189512439 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2563468025 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 6964642697 ps |
| CPU time | 551.31 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 07:54:29 PM PDT 24 |
| Peak memory | 638656 kb |
| Host | smart-3c04b7fc-8638-4996-ab50-b51cd7823147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563468025 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.2563468025 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1126088258 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4705598060 ps |
| CPU time | 352.26 seconds |
| Started | Jul 18 07:45:24 PM PDT 24 |
| Finished | Jul 18 07:51:18 PM PDT 24 |
| Peak memory | 597588 kb |
| Host | smart-f38bdb13-213d-499c-ba2e-b8343e2b5c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126088258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1126088258 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3960054473 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 30918216987 ps |
| CPU time | 5323.01 seconds |
| Started | Jul 18 07:44:54 PM PDT 24 |
| Finished | Jul 18 09:13:38 PM PDT 24 |
| Peak memory | 593144 kb |
| Host | smart-c55331f2-dfb0-422b-bc78-9b6162a70e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960054473 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3960054473 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.3398225723 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 6060198600 ps |
| CPU time | 737.4 seconds |
| Started | Jul 18 07:45:00 PM PDT 24 |
| Finished | Jul 18 07:57:18 PM PDT 24 |
| Peak memory | 603732 kb |
| Host | smart-817fba21-65e0-4923-a2cb-1b898d77cbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398225723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.3398225723 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2953092786 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 556049288 ps |
| CPU time | 26.05 seconds |
| Started | Jul 18 07:44:56 PM PDT 24 |
| Finished | Jul 18 07:45:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-564542d0-c821-4eab-b562-b1e30e703c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953092786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2953092786 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1562599913 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 536075994 ps |
| CPU time | 21.84 seconds |
| Started | Jul 18 07:45:21 PM PDT 24 |
| Finished | Jul 18 07:45:43 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-f5e4e83f-3df7-44f9-80b8-0beb302372bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562599913 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .1562599913 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.737355195 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 2455538857 ps |
| CPU time | 83.99 seconds |
| Started | Jul 18 07:44:52 PM PDT 24 |
| Finished | Jul 18 07:46:17 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-31337e7b-2d8b-4eb7-95bb-3b449c9b5ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737355195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.737355195 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.3391773445 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 2640175899 ps |
| CPU time | 81.95 seconds |
| Started | Jul 18 07:45:01 PM PDT 24 |
| Finished | Jul 18 07:46:23 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-e92709cf-c409-477b-8b0a-5bf6088a119d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391773445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.3391773445 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.1054828255 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 56400277485 ps |
| CPU time | 639.93 seconds |
| Started | Jul 18 07:44:54 PM PDT 24 |
| Finished | Jul 18 07:55:34 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c28f590c-9f5c-434c-b356-bb63b2c7436e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054828255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.1054828255 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3816670474 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 50888110569 ps |
| CPU time | 844.33 seconds |
| Started | Jul 18 07:44:54 PM PDT 24 |
| Finished | Jul 18 07:58:59 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-ec2f833b-ac95-4073-b030-f4a9a404cadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816670474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3816670474 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.1898766623 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 566276665 ps |
| CPU time | 43.53 seconds |
| Started | Jul 18 07:44:52 PM PDT 24 |
| Finished | Jul 18 07:45:36 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-bad600fe-ff07-4955-9973-4b79d12348e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898766623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.1898766623 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.4226940365 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 1954643191 ps |
| CPU time | 65.88 seconds |
| Started | Jul 18 07:44:57 PM PDT 24 |
| Finished | Jul 18 07:46:03 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-92a0e859-6e6c-4c94-a6ac-8402f5b5e872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226940365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.4226940365 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1169296446 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 200180732 ps |
| CPU time | 9.14 seconds |
| Started | Jul 18 07:44:53 PM PDT 24 |
| Finished | Jul 18 07:45:03 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-ae195f28-99d0-4a9f-9e4f-5feae3a73f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169296446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1169296446 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2982182466 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 7843607767 ps |
| CPU time | 84.8 seconds |
| Started | Jul 18 07:44:57 PM PDT 24 |
| Finished | Jul 18 07:46:22 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-eaa6d1c1-08ad-4a62-8abb-8302015b8c91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982182466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2982182466 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1546504912 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 5837952935 ps |
| CPU time | 106.36 seconds |
| Started | Jul 18 07:44:53 PM PDT 24 |
| Finished | Jul 18 07:46:41 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-8b66c7b9-542d-4393-a616-b64820acac15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546504912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1546504912 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2524436840 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 53476498 ps |
| CPU time | 6.28 seconds |
| Started | Jul 18 07:45:00 PM PDT 24 |
| Finished | Jul 18 07:45:07 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-b51d52ea-f2c7-4e46-b631-0be249603e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524436840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2524436840 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.1234389948 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 1360106165 ps |
| CPU time | 128.69 seconds |
| Started | Jul 18 07:45:16 PM PDT 24 |
| Finished | Jul 18 07:47:25 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b4cb951e-fa22-4d85-8bed-36f6fbd4dd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234389948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1234389948 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1007680653 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 3501639007 ps |
| CPU time | 105.13 seconds |
| Started | Jul 18 07:45:24 PM PDT 24 |
| Finished | Jul 18 07:47:10 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8f650bd3-9742-4231-bb85-dacf99e3df12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007680653 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.1007680653 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3242387511 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6766184694 ps |
| CPU time | 529.99 seconds |
| Started | Jul 18 07:45:24 PM PDT 24 |
| Finished | Jul 18 07:54:15 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c7433c2a-3f3e-4d43-8e60-76d944fa7269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242387511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.3242387511 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.3590913650 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 268411258 ps |
| CPU time | 104.06 seconds |
| Started | Jul 18 07:45:18 PM PDT 24 |
| Finished | Jul 18 07:47:03 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c6387916-56c7-4a53-8a71-6795f173787b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590913650 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.3590913650 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.1932882615 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 1156440750 ps |
| CPU time | 53.56 seconds |
| Started | Jul 18 07:45:18 PM PDT 24 |
| Finished | Jul 18 07:46:12 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-a7e4c2a3-46b4-4acf-ab46-9a168d64acca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932882615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1932882615 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2599586052 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 2188072557 ps |
| CPU time | 75.77 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:05:10 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-804f8196-3252-45d0-9665-32da723bb3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599586052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2599586052 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.1775657987 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 48218353192 ps |
| CPU time | 950.01 seconds |
| Started | Jul 18 08:03:51 PM PDT 24 |
| Finished | Jul 18 08:19:43 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-3f84ae1d-d724-4d5f-8c0a-fec1ccec38a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775657987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.1775657987 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3322636252 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 218172128 ps |
| CPU time | 25.32 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:04:20 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-56a1d3f7-3c1e-469b-98fb-d4591ffb9c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322636252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3322636252 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.3433028605 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 293614642 ps |
| CPU time | 21.52 seconds |
| Started | Jul 18 08:03:49 PM PDT 24 |
| Finished | Jul 18 08:04:12 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-b22769fd-53dd-47c6-a98e-3422ec6b4237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433028605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3433028605 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.2129672804 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 2079109729 ps |
| CPU time | 72.7 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:05:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-14040ffb-9a86-4cb5-ac05-92c07a1224ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129672804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.2129672804 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2735337855 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 72851522600 ps |
| CPU time | 923.13 seconds |
| Started | Jul 18 08:03:48 PM PDT 24 |
| Finished | Jul 18 08:19:14 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-ddd4e21a-1a68-47c3-9bea-b7f59983b689 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735337855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2735337855 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2845724464 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 47622431069 ps |
| CPU time | 923.56 seconds |
| Started | Jul 18 08:03:54 PM PDT 24 |
| Finished | Jul 18 08:19:20 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-ba6f57bf-7a51-4f38-80fd-215558f09ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845724464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2845724464 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2920793664 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 77900153 ps |
| CPU time | 8.98 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:04 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-ae590263-3b3f-4357-8d2a-3e590618d38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920793664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2920793664 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.1677022709 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 234232759 ps |
| CPU time | 18.32 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:13 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-0ccbd37b-932b-4d89-9e9a-50f7c7cfa9b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677022709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.1677022709 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.3135847776 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 48349890 ps |
| CPU time | 6.63 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:02 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-6597e2f8-b92f-4f49-aac1-d6010ca118e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135847776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3135847776 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.3594981687 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 8259477345 ps |
| CPU time | 94.71 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:05:30 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-e6072ff4-0fc0-42cf-90dc-6c03c2e5e860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594981687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.3594981687 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3597720945 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 4518907426 ps |
| CPU time | 79.04 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:05:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-8f86c50c-5009-43a7-be1d-7c2d2b6f8e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597720945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3597720945 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1482653748 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 54888197 ps |
| CPU time | 6.86 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-3bd651d5-cc2e-43ef-a0fa-9c5679099ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482653748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.1482653748 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.4182757278 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 1230445890 ps |
| CPU time | 95.18 seconds |
| Started | Jul 18 08:03:50 PM PDT 24 |
| Finished | Jul 18 08:05:27 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-a44b5d6a-129e-482c-a39b-355a798532ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182757278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.4182757278 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1025918284 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 3760886970 ps |
| CPU time | 121.12 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:05:56 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-1481cb45-94d4-404b-9933-aa9b9b73ec48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025918284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1025918284 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.439093308 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 632685481 ps |
| CPU time | 176.01 seconds |
| Started | Jul 18 08:03:49 PM PDT 24 |
| Finished | Jul 18 08:06:47 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-6ac50ff6-498b-40c6-acd3-5b38678abe9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439093308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.439093308 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.2550978074 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 29900248 ps |
| CPU time | 21.45 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:17 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-c88dd4a8-ec70-4835-90e2-e3fc61d91769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550978074 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.2550978074 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.2988371630 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1230959355 ps |
| CPU time | 48.82 seconds |
| Started | Jul 18 08:03:56 PM PDT 24 |
| Finished | Jul 18 08:04:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-af6c8ea1-aef4-472e-ac29-f12237e997b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988371630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.2988371630 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.1998568936 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 2471853549 ps |
| CPU time | 115.49 seconds |
| Started | Jul 18 08:04:04 PM PDT 24 |
| Finished | Jul 18 08:06:00 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c880fe85-1ec6-4ed0-9cae-5be35503fb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998568936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .1998568936 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.4264193143 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 71426524740 ps |
| CPU time | 1286.91 seconds |
| Started | Jul 18 08:04:08 PM PDT 24 |
| Finished | Jul 18 08:25:36 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3505da53-d8f7-4444-8c04-188a3955312f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264193143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.4264193143 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.2949994733 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 268817600 ps |
| CPU time | 26.58 seconds |
| Started | Jul 18 08:04:09 PM PDT 24 |
| Finished | Jul 18 08:04:37 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-121b7031-2d67-478e-a49e-f56f631a93fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949994733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.2949994733 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.770078959 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 599229210 ps |
| CPU time | 45.22 seconds |
| Started | Jul 18 08:04:07 PM PDT 24 |
| Finished | Jul 18 08:04:54 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-8354de29-4a8c-4437-be8a-c53521e219e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770078959 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.770078959 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.127060716 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 2418126277 ps |
| CPU time | 83.41 seconds |
| Started | Jul 18 08:03:54 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-fbb5f536-dfaa-41ef-b608-ce2140bcc685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127060716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.127060716 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.2861872417 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 47238827957 ps |
| CPU time | 520.89 seconds |
| Started | Jul 18 08:04:03 PM PDT 24 |
| Finished | Jul 18 08:12:45 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-6604843d-8bac-404d-87c5-2ea8ffa3587e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861872417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.2861872417 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3349093274 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 24184675155 ps |
| CPU time | 474.67 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:12:01 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-7886cc9b-84d2-440a-9d13-a0afb6926317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349093274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3349093274 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.3428232575 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 557785507 ps |
| CPU time | 44.54 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:39 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-b4252218-5b60-4dc2-81b6-6a189d720d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428232575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.3428232575 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3122106221 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 2096804032 ps |
| CPU time | 60.76 seconds |
| Started | Jul 18 08:04:09 PM PDT 24 |
| Finished | Jul 18 08:05:11 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-57966937-f70c-437e-bbab-1fc6a95e9398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122106221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3122106221 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.2247581710 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 45879581 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-3bf913bb-0a33-43fd-86f2-792432c92a1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247581710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2247581710 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.4050987069 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 9569569759 ps |
| CPU time | 117.03 seconds |
| Started | Jul 18 08:03:51 PM PDT 24 |
| Finished | Jul 18 08:05:50 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-2d2437a8-82d0-4e4c-bff9-aff58acc490f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050987069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.4050987069 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.2983936802 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 5647123472 ps |
| CPU time | 99.08 seconds |
| Started | Jul 18 08:03:52 PM PDT 24 |
| Finished | Jul 18 08:05:33 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-03648b1c-79f2-4623-acc2-be4d2b9688b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983936802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.2983936802 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.2203596385 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 46530161 ps |
| CPU time | 6.23 seconds |
| Started | Jul 18 08:03:53 PM PDT 24 |
| Finished | Jul 18 08:04:01 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-4c9f24f0-2bb6-4795-b9a5-ca465b93425b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203596385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.2203596385 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.953562183 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 10593046596 ps |
| CPU time | 401.47 seconds |
| Started | Jul 18 08:04:10 PM PDT 24 |
| Finished | Jul 18 08:10:53 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-9588c435-6f50-46c5-8d0a-d72dcc5f5e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953562183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.953562183 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.438001686 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 235856213 ps |
| CPU time | 11.37 seconds |
| Started | Jul 18 08:04:06 PM PDT 24 |
| Finished | Jul 18 08:04:18 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-febaa9f5-03f6-4ca8-808d-03b7aef3d814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438001686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.438001686 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3622687173 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 6064579139 ps |
| CPU time | 290.53 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:08:57 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-6845a59c-3494-40eb-bf1e-bfd76889a88e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622687173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3622687173 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2207970405 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 148521417 ps |
| CPU time | 18.84 seconds |
| Started | Jul 18 08:04:09 PM PDT 24 |
| Finished | Jul 18 08:04:30 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-cf52c717-5ba9-427c-addf-3ed88daeb628 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207970405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2207970405 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.4257619332 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 455970889 ps |
| CPU time | 21.5 seconds |
| Started | Jul 18 08:04:06 PM PDT 24 |
| Finished | Jul 18 08:04:29 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-ebe6e08e-ed0d-489b-8ee8-338e424e4a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257619332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .4257619332 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.443894138 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 94073615378 ps |
| CPU time | 1882 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:35:28 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-cfcda7c4-e900-42a3-888f-7ea933e7f4ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443894138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.443894138 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3652711327 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 440326117 ps |
| CPU time | 17.96 seconds |
| Started | Jul 18 08:04:07 PM PDT 24 |
| Finished | Jul 18 08:04:26 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-2214053d-92c7-4062-9ee2-26b04d6d0392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652711327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.3652711327 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2855724494 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 204740095 ps |
| CPU time | 19.58 seconds |
| Started | Jul 18 08:04:07 PM PDT 24 |
| Finished | Jul 18 08:04:28 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a35f1832-39d0-4b1d-ac23-920617c625b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855724494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2855724494 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.3107631978 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 518146410 ps |
| CPU time | 49.91 seconds |
| Started | Jul 18 08:04:06 PM PDT 24 |
| Finished | Jul 18 08:04:57 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e8db0ba2-73f6-4980-a8a4-4d0449f8a2ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107631978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3107631978 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.1978796473 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 60234523754 ps |
| CPU time | 685.99 seconds |
| Started | Jul 18 08:04:03 PM PDT 24 |
| Finished | Jul 18 08:15:30 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a13e4bb0-e729-46d8-81e6-424fef925820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978796473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.1978796473 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.2683693159 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 49944309511 ps |
| CPU time | 926.12 seconds |
| Started | Jul 18 08:04:10 PM PDT 24 |
| Finished | Jul 18 08:19:37 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2eb04eb2-8534-4211-8918-7041af724651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683693159 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.2683693159 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.2352253776 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 274389926 ps |
| CPU time | 26.86 seconds |
| Started | Jul 18 08:04:10 PM PDT 24 |
| Finished | Jul 18 08:04:38 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-44b0a40d-0519-4644-acae-6b5f4a44e5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352253776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.2352253776 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.922961225 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 2564373170 ps |
| CPU time | 74.8 seconds |
| Started | Jul 18 08:04:04 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a045d486-722e-4d61-8007-caafcfd778ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922961225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.922961225 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.3957936781 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 181464870 ps |
| CPU time | 8.32 seconds |
| Started | Jul 18 08:04:09 PM PDT 24 |
| Finished | Jul 18 08:04:18 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-c83741f8-7e62-486d-a347-df529c43a822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957936781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3957936781 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3122311860 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 9161877446 ps |
| CPU time | 96.16 seconds |
| Started | Jul 18 08:04:08 PM PDT 24 |
| Finished | Jul 18 08:05:46 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-7ae764d6-8469-4b33-b921-b9bd0824cd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122311860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3122311860 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.4103865089 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 5567545830 ps |
| CPU time | 99.96 seconds |
| Started | Jul 18 08:04:06 PM PDT 24 |
| Finished | Jul 18 08:05:47 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e83d8032-8ec0-48f1-8dc5-2e9e648ef56e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103865089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.4103865089 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3424217033 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 42923505 ps |
| CPU time | 6.3 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:04:12 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-7c09d30e-2a5a-417c-9003-1ffcc30388ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424217033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3424217033 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2473082198 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 1730943670 ps |
| CPU time | 153.89 seconds |
| Started | Jul 18 08:04:07 PM PDT 24 |
| Finished | Jul 18 08:06:42 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-661a7392-615c-4235-94b4-15cd9ff73bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473082198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2473082198 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2875540752 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 4072372443 ps |
| CPU time | 313.19 seconds |
| Started | Jul 18 08:04:06 PM PDT 24 |
| Finished | Jul 18 08:09:21 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-34ef7a0a-aa71-4f84-b8a4-8bf7bac2fba7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875540752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2875540752 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.748248131 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 84264116 ps |
| CPU time | 13.8 seconds |
| Started | Jul 18 08:04:04 PM PDT 24 |
| Finished | Jul 18 08:04:18 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-1dd86dc8-27a1-43f0-9bef-c42a1da4350f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748248131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.748248131 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.3214447054 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 34760684 ps |
| CPU time | 30.68 seconds |
| Started | Jul 18 08:04:05 PM PDT 24 |
| Finished | Jul 18 08:04:36 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-605933c3-45e7-412b-a762-6dfd5cd14e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214447054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.3214447054 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2001063695 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 824302331 ps |
| CPU time | 37.33 seconds |
| Started | Jul 18 08:04:04 PM PDT 24 |
| Finished | Jul 18 08:04:42 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-91d4a309-29dd-4ed4-ad34-fdb6ccb22a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001063695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2001063695 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3072908374 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 199483536 ps |
| CPU time | 16.59 seconds |
| Started | Jul 18 08:04:27 PM PDT 24 |
| Finished | Jul 18 08:04:44 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-29dd7757-6596-45f6-84a6-38d7cd989cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072908374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3072908374 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.4023184121 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 130839500128 ps |
| CPU time | 2456.6 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:45:20 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-fcd2585e-ac6d-4687-8052-833e5e881320 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023184121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.4023184121 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2718826611 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 263274482 ps |
| CPU time | 12.23 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:04:35 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-b107acbd-215e-4f05-b29e-22c03af2a87b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718826611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2718826611 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.526433336 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 1974994554 ps |
| CPU time | 68.17 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:05:33 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ae5c6f77-7057-44a2-bd21-8ef17250e0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526433336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.526433336 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.3256312563 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 291596148 ps |
| CPU time | 26.89 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:04:54 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-357f8007-0ed2-4f8c-901c-9a0e11cb375b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256312563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.3256312563 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.2104904177 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 73845346047 ps |
| CPU time | 812.54 seconds |
| Started | Jul 18 08:07:23 PM PDT 24 |
| Finished | Jul 18 08:20:56 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-85653b94-be99-4801-a0ed-fc358f4ec34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104904177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.2104904177 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.4054354563 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 16431276274 ps |
| CPU time | 269.3 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:08:53 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-8371cd4c-8215-430e-9412-fa9784d115e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054354563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.4054354563 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3844723489 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 561143340 ps |
| CPU time | 45.33 seconds |
| Started | Jul 18 08:04:30 PM PDT 24 |
| Finished | Jul 18 08:05:17 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-ffd7a56d-0bcb-4987-a67a-2bd38842c032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844723489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3844723489 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.274793588 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 1506260993 ps |
| CPU time | 45.55 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:05:12 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-e6cdb9bc-bbb7-46b4-a251-a00256e68b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274793588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.274793588 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.647308191 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 256678264 ps |
| CPU time | 10.3 seconds |
| Started | Jul 18 08:04:33 PM PDT 24 |
| Finished | Jul 18 08:04:45 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-bfeba91d-ea1f-4cb3-9502-75d7773328e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647308191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.647308191 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.3198496004 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 7174036372 ps |
| CPU time | 80.91 seconds |
| Started | Jul 18 08:04:31 PM PDT 24 |
| Finished | Jul 18 08:05:53 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-ca92f006-1c53-46d0-848b-7c496072ea54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198496004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.3198496004 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3057612475 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 5034752647 ps |
| CPU time | 89.96 seconds |
| Started | Jul 18 08:09:15 PM PDT 24 |
| Finished | Jul 18 08:10:45 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e143e4e2-a736-4710-bb49-d8b623dc6410 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057612475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3057612475 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2563321372 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 49011363 ps |
| CPU time | 6.45 seconds |
| Started | Jul 18 08:04:21 PM PDT 24 |
| Finished | Jul 18 08:04:28 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-e5effcff-5a84-4c6f-b57e-71b44d7dbaca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563321372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2563321372 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.52652508 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 8061403830 ps |
| CPU time | 321.79 seconds |
| Started | Jul 18 08:04:23 PM PDT 24 |
| Finished | Jul 18 08:09:45 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-2fbcd74d-5fbb-4d4c-9e47-e6cedef5f6ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52652508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.52652508 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2689630934 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 15069886629 ps |
| CPU time | 623.31 seconds |
| Started | Jul 18 08:04:27 PM PDT 24 |
| Finished | Jul 18 08:14:51 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d1dfd8e2-9598-4d4c-8544-06a15d752585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689630934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2689630934 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.2788606046 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 6427509158 ps |
| CPU time | 475.61 seconds |
| Started | Jul 18 08:04:34 PM PDT 24 |
| Finished | Jul 18 08:12:31 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-ffda12f8-8374-4a5e-949c-8c7f801ba23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788606046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.2788606046 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.386358071 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 3948621570 ps |
| CPU time | 405.95 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:11:12 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-c63f4dc3-4b6d-46c0-b8f0-32393fb70eb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386358071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_reset_error.386358071 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.459446551 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 227255624 ps |
| CPU time | 11.78 seconds |
| Started | Jul 18 08:04:23 PM PDT 24 |
| Finished | Jul 18 08:04:36 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-18d2a6a7-5c4a-4e32-9e3f-12798efc2048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459446551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.459446551 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.212181717 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 758658732 ps |
| CPU time | 34.13 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:05:00 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-eb985994-b5a7-45d3-a583-89fc4547017d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212181717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device. 212181717 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3176831227 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 120842612857 ps |
| CPU time | 2594.14 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:47:41 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-a5bdd54d-5712-4a51-bce2-0bf3e505cabf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176831227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3176831227 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2263274845 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 1292803459 ps |
| CPU time | 48.3 seconds |
| Started | Jul 18 08:04:28 PM PDT 24 |
| Finished | Jul 18 08:05:18 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-eab519c6-0f2a-41c3-87e8-875a1d866799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263274845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.2263274845 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.1930558206 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 860884301 ps |
| CPU time | 29.31 seconds |
| Started | Jul 18 08:04:26 PM PDT 24 |
| Finished | Jul 18 08:04:56 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-18849a28-3837-4f87-847f-cdb02ad1a1ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930558206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.1930558206 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.1987279629 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 559435318 ps |
| CPU time | 43.68 seconds |
| Started | Jul 18 08:04:23 PM PDT 24 |
| Finished | Jul 18 08:05:08 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e0836d95-d97b-4f8d-8150-62b50805e176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987279629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1987279629 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.2271909439 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 82232459516 ps |
| CPU time | 937.93 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:20:03 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-d41e43c1-4df6-45b6-ab0f-97cbd2d3fed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271909439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.2271909439 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.944556527 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 24610813148 ps |
| CPU time | 481.44 seconds |
| Started | Jul 18 08:04:31 PM PDT 24 |
| Finished | Jul 18 08:12:34 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-53d9738c-2eaf-45b9-ac46-06f8354a5ed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944556527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.944556527 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1817326552 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 289896051 ps |
| CPU time | 22.17 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:04:47 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-6930d663-b0ed-4bf1-b144-34e1adb3894d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817326552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1817326552 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.2265315775 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 255210347 ps |
| CPU time | 20.55 seconds |
| Started | Jul 18 08:04:26 PM PDT 24 |
| Finished | Jul 18 08:04:48 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-6c4e57b3-62a2-4ef5-a223-da0166256a71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265315775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.2265315775 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.881322693 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 252739157 ps |
| CPU time | 10.54 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:04:33 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-01998b41-8bec-4b7f-981e-45f297d92528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881322693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.881322693 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3364850037 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 10260702458 ps |
| CPU time | 123.92 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:06:27 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-40054030-c7e9-48f4-853b-e8d40250d8d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364850037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3364850037 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.269781334 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 5413339284 ps |
| CPU time | 95.3 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:06:02 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-1b507d85-1dcc-46a9-b1ce-04f8a172ec21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269781334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.269781334 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2400203433 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 51751336 ps |
| CPU time | 6.43 seconds |
| Started | Jul 18 08:04:22 PM PDT 24 |
| Finished | Jul 18 08:04:29 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-8154ce33-02be-4b70-bd22-30668aafbb52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400203433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2400203433 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.3454054232 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 19830549291 ps |
| CPU time | 853.66 seconds |
| Started | Jul 18 08:04:33 PM PDT 24 |
| Finished | Jul 18 08:18:48 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-cf7f8187-e1fc-43a1-bd66-a62403d2421b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454054232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.3454054232 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3133894327 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 8449440508 ps |
| CPU time | 325.63 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:09:52 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-2c82d986-0732-4c40-bea4-0dbaaafcad2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133894327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3133894327 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.868641294 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 8037218681 ps |
| CPU time | 551.88 seconds |
| Started | Jul 18 08:04:23 PM PDT 24 |
| Finished | Jul 18 08:13:36 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f5bb1cf7-d9bb-49a1-a677-2ecf182b5b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868641294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.868641294 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.715005482 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 14703601 ps |
| CPU time | 18.66 seconds |
| Started | Jul 18 08:04:23 PM PDT 24 |
| Finished | Jul 18 08:04:43 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-1e91664f-b076-4500-857d-dd557e958a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715005482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.715005482 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1459245043 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 182567027 ps |
| CPU time | 23.82 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:04:49 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-5dfd62a0-6df3-4139-81fa-19680dc6db2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459245043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1459245043 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3731870556 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 856149106 ps |
| CPU time | 60.45 seconds |
| Started | Jul 18 08:04:55 PM PDT 24 |
| Finished | Jul 18 08:05:56 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-321784b9-0bb3-43aa-8f81-8fcf586e02f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731870556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3731870556 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.3870864805 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 34999638836 ps |
| CPU time | 697.11 seconds |
| Started | Jul 18 08:04:44 PM PDT 24 |
| Finished | Jul 18 08:16:23 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-27bc5755-eeb4-4529-bb7a-dc043149e769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870864805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.3870864805 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1361682735 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 789046974 ps |
| CPU time | 35.13 seconds |
| Started | Jul 18 08:04:44 PM PDT 24 |
| Finished | Jul 18 08:05:20 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-ea774f1d-f588-436c-b8e7-c3f3fbf6d512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361682735 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.1361682735 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.903896226 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 482402942 ps |
| CPU time | 39.18 seconds |
| Started | Jul 18 08:04:48 PM PDT 24 |
| Finished | Jul 18 08:05:29 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a71cab6c-630b-48f5-b65f-c7456a2536b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903896226 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.903896226 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.3833426566 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 322991255 ps |
| CPU time | 26.13 seconds |
| Started | Jul 18 08:04:21 PM PDT 24 |
| Finished | Jul 18 08:04:48 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-7ec700d6-2e75-4178-b93a-69a12e13dba4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833426566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.3833426566 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2608508959 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 19688840143 ps |
| CPU time | 212 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:08:19 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-1af7f3f1-db25-49b9-9c79-ff6fe755de7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608508959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2608508959 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1549641074 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 49807252498 ps |
| CPU time | 970.74 seconds |
| Started | Jul 18 08:04:41 PM PDT 24 |
| Finished | Jul 18 08:20:53 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-4fcd65b5-6e5e-4366-9f2c-e5a402a17afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549641074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1549641074 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.229003715 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 283483545 ps |
| CPU time | 25.92 seconds |
| Started | Jul 18 08:04:24 PM PDT 24 |
| Finished | Jul 18 08:04:51 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-805965cf-38b6-469d-b926-859935bcaabd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229003715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.229003715 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1714022029 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 301286299 ps |
| CPU time | 11.56 seconds |
| Started | Jul 18 08:04:43 PM PDT 24 |
| Finished | Jul 18 08:04:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-5804aed6-58dc-4eec-9808-0a78331eff43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714022029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1714022029 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3205456278 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 250073339 ps |
| CPU time | 10.75 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:04:37 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-1d26e082-5bd4-47c9-ab01-4d55da5c10ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205456278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3205456278 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1986990898 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 8404944457 ps |
| CPU time | 94.55 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:06:01 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-11583569-37eb-4e0b-a032-9a5a9db7e4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986990898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.1986990898 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3913854851 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 4529535555 ps |
| CPU time | 77.69 seconds |
| Started | Jul 18 08:04:21 PM PDT 24 |
| Finished | Jul 18 08:05:40 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-9e377dad-0b14-48e4-84b5-188c888eebe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913854851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3913854851 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.717170943 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 41508401 ps |
| CPU time | 5.82 seconds |
| Started | Jul 18 08:04:25 PM PDT 24 |
| Finished | Jul 18 08:04:32 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-a94cc975-4884-4a57-86d3-b1de9a2e7282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717170943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delays .717170943 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1527758409 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 7554227825 ps |
| CPU time | 281.33 seconds |
| Started | Jul 18 08:04:42 PM PDT 24 |
| Finished | Jul 18 08:09:24 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-431b1a1b-bc4f-4603-b2fe-09d74ef8ebd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527758409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1527758409 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2714909888 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 425982903 ps |
| CPU time | 27.97 seconds |
| Started | Jul 18 08:04:42 PM PDT 24 |
| Finished | Jul 18 08:05:11 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-25f0bbb9-20ab-4462-9af1-95ffbaeaf248 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714909888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2714909888 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3610630349 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 5856487441 ps |
| CPU time | 802.72 seconds |
| Started | Jul 18 08:04:41 PM PDT 24 |
| Finished | Jul 18 08:18:05 PM PDT 24 |
| Peak memory | 577200 kb |
| Host | smart-d2f6ef3e-6366-43e2-b48f-1c15100ae3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610630349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3610630349 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.111041723 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 6309055935 ps |
| CPU time | 391.95 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:11:14 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-dc4b4e93-f88f-40ad-bd3e-857415585ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111041723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_reset_error.111041723 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.781646037 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 881767188 ps |
| CPU time | 34.01 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:05:16 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-e3176a54-7c16-4f3f-be7e-634adfb57c89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781646037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.781646037 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.3395162112 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 1585377432 ps |
| CPU time | 58.5 seconds |
| Started | Jul 18 08:04:46 PM PDT 24 |
| Finished | Jul 18 08:05:46 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a8b7115e-3697-43e1-88e9-342061500fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395162112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .3395162112 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.921779860 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 64122077663 ps |
| CPU time | 1187.9 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:24:35 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2e95d219-1ab1-4464-b042-d9e7bc258194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921779860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_d evice_slow_rsp.921779860 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3714978687 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 272219331 ps |
| CPU time | 30.94 seconds |
| Started | Jul 18 08:04:44 PM PDT 24 |
| Finished | Jul 18 08:05:16 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-d50430f2-5326-4862-80b6-cec7111d6fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714978687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3714978687 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.1937785504 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 2672775257 ps |
| CPU time | 96.67 seconds |
| Started | Jul 18 08:04:39 PM PDT 24 |
| Finished | Jul 18 08:06:17 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a064616d-8fdc-423d-8953-b3839a3db75d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937785504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1937785504 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1488749572 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 301586256 ps |
| CPU time | 30.04 seconds |
| Started | Jul 18 08:04:41 PM PDT 24 |
| Finished | Jul 18 08:05:13 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-1dc15f44-a7d8-44a6-b9f3-e956db5f117c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488749572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1488749572 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.2720056212 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 97083263637 ps |
| CPU time | 1119.48 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:23:26 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1940abca-ec43-4b19-8ab9-a5a85e9f9e02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720056212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.2720056212 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.659229164 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 51815780541 ps |
| CPU time | 935.6 seconds |
| Started | Jul 18 08:04:48 PM PDT 24 |
| Finished | Jul 18 08:20:25 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-29a9f0fa-d299-4759-9c3e-7e8334f768ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659229164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.659229164 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.2906261154 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 188605988 ps |
| CPU time | 17.82 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:04:59 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-95a0096d-b5ee-44b7-b998-d81035e8bc77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906261154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.2906261154 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.2183606102 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 717346223 ps |
| CPU time | 21.43 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:05:03 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-29a531bf-9d3d-4e4f-9da5-728cef470aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183606102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.2183606102 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.110463424 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 39040941 ps |
| CPU time | 5.96 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:04:47 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-711d2b0b-5bad-4a82-bed9-23f62afcacab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110463424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.110463424 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2991808029 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 8003273552 ps |
| CPU time | 90.23 seconds |
| Started | Jul 18 08:04:44 PM PDT 24 |
| Finished | Jul 18 08:06:16 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-78e0abc8-60c9-4fd7-b65e-7c7195b538d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991808029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2991808029 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.3051653798 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 5926576768 ps |
| CPU time | 106.1 seconds |
| Started | Jul 18 08:04:41 PM PDT 24 |
| Finished | Jul 18 08:06:28 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-9a448959-eb0c-4461-b8c0-ce391e841a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051653798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.3051653798 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3545359988 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 43020333 ps |
| CPU time | 6.08 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:04:53 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-7c80c377-d9c7-4396-ada5-7f8fd6d8c2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545359988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3545359988 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.4290832725 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 2592157310 ps |
| CPU time | 197.18 seconds |
| Started | Jul 18 08:04:44 PM PDT 24 |
| Finished | Jul 18 08:08:03 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-a8561d37-1b97-4dd5-a1bf-8246dfb2efc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290832725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.4290832725 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.47513440 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 5881316868 ps |
| CPU time | 204.42 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:08:11 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-be09e96b-f7f0-4e56-b4be-b16caab4363b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47513440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.47513440 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3998460039 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 149615219 ps |
| CPU time | 58.01 seconds |
| Started | Jul 18 08:04:45 PM PDT 24 |
| Finished | Jul 18 08:05:45 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-cedd76c0-c205-426c-b8da-913ec6bb2f3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998460039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3998460039 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.72243496 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 777025555 ps |
| CPU time | 217.12 seconds |
| Started | Jul 18 08:04:35 PM PDT 24 |
| Finished | Jul 18 08:08:13 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-53875871-0cc3-44b4-ba58-7f991e4514ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72243496 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_reset_error.72243496 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.1528666537 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 21402457 ps |
| CPU time | 5.36 seconds |
| Started | Jul 18 08:04:49 PM PDT 24 |
| Finished | Jul 18 08:04:56 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-863df311-f445-470e-b1a3-7e90714f81d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528666537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.1528666537 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.4008153449 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 703019437 ps |
| CPU time | 57.39 seconds |
| Started | Jul 18 08:05:03 PM PDT 24 |
| Finished | Jul 18 08:06:01 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a6d033fb-80eb-49b5-9d87-cf90aeeb44f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008153449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .4008153449 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.3902008775 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 129755770054 ps |
| CPU time | 2522.06 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:47:05 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-10f206d1-a2d2-4343-a19c-db2fdd7da8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902008775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.3902008775 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1007312230 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 106568496 ps |
| CPU time | 12.92 seconds |
| Started | Jul 18 08:05:04 PM PDT 24 |
| Finished | Jul 18 08:05:18 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-fc572b0e-c2cf-4530-ad5d-cbba3d716771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007312230 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1007312230 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.4062999501 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 1070259257 ps |
| CPU time | 38.58 seconds |
| Started | Jul 18 08:05:00 PM PDT 24 |
| Finished | Jul 18 08:05:39 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-670fd234-f1f3-4dbf-9a1e-19975a27f267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062999501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.4062999501 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.1134178625 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 603115088 ps |
| CPU time | 53.35 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:05:57 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-e0c6b1f0-248a-4b3c-b167-cad98690d442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134178625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.1134178625 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.2357643236 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 20848967192 ps |
| CPU time | 231.58 seconds |
| Started | Jul 18 08:04:58 PM PDT 24 |
| Finished | Jul 18 08:08:51 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-810583e9-6fff-4829-9a4f-0b11c8d21a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357643236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.2357643236 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2085705256 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 52544724219 ps |
| CPU time | 1009.96 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:21:54 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-63f988ab-7511-4965-9731-06e31771e929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085705256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2085705256 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1193553947 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 560685069 ps |
| CPU time | 46.71 seconds |
| Started | Jul 18 08:05:04 PM PDT 24 |
| Finished | Jul 18 08:05:52 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-15fb7852-3e45-49ed-bcd0-6794f6f915e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193553947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.1193553947 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.4051748194 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 2416355544 ps |
| CPU time | 72.2 seconds |
| Started | Jul 18 08:05:04 PM PDT 24 |
| Finished | Jul 18 08:06:17 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-be5c07e1-bb4b-4277-80aa-fe701e7ddab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051748194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.4051748194 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.32374625 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 186505880 ps |
| CPU time | 7.98 seconds |
| Started | Jul 18 08:04:40 PM PDT 24 |
| Finished | Jul 18 08:04:49 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-7ba69978-e2e9-4ec2-b1f1-cb3c7e285510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.32374625 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3135385603 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 5482294251 ps |
| CPU time | 62.52 seconds |
| Started | Jul 18 08:04:59 PM PDT 24 |
| Finished | Jul 18 08:06:02 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-fcd11a9e-d58e-4a94-b3e4-c24d5acbf2b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135385603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3135385603 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.923889985 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 2490046771 ps |
| CPU time | 43.81 seconds |
| Started | Jul 18 08:04:59 PM PDT 24 |
| Finished | Jul 18 08:05:44 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-9269ea47-da4e-4482-9c85-341cc5aadb12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923889985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.923889985 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.320808266 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 47734370 ps |
| CPU time | 6.39 seconds |
| Started | Jul 18 08:04:46 PM PDT 24 |
| Finished | Jul 18 08:04:54 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-029578b5-e94f-4c0f-8347-2b80a3c848ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320808266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays .320808266 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.2273465105 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 11331693852 ps |
| CPU time | 492.24 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:13:15 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-ab97884e-9b75-4063-9362-cbccf6c9c2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273465105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.2273465105 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.2209966 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 10015322285 ps |
| CPU time | 347.69 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:10:51 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-34fca439-9b00-4734-8abf-62a2c75c8512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.2209966 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3526632071 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 305239061 ps |
| CPU time | 165.5 seconds |
| Started | Jul 18 08:05:00 PM PDT 24 |
| Finished | Jul 18 08:07:46 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-fc0e82fc-52cc-4a21-b636-9fe6192cbdc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526632071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3526632071 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.1544346908 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 939298519 ps |
| CPU time | 165.6 seconds |
| Started | Jul 18 08:05:01 PM PDT 24 |
| Finished | Jul 18 08:07:48 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b672bc3b-9f0f-4296-8017-3a0748f7f769 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544346908 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.1544346908 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1210592713 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 257969304 ps |
| CPU time | 27.48 seconds |
| Started | Jul 18 08:04:57 PM PDT 24 |
| Finished | Jul 18 08:05:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-6a9a9937-255e-4ca8-a19b-6e2db375206d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210592713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1210592713 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.333591255 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 998347623 ps |
| CPU time | 72.71 seconds |
| Started | Jul 18 08:05:03 PM PDT 24 |
| Finished | Jul 18 08:06:17 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a34a34fe-1c56-488d-b5ff-8987888ef263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333591255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device. 333591255 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.2503713343 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 74273865349 ps |
| CPU time | 1345.19 seconds |
| Started | Jul 18 08:05:03 PM PDT 24 |
| Finished | Jul 18 08:27:29 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-1b91e8f9-f0f0-4042-a1aa-0df8baca6adb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503713343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.2503713343 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2635198126 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 304746008 ps |
| CPU time | 28.39 seconds |
| Started | Jul 18 08:05:19 PM PDT 24 |
| Finished | Jul 18 08:05:49 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-d18a0984-c229-40cf-bcdf-b8cd61d5fa23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635198126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.2635198126 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.2409462090 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 1249469147 ps |
| CPU time | 47.2 seconds |
| Started | Jul 18 08:05:03 PM PDT 24 |
| Finished | Jul 18 08:05:51 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-5661a2cf-bd14-4fad-854e-d95a37d77aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409462090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.2409462090 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.4048383589 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 388847395 ps |
| CPU time | 35.41 seconds |
| Started | Jul 18 08:05:04 PM PDT 24 |
| Finished | Jul 18 08:05:40 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-bdbae2e5-ce7a-483f-a50c-10a7749b0711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048383589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.4048383589 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1752159448 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 31851469788 ps |
| CPU time | 390.86 seconds |
| Started | Jul 18 08:05:01 PM PDT 24 |
| Finished | Jul 18 08:11:33 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b6fc88e1-c771-434e-86d9-16eae1703e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752159448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1752159448 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.47844275 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 55863941966 ps |
| CPU time | 1052.21 seconds |
| Started | Jul 18 08:04:57 PM PDT 24 |
| Finished | Jul 18 08:22:30 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-4ac0e952-7c67-43d6-82ec-723a8431455e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47844275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.47844275 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.3230289482 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 492450056 ps |
| CPU time | 45.05 seconds |
| Started | Jul 18 08:04:56 PM PDT 24 |
| Finished | Jul 18 08:05:43 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-17e58890-4acd-41f2-9112-ad926886acb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230289482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.3230289482 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.1082551875 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 584180375 ps |
| CPU time | 19.03 seconds |
| Started | Jul 18 08:05:03 PM PDT 24 |
| Finished | Jul 18 08:05:23 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c75f17cd-0b6d-4d30-b4ca-1cbcc84661b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082551875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1082551875 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3537940205 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 205412785 ps |
| CPU time | 8.69 seconds |
| Started | Jul 18 08:05:05 PM PDT 24 |
| Finished | Jul 18 08:05:14 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-84b54aee-ea41-470e-af3e-273b5211c61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537940205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3537940205 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3285880480 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 7352430920 ps |
| CPU time | 82.57 seconds |
| Started | Jul 18 08:04:59 PM PDT 24 |
| Finished | Jul 18 08:06:23 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-819aae7d-88f6-4c15-98a5-43de02c3fa8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285880480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3285880480 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2271969845 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 5594764324 ps |
| CPU time | 97.53 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:06:41 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f4eec603-d3b7-4aa3-8925-02ca38f58ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271969845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2271969845 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.1063370246 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 59859199 ps |
| CPU time | 6.91 seconds |
| Started | Jul 18 08:05:02 PM PDT 24 |
| Finished | Jul 18 08:05:10 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-471340e8-a2b1-4581-bd64-a9e081dcd99d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063370246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.1063370246 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.2495682193 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 2637926917 ps |
| CPU time | 97.29 seconds |
| Started | Jul 18 08:05:16 PM PDT 24 |
| Finished | Jul 18 08:06:55 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-56f9d3ab-a063-4c44-ba6b-b0a10d15ce2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495682193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.2495682193 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.4039771342 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 1609579333 ps |
| CPU time | 119.82 seconds |
| Started | Jul 18 08:05:18 PM PDT 24 |
| Finished | Jul 18 08:07:19 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-427c8dd8-adeb-4e7c-92c5-96f0ce416e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039771342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.4039771342 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1341640255 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 490754678 ps |
| CPU time | 97.27 seconds |
| Started | Jul 18 08:05:17 PM PDT 24 |
| Finished | Jul 18 08:06:55 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f4b96f29-b942-43c8-8ece-46c5e76610b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341640255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.1341640255 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3997117462 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 78760138 ps |
| CPU time | 12.13 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:05:28 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-559bb1c9-5f94-4336-88ee-d60025409a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997117462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3997117462 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.4287147962 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 72927404740 ps |
| CPU time | 1303.15 seconds |
| Started | Jul 18 08:08:34 PM PDT 24 |
| Finished | Jul 18 08:30:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-d93eac3e-3843-4d17-93b5-1cec18f59a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287147962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.4287147962 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.418639061 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 414350440 ps |
| CPU time | 21.27 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:05:38 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-bade6d1e-9356-4f7e-8caf-c98beab8f322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418639061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .418639061 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.2163100656 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 1784495813 ps |
| CPU time | 63.53 seconds |
| Started | Jul 18 08:05:21 PM PDT 24 |
| Finished | Jul 18 08:06:26 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-4ce68492-19bc-473f-b7dc-9081d11fb842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163100656 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.2163100656 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3680656449 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 1210575688 ps |
| CPU time | 44.3 seconds |
| Started | Jul 18 08:05:18 PM PDT 24 |
| Finished | Jul 18 08:06:03 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-ed680859-0978-4b0b-a2ff-336f74fc2611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680656449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3680656449 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.2502371104 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 52616958990 ps |
| CPU time | 621.76 seconds |
| Started | Jul 18 08:05:38 PM PDT 24 |
| Finished | Jul 18 08:16:00 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-32c9aa73-1964-4900-8132-f5404d8b24e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502371104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.2502371104 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.652885389 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 18247839979 ps |
| CPU time | 325.42 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:10:42 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-8b491fc3-286f-4ba7-a5b3-078d5d4c9ece |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652885389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.652885389 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2348259959 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 360246514 ps |
| CPU time | 34.98 seconds |
| Started | Jul 18 08:05:16 PM PDT 24 |
| Finished | Jul 18 08:05:52 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-7ca4b1c6-c496-4a92-b743-c2e055214c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348259959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2348259959 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.351176505 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 418253106 ps |
| CPU time | 15.07 seconds |
| Started | Jul 18 08:05:13 PM PDT 24 |
| Finished | Jul 18 08:05:29 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-5e90d125-e847-4429-955f-41edf6773641 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351176505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.351176505 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.3719878475 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 212505259 ps |
| CPU time | 9.32 seconds |
| Started | Jul 18 08:05:19 PM PDT 24 |
| Finished | Jul 18 08:05:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-1407bf26-9cfe-441c-a442-f8f4d7994b40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719878475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.3719878475 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2808221777 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 7478610081 ps |
| CPU time | 85.28 seconds |
| Started | Jul 18 08:05:18 PM PDT 24 |
| Finished | Jul 18 08:06:44 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-e8f02fc9-8eae-48de-9244-88d51906280d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808221777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2808221777 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.3509919938 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 6299786662 ps |
| CPU time | 114.93 seconds |
| Started | Jul 18 08:05:17 PM PDT 24 |
| Finished | Jul 18 08:07:14 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-2e2ff819-3175-4610-838d-dd86d55f321e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509919938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.3509919938 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2970321917 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 48872929 ps |
| CPU time | 6.63 seconds |
| Started | Jul 18 08:05:16 PM PDT 24 |
| Finished | Jul 18 08:05:24 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-03b1f705-2fa1-44f0-813e-e9cc075b8828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970321917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2970321917 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.3833190680 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 3644695046 ps |
| CPU time | 297.63 seconds |
| Started | Jul 18 08:05:20 PM PDT 24 |
| Finished | Jul 18 08:10:19 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-33c9afb4-8cdd-419e-8980-344a593d6e7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833190680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.3833190680 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.860496580 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 4601423401 ps |
| CPU time | 341.59 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:10:57 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a85386a9-cec6-427d-a21f-595750437296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860496580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.860496580 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1980584136 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 7401175250 ps |
| CPU time | 410.97 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:12:07 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8e34ac02-5f46-42a8-9463-3debdbbfa8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980584136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1980584136 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.767279862 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 7620713307 ps |
| CPU time | 500.51 seconds |
| Started | Jul 18 08:05:21 PM PDT 24 |
| Finished | Jul 18 08:13:43 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-a39e696b-c2da-4c29-8f44-0d686e6dc217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767279862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.767279862 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.4214848167 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 186336201 ps |
| CPU time | 20.23 seconds |
| Started | Jul 18 08:05:15 PM PDT 24 |
| Finished | Jul 18 08:05:35 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-cecb141f-dbb5-4aba-bb12-93b4e8927ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214848167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.4214848167 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2200297178 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4386832922 ps |
| CPU time | 329.54 seconds |
| Started | Jul 18 08:06:59 PM PDT 24 |
| Finished | Jul 18 08:12:30 PM PDT 24 |
| Peak memory | 608020 kb |
| Host | smart-7fb3e6a0-2303-4f8d-a547-8df3d1734a18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200297178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2200297178 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3737612167 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 13807646089 ps |
| CPU time | 1687.84 seconds |
| Started | Jul 18 08:06:56 PM PDT 24 |
| Finished | Jul 18 08:35:05 PM PDT 24 |
| Peak memory | 607956 kb |
| Host | smart-706b1162-db2b-4374-b623-140a90164156 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737612167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 737612167 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2134983919 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3480533772 ps |
| CPU time | 288.53 seconds |
| Started | Jul 18 08:14:18 PM PDT 24 |
| Finished | Jul 18 08:19:07 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-b1719596-76bd-4568-af7c-8b52e4f7d95a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2134983919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2134983919 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1831365192 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2722534324 ps |
| CPU time | 226.24 seconds |
| Started | Jul 18 08:12:59 PM PDT 24 |
| Finished | Jul 18 08:16:47 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-bf7b68da-3d46-49a4-89fc-11a739a4072e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831365192 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1831365192 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1518582950 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3050834629 ps |
| CPU time | 327.57 seconds |
| Started | Jul 18 08:16:06 PM PDT 24 |
| Finished | Jul 18 08:21:35 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-f9749e74-96f1-42e0-869d-1290b1fe7c2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518 582950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.1518582950 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3681734621 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3066534668 ps |
| CPU time | 229.46 seconds |
| Started | Jul 18 08:18:20 PM PDT 24 |
| Finished | Jul 18 08:22:11 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-3cc24089-c3ea-4b90-9995-8e1d4bea4d86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681734621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3681734621 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.2650997987 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 2814951752 ps |
| CPU time | 226.92 seconds |
| Started | Jul 18 08:14:22 PM PDT 24 |
| Finished | Jul 18 08:18:11 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-1a713fcb-e587-4ddb-84bd-4996935ad89a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650997987 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.2650997987 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.2138000011 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 2085878472 ps |
| CPU time | 311.45 seconds |
| Started | Jul 18 08:14:09 PM PDT 24 |
| Finished | Jul 18 08:19:22 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-0645647c-3348-42f7-a075-e25ffbba3e77 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138000011 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2138000011 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2172161048 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3258819086 ps |
| CPU time | 308.49 seconds |
| Started | Jul 18 08:14:16 PM PDT 24 |
| Finished | Jul 18 08:19:25 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-6f3962dc-c2bf-4ff4-bb4d-fc586437e64e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172161048 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2172161048 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.265206113 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2609682750 ps |
| CPU time | 307.28 seconds |
| Started | Jul 18 08:19:22 PM PDT 24 |
| Finished | Jul 18 08:24:30 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-6f83927a-25b9-46b4-bf28-66938a154ea6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265206113 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.265206113 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.527131059 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 3418903435 ps |
| CPU time | 382.77 seconds |
| Started | Jul 18 08:17:21 PM PDT 24 |
| Finished | Jul 18 08:23:45 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-cf2d10b5-89c0-401c-97ae-a05fb90bc81f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=527131059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.527131059 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3711035667 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 5545448888 ps |
| CPU time | 582.11 seconds |
| Started | Jul 18 08:14:06 PM PDT 24 |
| Finished | Jul 18 08:23:50 PM PDT 24 |
| Peak memory | 619412 kb |
| Host | smart-e8669531-ac77-4f79-8163-a3ce8db538c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3711035667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.3711035667 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2646974091 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 7695218352 ps |
| CPU time | 1710.31 seconds |
| Started | Jul 18 08:15:53 PM PDT 24 |
| Finished | Jul 18 08:44:24 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-e48da638-e494-4992-9561-0bdec984e00f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2646974091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.2646974091 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1899358639 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 7929188040 ps |
| CPU time | 1701.68 seconds |
| Started | Jul 18 08:15:40 PM PDT 24 |
| Finished | Jul 18 08:44:02 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-22c41cb0-eb36-4590-ae20-e23e2d0b6f20 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899358639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.1899358639 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.654764376 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 9694648060 ps |
| CPU time | 1056.73 seconds |
| Started | Jul 18 08:14:57 PM PDT 24 |
| Finished | Jul 18 08:32:35 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-b4613ee7-ca9a-4b9a-8d3c-e0592e9d2d11 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654764376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.654764376 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2927449724 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 8478691048 ps |
| CPU time | 986.92 seconds |
| Started | Jul 18 08:12:56 PM PDT 24 |
| Finished | Jul 18 08:29:24 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-11579440-f8d4-4a99-9465-1374293ca9d7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2927449724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2927449724 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1431295212 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 4244221032 ps |
| CPU time | 496.36 seconds |
| Started | Jul 18 08:16:24 PM PDT 24 |
| Finished | Jul 18 08:24:41 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-4fb20a99-8f69-4791-99f3-258df8eabaf8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1431295212 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1431295212 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4093852055 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 255306127658 ps |
| CPU time | 12578.2 seconds |
| Started | Jul 18 08:16:33 PM PDT 24 |
| Finished | Jul 18 11:46:14 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-67c3fcfb-0d77-461d-b303-1d75ca0f8178 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093852055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4093852055 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.2369950629 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2700439996 ps |
| CPU time | 401.12 seconds |
| Started | Jul 18 08:16:36 PM PDT 24 |
| Finished | Jul 18 08:23:19 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-943fdf26-c6e9-46da-8556-f85a938f60fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369950629 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2369950629 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.2725955235 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3993584994 ps |
| CPU time | 400.23 seconds |
| Started | Jul 18 08:14:45 PM PDT 24 |
| Finished | Jul 18 08:21:27 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-6995e75d-3129-487f-86de-4f1832f30dcf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725955235 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2725955235 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.680111158 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 6359991870 ps |
| CPU time | 533.9 seconds |
| Started | Jul 18 08:14:55 PM PDT 24 |
| Finished | Jul 18 08:23:50 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-5970ec62-1e88-43e9-bef5-bdce5ece09cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=680111158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.680111158 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3422634097 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 2497680956 ps |
| CPU time | 273.62 seconds |
| Started | Jul 18 08:21:27 PM PDT 24 |
| Finished | Jul 18 08:26:02 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-0bf59a54-9f50-45cc-b4c3-2a8c6d38db84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422634097 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3422634097 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.556537442 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 9715527704 ps |
| CPU time | 950.95 seconds |
| Started | Jul 18 08:14:24 PM PDT 24 |
| Finished | Jul 18 08:30:16 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-9ec13897-0b9d-42d6-82da-9da48d9ab2d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 556537442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.556537442 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3594436224 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4773779712 ps |
| CPU time | 599.65 seconds |
| Started | Jul 18 08:16:21 PM PDT 24 |
| Finished | Jul 18 08:26:23 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-c9e0a566-85ba-48d6-920f-1a0e4a290b13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3594436224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3594436224 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.1679487276 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 7737278544 ps |
| CPU time | 877.9 seconds |
| Started | Jul 18 08:16:50 PM PDT 24 |
| Finished | Jul 18 08:31:30 PM PDT 24 |
| Peak memory | 617092 kb |
| Host | smart-4bd9adff-8044-4e8b-808b-3e122dbaa08f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679487276 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.1679487276 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2846045839 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 5752565111 ps |
| CPU time | 404.89 seconds |
| Started | Jul 18 08:15:01 PM PDT 24 |
| Finished | Jul 18 08:21:47 PM PDT 24 |
| Peak memory | 622376 kb |
| Host | smart-c9d3ab05-764e-4eee-9b64-6529107f9bb4 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2846045839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2846045839 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1697569544 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 4486061200 ps |
| CPU time | 605.64 seconds |
| Started | Jul 18 08:14:44 PM PDT 24 |
| Finished | Jul 18 08:24:51 PM PDT 24 |
| Peak memory | 611928 kb |
| Host | smart-b7ff38ed-88ec-41ad-9c31-7d049ade5ee5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697569544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1697569544 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3713435294 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3872764688 ps |
| CPU time | 757.23 seconds |
| Started | Jul 18 08:16:45 PM PDT 24 |
| Finished | Jul 18 08:29:24 PM PDT 24 |
| Peak memory | 612712 kb |
| Host | smart-8310c049-fe15-4354-91f2-d078ae7d1d72 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713435294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3713435294 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3012285568 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3918997914 ps |
| CPU time | 669.33 seconds |
| Started | Jul 18 08:16:17 PM PDT 24 |
| Finished | Jul 18 08:27:28 PM PDT 24 |
| Peak memory | 612896 kb |
| Host | smart-2f8e36f1-8a9b-45a4-ad5d-66e918629ea1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012285568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3012285568 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.787062829 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 4742186498 ps |
| CPU time | 712.6 seconds |
| Started | Jul 18 08:17:01 PM PDT 24 |
| Finished | Jul 18 08:28:55 PM PDT 24 |
| Peak memory | 612784 kb |
| Host | smart-ecf937e0-176d-4af7-a60a-daf8c0aae12d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787062829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.787062829 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4248035838 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 4903024104 ps |
| CPU time | 614.61 seconds |
| Started | Jul 18 08:15:47 PM PDT 24 |
| Finished | Jul 18 08:26:02 PM PDT 24 |
| Peak memory | 612892 kb |
| Host | smart-f10caae3-5544-4fae-8630-5d4df6fbcb90 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248035838 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4248035838 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.504938068 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 4419460538 ps |
| CPU time | 433.45 seconds |
| Started | Jul 18 08:16:10 PM PDT 24 |
| Finished | Jul 18 08:23:24 PM PDT 24 |
| Peak memory | 612940 kb |
| Host | smart-3ed718b2-07d9-4032-96a7-f1e43acc5cfa |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504938068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.504938068 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.219089507 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2681351985 ps |
| CPU time | 228.34 seconds |
| Started | Jul 18 08:16:17 PM PDT 24 |
| Finished | Jul 18 08:20:05 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-6f710ec8-405e-436b-a5bd-aaa8c42a5eb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219089507 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter.219089507 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.352633574 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 3945542316 ps |
| CPU time | 468.66 seconds |
| Started | Jul 18 08:16:28 PM PDT 24 |
| Finished | Jul 18 08:24:18 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-b2560710-404a-4bd9-bea9-de4521c71f5b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352633574 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.352633574 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2233580653 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 3314658610 ps |
| CPU time | 214.6 seconds |
| Started | Jul 18 08:14:52 PM PDT 24 |
| Finished | Jul 18 08:18:28 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-dbbff356-047d-462b-a9c7-4415a2a2d5f4 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233580653 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2233580653 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2971191847 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 4818204702 ps |
| CPU time | 597.25 seconds |
| Started | Jul 18 08:15:38 PM PDT 24 |
| Finished | Jul 18 08:25:36 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-87a3e6be-0402-4459-bd12-df0c45899f7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971191847 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.2971191847 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2230810054 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 5340393788 ps |
| CPU time | 669.23 seconds |
| Started | Jul 18 08:16:34 PM PDT 24 |
| Finished | Jul 18 08:27:45 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-3f6ad3da-dc1f-4e66-8aea-7f2c686b17d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230810054 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2230810054 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.865713610 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 3961104544 ps |
| CPU time | 532.09 seconds |
| Started | Jul 18 08:17:24 PM PDT 24 |
| Finished | Jul 18 08:26:17 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-fdf8d475-4bd8-4c40-a4ba-9b45de6544ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865713610 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.865713610 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1922019373 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 3823689728 ps |
| CPU time | 435.1 seconds |
| Started | Jul 18 08:17:13 PM PDT 24 |
| Finished | Jul 18 08:24:29 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-e2ec538f-9767-4e4d-9505-3d95c0229f4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922019373 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1922019373 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2143610948 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 10324829566 ps |
| CPU time | 1424.55 seconds |
| Started | Jul 18 08:16:01 PM PDT 24 |
| Finished | Jul 18 08:39:46 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-b0eccf05-792f-41a7-9785-2122351f9fd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143610948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2143610948 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.147890892 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 3075682280 ps |
| CPU time | 412.68 seconds |
| Started | Jul 18 08:13:53 PM PDT 24 |
| Finished | Jul 18 08:20:47 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-a2ac7c22-83cf-47fd-9692-14e6826bdc67 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147890892 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.147890892 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3519492753 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 4890820930 ps |
| CPU time | 803 seconds |
| Started | Jul 18 08:17:06 PM PDT 24 |
| Finished | Jul 18 08:30:30 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-f57cdf6f-4a44-4309-84ac-7fea34f6c6a9 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519492753 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.3519492753 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2438423067 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3122536440 ps |
| CPU time | 236.51 seconds |
| Started | Jul 18 08:18:21 PM PDT 24 |
| Finished | Jul 18 08:22:20 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-fd203818-6452-4310-96da-d7f7aef422a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438423067 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2438423067 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1809509380 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 71280804104 ps |
| CPU time | 14621.2 seconds |
| Started | Jul 18 08:14:38 PM PDT 24 |
| Finished | Jul 19 12:18:22 AM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-fa3848da-f082-47f2-8f57-a21229e75908 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1809509380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1809509380 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3939522927 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 19114969800 ps |
| CPU time | 4166.65 seconds |
| Started | Jul 18 08:25:41 PM PDT 24 |
| Finished | Jul 18 09:35:09 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-7dab6370-819b-4813-bce7-a06f2c4fa8d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939522927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.3939522927 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4019989864 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 30128902351 ps |
| CPU time | 5148.9 seconds |
| Started | Jul 18 08:18:30 PM PDT 24 |
| Finished | Jul 18 09:44:21 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-d571b439-ab79-43ab-9d63-5fdac5041963 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4019989864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.4019989864 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2798679266 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2971090088 ps |
| CPU time | 324.2 seconds |
| Started | Jul 18 08:15:11 PM PDT 24 |
| Finished | Jul 18 08:20:37 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-22a8f364-b196-4d4b-b164-9b608fbe07e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798679266 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2798679266 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3551680418 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 6351851363 ps |
| CPU time | 651.59 seconds |
| Started | Jul 18 08:15:38 PM PDT 24 |
| Finished | Jul 18 08:26:30 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-d390e332-4e1f-4bdc-95bc-43b57f522848 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551680418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.3551680418 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.3139355216 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 2433158906 ps |
| CPU time | 283.54 seconds |
| Started | Jul 18 08:16:29 PM PDT 24 |
| Finished | Jul 18 08:21:13 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-9cdf5c65-7859-44fd-bf6b-ef5dd0a6ad10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139355216 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3139355216 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.2262121180 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 5879034760 ps |
| CPU time | 1599.99 seconds |
| Started | Jul 18 08:13:37 PM PDT 24 |
| Finished | Jul 18 08:40:18 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-35289485-e3f7-4a20-bb15-3a5e04ad9e7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262121180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.2262121180 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2586255901 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 6618606760 ps |
| CPU time | 1140.03 seconds |
| Started | Jul 18 08:13:55 PM PDT 24 |
| Finished | Jul 18 08:32:56 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-ca30047f-3fb2-4c49-b8b8-490e02ddb1b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586255901 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2586255901 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.3471349826 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 3631642968 ps |
| CPU time | 586.45 seconds |
| Started | Jul 18 08:23:41 PM PDT 24 |
| Finished | Jul 18 08:33:30 PM PDT 24 |
| Peak memory | 614260 kb |
| Host | smart-7ac94d10-f437-4bdb-b33f-7c5507f0ac86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471349826 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3471349826 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2660621728 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3090918622 ps |
| CPU time | 261.84 seconds |
| Started | Jul 18 08:15:44 PM PDT 24 |
| Finished | Jul 18 08:20:06 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-dc48e01d-e225-4f93-8e39-66d75219b6f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26 60621728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2660621728 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2798694937 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 3614567848 ps |
| CPU time | 284.39 seconds |
| Started | Jul 18 08:14:34 PM PDT 24 |
| Finished | Jul 18 08:19:19 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-83b24a7c-862b-481c-8d62-e34cbc8e9e11 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798694937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2798694937 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1675389950 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 3056290100 ps |
| CPU time | 415.84 seconds |
| Started | Jul 18 08:25:44 PM PDT 24 |
| Finished | Jul 18 08:32:42 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-93545e75-fa96-4149-bc67-799f70e65171 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1675389950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.1675389950 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.98329703 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2807292872 ps |
| CPU time | 170.66 seconds |
| Started | Jul 18 08:14:10 PM PDT 24 |
| Finished | Jul 18 08:17:02 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-2acb7277-edcc-4991-8217-510a44f57b6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98329703 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_concurrency.98329703 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.544964609 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2513878860 ps |
| CPU time | 182.21 seconds |
| Started | Jul 18 08:12:58 PM PDT 24 |
| Finished | Jul 18 08:16:01 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-104f91c3-79c9-4e3b-9379-8be5c319a54d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544964609 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.544964609 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.3555142197 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 3502649602 ps |
| CPU time | 287.89 seconds |
| Started | Jul 18 08:13:26 PM PDT 24 |
| Finished | Jul 18 08:18:17 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-f7d37294-8877-4ad7-8cc5-50b52e24eb15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555142197 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.3555142197 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.3680684290 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2467486660 ps |
| CPU time | 117.85 seconds |
| Started | Jul 18 08:12:37 PM PDT 24 |
| Finished | Jul 18 08:14:37 PM PDT 24 |
| Peak memory | 609056 kb |
| Host | smart-ba67dd81-5221-4ace-9c1c-56b99d6f81c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680684290 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.3680684290 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2068045808 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 59464398552 ps |
| CPU time | 10941.8 seconds |
| Started | Jul 18 08:14:31 PM PDT 24 |
| Finished | Jul 18 11:16:54 PM PDT 24 |
| Peak memory | 623784 kb |
| Host | smart-3e11842f-f3c8-4a26-af62-e91f334fb20f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2068045808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2068045808 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.3102725374 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5357857848 ps |
| CPU time | 576.44 seconds |
| Started | Jul 18 08:14:51 PM PDT 24 |
| Finished | Jul 18 08:24:29 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-f82ba88e-69f8-46ac-96d3-c7dc0c4baa8f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3102725374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3102725374 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1850012747 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 5739980364 ps |
| CPU time | 1073.57 seconds |
| Started | Jul 18 08:13:55 PM PDT 24 |
| Finished | Jul 18 08:31:50 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-17a637e1-0c12-4041-8873-7bd138b99516 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850012747 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1850012747 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.979629730 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 6126061809 ps |
| CPU time | 1143.11 seconds |
| Started | Jul 18 08:14:21 PM PDT 24 |
| Finished | Jul 18 08:33:26 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-8020028a-bd40-4f24-acb3-b8faf8e26bab |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979629730 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.979629730 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2317046636 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6826404796 ps |
| CPU time | 1191.18 seconds |
| Started | Jul 18 08:18:22 PM PDT 24 |
| Finished | Jul 18 08:38:15 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-67e08ab3-5624-4650-8fe4-cdbaa932c445 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317046636 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2317046636 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3364916456 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 5933579882 ps |
| CPU time | 1226.29 seconds |
| Started | Jul 18 08:13:05 PM PDT 24 |
| Finished | Jul 18 08:33:32 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-7f644342-9475-4791-b96b-4f3d10e37e28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364916456 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.3364916456 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2664932119 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3946906350 ps |
| CPU time | 468.45 seconds |
| Started | Jul 18 08:13:58 PM PDT 24 |
| Finished | Jul 18 08:21:48 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-ae3f1ac5-4515-4d05-9459-23941aeb157e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664932119 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2664932119 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1140058428 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5356593952 ps |
| CPU time | 589.18 seconds |
| Started | Jul 18 08:13:18 PM PDT 24 |
| Finished | Jul 18 08:23:09 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-07a10a92-0020-4821-a501-2fb3b02e0543 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 40058428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1140058428 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.261041757 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 5805847870 ps |
| CPU time | 1115.55 seconds |
| Started | Jul 18 08:17:20 PM PDT 24 |
| Finished | Jul 18 08:35:56 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-6a1c3da7-99ec-46bd-931d-d7a119527f2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261041757 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.261041757 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2018134335 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3763662245 ps |
| CPU time | 731.42 seconds |
| Started | Jul 18 08:13:22 PM PDT 24 |
| Finished | Jul 18 08:25:34 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-18a7960e-13c7-468e-9e44-fa44dff23986 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2018134335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2018134335 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1423368811 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 4699652489 ps |
| CPU time | 654.13 seconds |
| Started | Jul 18 08:18:47 PM PDT 24 |
| Finished | Jul 18 08:29:43 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-979fc6fe-3c4d-41b6-aa5c-5fa53c0b0a8a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1423368811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1423368811 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2471944799 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 3443101420 ps |
| CPU time | 380.81 seconds |
| Started | Jul 18 08:17:36 PM PDT 24 |
| Finished | Jul 18 08:23:57 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-e6930c78-3fd7-4935-bc76-b909374c6236 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471944 799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2471944799 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2844854782 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 18090163384 ps |
| CPU time | 1672.74 seconds |
| Started | Jul 18 08:12:43 PM PDT 24 |
| Finished | Jul 18 08:40:37 PM PDT 24 |
| Peak memory | 613520 kb |
| Host | smart-1ac8c86d-3bf9-45b3-88ed-621761b7f628 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844854782 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2844854782 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1258553522 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 26683228645 ps |
| CPU time | 2457.58 seconds |
| Started | Jul 18 08:19:38 PM PDT 24 |
| Finished | Jul 18 09:00:39 PM PDT 24 |
| Peak memory | 613420 kb |
| Host | smart-88cbb678-9eca-4117-b3e0-a5533e4edf2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1258553522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.1258553522 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.860191895 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 2351787060 ps |
| CPU time | 243.75 seconds |
| Started | Jul 18 08:22:47 PM PDT 24 |
| Finished | Jul 18 08:26:52 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-c13aa34b-eb26-41fb-9444-5303de591c1a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=860191895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.860191895 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1046279580 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 3061871749 ps |
| CPU time | 276.72 seconds |
| Started | Jul 18 08:17:15 PM PDT 24 |
| Finished | Jul 18 08:21:52 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-606bd03c-75ea-42be-b002-08699b917541 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046279580 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.1046279580 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.808876993 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 3217349904 ps |
| CPU time | 299.61 seconds |
| Started | Jul 18 08:15:51 PM PDT 24 |
| Finished | Jul 18 08:20:52 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-60038935-c32b-4d09-bb74-4774ef29c14b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808876993 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.808876993 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.665731175 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3554400527 ps |
| CPU time | 271.21 seconds |
| Started | Jul 18 08:17:29 PM PDT 24 |
| Finished | Jul 18 08:22:00 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-24911a80-9836-4b08-9f7b-7672e7dde127 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665731175 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.665731175 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.3376411342 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 7804309336 ps |
| CPU time | 1486.55 seconds |
| Started | Jul 18 08:25:08 PM PDT 24 |
| Finished | Jul 18 08:49:57 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-e7464336-d26a-46e9-b7f5-04771dc9f744 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376411342 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.3376411342 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.3392490426 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 3648927640 ps |
| CPU time | 392.5 seconds |
| Started | Jul 18 08:14:55 PM PDT 24 |
| Finished | Jul 18 08:21:29 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-2821fb63-e24b-465a-9016-05f29fc5863c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392490426 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3392490426 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1119814691 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3060152200 ps |
| CPU time | 328.77 seconds |
| Started | Jul 18 08:17:18 PM PDT 24 |
| Finished | Jul 18 08:22:48 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-ec4f1296-27d7-4470-a608-1393aba498b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119814691 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1119814691 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3315913698 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 3599224212 ps |
| CPU time | 576.18 seconds |
| Started | Jul 18 08:14:24 PM PDT 24 |
| Finished | Jul 18 08:24:02 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-2ae16dc2-aa31-4807-bea5-1f4d9caf3f3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315913698 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.3315913698 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1074175276 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 64994632067 ps |
| CPU time | 12249 seconds |
| Started | Jul 18 08:13:30 PM PDT 24 |
| Finished | Jul 18 11:37:41 PM PDT 24 |
| Peak memory | 624776 kb |
| Host | smart-7b408521-4587-40a1-962e-9b27b24fdaa1 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1074175276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.1074175276 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3150147804 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 7609701391 ps |
| CPU time | 1696.78 seconds |
| Started | Jul 18 08:15:52 PM PDT 24 |
| Finished | Jul 18 08:44:09 PM PDT 24 |
| Peak memory | 617652 kb |
| Host | smart-989f5402-ddf4-4990-8b18-3869cd00ffe0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150 147804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.3150147804 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.208297281 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 9328877461 ps |
| CPU time | 1726.37 seconds |
| Started | Jul 18 08:16:09 PM PDT 24 |
| Finished | Jul 18 08:44:57 PM PDT 24 |
| Peak memory | 617724 kb |
| Host | smart-8b42df98-3523-466c-86a3-bb4839ef07ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=208297281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.208297281 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2736898379 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 10545503115 ps |
| CPU time | 1695.97 seconds |
| Started | Jul 18 08:14:44 PM PDT 24 |
| Finished | Jul 18 08:43:01 PM PDT 24 |
| Peak memory | 617708 kb |
| Host | smart-4b453b70-48f7-4828-8b39-9e0eb22569e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2736898379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2736898379 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.63902442 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7995844880 ps |
| CPU time | 1178.59 seconds |
| Started | Jul 18 08:13:39 PM PDT 24 |
| Finished | Jul 18 08:33:18 PM PDT 24 |
| Peak memory | 617652 kb |
| Host | smart-ed956596-1a44-4996-9927-f5d8e56fc303 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=63902442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.63902442 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3628868938 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 11452822976 ps |
| CPU time | 2885.29 seconds |
| Started | Jul 18 08:16:18 PM PDT 24 |
| Finished | Jul 18 09:04:24 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-c1033b77-cd70-4d25-9a3c-0709e51bab73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288 68938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3628868938 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2627229498 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3031454170 ps |
| CPU time | 261.94 seconds |
| Started | Jul 18 08:25:04 PM PDT 24 |
| Finished | Jul 18 08:29:27 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-e64e7366-18ad-4de2-bf2d-d32183eb0ff4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627229498 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2627229498 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.954784967 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 3243531862 ps |
| CPU time | 301.88 seconds |
| Started | Jul 18 08:13:28 PM PDT 24 |
| Finished | Jul 18 08:18:31 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-de69665c-599e-46aa-9cc6-dc4c51b86d35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954784967 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.954784967 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2539878076 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2327746360 ps |
| CPU time | 260.45 seconds |
| Started | Jul 18 08:14:41 PM PDT 24 |
| Finished | Jul 18 08:19:03 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-b901f0cf-a583-470b-bb3d-9e8490d935f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539878076 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2539878076 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3962331066 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3458881300 ps |
| CPU time | 238.66 seconds |
| Started | Jul 18 08:14:08 PM PDT 24 |
| Finished | Jul 18 08:18:08 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-53f3c110-633a-48fa-81ac-f5e4ca24ce03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962331066 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3962331066 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3201140370 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 2853518792 ps |
| CPU time | 231.31 seconds |
| Started | Jul 18 08:23:43 PM PDT 24 |
| Finished | Jul 18 08:27:37 PM PDT 24 |
| Peak memory | 609184 kb |
| Host | smart-85791220-7993-470e-b41f-bf630ee2509e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201140370 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.3201140370 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1254951464 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3122621251 ps |
| CPU time | 309.24 seconds |
| Started | Jul 18 08:23:52 PM PDT 24 |
| Finished | Jul 18 08:29:03 PM PDT 24 |
| Peak memory | 608976 kb |
| Host | smart-6d0097b8-8826-4ae2-a425-f07fdb7373d0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254951464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1254951464 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1365389153 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 2919680095 ps |
| CPU time | 280.48 seconds |
| Started | Jul 18 08:22:09 PM PDT 24 |
| Finished | Jul 18 08:26:52 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-020d5d99-e4e7-4e4e-9aac-b2d76bca84eb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13653891 53 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1365389153 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.1894258935 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 3156357930 ps |
| CPU time | 276.8 seconds |
| Started | Jul 18 08:18:39 PM PDT 24 |
| Finished | Jul 18 08:23:17 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-ecd9ee7e-0f81-49ae-8c95-8a01cd22a472 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894258935 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1894258935 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2759145879 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 2424576896 ps |
| CPU time | 301.93 seconds |
| Started | Jul 18 08:14:37 PM PDT 24 |
| Finished | Jul 18 08:19:40 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-3e7e7f1d-07bf-4540-b9fc-3a2ed5ac989d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759145879 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.2759145879 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2025115241 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 3166486595 ps |
| CPU time | 156.5 seconds |
| Started | Jul 18 08:13:57 PM PDT 24 |
| Finished | Jul 18 08:16:34 PM PDT 24 |
| Peak memory | 620496 kb |
| Host | smart-a22d2290-85ce-4c45-8b70-e75439e948eb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025115241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.2025115241 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1841616950 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 3800154176 ps |
| CPU time | 161.76 seconds |
| Started | Jul 18 08:16:11 PM PDT 24 |
| Finished | Jul 18 08:18:54 PM PDT 24 |
| Peak memory | 620656 kb |
| Host | smart-9a654ebf-69c1-4bdf-900b-0ad5074a1557 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841616950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1841616950 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2310304119 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3212947466 ps |
| CPU time | 132.07 seconds |
| Started | Jul 18 08:15:09 PM PDT 24 |
| Finished | Jul 18 08:17:22 PM PDT 24 |
| Peak memory | 620052 kb |
| Host | smart-f341d75e-862a-4d6e-ac5f-f213083dd14c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310304119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.2310304119 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4004614984 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 8806805028 ps |
| CPU time | 1117.78 seconds |
| Started | Jul 18 08:13:54 PM PDT 24 |
| Finished | Jul 18 08:32:33 PM PDT 24 |
| Peak memory | 624776 kb |
| Host | smart-f00242c1-db1d-444d-8440-fcc5e2400112 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004614984 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.4004614984 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2136297932 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2557567404 ps |
| CPU time | 128.22 seconds |
| Started | Jul 18 08:15:09 PM PDT 24 |
| Finished | Jul 18 08:17:18 PM PDT 24 |
| Peak memory | 617596 kb |
| Host | smart-28ffb0cc-34e1-42f2-8c38-b7eada12c620 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2136297932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2136297932 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3212463471 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 1993270698 ps |
| CPU time | 97.91 seconds |
| Started | Jul 18 08:13:46 PM PDT 24 |
| Finished | Jul 18 08:15:26 PM PDT 24 |
| Peak memory | 616972 kb |
| Host | smart-e49ab25c-5e37-4f57-bba8-e4e77eff1b67 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212463471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3212463471 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1294623344 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 48057529509 ps |
| CPU time | 6089.86 seconds |
| Started | Jul 18 08:14:15 PM PDT 24 |
| Finished | Jul 18 09:55:47 PM PDT 24 |
| Peak memory | 620284 kb |
| Host | smart-fd059b27-348b-402f-b3ec-b1d2945e3c26 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294623344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.1294623344 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3881843447 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 11504327528 ps |
| CPU time | 1120.57 seconds |
| Started | Jul 18 08:13:34 PM PDT 24 |
| Finished | Jul 18 08:32:17 PM PDT 24 |
| Peak memory | 619092 kb |
| Host | smart-6e8ad600-82dc-41ef-b045-1d084bf43566 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881843447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3881843447 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.520862341 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 49329072904 ps |
| CPU time | 6080.78 seconds |
| Started | Jul 18 08:12:41 PM PDT 24 |
| Finished | Jul 18 09:54:03 PM PDT 24 |
| Peak memory | 620272 kb |
| Host | smart-4a62495a-5b1b-4655-99f8-e477f071fb21 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520862341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_rma.520862341 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3105130780 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 32582374536 ps |
| CPU time | 2145.41 seconds |
| Started | Jul 18 08:13:29 PM PDT 24 |
| Finished | Jul 18 08:49:15 PM PDT 24 |
| Peak memory | 621484 kb |
| Host | smart-6fafe5ad-d9ac-4ca3-ba9c-a0e56203c75d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3105130780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3105130780 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3121818205 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 16965440480 ps |
| CPU time | 3530.42 seconds |
| Started | Jul 18 08:14:19 PM PDT 24 |
| Finished | Jul 18 09:13:11 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-bd6a55db-89d4-4bca-9047-11e5c87c98ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3121818205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3121818205 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2101574751 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 19103968808 ps |
| CPU time | 3919.34 seconds |
| Started | Jul 18 08:16:17 PM PDT 24 |
| Finished | Jul 18 09:21:38 PM PDT 24 |
| Peak memory | 610332 kb |
| Host | smart-b023cbc7-c60c-434d-81ec-09ab1fe35627 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2101574751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2101574751 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2708534389 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 24751879890 ps |
| CPU time | 4119.6 seconds |
| Started | Jul 18 08:16:35 PM PDT 24 |
| Finished | Jul 18 09:25:16 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-b2ad13d2-94f0-43ae-881c-1cc50cda3b09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708534389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2708534389 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1593216788 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3088658524 ps |
| CPU time | 627.79 seconds |
| Started | Jul 18 08:14:26 PM PDT 24 |
| Finished | Jul 18 08:24:55 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-aedb780a-c3d7-432b-b9cf-5609a202185a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593216788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1593216788 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2111668138 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 6130500080 ps |
| CPU time | 891.84 seconds |
| Started | Jul 18 08:14:07 PM PDT 24 |
| Finished | Jul 18 08:29:00 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-446d9598-eff2-4a7e-b2d9-fe4ecaaf6d35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2111668138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2111668138 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2567966253 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 6104288960 ps |
| CPU time | 953.61 seconds |
| Started | Jul 18 08:19:47 PM PDT 24 |
| Finished | Jul 18 08:35:41 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-388a5038-f70a-41bb-93cf-73c5d56397ec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567966253 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2567966253 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1127417814 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 27912313802 ps |
| CPU time | 5393.22 seconds |
| Started | Jul 18 08:13:19 PM PDT 24 |
| Finished | Jul 18 09:43:14 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-2aed1501-91bd-488b-b961-e29cc3c58872 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112741 7814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1127417814 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1246853829 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2589095693 ps |
| CPU time | 271.94 seconds |
| Started | Jul 18 08:12:29 PM PDT 24 |
| Finished | Jul 18 08:17:02 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-5c3751e1-9626-45fb-a143-9a1429aa6679 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246853829 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1246853829 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2059227967 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 6989081632 ps |
| CPU time | 1100.05 seconds |
| Started | Jul 18 08:15:46 PM PDT 24 |
| Finished | Jul 18 08:34:07 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-f8db8141-968a-4f03-86c1-05c036674820 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2059227967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2059227967 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3663217505 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 7296085046 ps |
| CPU time | 1279.9 seconds |
| Started | Jul 18 08:14:00 PM PDT 24 |
| Finished | Jul 18 08:35:21 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-e7392426-ccef-4a64-9ecc-a8cc424fda06 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3663217505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3663217505 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2101994757 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 7756738750 ps |
| CPU time | 1112.32 seconds |
| Started | Jul 18 08:13:49 PM PDT 24 |
| Finished | Jul 18 08:32:23 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-f62c24f7-8bcc-4d16-9450-70defff8f9bd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2101994757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2101994757 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2092695540 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 4187485282 ps |
| CPU time | 762.53 seconds |
| Started | Jul 18 08:14:01 PM PDT 24 |
| Finished | Jul 18 08:26:45 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-4c6aff46-0d75-41dc-9a08-032e9f65e0b4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2092695540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2092695540 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3691859018 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3230304924 ps |
| CPU time | 217.34 seconds |
| Started | Jul 18 08:18:07 PM PDT 24 |
| Finished | Jul 18 08:21:45 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-8edc15b4-5393-4ee8-8144-28bec00adb55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691859018 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.3691859018 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.3814092238 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2991886008 ps |
| CPU time | 245.17 seconds |
| Started | Jul 18 08:12:38 PM PDT 24 |
| Finished | Jul 18 08:16:45 PM PDT 24 |
| Peak memory | 610508 kb |
| Host | smart-03aceaaf-5aba-4653-a973-1e601b86bb47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814092238 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3814092238 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.2495780153 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 4695410290 ps |
| CPU time | 883.85 seconds |
| Started | Jul 18 08:23:20 PM PDT 24 |
| Finished | Jul 18 08:38:05 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-4d27a23e-42e9-43b5-a331-6e1c7a239de8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495780153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2495780153 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.764622723 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 8276186930 ps |
| CPU time | 1550.35 seconds |
| Started | Jul 18 08:15:21 PM PDT 24 |
| Finished | Jul 18 08:41:12 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-9a739291-ab93-4794-b670-feb679e29f5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7646 22723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.764622723 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3945710099 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 27970637892 ps |
| CPU time | 3187.44 seconds |
| Started | Jul 18 08:16:33 PM PDT 24 |
| Finished | Jul 18 09:09:41 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-7aede5da-3928-4208-a187-b6e46aaab68a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394 5710099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3945710099 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3934034118 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 15577861839 ps |
| CPU time | 1063.19 seconds |
| Started | Jul 18 08:14:25 PM PDT 24 |
| Finished | Jul 18 08:32:09 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-094419d1-5a61-4535-9d4b-e16c293e9782 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3934034118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3934034118 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3330398826 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 8597212030 ps |
| CPU time | 699.79 seconds |
| Started | Jul 18 08:13:48 PM PDT 24 |
| Finished | Jul 18 08:25:29 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-f5c80292-7a45-433d-81b6-02478be379c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330398826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.3330398826 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1900879406 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 7367982710 ps |
| CPU time | 567.43 seconds |
| Started | Jul 18 08:14:15 PM PDT 24 |
| Finished | Jul 18 08:23:44 PM PDT 24 |
| Peak memory | 616148 kb |
| Host | smart-4b954ce8-ffa5-496d-b4e1-39db1c562e0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1900879406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1900879406 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4108702104 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4991285794 ps |
| CPU time | 594.56 seconds |
| Started | Jul 18 08:15:09 PM PDT 24 |
| Finished | Jul 18 08:25:04 PM PDT 24 |
| Peak memory | 616120 kb |
| Host | smart-288c9a4e-4329-4412-990a-5a49681cd83c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=4108702104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.4108702104 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3963739409 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 9443733302 ps |
| CPU time | 1427.34 seconds |
| Started | Jul 18 08:15:11 PM PDT 24 |
| Finished | Jul 18 08:39:00 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-292b30d0-7088-4db5-b618-12f2e8d2ca61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963739409 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3963739409 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.199015061 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7858419628 ps |
| CPU time | 387.31 seconds |
| Started | Jul 18 08:16:33 PM PDT 24 |
| Finished | Jul 18 08:23:00 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-ac0bccc0-c4ff-4c15-9400-3d02820d9467 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199015061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.199015061 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2905559446 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 7407773012 ps |
| CPU time | 859.46 seconds |
| Started | Jul 18 08:15:05 PM PDT 24 |
| Finished | Jul 18 08:29:25 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-3a4620ce-a895-43b6-bfda-f19970eef1a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905559446 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2905559446 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3457271248 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 27977819523 ps |
| CPU time | 2741.12 seconds |
| Started | Jul 18 08:13:58 PM PDT 24 |
| Finished | Jul 18 08:59:41 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-03e9b745-a6e0-432e-80ca-74e90a359d2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3457271248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3457271248 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.330064892 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2653604004 ps |
| CPU time | 255.22 seconds |
| Started | Jul 18 08:14:33 PM PDT 24 |
| Finished | Jul 18 08:18:50 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-9ea7b6b6-fe58-4af3-9765-3c9cd152360b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330064892 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.330064892 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3611443879 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 5028663525 ps |
| CPU time | 319.45 seconds |
| Started | Jul 18 08:14:16 PM PDT 24 |
| Finished | Jul 18 08:19:37 PM PDT 24 |
| Peak memory | 616304 kb |
| Host | smart-22362533-630c-4d0b-9fc1-d2258e52e17b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3611443879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3611443879 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.988676425 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 5618380242 ps |
| CPU time | 398.17 seconds |
| Started | Jul 18 08:19:12 PM PDT 24 |
| Finished | Jul 18 08:25:52 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-2371f818-c4fb-48d5-99cc-1fc92939f2cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=988676425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.988676425 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.339433777 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 4807677672 ps |
| CPU time | 387.36 seconds |
| Started | Jul 18 08:19:04 PM PDT 24 |
| Finished | Jul 18 08:25:33 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-243e0db7-caba-4cb6-a263-62094ca87ff6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339433777 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.339433777 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.168709830 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 5433536960 ps |
| CPU time | 539.89 seconds |
| Started | Jul 18 08:15:00 PM PDT 24 |
| Finished | Jul 18 08:24:01 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-3c1efc11-86dd-46d0-bd7e-25299c6018bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168709830 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.168709830 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1858999992 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5121303128 ps |
| CPU time | 336.64 seconds |
| Started | Jul 18 08:26:16 PM PDT 24 |
| Finished | Jul 18 08:31:55 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-758af2d1-61b0-4041-afa5-309ef89e23f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858999992 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.1858999992 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3420197873 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4459323260 ps |
| CPU time | 624.94 seconds |
| Started | Jul 18 08:14:52 PM PDT 24 |
| Finished | Jul 18 08:25:18 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-2c0cae18-826b-4c11-a057-a6cd45a77bb2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342 0197873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3420197873 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.408932057 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 9331567052 ps |
| CPU time | 460.82 seconds |
| Started | Jul 18 08:25:37 PM PDT 24 |
| Finished | Jul 18 08:33:18 PM PDT 24 |
| Peak memory | 623396 kb |
| Host | smart-1a13839a-fe36-4bf8-9070-f7a854332bf1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408932057 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.408932057 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3605218534 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 6723041832 ps |
| CPU time | 806.76 seconds |
| Started | Jul 18 08:13:58 PM PDT 24 |
| Finished | Jul 18 08:27:26 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-4860ddbb-626a-4587-8702-ec51240b7ee7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605218534 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3605218534 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2385607107 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 4857446986 ps |
| CPU time | 719.77 seconds |
| Started | Jul 18 08:12:05 PM PDT 24 |
| Finished | Jul 18 08:24:05 PM PDT 24 |
| Peak memory | 641576 kb |
| Host | smart-2551ca76-eee6-4920-8c60-246cf74f1c61 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2385607107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2385607107 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2377380183 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2881208988 ps |
| CPU time | 276.43 seconds |
| Started | Jul 18 08:17:07 PM PDT 24 |
| Finished | Jul 18 08:21:45 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-60882018-68de-4e51-a11a-f96be9b0ad71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377380183 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2377380183 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2894848895 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3240716564 ps |
| CPU time | 309.53 seconds |
| Started | Jul 18 08:14:18 PM PDT 24 |
| Finished | Jul 18 08:19:28 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-2a4499c3-4e47-45b3-b425-33c0a4b161b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894848895 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2894848895 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.948998197 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3363065744 ps |
| CPU time | 196.39 seconds |
| Started | Jul 18 08:12:15 PM PDT 24 |
| Finished | Jul 18 08:15:33 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-d008c721-2993-4110-9275-67030a5ff2f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948998197 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.948998197 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2469532005 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3365041590 ps |
| CPU time | 293.29 seconds |
| Started | Jul 18 08:15:41 PM PDT 24 |
| Finished | Jul 18 08:20:35 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-40aa43ff-5092-4877-b39b-4f6ad23901f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2469532005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.2469532005 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1154995889 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3206361524 ps |
| CPU time | 199.85 seconds |
| Started | Jul 18 08:16:34 PM PDT 24 |
| Finished | Jul 18 08:19:55 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-63c12fd7-9d32-4557-83d8-a87cb8c6c863 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154995889 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1154995889 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1585307225 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 5950714924 ps |
| CPU time | 1035.77 seconds |
| Started | Jul 18 08:15:39 PM PDT 24 |
| Finished | Jul 18 08:32:56 PM PDT 24 |
| Peak memory | 610028 kb |
| Host | smart-92703a04-470e-4f60-81c2-48557c9278cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1585307225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1585307225 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2270622357 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 7278545920 ps |
| CPU time | 651.66 seconds |
| Started | Jul 18 08:18:08 PM PDT 24 |
| Finished | Jul 18 08:29:01 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-79542029-6386-4203-9301-33b33fd5fc48 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270622357 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2270622357 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.782778094 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3452555022 ps |
| CPU time | 242.24 seconds |
| Started | Jul 18 08:26:41 PM PDT 24 |
| Finished | Jul 18 08:30:45 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-dc24f3a5-1fe3-4eaf-8350-9f8a04d89eac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782778094 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rv_plic_smoketest.782778094 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.4063422314 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 3499200660 ps |
| CPU time | 351.72 seconds |
| Started | Jul 18 08:15:58 PM PDT 24 |
| Finished | Jul 18 08:21:51 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-ebafa5bc-1926-4d9e-8693-89a177e2d95b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063422314 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.4063422314 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.773751776 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 3335355984 ps |
| CPU time | 285.49 seconds |
| Started | Jul 18 08:26:10 PM PDT 24 |
| Finished | Jul 18 08:30:57 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-f322e2c7-a61d-4576-a6e6-842f7b1ea902 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773751776 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_smoketest.773751776 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3902717068 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 5133564176 ps |
| CPU time | 557.57 seconds |
| Started | Jul 18 08:17:01 PM PDT 24 |
| Finished | Jul 18 08:26:20 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-be29c59c-31b0-453c-bfd2-7214760d275c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39027170 68 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.3902717068 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4115033047 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 2809516984 ps |
| CPU time | 247.4 seconds |
| Started | Jul 18 08:15:50 PM PDT 24 |
| Finished | Jul 18 08:19:58 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-2b6ce50f-41f5-440e-9b9a-e8dc3670b7b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115033 047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.4115033047 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.625138683 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3232090002 ps |
| CPU time | 363.22 seconds |
| Started | Jul 18 08:15:10 PM PDT 24 |
| Finished | Jul 18 08:21:15 PM PDT 24 |
| Peak memory | 609156 kb |
| Host | smart-8dc5df19-b291-4eb3-b57f-9ef4b7981fda |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625138683 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.625138683 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3752213777 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 10002959062 ps |
| CPU time | 1722.23 seconds |
| Started | Jul 18 08:13:26 PM PDT 24 |
| Finished | Jul 18 08:42:10 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-27f84e6c-94da-46ae-9a18-99722fd898f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752213777 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3752213777 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3847115982 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 8269870220 ps |
| CPU time | 599.13 seconds |
| Started | Jul 18 08:15:18 PM PDT 24 |
| Finished | Jul 18 08:25:19 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-3b284ce3-e2d8-46b6-b024-dae63721bc32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847115982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.3847115982 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1856277526 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 7240436266 ps |
| CPU time | 633.17 seconds |
| Started | Jul 18 08:15:47 PM PDT 24 |
| Finished | Jul 18 08:26:20 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-c0267308-6c7c-486d-937b-8efdc0430dd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856277526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1856277526 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1447448053 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 6826224642 ps |
| CPU time | 746.67 seconds |
| Started | Jul 18 08:13:09 PM PDT 24 |
| Finished | Jul 18 08:25:37 PM PDT 24 |
| Peak memory | 624816 kb |
| Host | smart-5f8c2992-f261-438a-b0c9-208ffdf5c015 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447448053 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1447448053 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2967832015 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 5142256037 ps |
| CPU time | 565.3 seconds |
| Started | Jul 18 08:14:48 PM PDT 24 |
| Finished | Jul 18 08:24:15 PM PDT 24 |
| Peak memory | 624896 kb |
| Host | smart-46d4b177-7ad9-406e-b477-95d27165ddc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967832015 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.2967832015 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2997795873 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3821136799 ps |
| CPU time | 369.81 seconds |
| Started | Jul 18 08:12:28 PM PDT 24 |
| Finished | Jul 18 08:18:39 PM PDT 24 |
| Peak memory | 619480 kb |
| Host | smart-28395bfd-a99f-4d5c-91ec-718ec382f036 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997795873 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2997795873 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2806219109 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 3921793993 ps |
| CPU time | 518.45 seconds |
| Started | Jul 18 08:14:10 PM PDT 24 |
| Finished | Jul 18 08:22:50 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-9f8c1278-df33-406e-9bd1-cda85f90da88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806219109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2806219109 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1344087720 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 5029027542 ps |
| CPU time | 544.13 seconds |
| Started | Jul 18 08:17:28 PM PDT 24 |
| Finished | Jul 18 08:26:33 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-3dbd4615-87aa-4e52-95e8-d93d95925b62 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344087720 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1344087720 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2717619640 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 2842768600 ps |
| CPU time | 201.64 seconds |
| Started | Jul 18 08:18:56 PM PDT 24 |
| Finished | Jul 18 08:22:19 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-269587d1-dc10-4974-8b74-323de608cbe4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717619640 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.2717619640 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3019222886 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 20518664356 ps |
| CPU time | 4108.21 seconds |
| Started | Jul 18 08:14:31 PM PDT 24 |
| Finished | Jul 18 09:23:01 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-b316721d-1629-4277-97a8-4968ef83c427 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019222886 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3019222886 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2303200509 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3454711656 ps |
| CPU time | 376.51 seconds |
| Started | Jul 18 08:15:32 PM PDT 24 |
| Finished | Jul 18 08:21:51 PM PDT 24 |
| Peak memory | 613220 kb |
| Host | smart-8bf46a40-9b07-46f8-9088-015f9b74cd87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303200509 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2303200509 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3858016388 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3981240592 ps |
| CPU time | 451.78 seconds |
| Started | Jul 18 08:14:31 PM PDT 24 |
| Finished | Jul 18 08:22:04 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-c05ff243-0ade-4d38-bec0-bc8cb665bef1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858016388 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3858016388 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2005904121 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 21550632596 ps |
| CPU time | 1829.73 seconds |
| Started | Jul 18 08:14:16 PM PDT 24 |
| Finished | Jul 18 08:44:47 PM PDT 24 |
| Peak memory | 614656 kb |
| Host | smart-f2cd0c8f-3f53-491d-adac-9dd4929f4e6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059041 21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2005904121 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2284261238 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 5882753962 ps |
| CPU time | 514.17 seconds |
| Started | Jul 18 08:17:04 PM PDT 24 |
| Finished | Jul 18 08:25:40 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-467944d8-fc39-4975-9433-b524014fa850 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284261238 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2284261238 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2263651280 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 9480765662 ps |
| CPU time | 1607.59 seconds |
| Started | Jul 18 08:12:45 PM PDT 24 |
| Finished | Jul 18 08:39:34 PM PDT 24 |
| Peak memory | 618768 kb |
| Host | smart-9811a3ca-3619-44bc-84f8-966558f8032b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2263651280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2263651280 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.4211743896 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 2869578208 ps |
| CPU time | 277.5 seconds |
| Started | Jul 18 08:16:58 PM PDT 24 |
| Finished | Jul 18 08:21:37 PM PDT 24 |
| Peak memory | 616156 kb |
| Host | smart-dfac4cd9-dbbe-4056-8d61-d3ae15f0c1a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211743896 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.4211743896 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1880675439 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 8837931895 ps |
| CPU time | 1463.66 seconds |
| Started | Jul 18 08:14:08 PM PDT 24 |
| Finished | Jul 18 08:38:34 PM PDT 24 |
| Peak memory | 624724 kb |
| Host | smart-43d495e8-9063-4224-8df6-2929430443f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880675439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1880675439 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3342834000 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5013077820 ps |
| CPU time | 459.57 seconds |
| Started | Jul 18 08:13:01 PM PDT 24 |
| Finished | Jul 18 08:20:41 PM PDT 24 |
| Peak memory | 624724 kb |
| Host | smart-eaf5f74f-45a3-440e-bec9-1c087e732d0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342834000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3342834000 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2043302316 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 79474317450 ps |
| CPU time | 13247.1 seconds |
| Started | Jul 18 08:13:50 PM PDT 24 |
| Finished | Jul 18 11:54:40 PM PDT 24 |
| Peak memory | 634096 kb |
| Host | smart-abb82e49-3587-409d-822e-e3e96af1e4a6 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2043302316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2043302316 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3458113071 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 4095776040 ps |
| CPU time | 591.2 seconds |
| Started | Jul 18 08:12:59 PM PDT 24 |
| Finished | Jul 18 08:22:51 PM PDT 24 |
| Peak memory | 622520 kb |
| Host | smart-933931f1-b70f-46c0-b9ee-a59c87011590 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458113071 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3458113071 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2685878351 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 4100940476 ps |
| CPU time | 654.99 seconds |
| Started | Jul 18 08:13:02 PM PDT 24 |
| Finished | Jul 18 08:23:58 PM PDT 24 |
| Peak memory | 623776 kb |
| Host | smart-6525102c-2b37-4f23-a0cf-7ce345140ea9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685878351 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2685878351 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3873814572 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3105884818 ps |
| CPU time | 343.46 seconds |
| Started | Jul 18 08:17:21 PM PDT 24 |
| Finished | Jul 18 08:23:05 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-c29e94dd-6325-43fe-a72c-a264e4ba3b1e |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873814572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3873814572 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2674169595 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 11953259150 ps |
| CPU time | 2670.67 seconds |
| Started | Jul 18 08:13:15 PM PDT 24 |
| Finished | Jul 18 08:57:47 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-9a873305-b52b-4d7d-87fb-787e65bf4793 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2674169595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2674169595 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2440083114 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 31871990782 ps |
| CPU time | 7273.24 seconds |
| Started | Jul 18 08:12:57 PM PDT 24 |
| Finished | Jul 18 10:14:12 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-caa20edc-ed6e-49d8-8346-2a11144a9f25 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2440083114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.2440083114 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.185147822 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 3499071504 ps |
| CPU time | 388.66 seconds |
| Started | Jul 18 08:13:53 PM PDT 24 |
| Finished | Jul 18 08:20:24 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-a2b822d3-39a9-43b4-833d-2999ccf9d4bf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185147822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.185147822 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2959120265 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 4167011644 ps |
| CPU time | 667.53 seconds |
| Started | Jul 18 08:13:57 PM PDT 24 |
| Finished | Jul 18 08:25:06 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-2fe2377e-11a8-4fa0-8b30-fe1db22749bf |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295912026 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.2959120265 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3736020094 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 18741560224 ps |
| CPU time | 4320.11 seconds |
| Started | Jul 18 08:12:14 PM PDT 24 |
| Finished | Jul 18 09:24:16 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-97d943ff-7bf6-4d8a-8db8-559fb9271308 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3736020094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3736020094 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.1275540896 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3007875528 ps |
| CPU time | 232.63 seconds |
| Started | Jul 18 08:14:36 PM PDT 24 |
| Finished | Jul 18 08:18:30 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-a0232e1c-4f46-48e6-ada9-915b8416ac8c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275540896 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.1275540896 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3654477489 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 2672713379 ps |
| CPU time | 196.69 seconds |
| Started | Jul 18 08:17:46 PM PDT 24 |
| Finished | Jul 18 08:21:04 PM PDT 24 |
| Peak memory | 621268 kb |
| Host | smart-e8d0b200-eb8f-4138-a5a0-12a5d0f434be |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3654477489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3654477489 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2870520586 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 2872470355 ps |
| CPU time | 177.99 seconds |
| Started | Jul 18 08:14:05 PM PDT 24 |
| Finished | Jul 18 08:17:04 PM PDT 24 |
| Peak memory | 620948 kb |
| Host | smart-04a01275-3dd0-49a3-a92f-2e2a00e106b1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870520586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2870520586 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.4226702772 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 4966396751 ps |
| CPU time | 446.82 seconds |
| Started | Jul 18 08:16:07 PM PDT 24 |
| Finished | Jul 18 08:23:35 PM PDT 24 |
| Peak memory | 620932 kb |
| Host | smart-80476295-958a-403a-8bf4-80b707103724 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226702772 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.4226702772 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.2300255400 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15856258100 ps |
| CPU time | 4088.96 seconds |
| Started | Jul 18 08:26:33 PM PDT 24 |
| Finished | Jul 18 09:34:43 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-e63029b8-e4a8-4d98-8a54-0c4c21931586 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300255400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.2300255400 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.3143405 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 15624712124 ps |
| CPU time | 4225.6 seconds |
| Started | Jul 18 08:19:05 PM PDT 24 |
| Finished | Jul 18 09:29:32 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-d4ee7990-923c-4afc-8247-7a94effc1c70 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. rom_e2e_asm_init_prod.3143405 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.66495768 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 15125806571 ps |
| CPU time | 4024.21 seconds |
| Started | Jul 18 08:19:04 PM PDT 24 |
| Finished | Jul 18 09:26:09 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-ee0f2b99-4f8e-469a-af2a-8bacf23bae3c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66495768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. rom_e2e_asm_init_rma.66495768 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2408825969 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 11315710708 ps |
| CPU time | 3140.71 seconds |
| Started | Jul 18 08:23:22 PM PDT 24 |
| Finished | Jul 18 09:15:44 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-ee94cc6d-3c9c-46df-95f0-2fed4528966d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408825969 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2408825969 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1393304873 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 24185499560 ps |
| CPU time | 5390.55 seconds |
| Started | Jul 18 08:20:07 PM PDT 24 |
| Finished | Jul 18 09:49:59 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-44fa91a4-769f-443e-b424-96e78fc4d8bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1393304873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1393304873 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4175417420 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 24867732674 ps |
| CPU time | 6435.56 seconds |
| Started | Jul 18 08:24:03 PM PDT 24 |
| Finished | Jul 18 10:11:21 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-72a88222-21e1-4b3b-9866-3b81a6b00694 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4175417420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4175417420 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1034851545 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 23519707240 ps |
| CPU time | 7510.16 seconds |
| Started | Jul 18 08:24:28 PM PDT 24 |
| Finished | Jul 18 10:29:41 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-a1b3bb77-fee1-46bd-8157-92d97f7cb455 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1034851545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1034851545 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3206351957 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 18613004492 ps |
| CPU time | 4501.38 seconds |
| Started | Jul 18 08:20:32 PM PDT 24 |
| Finished | Jul 18 09:35:35 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-3032a58e-30b6-4186-9362-fb5983cd2db9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206351957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3206351957 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.833603661 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 15520505446 ps |
| CPU time | 3612.27 seconds |
| Started | Jul 18 08:23:26 PM PDT 24 |
| Finished | Jul 18 09:23:40 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-0ad6750b-b4fd-4f00-935d-0da3bcb6ae7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=833603661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.833603661 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.178496872 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 15442533576 ps |
| CPU time | 3489.59 seconds |
| Started | Jul 18 08:22:57 PM PDT 24 |
| Finished | Jul 18 09:21:08 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-5bf70783-3ed3-45fa-9883-edfe615711b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=178496872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.178496872 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4139038045 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 15019798420 ps |
| CPU time | 4083.71 seconds |
| Started | Jul 18 08:20:44 PM PDT 24 |
| Finished | Jul 18 09:28:48 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-f125189c-74ea-4b63-9140-b03c07ea1d32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4139038045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4139038045 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.742430605 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 14610004700 ps |
| CPU time | 3867.54 seconds |
| Started | Jul 18 08:22:06 PM PDT 24 |
| Finished | Jul 18 09:26:34 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-606741fb-5aa7-4b14-bcbe-2bb6565b972e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=742430605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.742430605 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3532603215 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 11267972100 ps |
| CPU time | 2952.33 seconds |
| Started | Jul 18 08:22:08 PM PDT 24 |
| Finished | Jul 18 09:11:22 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-fcabbe85-7703-43f4-b05e-2c29402099ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532603215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3532603215 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.679056896 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 15487224228 ps |
| CPU time | 3979.54 seconds |
| Started | Jul 18 08:18:53 PM PDT 24 |
| Finished | Jul 18 09:25:14 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-0132205d-c4c7-4ab2-988f-f7edecc6cf42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679056896 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.679056896 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.858896294 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 15938614720 ps |
| CPU time | 3699.86 seconds |
| Started | Jul 18 08:21:21 PM PDT 24 |
| Finished | Jul 18 09:23:02 PM PDT 24 |
| Peak memory | 609896 kb |
| Host | smart-d885895a-06f4-4bfa-b9f4-6715335e2a20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858896294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.858896294 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1103135038 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 15018265530 ps |
| CPU time | 5063.14 seconds |
| Started | Jul 18 08:23:54 PM PDT 24 |
| Finished | Jul 18 09:48:19 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-ab95ee4f-1eb0-4215-ad03-13f280cdf76d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110313 5038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1103135038 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935857902 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 14694482904 ps |
| CPU time | 3736.26 seconds |
| Started | Jul 18 08:22:33 PM PDT 24 |
| Finished | Jul 18 09:24:51 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-cf960858-f8ed-4120-8afd-8c660f656879 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935857902 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935857902 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1292555167 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 11930242808 ps |
| CPU time | 3368.52 seconds |
| Started | Jul 18 08:28:45 PM PDT 24 |
| Finished | Jul 18 09:24:55 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-5f4d793e-93be-4eac-9e3d-69421905a499 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1292555167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1292555167 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1803211299 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 11997590666 ps |
| CPU time | 2340.69 seconds |
| Started | Jul 18 08:18:28 PM PDT 24 |
| Finished | Jul 18 08:57:31 PM PDT 24 |
| Peak memory | 624172 kb |
| Host | smart-46921d1b-efaf-40b8-bc1a-8bf4fd30815a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18032 11299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.1803211299 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2861157871 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 11031747080 ps |
| CPU time | 2482.73 seconds |
| Started | Jul 18 08:16:43 PM PDT 24 |
| Finished | Jul 18 08:58:07 PM PDT 24 |
| Peak memory | 624196 kb |
| Host | smart-1a8ccd8f-4fd2-4179-b3b3-a787524cd54b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611 57871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.2861157871 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2778125354 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 10727882510 ps |
| CPU time | 1919.48 seconds |
| Started | Jul 18 08:19:07 PM PDT 24 |
| Finished | Jul 18 08:51:09 PM PDT 24 |
| Peak memory | 624200 kb |
| Host | smart-e64778f4-7a5d-467e-8385-7716823a174c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2778125354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2778125354 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1527322937 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 25043213094 ps |
| CPU time | 3438.15 seconds |
| Started | Jul 18 08:22:23 PM PDT 24 |
| Finished | Jul 18 09:19:44 PM PDT 24 |
| Peak memory | 620256 kb |
| Host | smart-9f581191-f314-4673-880c-8b39fa21d0dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1527322937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1527322937 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.727051997 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 34757172268 ps |
| CPU time | 2931 seconds |
| Started | Jul 18 08:18:12 PM PDT 24 |
| Finished | Jul 18 09:07:04 PM PDT 24 |
| Peak memory | 622408 kb |
| Host | smart-39d7b356-c507-4f86-becb-54373bdf5e92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=727051997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.727051997 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2136393030 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 24514060302 ps |
| CPU time | 1577.57 seconds |
| Started | Jul 18 08:16:27 PM PDT 24 |
| Finished | Jul 18 08:42:45 PM PDT 24 |
| Peak memory | 620568 kb |
| Host | smart-58675edf-63f5-49b5-a903-e0ea2998c758 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136393030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.2136393030 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.114896835 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 15360707116 ps |
| CPU time | 3984.56 seconds |
| Started | Jul 18 08:28:42 PM PDT 24 |
| Finished | Jul 18 09:35:08 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-3b233642-02e6-44d7-b38e-9bfa848b9332 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114896835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.114896835 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.315751355 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15433027702 ps |
| CPU time | 4092.32 seconds |
| Started | Jul 18 08:21:26 PM PDT 24 |
| Finished | Jul 18 09:29:40 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-9bd994db-d365-4af7-a485-4ed1ccd8ca5a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315751355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.315751355 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3238748239 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 15219009352 ps |
| CPU time | 3733.54 seconds |
| Started | Jul 18 08:21:02 PM PDT 24 |
| Finished | Jul 18 09:23:16 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-5a016940-1cc4-43eb-bb66-c0c82626f88f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238748239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3238748239 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.3970324451 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 26075515144 ps |
| CPU time | 5934.3 seconds |
| Started | Jul 18 08:28:24 PM PDT 24 |
| Finished | Jul 18 10:07:20 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-b7e82565-ba85-4f0b-840f-86f39f99b988 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970324451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.3970324451 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2851010960 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 14896486804 ps |
| CPU time | 3489.35 seconds |
| Started | Jul 18 08:18:16 PM PDT 24 |
| Finished | Jul 18 09:16:26 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-fd290e17-db6e-4b44-9dd7-eae6b49ea6d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851010960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2851010960 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.3686813639 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 27460246009 ps |
| CPU time | 3395.79 seconds |
| Started | Jul 18 08:27:20 PM PDT 24 |
| Finished | Jul 18 09:23:58 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-c2dabc34-21ad-40c1-971f-4d1f81835945 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686813639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3686813639 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2925554940 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 23568002165 ps |
| CPU time | 7011.73 seconds |
| Started | Jul 18 08:24:51 PM PDT 24 |
| Finished | Jul 18 10:21:46 PM PDT 24 |
| Peak memory | 611136 kb |
| Host | smart-cc5edc81-f15f-44b5-a87c-b0e608c77ad3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2925554940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.2925554940 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3936523745 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 22950833428 ps |
| CPU time | 5653.14 seconds |
| Started | Jul 18 08:23:42 PM PDT 24 |
| Finished | Jul 18 09:57:56 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-95714969-04e2-4918-97dc-b383dd0155c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3936523745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3936523745 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.796891143 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 23799465313 ps |
| CPU time | 6256.94 seconds |
| Started | Jul 18 08:23:06 PM PDT 24 |
| Finished | Jul 18 10:07:24 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-c12ff860-2dd8-4e2e-a57f-73561ddeeb90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=796891143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.796891143 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.647506405 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 23064277750 ps |
| CPU time | 5892 seconds |
| Started | Jul 18 08:24:26 PM PDT 24 |
| Finished | Jul 18 10:02:39 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-e377a387-be94-47c0-ad77-accc503cc341 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=647506405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_ bad_rma.647506405 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2611992783 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 17206815453 ps |
| CPU time | 4481.94 seconds |
| Started | Jul 18 08:22:47 PM PDT 24 |
| Finished | Jul 18 09:37:31 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-b91e7aac-4402-457c-bcb5-ebcebdf3a73e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2611992783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2611992783 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2823500061 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 14346559100 ps |
| CPU time | 4160.89 seconds |
| Started | Jul 18 08:20:12 PM PDT 24 |
| Finished | Jul 18 09:29:35 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-ff5f4da6-afc7-4913-a346-c5609d6f9970 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823500061 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2823500061 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3026239988 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 14770958752 ps |
| CPU time | 3416.11 seconds |
| Started | Jul 18 08:26:08 PM PDT 24 |
| Finished | Jul 18 09:23:06 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-3a6bf5e3-0d6d-4e96-b7b9-7848ffc799b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026239988 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3026239988 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2071006619 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 14635148392 ps |
| CPU time | 4884.83 seconds |
| Started | Jul 18 08:23:15 PM PDT 24 |
| Finished | Jul 18 09:44:41 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-580008b4-2d73-46a0-af4f-323682074012 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071006619 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2071006619 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.425023134 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 11370952964 ps |
| CPU time | 3657.77 seconds |
| Started | Jul 18 08:23:07 PM PDT 24 |
| Finished | Jul 18 09:24:06 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-29271bbc-c48f-4245-b11f-9843caa7ed2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425023134 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.425023134 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1220607580 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 14269790990 ps |
| CPU time | 3730.08 seconds |
| Started | Jul 18 08:23:41 PM PDT 24 |
| Finished | Jul 18 09:25:53 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-c31169e2-7476-4825-8617-4da286ebd8df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220607580 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1220607580 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3237312212 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 15083417850 ps |
| CPU time | 3542.28 seconds |
| Started | Jul 18 08:19:40 PM PDT 24 |
| Finished | Jul 18 09:18:43 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-1bd23a63-326d-4803-8598-7f1afe35f87e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237312212 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3237312212 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3141091534 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 14796659972 ps |
| CPU time | 3192.76 seconds |
| Started | Jul 18 08:23:28 PM PDT 24 |
| Finished | Jul 18 09:16:42 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-25dbe9b9-718f-4a83-93b3-1e7456ed1494 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141091534 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3141091534 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3789800076 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 13757084444 ps |
| CPU time | 3427.04 seconds |
| Started | Jul 18 08:22:53 PM PDT 24 |
| Finished | Jul 18 09:20:01 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-ab43ac42-d0e2-49e8-9d32-37294997ee99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789800076 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3789800076 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2043429112 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 11077434540 ps |
| CPU time | 3180.28 seconds |
| Started | Jul 18 08:26:09 PM PDT 24 |
| Finished | Jul 18 09:19:10 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-c8698bf1-736c-4560-9109-a2d04fba1556 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043429112 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2043429112 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.2059435427 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 14614261264 ps |
| CPU time | 3706.76 seconds |
| Started | Jul 18 08:28:03 PM PDT 24 |
| Finished | Jul 18 09:29:52 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-a2df1fb8-f1ec-4735-8938-3fdde8e16582 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2059435427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2059435427 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.727854304 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 16778500260 ps |
| CPU time | 4910.66 seconds |
| Started | Jul 18 08:23:33 PM PDT 24 |
| Finished | Jul 18 09:45:25 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-3977f79a-0f32-4ec9-8bd3-7bdc2da8ad6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727854304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.727854304 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.3941562035 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 3991180078 ps |
| CPU time | 604.79 seconds |
| Started | Jul 18 08:22:48 PM PDT 24 |
| Finished | Jul 18 08:32:54 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-4fa1aeba-b121-4387-86bc-d0d810118770 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941562035 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.3941562035 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.2180752952 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 6852439264 ps |
| CPU time | 333.84 seconds |
| Started | Jul 18 08:18:59 PM PDT 24 |
| Finished | Jul 18 08:24:34 PM PDT 24 |
| Peak memory | 623848 kb |
| Host | smart-99b32515-2f19-4212-beb4-920230c90dc1 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2180752952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.2180752952 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.794030815 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2305335191 ps |
| CPU time | 103.92 seconds |
| Started | Jul 18 08:16:22 PM PDT 24 |
| Finished | Jul 18 08:18:06 PM PDT 24 |
| Peak memory | 617128 kb |
| Host | smart-d9291597-db9c-43a6-b9c8-96d729b9c52e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794030815 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.794030815 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.2725728590 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 13675827736 ps |
| CPU time | 1579.62 seconds |
| Started | Jul 18 08:19:34 PM PDT 24 |
| Finished | Jul 18 08:45:55 PM PDT 24 |
| Peak memory | 604792 kb |
| Host | smart-5d806028-7f9a-419b-bb76-e1376f24f7a4 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725728590 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 725728590 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1737667529 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4121471560 ps |
| CPU time | 320.4 seconds |
| Started | Jul 18 08:28:47 PM PDT 24 |
| Finished | Jul 18 08:34:08 PM PDT 24 |
| Peak memory | 619648 kb |
| Host | smart-a9f29489-0602-411f-aa3b-da3ccee9acba |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 737667529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.1737667529 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.4016861997 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 3747642298 ps |
| CPU time | 395.32 seconds |
| Started | Jul 18 08:18:03 PM PDT 24 |
| Finished | Jul 18 08:24:39 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-9928c913-da90-46b8-9755-f1da02dff9fd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4016861997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.4016861997 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1071638698 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 19059713998 ps |
| CPU time | 507.78 seconds |
| Started | Jul 18 08:24:22 PM PDT 24 |
| Finished | Jul 18 08:32:52 PM PDT 24 |
| Peak memory | 619108 kb |
| Host | smart-85d50cf2-d2e2-4c6f-8db6-e7c1b010f941 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1071638698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1071638698 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.1429646872 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3115936128 ps |
| CPU time | 427.4 seconds |
| Started | Jul 18 08:23:31 PM PDT 24 |
| Finished | Jul 18 08:30:40 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-068efaeb-7f15-4007-aff0-bc0fa6563b1a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429646872 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.1429646872 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3381163726 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 2657916200 ps |
| CPU time | 193.69 seconds |
| Started | Jul 18 08:22:22 PM PDT 24 |
| Finished | Jul 18 08:25:38 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-0e086727-dd2c-4583-a6d9-fccbc1b54d73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381 163726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.3381163726 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1968080802 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 2729625362 ps |
| CPU time | 280.28 seconds |
| Started | Jul 18 08:29:50 PM PDT 24 |
| Finished | Jul 18 08:34:31 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-66710d76-7333-4bcb-8728-891bb3fd6133 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968080802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.1968080802 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2002669056 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2547330500 ps |
| CPU time | 230.19 seconds |
| Started | Jul 18 08:22:56 PM PDT 24 |
| Finished | Jul 18 08:26:47 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-67063f04-2637-4ca6-86dd-721eeb003bed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002669056 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2002669056 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.3022128381 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 3060583168 ps |
| CPU time | 240.1 seconds |
| Started | Jul 18 08:22:35 PM PDT 24 |
| Finished | Jul 18 08:26:37 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-5986a9d5-9ae6-4cc3-a2a9-4e81763942eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022128381 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.3022128381 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3716148293 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 2705389201 ps |
| CPU time | 341 seconds |
| Started | Jul 18 08:21:49 PM PDT 24 |
| Finished | Jul 18 08:27:31 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-ce2d417c-af1e-4676-9198-c1969b8d05f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716148293 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3716148293 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.75487658 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 3536554092 ps |
| CPU time | 319.35 seconds |
| Started | Jul 18 08:29:42 PM PDT 24 |
| Finished | Jul 18 08:35:02 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-a46bfa2b-eb62-4335-b42e-d731003ba88c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75487658 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_aes_smoketest.75487658 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3065848244 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 2422832013 ps |
| CPU time | 229.06 seconds |
| Started | Jul 18 08:22:54 PM PDT 24 |
| Finished | Jul 18 08:26:44 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-1bceb171-533a-4365-94fd-fb7c663a041e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3065848244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3065848244 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.611650164 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 5196711726 ps |
| CPU time | 548.61 seconds |
| Started | Jul 18 08:21:05 PM PDT 24 |
| Finished | Jul 18 08:30:14 PM PDT 24 |
| Peak memory | 619168 kb |
| Host | smart-23e46d70-921c-40f5-b2a2-71952ee696a7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=611650164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.611650164 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.434510690 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 7729759662 ps |
| CPU time | 1571.97 seconds |
| Started | Jul 18 08:25:15 PM PDT 24 |
| Finished | Jul 18 08:51:28 PM PDT 24 |
| Peak memory | 610000 kb |
| Host | smart-43fbe611-5295-4895-a25f-fdc2ef407a4e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=434510690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.434510690 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2444298788 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 6944908958 ps |
| CPU time | 1547.17 seconds |
| Started | Jul 18 08:22:27 PM PDT 24 |
| Finished | Jul 18 08:48:15 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-d009f678-129e-4ede-9d87-489b7f246a97 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444298788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2444298788 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1251651102 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 9389419048 ps |
| CPU time | 1089.89 seconds |
| Started | Jul 18 08:22:22 PM PDT 24 |
| Finished | Jul 18 08:40:35 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-6b707241-ba4e-49b5-a34c-9009912915fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251651102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1251651102 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1416457050 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 8087191426 ps |
| CPU time | 1456.56 seconds |
| Started | Jul 18 08:21:34 PM PDT 24 |
| Finished | Jul 18 08:45:52 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-e59f0749-2031-4ad2-a8bf-805a9811a760 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1416457050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1416457050 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1434483576 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 4088894072 ps |
| CPU time | 416.33 seconds |
| Started | Jul 18 08:22:27 PM PDT 24 |
| Finished | Jul 18 08:29:25 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-5e59ce9a-f48e-4a88-8a9a-5c1f3fccaffc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1434483576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1434483576 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3469312533 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 254992690664 ps |
| CPU time | 12531.3 seconds |
| Started | Jul 18 08:22:30 PM PDT 24 |
| Finished | Jul 18 11:51:23 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-d5de7ee1-efaa-473d-a37a-c19893dc60e4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469312533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3469312533 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.846345271 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2953498570 ps |
| CPU time | 321.76 seconds |
| Started | Jul 18 08:21:39 PM PDT 24 |
| Finished | Jul 18 08:27:02 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-2d8b92aa-303d-4561-b37c-e7b5ee4b8ad0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846345271 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.846345271 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.595900570 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5358711392 ps |
| CPU time | 634.84 seconds |
| Started | Jul 18 08:18:33 PM PDT 24 |
| Finished | Jul 18 08:29:09 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-64baf31a-1447-4e62-88ab-ec5d7800bd1c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 595900570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.595900570 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.3830353223 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 4123779940 ps |
| CPU time | 404.27 seconds |
| Started | Jul 18 08:20:59 PM PDT 24 |
| Finished | Jul 18 08:27:44 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-d6fa732d-103a-4602-9c18-0ec517b7cea9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830353223 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.3830353223 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.679541999 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 7459731648 ps |
| CPU time | 601.74 seconds |
| Started | Jul 18 08:20:15 PM PDT 24 |
| Finished | Jul 18 08:30:18 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-da3df8ff-a306-4d1c-9fb4-e3b9b5653a1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=679541999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.679541999 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2855958134 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 2878150568 ps |
| CPU time | 327.63 seconds |
| Started | Jul 18 08:29:28 PM PDT 24 |
| Finished | Jul 18 08:34:56 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-3a6d8cc6-3aef-4e16-b7ff-f7cf9688cf24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855958134 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2855958134 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2789210056 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 8614473330 ps |
| CPU time | 591.69 seconds |
| Started | Jul 18 08:20:32 PM PDT 24 |
| Finished | Jul 18 08:30:25 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-6416ee19-7943-45bb-8683-60725c9dcb4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2789210056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2789210056 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1422207801 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 5374693350 ps |
| CPU time | 573.01 seconds |
| Started | Jul 18 08:20:31 PM PDT 24 |
| Finished | Jul 18 08:30:05 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-54abed4a-f9d7-40b4-970e-0cccfc970596 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1422207801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.1422207801 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1096415124 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 6919933160 ps |
| CPU time | 980.92 seconds |
| Started | Jul 18 08:27:34 PM PDT 24 |
| Finished | Jul 18 08:43:56 PM PDT 24 |
| Peak memory | 617096 kb |
| Host | smart-9bf70064-9e5e-44bf-a16b-8237e2b4686b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096415124 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.1096415124 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2018872807 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 4729112437 ps |
| CPU time | 507.5 seconds |
| Started | Jul 18 08:26:46 PM PDT 24 |
| Finished | Jul 18 08:35:15 PM PDT 24 |
| Peak memory | 624424 kb |
| Host | smart-f7aac535-79ec-4229-a66c-6827f067cd63 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2018872807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2018872807 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1234304586 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 4509549664 ps |
| CPU time | 668.36 seconds |
| Started | Jul 18 08:27:31 PM PDT 24 |
| Finished | Jul 18 08:38:40 PM PDT 24 |
| Peak memory | 612780 kb |
| Host | smart-fef99b30-ccd0-4213-936c-8f746c01bb93 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234304586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1234304586 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3883046806 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 4588990112 ps |
| CPU time | 654.05 seconds |
| Started | Jul 18 08:27:35 PM PDT 24 |
| Finished | Jul 18 08:38:30 PM PDT 24 |
| Peak memory | 614068 kb |
| Host | smart-c37eb83b-0a04-42ff-b5e9-d1227bfac318 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883046806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3883046806 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2250147312 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 3597624192 ps |
| CPU time | 551.52 seconds |
| Started | Jul 18 08:30:55 PM PDT 24 |
| Finished | Jul 18 08:40:08 PM PDT 24 |
| Peak memory | 612916 kb |
| Host | smart-32217602-5087-4a25-ac7d-77bc0ce8a621 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250147312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2250147312 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1202816475 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 4961988480 ps |
| CPU time | 795.06 seconds |
| Started | Jul 18 08:26:25 PM PDT 24 |
| Finished | Jul 18 08:39:41 PM PDT 24 |
| Peak memory | 614048 kb |
| Host | smart-f697e721-276d-48a7-a3d2-099ac91b7616 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202816475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1202816475 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2077613137 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 4842708144 ps |
| CPU time | 740.67 seconds |
| Started | Jul 18 08:30:31 PM PDT 24 |
| Finished | Jul 18 08:42:54 PM PDT 24 |
| Peak memory | 614076 kb |
| Host | smart-3811f293-15a8-4b28-9094-7f5c0c32c9b5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077613137 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2077613137 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3153136401 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2826819032 ps |
| CPU time | 275.1 seconds |
| Started | Jul 18 08:26:36 PM PDT 24 |
| Finished | Jul 18 08:31:12 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-f387531e-3220-4045-8d9c-b47fe284590d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153136401 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3153136401 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3198875614 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 4257045528 ps |
| CPU time | 473.87 seconds |
| Started | Jul 18 08:26:33 PM PDT 24 |
| Finished | Jul 18 08:34:28 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-10ee983c-6d3c-4c13-b70c-b9e0b5449f8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198875614 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.3198875614 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1803085479 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2784038681 ps |
| CPU time | 194.03 seconds |
| Started | Jul 18 08:28:31 PM PDT 24 |
| Finished | Jul 18 08:31:46 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-3acc9662-611b-4715-baca-b67eb4e3adb4 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803085479 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1803085479 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2944257791 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5654257780 ps |
| CPU time | 459.06 seconds |
| Started | Jul 18 08:27:04 PM PDT 24 |
| Finished | Jul 18 08:34:45 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-1b5d4899-fc8b-4c22-8641-ec47944870d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944257791 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2944257791 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.189189369 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 5433404168 ps |
| CPU time | 590.1 seconds |
| Started | Jul 18 08:31:06 PM PDT 24 |
| Finished | Jul 18 08:40:57 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-282fe5c7-dce5-4ddb-8aaa-49e5cb34dd61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189189369 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.189189369 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1006440278 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5490076488 ps |
| CPU time | 658.17 seconds |
| Started | Jul 18 08:28:50 PM PDT 24 |
| Finished | Jul 18 08:39:50 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-65338ed6-eb36-4436-85ba-f27719aadcff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006440278 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.1006440278 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2027195792 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 8380935792 ps |
| CPU time | 1375.24 seconds |
| Started | Jul 18 08:27:22 PM PDT 24 |
| Finished | Jul 18 08:50:18 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-7decc538-b682-401c-898c-3346ef692ab6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027195792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2027195792 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3345220149 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3227301416 ps |
| CPU time | 462.17 seconds |
| Started | Jul 18 08:30:53 PM PDT 24 |
| Finished | Jul 18 08:38:37 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-dea2fde5-d449-4d47-861a-6a44fa719925 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345220149 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.3345220149 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2161657378 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 4627016780 ps |
| CPU time | 559.75 seconds |
| Started | Jul 18 08:26:40 PM PDT 24 |
| Finished | Jul 18 08:36:00 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-329f5646-e21c-4a44-a6d7-e013b7e440ab |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161657378 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2161657378 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3373078601 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 2473225900 ps |
| CPU time | 298.57 seconds |
| Started | Jul 18 08:28:49 PM PDT 24 |
| Finished | Jul 18 08:33:48 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-3d2740a0-1013-459a-9d2b-73f42a56aaf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373078601 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.3373078601 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3338169613 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 27817446143 ps |
| CPU time | 4441.71 seconds |
| Started | Jul 18 08:29:16 PM PDT 24 |
| Finished | Jul 18 09:43:19 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-d75539c8-86b8-4c10-b1f8-374ce946ace5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3338169613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.3338169613 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1330406485 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4231988742 ps |
| CPU time | 526.59 seconds |
| Started | Jul 18 08:24:06 PM PDT 24 |
| Finished | Jul 18 08:32:54 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-a0866bc9-70d5-4f0e-9d4f-d6c6c955fa0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13304 06485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1330406485 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3670275800 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 2392374954 ps |
| CPU time | 302.88 seconds |
| Started | Jul 18 08:22:28 PM PDT 24 |
| Finished | Jul 18 08:27:32 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-5fb56154-2425-469d-a76a-987f7e935148 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670275800 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3670275800 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.2716741588 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 6577053125 ps |
| CPU time | 643.87 seconds |
| Started | Jul 18 08:23:04 PM PDT 24 |
| Finished | Jul 18 08:33:48 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-8196909e-b576-40d0-a808-a4883e0f7906 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716741588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.2716741588 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.3144551304 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 2131543154 ps |
| CPU time | 191.25 seconds |
| Started | Jul 18 08:34:11 PM PDT 24 |
| Finished | Jul 18 08:37:24 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-e708c9b2-288d-4105-811a-d418505b2307 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144551304 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.3144551304 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3006358674 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 5303822000 ps |
| CPU time | 789.18 seconds |
| Started | Jul 18 08:17:31 PM PDT 24 |
| Finished | Jul 18 08:30:41 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-445aee4a-66ca-48ba-83e1-4b52f3b613d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3006358674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3006358674 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.417546011 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4776732766 ps |
| CPU time | 1023.06 seconds |
| Started | Jul 18 08:22:37 PM PDT 24 |
| Finished | Jul 18 08:39:41 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-5265d21e-3b64-4f9f-aeb1-9b68c68ab19d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417546011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_a uto_mode.417546011 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2982448862 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3560141640 ps |
| CPU time | 708.36 seconds |
| Started | Jul 18 08:21:45 PM PDT 24 |
| Finished | Jul 18 08:33:35 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-1851bfe7-3a8c-444f-8a4f-a62e10b01913 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982448862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2982448862 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.445569547 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 6411920456 ps |
| CPU time | 1073.97 seconds |
| Started | Jul 18 08:25:17 PM PDT 24 |
| Finished | Jul 18 08:43:13 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-926f25c8-09f7-48b8-b310-ee7aa30420c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=445569547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.445569547 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1565608260 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 6578749995 ps |
| CPU time | 1352.37 seconds |
| Started | Jul 18 08:23:58 PM PDT 24 |
| Finished | Jul 18 08:46:33 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-027f80fd-826a-4099-bb63-7ef9aad92502 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565608260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1565608260 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3990521849 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3122651216 ps |
| CPU time | 628.78 seconds |
| Started | Jul 18 08:22:45 PM PDT 24 |
| Finished | Jul 18 08:33:15 PM PDT 24 |
| Peak memory | 616320 kb |
| Host | smart-da48fd42-4097-4084-b00e-5523686412dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990521849 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3990521849 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1198056351 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 8747813692 ps |
| CPU time | 2008.72 seconds |
| Started | Jul 18 08:21:45 PM PDT 24 |
| Finished | Jul 18 08:55:15 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-75f1e02a-bb21-46f4-b2b6-557f6ba8a33c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198056351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1198056351 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2870278205 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 2957656464 ps |
| CPU time | 182.74 seconds |
| Started | Jul 18 08:22:18 PM PDT 24 |
| Finished | Jul 18 08:25:22 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-6adbd69e-b5da-4824-b3fa-c37b24335db2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28 70278205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2870278205 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.456820386 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 6292429296 ps |
| CPU time | 1342.49 seconds |
| Started | Jul 18 08:24:22 PM PDT 24 |
| Finished | Jul 18 08:46:46 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-c9126f7b-6b17-4171-8138-41e47353644e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=456820386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.456820386 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.144488164 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2404896100 ps |
| CPU time | 278.47 seconds |
| Started | Jul 18 08:21:44 PM PDT 24 |
| Finished | Jul 18 08:26:24 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-f2007614-0942-403f-85cf-80a2518be851 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144488164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.144488164 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2438565326 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4097903350 ps |
| CPU time | 524.3 seconds |
| Started | Jul 18 08:30:29 PM PDT 24 |
| Finished | Jul 18 08:39:15 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-47f2f26d-5777-44bd-a78f-2623c36e79f8 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2438565326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2438565326 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.3092233083 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 3207113672 ps |
| CPU time | 347.18 seconds |
| Started | Jul 18 08:19:49 PM PDT 24 |
| Finished | Jul 18 08:25:37 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-cff31d60-a4e6-401a-85bd-f159dd840daf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092233083 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.3092233083 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.2308293714 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 2946898664 ps |
| CPU time | 140.97 seconds |
| Started | Jul 18 08:16:18 PM PDT 24 |
| Finished | Jul 18 08:18:40 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-c2f64aef-3f00-4d96-9600-bf38cc51bc3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308293714 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.2308293714 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.1403216015 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2353884482 ps |
| CPU time | 187.66 seconds |
| Started | Jul 18 08:16:29 PM PDT 24 |
| Finished | Jul 18 08:19:37 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-10717dc4-8302-4bfe-8189-7e3610b11b83 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403216015 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.1403216015 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.148927998 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3090386392 ps |
| CPU time | 114.64 seconds |
| Started | Jul 18 08:16:26 PM PDT 24 |
| Finished | Jul 18 08:18:21 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-70ebd936-3a1a-418f-bf4f-bdd3245d5437 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148927998 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.148927998 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2739377301 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 58902493088 ps |
| CPU time | 10641.9 seconds |
| Started | Jul 18 08:17:56 PM PDT 24 |
| Finished | Jul 18 11:15:20 PM PDT 24 |
| Peak memory | 624800 kb |
| Host | smart-58948bde-723a-44b6-8df1-928a77da78ab |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2739377301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.2739377301 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.1191626898 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5895262304 ps |
| CPU time | 794.46 seconds |
| Started | Jul 18 08:27:46 PM PDT 24 |
| Finished | Jul 18 08:41:02 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-2a8226d6-8db4-43d1-bc89-d5f91daa4699 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=1191626898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.1191626898 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3052815993 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5962962200 ps |
| CPU time | 1107.4 seconds |
| Started | Jul 18 08:18:06 PM PDT 24 |
| Finished | Jul 18 08:36:34 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-aed46bfc-86eb-4737-8d8d-0f1e166a1e86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052815993 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.3052815993 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1077544582 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 5848479332 ps |
| CPU time | 1113.7 seconds |
| Started | Jul 18 08:18:39 PM PDT 24 |
| Finished | Jul 18 08:37:14 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-0c5c9ca5-c579-45d8-8b4b-bce7388bc558 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077544582 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1077544582 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2912196270 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 7417820128 ps |
| CPU time | 1029.76 seconds |
| Started | Jul 18 08:29:42 PM PDT 24 |
| Finished | Jul 18 08:46:53 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-274df806-a06b-487d-aabe-5c3b4d934e4c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912196270 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2912196270 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.290209921 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 5900894541 ps |
| CPU time | 1086.84 seconds |
| Started | Jul 18 08:21:02 PM PDT 24 |
| Finished | Jul 18 08:39:10 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-5b1953db-65cb-4b4b-90b6-3f728a07a0d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290209921 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.290209921 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1975676569 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3744616562 ps |
| CPU time | 327.03 seconds |
| Started | Jul 18 08:20:34 PM PDT 24 |
| Finished | Jul 18 08:26:01 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-9586c0a6-b529-4932-895d-315210fe720b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975676569 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1975676569 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1154389445 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4159076726 ps |
| CPU time | 411.77 seconds |
| Started | Jul 18 08:20:03 PM PDT 24 |
| Finished | Jul 18 08:26:56 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-adfc983f-ae93-4faf-9c49-dfffcd5a1e62 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 54389445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1154389445 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1963057220 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 5212082268 ps |
| CPU time | 1163.01 seconds |
| Started | Jul 18 08:27:44 PM PDT 24 |
| Finished | Jul 18 08:47:08 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-28a88c23-fe89-47b6-a194-b65244c353d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963057220 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1963057220 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4271283124 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3759638746 ps |
| CPU time | 722.8 seconds |
| Started | Jul 18 08:19:07 PM PDT 24 |
| Finished | Jul 18 08:31:12 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-403be7ed-1b3e-4f21-bffe-dc1b482c2d9d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271283124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.4271283124 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1011197008 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3745904350 ps |
| CPU time | 692.32 seconds |
| Started | Jul 18 08:20:16 PM PDT 24 |
| Finished | Jul 18 08:31:50 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-f8356e82-2751-47cd-a048-1e4eaebc544b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1011197008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.1011197008 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.640548234 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2937765396 ps |
| CPU time | 350.37 seconds |
| Started | Jul 18 08:27:55 PM PDT 24 |
| Finished | Jul 18 08:33:46 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-4cbdf1e3-490c-4be7-96e3-c5a72db2dae6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6405482 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.640548234 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1267741513 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 20914806443 ps |
| CPU time | 2203.74 seconds |
| Started | Jul 18 08:28:15 PM PDT 24 |
| Finished | Jul 18 09:05:00 PM PDT 24 |
| Peak memory | 614448 kb |
| Host | smart-790ea42b-5034-4275-a56f-daa743e31b27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1267741513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1267741513 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4039656828 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 3579751128 ps |
| CPU time | 267.67 seconds |
| Started | Jul 18 08:32:41 PM PDT 24 |
| Finished | Jul 18 08:37:10 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-36ef43c2-702e-4002-868d-66ed1b87e2a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4039656828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.4039656828 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1807439413 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2550452855 ps |
| CPU time | 341.19 seconds |
| Started | Jul 18 08:30:12 PM PDT 24 |
| Finished | Jul 18 08:35:55 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-60c887ea-d0af-4c83-83a8-1f35543ff293 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807439413 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1807439413 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2922703695 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3292811400 ps |
| CPU time | 340.48 seconds |
| Started | Jul 18 08:24:36 PM PDT 24 |
| Finished | Jul 18 08:30:17 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-0f8f8b1e-80bd-43b7-88db-decc7dc15f1c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922703695 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2922703695 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1698935976 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 2761711896 ps |
| CPU time | 300.7 seconds |
| Started | Jul 18 08:26:33 PM PDT 24 |
| Finished | Jul 18 08:31:35 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-91eeff95-132d-4cba-92f8-6c9a2acfad16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698935976 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1698935976 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3353735081 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 2879579690 ps |
| CPU time | 255.46 seconds |
| Started | Jul 18 08:23:56 PM PDT 24 |
| Finished | Jul 18 08:28:12 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-024a9541-6691-43e4-b0e3-4793e3e108ac |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353735081 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.3353735081 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2541650809 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 2674246972 ps |
| CPU time | 255.04 seconds |
| Started | Jul 18 08:31:40 PM PDT 24 |
| Finished | Jul 18 08:35:56 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-527298ee-4841-471e-b3bf-77b1fa391e79 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541650809 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2541650809 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2840111818 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7706174264 ps |
| CPU time | 1569.09 seconds |
| Started | Jul 18 08:26:02 PM PDT 24 |
| Finished | Jul 18 08:52:12 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-4a8011c6-fdeb-4cfe-9723-d90bc240792f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840111818 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2840111818 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2075527783 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3227375930 ps |
| CPU time | 289.64 seconds |
| Started | Jul 18 08:25:20 PM PDT 24 |
| Finished | Jul 18 08:30:11 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-aec30b62-51ba-4a4f-823a-f4b1670d8218 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075527783 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2075527783 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.864502686 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3416911404 ps |
| CPU time | 363.35 seconds |
| Started | Jul 18 08:34:23 PM PDT 24 |
| Finished | Jul 18 08:40:27 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-0b300271-2627-47ac-84fc-229bc477cc5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864502686 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.864502686 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2818666611 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 3990242386 ps |
| CPU time | 499.11 seconds |
| Started | Jul 18 08:21:20 PM PDT 24 |
| Finished | Jul 18 08:29:42 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-7b76666a-6c76-4a48-b8aa-f3f817e9df17 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818666611 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2818666611 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2156826800 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 4890187644 ps |
| CPU time | 822.84 seconds |
| Started | Jul 18 08:19:45 PM PDT 24 |
| Finished | Jul 18 08:33:29 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-16f51be4-011f-4573-9099-4fe1fa67557e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156826800 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.2156826800 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2147767091 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5069717046 ps |
| CPU time | 682.18 seconds |
| Started | Jul 18 08:21:20 PM PDT 24 |
| Finished | Jul 18 08:32:44 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-06143d7c-0554-4fbe-8592-0ec7d61aaf9a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147767091 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.2147767091 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1381532925 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 5313816160 ps |
| CPU time | 1069.15 seconds |
| Started | Jul 18 08:17:55 PM PDT 24 |
| Finished | Jul 18 08:35:45 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-af8e87c8-b1a7-49cd-922b-ab4debdb204a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381532925 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.1381532925 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.563839502 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 65603562275 ps |
| CPU time | 12425.6 seconds |
| Started | Jul 18 08:21:03 PM PDT 24 |
| Finished | Jul 18 11:48:11 PM PDT 24 |
| Peak memory | 624788 kb |
| Host | smart-f0fd54b0-4eee-4412-b970-21fd2b00d672 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=563839502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.563839502 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3080378071 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 11709441920 ps |
| CPU time | 2251.94 seconds |
| Started | Jul 18 08:28:19 PM PDT 24 |
| Finished | Jul 18 09:05:52 PM PDT 24 |
| Peak memory | 616664 kb |
| Host | smart-099c577b-f462-4e50-b106-07cc66899136 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080 378071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3080378071 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3018144185 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 13114326584 ps |
| CPU time | 2470.46 seconds |
| Started | Jul 18 08:26:48 PM PDT 24 |
| Finished | Jul 18 09:08:00 PM PDT 24 |
| Peak memory | 617768 kb |
| Host | smart-ea107a42-7128-4fa7-b2d6-fc7d1863d7ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3018144185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3018144185 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2710416508 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 8578411913 ps |
| CPU time | 1251.4 seconds |
| Started | Jul 18 08:28:06 PM PDT 24 |
| Finished | Jul 18 08:48:58 PM PDT 24 |
| Peak memory | 617432 kb |
| Host | smart-7f28be04-d2e8-4871-8b3f-c8537cbaede6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2710416508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2710416508 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1702981799 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 12218082512 ps |
| CPU time | 2515.03 seconds |
| Started | Jul 18 08:26:32 PM PDT 24 |
| Finished | Jul 18 09:08:27 PM PDT 24 |
| Peak memory | 617968 kb |
| Host | smart-ef6fbf9c-bc06-4722-b8bd-0e3247281474 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1702981799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.1702981799 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.873020836 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 7797577666 ps |
| CPU time | 1311.59 seconds |
| Started | Jul 18 08:26:54 PM PDT 24 |
| Finished | Jul 18 08:48:46 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-9b78edac-3054-45ed-bf71-79275302cfd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873020 836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.873020836 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1523619442 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 7895171696 ps |
| CPU time | 1783.11 seconds |
| Started | Jul 18 08:26:25 PM PDT 24 |
| Finished | Jul 18 08:56:09 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-41dad065-5e80-4b17-a9b0-a5db3ee13675 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15236 19442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1523619442 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2205817664 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 13346797648 ps |
| CPU time | 4252.18 seconds |
| Started | Jul 18 08:27:06 PM PDT 24 |
| Finished | Jul 18 09:38:01 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-a09143a9-8c86-467f-923e-a450bb1e7b59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22058 17664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2205817664 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2749701367 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2740458244 ps |
| CPU time | 180.03 seconds |
| Started | Jul 18 08:26:22 PM PDT 24 |
| Finished | Jul 18 08:29:24 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-3478981a-f301-4181-90c1-1d692e5e688c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749701367 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2749701367 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.3652067862 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3523020520 ps |
| CPU time | 305.34 seconds |
| Started | Jul 18 08:20:29 PM PDT 24 |
| Finished | Jul 18 08:25:35 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-08f40b07-c542-4bfa-8779-944139cade98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652067862 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.3652067862 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3689536259 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2977432602 ps |
| CPU time | 263.15 seconds |
| Started | Jul 18 08:26:48 PM PDT 24 |
| Finished | Jul 18 08:31:11 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-6467d208-1398-418f-9aa2-3da3fcf9f160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689536259 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3689536259 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2303842949 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 2166158856 ps |
| CPU time | 230.9 seconds |
| Started | Jul 18 08:25:29 PM PDT 24 |
| Finished | Jul 18 08:29:20 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-efa5bc59-252e-4582-a9b0-b40a6f7a3832 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303842949 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.2303842949 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1479226803 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2414437566 ps |
| CPU time | 278.55 seconds |
| Started | Jul 18 08:26:48 PM PDT 24 |
| Finished | Jul 18 08:31:28 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-b8328e3c-ae2d-48fd-b1f9-ce48684083f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479226803 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1479226803 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.455199919 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2505207089 ps |
| CPU time | 294.89 seconds |
| Started | Jul 18 08:26:05 PM PDT 24 |
| Finished | Jul 18 08:31:01 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-cdd10da0-41da-47d3-98be-3392e1954340 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455199919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.455199919 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2601119870 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 2927273310 ps |
| CPU time | 324.41 seconds |
| Started | Jul 18 08:29:26 PM PDT 24 |
| Finished | Jul 18 08:34:51 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-55b20dfa-655c-4ecb-8a32-b938edcfe059 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26011198 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2601119870 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.2627323895 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2699768400 ps |
| CPU time | 374.77 seconds |
| Started | Jul 18 08:28:40 PM PDT 24 |
| Finished | Jul 18 08:34:55 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-3a34f7d8-fae2-4e33-8b57-00999648b0c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627323895 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.2627323895 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4187404441 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2969030356 ps |
| CPU time | 344.77 seconds |
| Started | Jul 18 08:19:07 PM PDT 24 |
| Finished | Jul 18 08:24:53 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-9ab1a9d5-3381-46f2-97ea-c222a357dca6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187404441 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.4187404441 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.637987537 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4908008548 ps |
| CPU time | 592.3 seconds |
| Started | Jul 18 08:28:29 PM PDT 24 |
| Finished | Jul 18 08:38:22 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-67ce2958-7f85-490a-890c-857334ef1952 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=637987537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.637987537 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3119835714 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 3100767788 ps |
| CPU time | 150.68 seconds |
| Started | Jul 18 08:20:17 PM PDT 24 |
| Finished | Jul 18 08:22:49 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-3d2c733c-6447-49a8-a21c-4a9a9c8b6fe1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31198357 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.3119835714 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3269775595 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 1865101868 ps |
| CPU time | 120.61 seconds |
| Started | Jul 18 08:20:30 PM PDT 24 |
| Finished | Jul 18 08:22:31 PM PDT 24 |
| Peak memory | 617516 kb |
| Host | smart-ee65f909-2708-4e57-864a-00a4d862703f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3269775595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.3269775595 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4118883853 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 1925456887 ps |
| CPU time | 112.23 seconds |
| Started | Jul 18 08:19:30 PM PDT 24 |
| Finished | Jul 18 08:21:23 PM PDT 24 |
| Peak memory | 617756 kb |
| Host | smart-0d0f064c-8bf8-4f38-95ce-82e050492049 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118883853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4118883853 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3186072517 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 50039568210 ps |
| CPU time | 5277.9 seconds |
| Started | Jul 18 08:20:57 PM PDT 24 |
| Finished | Jul 18 09:48:57 PM PDT 24 |
| Peak memory | 620468 kb |
| Host | smart-43d79954-b053-4d46-89cd-ca5185b479a6 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186072517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.3186072517 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1170544895 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 8139243490 ps |
| CPU time | 1151.12 seconds |
| Started | Jul 18 08:22:00 PM PDT 24 |
| Finished | Jul 18 08:41:12 PM PDT 24 |
| Peak memory | 620036 kb |
| Host | smart-99288643-0ec9-414c-ba8e-4d6f86980b90 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170544895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.1170544895 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3507094684 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 24758609400 ps |
| CPU time | 2116.87 seconds |
| Started | Jul 18 08:19:56 PM PDT 24 |
| Finished | Jul 18 08:55:14 PM PDT 24 |
| Peak memory | 620840 kb |
| Host | smart-88f53cc1-da2d-4000-a463-8670548a64a9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3507094684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3507094684 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.68496242 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 16489964452 ps |
| CPU time | 3601.42 seconds |
| Started | Jul 18 08:21:00 PM PDT 24 |
| Finished | Jul 18 09:21:02 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-2cf9137f-c43d-48d3-a47b-1e7661451aac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=68496242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.68496242 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3507787911 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 18829602391 ps |
| CPU time | 4518.54 seconds |
| Started | Jul 18 08:24:41 PM PDT 24 |
| Finished | Jul 18 09:40:01 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-e864256f-c950-4775-9880-4218e3d0b637 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3507787911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3507787911 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3696644640 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 24777333053 ps |
| CPU time | 3842.74 seconds |
| Started | Jul 18 08:28:58 PM PDT 24 |
| Finished | Jul 18 09:33:02 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-c5a818de-7238-475c-b76c-4303e8a01003 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696644640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3696644640 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3246698266 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 3780405320 ps |
| CPU time | 662.4 seconds |
| Started | Jul 18 08:20:53 PM PDT 24 |
| Finished | Jul 18 08:31:57 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-47783888-9a08-4c43-a79e-6549824eb1a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246698266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3246698266 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.10080304 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 6155006670 ps |
| CPU time | 970.88 seconds |
| Started | Jul 18 08:21:14 PM PDT 24 |
| Finished | Jul 18 08:37:26 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-174177d6-c288-4b46-9b77-acc80ae32a21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=10080304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.10080304 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2180875478 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 8753321572 ps |
| CPU time | 2186.78 seconds |
| Started | Jul 18 08:29:52 PM PDT 24 |
| Finished | Jul 18 09:06:19 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-0134d0ec-f666-42f4-9d29-68828da6e732 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180875478 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2180875478 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1470287966 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3506932602 ps |
| CPU time | 342.35 seconds |
| Started | Jul 18 08:21:52 PM PDT 24 |
| Finished | Jul 18 08:27:35 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-0feb0239-6ece-478d-967a-6cd88c80144e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470287966 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.1470287966 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.754664145 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 7127899560 ps |
| CPU time | 1156.45 seconds |
| Started | Jul 18 08:19:04 PM PDT 24 |
| Finished | Jul 18 08:38:21 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-db3e0848-6034-47fe-9aa3-b6c39c0b0c7d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=754664145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.754664145 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4201910867 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 7591795992 ps |
| CPU time | 1107.86 seconds |
| Started | Jul 18 08:19:23 PM PDT 24 |
| Finished | Jul 18 08:37:52 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-6855a93d-7697-4e9f-b0e7-1abe808ed8ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4201910867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.4201910867 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.929105160 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 6175622558 ps |
| CPU time | 1191.63 seconds |
| Started | Jul 18 08:21:45 PM PDT 24 |
| Finished | Jul 18 08:41:38 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-b5be0c4d-3bba-44d7-ae2c-b65467062c6d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=929105160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.929105160 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2080738465 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 4058266216 ps |
| CPU time | 827.6 seconds |
| Started | Jul 18 08:21:16 PM PDT 24 |
| Finished | Jul 18 08:35:05 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-36cec237-f950-448c-8163-3e2d4046c56a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2080738465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2080738465 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.203609264 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 2787776608 ps |
| CPU time | 274.08 seconds |
| Started | Jul 18 08:29:15 PM PDT 24 |
| Finished | Jul 18 08:33:50 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-6c507180-9a04-4882-aa6c-0756a04966eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203609264 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_otp_ctrl_smoketest.203609264 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.42216841 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2538187430 ps |
| CPU time | 245.24 seconds |
| Started | Jul 18 08:17:06 PM PDT 24 |
| Finished | Jul 18 08:21:13 PM PDT 24 |
| Peak memory | 613032 kb |
| Host | smart-b36fa9ac-89d3-4208-bf41-ba1c1e4a5f51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42216841 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.42216841 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.311444154 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 3592282150 ps |
| CPU time | 248.59 seconds |
| Started | Jul 18 08:27:36 PM PDT 24 |
| Finished | Jul 18 08:31:46 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-7d67aa7e-acb2-4cbc-9a76-3d180451b49d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311444154 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_plic_sw_irq.311444154 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4218891908 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 4322155390 ps |
| CPU time | 601.47 seconds |
| Started | Jul 18 08:26:59 PM PDT 24 |
| Finished | Jul 18 08:37:02 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-b4393a9d-cfb0-49bc-9211-105b235148b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218891908 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4218891908 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.1688103486 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 4705355728 ps |
| CPU time | 381.85 seconds |
| Started | Jul 18 08:28:39 PM PDT 24 |
| Finished | Jul 18 08:35:02 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-53f988d2-7380-4c6f-b5c3-c5a49e125bd7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688103486 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.1688103486 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1096586066 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 9547537083 ps |
| CPU time | 1920.29 seconds |
| Started | Jul 18 08:20:53 PM PDT 24 |
| Finished | Jul 18 08:52:54 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-f5f31a9a-7056-4957-8ca6-8234ed8fdf4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096 586066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1096586066 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1351081543 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 29411961480 ps |
| CPU time | 2029.66 seconds |
| Started | Jul 18 08:27:06 PM PDT 24 |
| Finished | Jul 18 09:00:58 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-b1312e50-0451-4839-8da5-c7e68428a6ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135 1081543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1351081543 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4151962526 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 18410497460 ps |
| CPU time | 1780.46 seconds |
| Started | Jul 18 08:20:38 PM PDT 24 |
| Finished | Jul 18 08:50:19 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-8bb93dc4-9b37-413c-84aa-cde72ab24028 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4151962526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4151962526 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.322431773 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 21990693812 ps |
| CPU time | 1609.22 seconds |
| Started | Jul 18 08:29:29 PM PDT 24 |
| Finished | Jul 18 08:56:20 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-a8d62d56-92f3-4402-a4b1-7230eb5ae143 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 322431773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.322431773 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1807829502 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 8279788128 ps |
| CPU time | 893.67 seconds |
| Started | Jul 18 08:23:30 PM PDT 24 |
| Finished | Jul 18 08:38:25 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-3c109f45-918d-4597-acab-38aef10f8659 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807829502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1807829502 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1501005370 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 6111735610 ps |
| CPU time | 423.95 seconds |
| Started | Jul 18 08:19:23 PM PDT 24 |
| Finished | Jul 18 08:26:28 PM PDT 24 |
| Peak memory | 617124 kb |
| Host | smart-f5f407e8-b58e-4b35-962b-81c75dda0859 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1501005370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1501005370 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2577380846 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 6785147040 ps |
| CPU time | 441.28 seconds |
| Started | Jul 18 08:19:15 PM PDT 24 |
| Finished | Jul 18 08:26:37 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-61b44f0a-430d-44d7-a103-59f95ac23b15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577380846 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.2577380846 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3194001023 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3795460946 ps |
| CPU time | 388.55 seconds |
| Started | Jul 18 08:22:28 PM PDT 24 |
| Finished | Jul 18 08:28:58 PM PDT 24 |
| Peak memory | 616092 kb |
| Host | smart-f99a8756-c44c-4964-8e76-4ebd6627217d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3194001023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3194001023 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2448430167 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 13456018406 ps |
| CPU time | 1803.71 seconds |
| Started | Jul 18 08:22:59 PM PDT 24 |
| Finished | Jul 18 08:53:04 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-7e520376-430e-4ebb-b196-830dad1ba32f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448430167 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2448430167 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4191072140 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 7395650020 ps |
| CPU time | 419.45 seconds |
| Started | Jul 18 08:29:57 PM PDT 24 |
| Finished | Jul 18 08:36:59 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-e3821c4c-361a-48a3-88ec-b3202bf09cb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191072140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4191072140 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1514092683 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 7904975484 ps |
| CPU time | 825.34 seconds |
| Started | Jul 18 08:23:25 PM PDT 24 |
| Finished | Jul 18 08:37:12 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-299200fa-88a5-4b0c-aef0-aae49ff7f48c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514092683 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1514092683 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2331098649 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 19738262751 ps |
| CPU time | 2274.83 seconds |
| Started | Jul 18 08:23:31 PM PDT 24 |
| Finished | Jul 18 09:01:27 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-d1a7810c-9bc6-4938-ac2d-d410307ddd0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2331098649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2331098649 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1910837024 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 21156101518 ps |
| CPU time | 1640.03 seconds |
| Started | Jul 18 08:27:42 PM PDT 24 |
| Finished | Jul 18 08:55:04 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-b421808c-2d62-4e3c-9e28-297f5a00e8d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1910837024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1910837024 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4104616934 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 35740512896 ps |
| CPU time | 2995.1 seconds |
| Started | Jul 18 08:19:55 PM PDT 24 |
| Finished | Jul 18 09:09:51 PM PDT 24 |
| Peak memory | 612324 kb |
| Host | smart-74b3f96b-c2ac-4ca5-941d-71a4fe37adca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104616934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4104616934 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2569067794 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 6327688604 ps |
| CPU time | 546.41 seconds |
| Started | Jul 18 08:27:15 PM PDT 24 |
| Finished | Jul 18 08:36:23 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-f33670bb-f6fe-48e0-9f0f-8676ce193040 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2569067794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2569067794 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4110267090 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3499766310 ps |
| CPU time | 265.29 seconds |
| Started | Jul 18 08:19:52 PM PDT 24 |
| Finished | Jul 18 08:24:18 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-20314808-0de8-4e3c-9d66-93aa95aaf24a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110267090 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.4110267090 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.804711899 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 5940516992 ps |
| CPU time | 431.6 seconds |
| Started | Jul 18 08:20:51 PM PDT 24 |
| Finished | Jul 18 08:28:03 PM PDT 24 |
| Peak memory | 617276 kb |
| Host | smart-43479566-a2f9-4489-8fdb-fe4386e6e47b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=804711899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.804711899 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2813096293 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 5417932744 ps |
| CPU time | 489.25 seconds |
| Started | Jul 18 08:26:02 PM PDT 24 |
| Finished | Jul 18 08:34:12 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-ee60e31b-60bd-4cf9-966c-c785f4806682 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28130962 93 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2813096293 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3925861381 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5946580900 ps |
| CPU time | 454.14 seconds |
| Started | Jul 18 08:28:07 PM PDT 24 |
| Finished | Jul 18 08:35:43 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-cfd4819d-f6e1-4868-9690-8004b7746c30 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3925861381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3925861381 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1911496953 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 4908614448 ps |
| CPU time | 344.54 seconds |
| Started | Jul 18 08:34:34 PM PDT 24 |
| Finished | Jul 18 08:40:20 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-7c2e40c4-8655-4552-a9d4-93ef30d3711d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911496953 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1911496953 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3178002859 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 6033068926 ps |
| CPU time | 1176.18 seconds |
| Started | Jul 18 08:28:23 PM PDT 24 |
| Finished | Jul 18 08:48:00 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-ea32ceac-65f6-4ae9-8c45-a1eb223b6825 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178002859 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.3178002859 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.330459217 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 4847725798 ps |
| CPU time | 573.64 seconds |
| Started | Jul 18 08:23:30 PM PDT 24 |
| Finished | Jul 18 08:33:05 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-ebce3e68-84a0-4c1e-b0f1-b73688d1ccdf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330459217 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.330459217 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2883469166 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 5807058696 ps |
| CPU time | 436.11 seconds |
| Started | Jul 18 08:28:48 PM PDT 24 |
| Finished | Jul 18 08:36:06 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-648270d5-2555-4050-9ba8-7fced858507c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883469166 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.2883469166 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.994543779 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5414032200 ps |
| CPU time | 464.42 seconds |
| Started | Jul 18 08:20:44 PM PDT 24 |
| Finished | Jul 18 08:28:30 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-55940217-1faa-4f5a-a535-01168f3a1647 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994 543779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.994543779 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3459674464 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 9453102542 ps |
| CPU time | 481.14 seconds |
| Started | Jul 18 08:25:30 PM PDT 24 |
| Finished | Jul 18 08:33:32 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-6b76ba6f-ad20-4334-942a-a7d776bd6c23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459674464 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3459674464 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.547352010 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 4366088096 ps |
| CPU time | 664.51 seconds |
| Started | Jul 18 08:20:20 PM PDT 24 |
| Finished | Jul 18 08:31:25 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-a4ca7069-a90f-481f-b5d4-674d05d7b719 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547352010 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.547352010 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1445115483 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 4532573992 ps |
| CPU time | 594.55 seconds |
| Started | Jul 18 08:17:26 PM PDT 24 |
| Finished | Jul 18 08:27:21 PM PDT 24 |
| Peak memory | 641580 kb |
| Host | smart-97f38695-2eae-4550-b59b-08b80c7617ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1445115483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1445115483 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2699270845 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3263196006 ps |
| CPU time | 214.15 seconds |
| Started | Jul 18 08:28:56 PM PDT 24 |
| Finished | Jul 18 08:32:31 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-750772fb-f91e-4136-98e7-b422eef0de66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699270845 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2699270845 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2044910838 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4084132212 ps |
| CPU time | 359.63 seconds |
| Started | Jul 18 08:18:39 PM PDT 24 |
| Finished | Jul 18 08:24:40 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-3cd842c0-03ff-48fc-b89c-45a8b1f094b0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044910838 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2044910838 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.306686087 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2509568096 ps |
| CPU time | 206.65 seconds |
| Started | Jul 18 08:18:55 PM PDT 24 |
| Finished | Jul 18 08:22:23 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-acfe5439-64b1-481e-a068-b28d23556083 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306686087 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.306686087 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.735832409 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2773081352 ps |
| CPU time | 331.98 seconds |
| Started | Jul 18 08:27:22 PM PDT 24 |
| Finished | Jul 18 08:32:55 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-5c136ea2-e8e4-4d80-be2f-225dcb5d6026 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=735832409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.735832409 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.511554522 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3138018253 ps |
| CPU time | 274.44 seconds |
| Started | Jul 18 08:28:55 PM PDT 24 |
| Finished | Jul 18 08:33:31 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-9e582bb0-5635-4402-ba3f-5b6194ae856b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511554522 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.511554522 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1899701858 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 5126903858 ps |
| CPU time | 1015.7 seconds |
| Started | Jul 18 08:22:35 PM PDT 24 |
| Finished | Jul 18 08:39:31 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-1a8ac1e2-6ef3-4307-a05b-614c8383c5e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18997 01858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.1899701858 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3945168086 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 5186198206 ps |
| CPU time | 1189.77 seconds |
| Started | Jul 18 08:21:23 PM PDT 24 |
| Finished | Jul 18 08:41:14 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-a5743422-0422-4e0a-b2a9-d69ce94b956d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3945168086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.3945168086 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.687118986 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 5228490510 ps |
| CPU time | 514.41 seconds |
| Started | Jul 18 08:28:25 PM PDT 24 |
| Finished | Jul 18 08:37:00 PM PDT 24 |
| Peak memory | 624152 kb |
| Host | smart-bf3327bf-daa1-4f90-bc74-f9f25ddc3474 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687118986 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.687118986 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.733148549 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5430850284 ps |
| CPU time | 540.76 seconds |
| Started | Jul 18 08:27:30 PM PDT 24 |
| Finished | Jul 18 08:36:31 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-4d230988-5f1f-4d68-9282-7c8ba022b1e4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733148549 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.733148549 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1087120093 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4908595144 ps |
| CPU time | 485.28 seconds |
| Started | Jul 18 08:27:51 PM PDT 24 |
| Finished | Jul 18 08:35:57 PM PDT 24 |
| Peak memory | 620160 kb |
| Host | smart-722ad50f-0352-496c-b0d8-0afff6b359e1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108712 0093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1087120093 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3414313349 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2680596476 ps |
| CPU time | 242.71 seconds |
| Started | Jul 18 08:29:32 PM PDT 24 |
| Finished | Jul 18 08:33:35 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-393832e2-bfb2-4a7f-b094-07f1719676e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414313349 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.3414313349 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.85047690 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 2869807500 ps |
| CPU time | 239.78 seconds |
| Started | Jul 18 08:20:09 PM PDT 24 |
| Finished | Jul 18 08:24:10 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-a3b386c9-7d8a-48f8-989d-ae3369199824 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85047690 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_timer_irq.85047690 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2967900848 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3549548748 ps |
| CPU time | 247.81 seconds |
| Started | Jul 18 08:29:37 PM PDT 24 |
| Finished | Jul 18 08:33:46 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-e9be99e8-8e44-435f-b827-e742acc19947 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967900848 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2967900848 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1708141059 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 5842154528 ps |
| CPU time | 884.96 seconds |
| Started | Jul 18 08:26:26 PM PDT 24 |
| Finished | Jul 18 08:41:12 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-c145101c-b44b-48fa-8735-802a74349fe7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17081410 59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1708141059 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2150056802 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2664438627 ps |
| CPU time | 287.46 seconds |
| Started | Jul 18 08:25:47 PM PDT 24 |
| Finished | Jul 18 08:30:35 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-aeedca31-e4b5-4e61-befc-26bc74109d98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150056 802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.2150056802 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3348949104 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3632969440 ps |
| CPU time | 320.56 seconds |
| Started | Jul 18 08:26:57 PM PDT 24 |
| Finished | Jul 18 08:32:19 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-99e0c230-28d3-4f21-b311-aecc1cde6a55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348949104 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3348949104 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2420487107 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 9603266890 ps |
| CPU time | 1340.74 seconds |
| Started | Jul 18 08:16:51 PM PDT 24 |
| Finished | Jul 18 08:39:13 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-4f21b46c-3b55-4bf6-9a42-1c96dacf3e72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420487107 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2420487107 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3346488267 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 8422539100 ps |
| CPU time | 932.12 seconds |
| Started | Jul 18 08:25:46 PM PDT 24 |
| Finished | Jul 18 08:41:18 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-541310df-b916-4eb1-96a2-4d4332fdb658 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346488267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3346488267 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1566847423 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 8120781916 ps |
| CPU time | 871.25 seconds |
| Started | Jul 18 08:26:12 PM PDT 24 |
| Finished | Jul 18 08:40:44 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-819098f5-9d33-4408-93ee-7c3abe841914 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566847423 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1566847423 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.780210942 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6770895736 ps |
| CPU time | 729.09 seconds |
| Started | Jul 18 08:17:55 PM PDT 24 |
| Finished | Jul 18 08:30:05 PM PDT 24 |
| Peak memory | 624896 kb |
| Host | smart-3bc121e9-ae74-4460-9152-f1bcd86bb2b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780210942 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.780210942 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1248981117 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 4505488786 ps |
| CPU time | 666.42 seconds |
| Started | Jul 18 08:22:03 PM PDT 24 |
| Finished | Jul 18 08:33:10 PM PDT 24 |
| Peak memory | 624868 kb |
| Host | smart-5a7ee210-d079-4edc-bcd0-f36a5f69f761 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248981117 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1248981117 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1558781401 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3020444444 ps |
| CPU time | 286.69 seconds |
| Started | Jul 18 08:18:23 PM PDT 24 |
| Finished | Jul 18 08:23:10 PM PDT 24 |
| Peak memory | 618544 kb |
| Host | smart-c5f8780c-f722-4515-8b55-a4d592d4f08c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558781401 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1558781401 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2442415719 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 2541020678 ps |
| CPU time | 249.55 seconds |
| Started | Jul 18 08:19:01 PM PDT 24 |
| Finished | Jul 18 08:23:12 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-e06a4ee0-f0c5-4913-bb93-3ca0d0925124 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442415719 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2442415719 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.1676932485 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 9190891711 ps |
| CPU time | 894.31 seconds |
| Started | Jul 18 08:25:22 PM PDT 24 |
| Finished | Jul 18 08:40:18 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-7487298f-73fb-4966-8627-19c7622ec65b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676932485 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.1676932485 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2195737378 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3681038032 ps |
| CPU time | 461.91 seconds |
| Started | Jul 18 08:25:31 PM PDT 24 |
| Finished | Jul 18 08:33:14 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-bdf119b9-5359-4936-bd22-244291e768e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195737378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2195737378 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1857582918 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4588455582 ps |
| CPU time | 628.91 seconds |
| Started | Jul 18 08:25:13 PM PDT 24 |
| Finished | Jul 18 08:35:44 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-8dc8c4bf-34b0-4d13-afa4-85d7481b554c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857582918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1857582918 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.708906735 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5403541488 ps |
| CPU time | 703.42 seconds |
| Started | Jul 18 08:27:09 PM PDT 24 |
| Finished | Jul 18 08:38:54 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-53501771-39a0-490a-bdd4-8693cdec9daa |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708906735 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.708906735 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4280086475 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2179978440 ps |
| CPU time | 281.58 seconds |
| Started | Jul 18 08:30:03 PM PDT 24 |
| Finished | Jul 18 08:34:46 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-e9c72a38-c1eb-41ab-bbbc-191c98ea761e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280086475 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.4280086475 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.413713299 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4766256888 ps |
| CPU time | 582.47 seconds |
| Started | Jul 18 08:19:31 PM PDT 24 |
| Finished | Jul 18 08:29:16 PM PDT 24 |
| Peak memory | 613584 kb |
| Host | smart-beeec5e0-537d-48cc-b825-1cbbd6316c39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413713299 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.413713299 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.336095073 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 3149936177 ps |
| CPU time | 296.07 seconds |
| Started | Jul 18 08:20:30 PM PDT 24 |
| Finished | Jul 18 08:25:28 PM PDT 24 |
| Peak memory | 613332 kb |
| Host | smart-f9516567-4a6d-4579-ad98-c7c15a922446 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336095073 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.336095073 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.311513395 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3381857160 ps |
| CPU time | 421.55 seconds |
| Started | Jul 18 08:20:59 PM PDT 24 |
| Finished | Jul 18 08:28:01 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-15df1979-051d-4319-9ded-926ca8fabadc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311513395 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.311513395 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3304424566 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 23125161470 ps |
| CPU time | 1503.22 seconds |
| Started | Jul 18 08:19:54 PM PDT 24 |
| Finished | Jul 18 08:44:58 PM PDT 24 |
| Peak memory | 614632 kb |
| Host | smart-bd794ff0-7b7a-4e12-a732-ec901313ba56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33044245 66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3304424566 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2175716992 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 5464759054 ps |
| CPU time | 476.61 seconds |
| Started | Jul 18 08:21:56 PM PDT 24 |
| Finished | Jul 18 08:29:54 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-01963536-d53e-425d-a67a-1d8ee38fb289 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175716992 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2175716992 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.859629583 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 3190147360 ps |
| CPU time | 213.34 seconds |
| Started | Jul 18 08:29:49 PM PDT 24 |
| Finished | Jul 18 08:33:24 PM PDT 24 |
| Peak memory | 615824 kb |
| Host | smart-efc573ec-ecd7-4e18-9a30-e1b8470e6165 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859629583 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.859629583 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.196202532 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 4825966568 ps |
| CPU time | 733.87 seconds |
| Started | Jul 18 08:18:54 PM PDT 24 |
| Finished | Jul 18 08:31:09 PM PDT 24 |
| Peak memory | 624072 kb |
| Host | smart-c8678acd-6abc-423c-8fb3-807f9a78c0d3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196202532 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.196202532 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2948170434 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 8034027642 ps |
| CPU time | 1370.3 seconds |
| Started | Jul 18 08:19:44 PM PDT 24 |
| Finished | Jul 18 08:42:36 PM PDT 24 |
| Peak memory | 624720 kb |
| Host | smart-502cd392-81bf-4eca-be67-f2468424fa03 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948170434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2948170434 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2245603964 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 4544203031 ps |
| CPU time | 586.31 seconds |
| Started | Jul 18 08:21:12 PM PDT 24 |
| Finished | Jul 18 08:31:00 PM PDT 24 |
| Peak memory | 622228 kb |
| Host | smart-6c02c588-882b-4c02-a5df-91b9e5383db2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245603964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2245603964 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4249078907 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 78426789622 ps |
| CPU time | 12908.6 seconds |
| Started | Jul 18 08:19:10 PM PDT 24 |
| Finished | Jul 18 11:54:20 PM PDT 24 |
| Peak memory | 634088 kb |
| Host | smart-43916a0e-2bb8-4f07-a200-256c4b5d6adc |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4249078907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.4249078907 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.723908717 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 3837609632 ps |
| CPU time | 595.85 seconds |
| Started | Jul 18 08:19:19 PM PDT 24 |
| Finished | Jul 18 08:29:16 PM PDT 24 |
| Peak memory | 623776 kb |
| Host | smart-2cafd163-36b4-481b-858a-c40a7184444d |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723908717 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.723908717 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.971108829 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3669688410 ps |
| CPU time | 706.25 seconds |
| Started | Jul 18 08:25:54 PM PDT 24 |
| Finished | Jul 18 08:37:41 PM PDT 24 |
| Peak memory | 623816 kb |
| Host | smart-7e2873d8-7521-4839-a84b-5a1d46240dad |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971108829 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.971108829 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2132890867 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 4638133928 ps |
| CPU time | 615.48 seconds |
| Started | Jul 18 08:18:56 PM PDT 24 |
| Finished | Jul 18 08:29:12 PM PDT 24 |
| Peak memory | 624064 kb |
| Host | smart-dd4ed9b3-4b27-437b-b0d6-dd1fe8a9ff43 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132890867 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2132890867 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1631564151 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 2629183396 ps |
| CPU time | 206.4 seconds |
| Started | Jul 18 08:26:15 PM PDT 24 |
| Finished | Jul 18 08:29:42 PM PDT 24 |
| Peak memory | 621564 kb |
| Host | smart-d8332b3e-4fa4-47d4-a066-beb70be894e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1631564151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1631564151 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.1361240219 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 12841604914 ps |
| CPU time | 1373.86 seconds |
| Started | Jul 18 08:26:28 PM PDT 24 |
| Finished | Jul 18 08:49:22 PM PDT 24 |
| Peak memory | 620920 kb |
| Host | smart-1f2fd953-dcdb-424a-a7f1-2c93c2642d8a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361240219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.1361240219 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2258505091 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 5094861792 ps |
| CPU time | 479.7 seconds |
| Started | Jul 18 08:27:11 PM PDT 24 |
| Finished | Jul 18 08:35:13 PM PDT 24 |
| Peak memory | 620968 kb |
| Host | smart-114d061f-b9e7-4636-886c-4fb5a2d5e81b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2258505091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2258505091 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1870377071 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 15442003250 ps |
| CPU time | 4811.2 seconds |
| Started | Jul 18 08:34:13 PM PDT 24 |
| Finished | Jul 18 09:54:25 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-3baeba0d-d346-4b53-ab9d-33d8d557f878 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870377071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1870377071 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1887144685 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 14890213372 ps |
| CPU time | 3978.17 seconds |
| Started | Jul 18 08:33:42 PM PDT 24 |
| Finished | Jul 18 09:40:02 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-afc3bad6-4704-4638-b54e-3ab52bc0957a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887144685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1887144685 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2716447665 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 15848133093 ps |
| CPU time | 3742.7 seconds |
| Started | Jul 18 08:31:54 PM PDT 24 |
| Finished | Jul 18 09:34:19 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-b5bd9bd6-5f14-48d1-845c-b876357c8a07 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716447665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.2716447665 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2745153189 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 14635425750 ps |
| CPU time | 3853.47 seconds |
| Started | Jul 18 08:34:15 PM PDT 24 |
| Finished | Jul 18 09:38:30 PM PDT 24 |
| Peak memory | 611352 kb |
| Host | smart-27cd7ddc-9376-4870-ad79-dfbe2100c2ee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745153189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2745153189 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.559923219 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 11603784360 ps |
| CPU time | 3288.26 seconds |
| Started | Jul 18 08:33:49 PM PDT 24 |
| Finished | Jul 18 09:28:40 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-54a573eb-4146-4943-91e0-eef58087ed36 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559923219 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.559923219 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1571716979 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 14766328290 ps |
| CPU time | 3316.39 seconds |
| Started | Jul 18 08:33:47 PM PDT 24 |
| Finished | Jul 18 09:29:04 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-97babe38-3928-42f3-9dee-7b674a562d4a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571716979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1571716979 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.343942160 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 15164305160 ps |
| CPU time | 3347.11 seconds |
| Started | Jul 18 08:32:48 PM PDT 24 |
| Finished | Jul 18 09:28:36 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-31b26caf-7e5d-4eb4-946c-4cee28c8973e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343942160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.343942160 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4167006027 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 14872841216 ps |
| CPU time | 3375.02 seconds |
| Started | Jul 18 08:32:53 PM PDT 24 |
| Finished | Jul 18 09:29:09 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-d2b88560-8344-4295-89cf-433c9b081675 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167006027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.4167006027 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.4182976474 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 26075714952 ps |
| CPU time | 5245.55 seconds |
| Started | Jul 18 08:41:46 PM PDT 24 |
| Finished | Jul 18 10:09:13 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-abdf0bf7-790a-492c-bd0d-d7771e80aba7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182976474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.4182976474 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2925755168 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 14772863108 ps |
| CPU time | 3848.15 seconds |
| Started | Jul 18 08:33:22 PM PDT 24 |
| Finished | Jul 18 09:37:31 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-a60b498c-f2ee-4831-897b-a1cd34ddd393 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925755168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2925755168 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.2198110187 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 25127308188 ps |
| CPU time | 3648.66 seconds |
| Started | Jul 18 08:33:02 PM PDT 24 |
| Finished | Jul 18 09:33:52 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-1a632236-1283-4f5e-9127-3d5b811cc2b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198110187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.2198110187 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.2067982743 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 14949023888 ps |
| CPU time | 4083.78 seconds |
| Started | Jul 18 08:34:08 PM PDT 24 |
| Finished | Jul 18 09:42:13 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-6904ab55-7da0-47c5-9256-1d926f0d61bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2067982743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.2067982743 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3281339381 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 17484483000 ps |
| CPU time | 3955.54 seconds |
| Started | Jul 18 08:32:02 PM PDT 24 |
| Finished | Jul 18 09:37:58 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-782850c5-fb99-43c2-ba56-d1fe55d87c63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281339381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3281339381 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.1695998641 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 4956290980 ps |
| CPU time | 719.99 seconds |
| Started | Jul 18 08:29:44 PM PDT 24 |
| Finished | Jul 18 08:41:45 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-27b32997-e745-4418-8dd4-20e1ae18ae52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695998641 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1695998641 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.2708965098 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 6058335440 ps |
| CPU time | 282 seconds |
| Started | Jul 18 08:30:09 PM PDT 24 |
| Finished | Jul 18 08:34:52 PM PDT 24 |
| Peak memory | 623904 kb |
| Host | smart-d8f95da2-0f0c-4e41-aa61-dacc66a738d1 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2708965098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2708965098 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.680899601 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 2876607947 ps |
| CPU time | 104.53 seconds |
| Started | Jul 18 08:29:49 PM PDT 24 |
| Finished | Jul 18 08:31:34 PM PDT 24 |
| Peak memory | 617708 kb |
| Host | smart-6442435b-7956-4453-81cd-df7087f1fb8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680899601 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.680899601 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3596923620 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 5518084589 ps |
| CPU time | 360.7 seconds |
| Started | Jul 18 08:44:09 PM PDT 24 |
| Finished | Jul 18 08:50:11 PM PDT 24 |
| Peak memory | 622020 kb |
| Host | smart-794d5406-cc45-4ab8-b865-510dae00f4f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596923620 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3596923620 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1102122599 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 8155202402 ps |
| CPU time | 1239.07 seconds |
| Started | Jul 18 08:43:58 PM PDT 24 |
| Finished | Jul 18 09:04:38 PM PDT 24 |
| Peak memory | 618784 kb |
| Host | smart-3800837a-973a-4ee5-ac16-35ec002b2617 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1102122599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.1102122599 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3070373236 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 10110607104 ps |
| CPU time | 993.09 seconds |
| Started | Jul 18 08:42:58 PM PDT 24 |
| Finished | Jul 18 08:59:33 PM PDT 24 |
| Peak memory | 624036 kb |
| Host | smart-5c4b6d37-d5c6-4b1d-90d1-1a5cd00bc66f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070373236 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.3070373236 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1911404542 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3990434228 ps |
| CPU time | 638.61 seconds |
| Started | Jul 18 08:44:13 PM PDT 24 |
| Finished | Jul 18 08:54:53 PM PDT 24 |
| Peak memory | 617812 kb |
| Host | smart-a8ca86f2-74fd-4311-a9fe-bbb44491eb63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1911404542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1911404542 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169962860 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 3734346200 ps |
| CPU time | 429.32 seconds |
| Started | Jul 18 08:43:06 PM PDT 24 |
| Finished | Jul 18 08:50:16 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-dad636da-72e7-49aa-8a82-b0eefc2d9284 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169962860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1169962860 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2715965839 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 9976400256 ps |
| CPU time | 1051.1 seconds |
| Started | Jul 18 08:46:48 PM PDT 24 |
| Finished | Jul 18 09:04:22 PM PDT 24 |
| Peak memory | 624040 kb |
| Host | smart-0ab8b9f2-5d09-43fb-8ba7-ae6d68d834ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715965839 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2715965839 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3147816890 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8208034052 ps |
| CPU time | 1535.92 seconds |
| Started | Jul 18 08:43:12 PM PDT 24 |
| Finished | Jul 18 09:08:49 PM PDT 24 |
| Peak memory | 618756 kb |
| Host | smart-b42310b4-d4b4-46e7-ae80-f8e911c77a93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3147816890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.3147816890 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.508818152 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 5657277276 ps |
| CPU time | 466.01 seconds |
| Started | Jul 18 08:45:27 PM PDT 24 |
| Finished | Jul 18 08:53:14 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-b0488712-f9e2-438e-bffd-b10718991e46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 508818152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.508818152 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.11425425 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 7657439236 ps |
| CPU time | 441.86 seconds |
| Started | Jul 18 08:45:14 PM PDT 24 |
| Finished | Jul 18 08:52:37 PM PDT 24 |
| Peak memory | 621332 kb |
| Host | smart-aefaf076-c771-4160-b50f-eac5a0549228 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11425425 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.11425425 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2410371921 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 8272601100 ps |
| CPU time | 1378.94 seconds |
| Started | Jul 18 08:43:05 PM PDT 24 |
| Finished | Jul 18 09:06:05 PM PDT 24 |
| Peak memory | 618928 kb |
| Host | smart-50291240-6116-4f19-9a32-1b39374314ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2410371921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.2410371921 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2109509084 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 6930149105 ps |
| CPU time | 506.16 seconds |
| Started | Jul 18 08:44:43 PM PDT 24 |
| Finished | Jul 18 08:53:10 PM PDT 24 |
| Peak memory | 624788 kb |
| Host | smart-2446f554-8f0d-4d60-9ed3-0a6d03594088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109509084 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2109509084 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.755599665 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 8100151450 ps |
| CPU time | 1527.16 seconds |
| Started | Jul 18 08:44:53 PM PDT 24 |
| Finished | Jul 18 09:10:22 PM PDT 24 |
| Peak memory | 618852 kb |
| Host | smart-6d4e8d2b-5910-4d80-98f9-28828cf2543a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=755599665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.755599665 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4088083387 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3712111932 ps |
| CPU time | 419.6 seconds |
| Started | Jul 18 08:43:51 PM PDT 24 |
| Finished | Jul 18 08:50:53 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-16ee6193-b8dc-45e7-bcd2-5248343278a5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088083387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4088083387 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3062014347 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 12620734176 ps |
| CPU time | 2364.78 seconds |
| Started | Jul 18 08:43:07 PM PDT 24 |
| Finished | Jul 18 09:22:34 PM PDT 24 |
| Peak memory | 618852 kb |
| Host | smart-ed5e30c8-ec90-4ec1-a7d9-5cd20e2b8865 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3062014347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.3062014347 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1687778714 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 7938663368 ps |
| CPU time | 1429.93 seconds |
| Started | Jul 18 08:43:37 PM PDT 24 |
| Finished | Jul 18 09:07:28 PM PDT 24 |
| Peak memory | 618844 kb |
| Host | smart-2b4eb2f0-1cbe-47b6-8021-627c849f295d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1687778714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1687778714 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1334877800 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3945846480 ps |
| CPU time | 532.24 seconds |
| Started | Jul 18 08:45:49 PM PDT 24 |
| Finished | Jul 18 08:54:42 PM PDT 24 |
| Peak memory | 618592 kb |
| Host | smart-49fa096f-210f-4b1e-882f-782437df881b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1334877800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1334877800 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3689481261 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 8242135786 ps |
| CPU time | 1510.17 seconds |
| Started | Jul 18 08:44:02 PM PDT 24 |
| Finished | Jul 18 09:09:14 PM PDT 24 |
| Peak memory | 618552 kb |
| Host | smart-c0aa49c9-bedc-4138-9357-8cb6575658aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3689481261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3689481261 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.239215091 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3073919608 ps |
| CPU time | 367.56 seconds |
| Started | Jul 18 08:53:12 PM PDT 24 |
| Finished | Jul 18 08:59:21 PM PDT 24 |
| Peak memory | 648820 kb |
| Host | smart-dab93898-6fea-4ed8-8ea8-0ce007c16989 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239215091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_s w_alert_handler_lpg_sleep_mode_alerts.239215091 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.914541608 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 12858597428 ps |
| CPU time | 2046.61 seconds |
| Started | Jul 18 08:52:01 PM PDT 24 |
| Finished | Jul 18 09:26:11 PM PDT 24 |
| Peak memory | 618784 kb |
| Host | smart-93812be1-3e59-43ae-8aa4-54d0bc7105b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=914541608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.914541608 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2125435692 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 11670677160 ps |
| CPU time | 1472.93 seconds |
| Started | Jul 18 08:29:08 PM PDT 24 |
| Finished | Jul 18 08:53:43 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-920ad32b-8a23-4b4f-90c1-9e75ea75f618 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125435692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2125435692 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.4014892190 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 13550583820 ps |
| CPU time | 1485.4 seconds |
| Started | Jul 18 08:29:02 PM PDT 24 |
| Finished | Jul 18 08:53:48 PM PDT 24 |
| Peak memory | 607780 kb |
| Host | smart-3f0cbb5e-537e-47ea-846b-47b4b9a8aa43 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014892190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.4 014892190 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3260169977 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 4960785278 ps |
| CPU time | 511.15 seconds |
| Started | Jul 18 08:39:09 PM PDT 24 |
| Finished | Jul 18 08:47:41 PM PDT 24 |
| Peak memory | 619600 kb |
| Host | smart-43bd53d9-a7b9-48b6-87f8-589bbbe26c03 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 260169977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3260169977 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.2614164579 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3129441382 ps |
| CPU time | 328.33 seconds |
| Started | Jul 18 08:33:23 PM PDT 24 |
| Finished | Jul 18 08:38:52 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-a35bfacd-12e8-408d-8810-d619a43d12bd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2614164579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2614164579 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3505156015 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 18487702166 ps |
| CPU time | 670.81 seconds |
| Started | Jul 18 08:34:27 PM PDT 24 |
| Finished | Jul 18 08:45:39 PM PDT 24 |
| Peak memory | 618896 kb |
| Host | smart-4f30ce8a-a522-45b1-98b5-0eadd6dc1891 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3505156015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3505156015 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.605519702 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 3147000600 ps |
| CPU time | 379.27 seconds |
| Started | Jul 18 08:33:31 PM PDT 24 |
| Finished | Jul 18 08:39:51 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-5524fefb-40d3-4a54-9c90-323e40ca67ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605519702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.605519702 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2255809763 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 2819280881 ps |
| CPU time | 202.53 seconds |
| Started | Jul 18 08:33:18 PM PDT 24 |
| Finished | Jul 18 08:36:42 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-c08e164d-2368-4786-bb20-b27cdf19d628 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255 809763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2255809763 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1298031802 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 3160857583 ps |
| CPU time | 291.15 seconds |
| Started | Jul 18 08:38:12 PM PDT 24 |
| Finished | Jul 18 08:43:05 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-8aca4e86-7eb1-435e-b657-eb3bd5017adb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298031802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.1298031802 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.2628547340 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 2613906856 ps |
| CPU time | 276.01 seconds |
| Started | Jul 18 08:37:36 PM PDT 24 |
| Finished | Jul 18 08:42:14 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-4b316ec0-cb19-46a0-99f6-f511889b9a75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628547340 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.2628547340 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2351049028 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2746671242 ps |
| CPU time | 272.69 seconds |
| Started | Jul 18 08:40:26 PM PDT 24 |
| Finished | Jul 18 08:45:01 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-2d925ea3-0ee3-4317-bd25-424852657669 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351049028 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2351049028 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3769177613 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 2885754539 ps |
| CPU time | 240.75 seconds |
| Started | Jul 18 08:40:22 PM PDT 24 |
| Finished | Jul 18 08:44:24 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-0b38ca3b-6e27-4f66-9627-d485ccf41231 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769177613 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3769177613 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1442149911 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3097763170 ps |
| CPU time | 250.51 seconds |
| Started | Jul 18 08:40:24 PM PDT 24 |
| Finished | Jul 18 08:44:35 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-7c713a2f-bffe-4cfd-9c17-97662e5d3b61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442149911 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1442149911 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.2119519439 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3153981673 ps |
| CPU time | 341.41 seconds |
| Started | Jul 18 08:36:49 PM PDT 24 |
| Finished | Jul 18 08:42:33 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-fa613fe0-585d-48dd-acd1-4a9d18b3a155 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2119519439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.2119519439 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2466390824 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 4553332696 ps |
| CPU time | 520.82 seconds |
| Started | Jul 18 08:41:39 PM PDT 24 |
| Finished | Jul 18 08:50:21 PM PDT 24 |
| Peak memory | 619428 kb |
| Host | smart-516239a1-21c6-4f91-9a0e-8132ea57de03 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2466390824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2466390824 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2496611407 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 7396000976 ps |
| CPU time | 1774.09 seconds |
| Started | Jul 18 08:35:17 PM PDT 24 |
| Finished | Jul 18 09:04:52 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-44892fca-0c17-47db-afb7-e99a9da23c61 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2496611407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.2496611407 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3941318467 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 6523534760 ps |
| CPU time | 1440.1 seconds |
| Started | Jul 18 08:34:30 PM PDT 24 |
| Finished | Jul 18 08:58:30 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-a0ff657e-342e-4d8b-96be-38ea3f9d2402 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941318467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.3941318467 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1006981052 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 7483540776 ps |
| CPU time | 1421.8 seconds |
| Started | Jul 18 08:41:25 PM PDT 24 |
| Finished | Jul 18 09:05:08 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-2a713097-d457-4380-8e5e-e1dcf10b29d4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1006981052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1006981052 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.198440145 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 5557274336 ps |
| CPU time | 504.31 seconds |
| Started | Jul 18 08:34:04 PM PDT 24 |
| Finished | Jul 18 08:42:29 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-32ca84eb-d1c8-4901-95c9-56df4c28e894 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=198440145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.198440145 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3572427001 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 255211063064 ps |
| CPU time | 12177.6 seconds |
| Started | Jul 18 08:42:07 PM PDT 24 |
| Finished | Jul 19 12:05:06 AM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-1ae8a94b-447a-4573-b2be-7fab50a9bead |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3572427001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3572427001 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1886752522 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 3895501794 ps |
| CPU time | 418.1 seconds |
| Started | Jul 18 08:33:06 PM PDT 24 |
| Finished | Jul 18 08:40:05 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-b8df57ce-9f47-4c56-b684-20ee4d1f29e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886752522 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1886752522 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3907981526 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 7463672500 ps |
| CPU time | 488.91 seconds |
| Started | Jul 18 08:33:36 PM PDT 24 |
| Finished | Jul 18 08:41:47 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-93b8d7e0-ebfb-4df7-a4b7-a29c223e0e3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3907981526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3907981526 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2232379771 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3559844668 ps |
| CPU time | 381.23 seconds |
| Started | Jul 18 08:41:31 PM PDT 24 |
| Finished | Jul 18 08:47:53 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-194f9e65-e6c0-42e9-9fa3-66cc722a9873 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232379771 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2232379771 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3603522877 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 7412151400 ps |
| CPU time | 957.98 seconds |
| Started | Jul 18 08:32:59 PM PDT 24 |
| Finished | Jul 18 08:48:58 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-2345f9cc-35b9-483d-b63b-c0f6f9a04912 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3603522877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3603522877 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1199382710 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 6370438784 ps |
| CPU time | 730.39 seconds |
| Started | Jul 18 08:40:52 PM PDT 24 |
| Finished | Jul 18 08:53:04 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-85168756-d81c-4200-91a0-7b74dbb9c72e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1199382710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1199382710 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3486111255 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 6755029100 ps |
| CPU time | 1005.12 seconds |
| Started | Jul 18 08:36:39 PM PDT 24 |
| Finished | Jul 18 08:53:25 PM PDT 24 |
| Peak memory | 617188 kb |
| Host | smart-b9858fcb-4eeb-445b-8c43-e31bf7493390 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486111255 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3486111255 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3832428996 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 21633627052 ps |
| CPU time | 2627.3 seconds |
| Started | Jul 18 08:42:33 PM PDT 24 |
| Finished | Jul 18 09:26:22 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-98a476c3-01d5-4f4f-b479-a47508b32872 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832428996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3832428996 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2172396771 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 6682968470 ps |
| CPU time | 571.09 seconds |
| Started | Jul 18 08:35:31 PM PDT 24 |
| Finished | Jul 18 08:45:03 PM PDT 24 |
| Peak memory | 622344 kb |
| Host | smart-59be2b4a-fddd-4429-8835-90ed642f1e2f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2172396771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.2172396771 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3852450224 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3573632792 ps |
| CPU time | 656.9 seconds |
| Started | Jul 18 08:36:01 PM PDT 24 |
| Finished | Jul 18 08:46:59 PM PDT 24 |
| Peak memory | 612764 kb |
| Host | smart-acde95a0-a0cf-45b4-bedb-8371dcc88f39 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852450224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3852450224 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.24614555 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4453335564 ps |
| CPU time | 659.9 seconds |
| Started | Jul 18 08:42:44 PM PDT 24 |
| Finished | Jul 18 08:53:45 PM PDT 24 |
| Peak memory | 614056 kb |
| Host | smart-26a91c94-33a0-48aa-82dc-a4f65a1d9296 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clk mgr_external_clk_src_for_sw_fast_rma.24614555 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1629555875 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 4487690930 ps |
| CPU time | 597.85 seconds |
| Started | Jul 18 08:35:55 PM PDT 24 |
| Finished | Jul 18 08:45:53 PM PDT 24 |
| Peak memory | 612900 kb |
| Host | smart-3ca33efa-c025-4fb3-8921-e26c0c4aee61 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629555875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1629555875 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2676249271 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4499842000 ps |
| CPU time | 633.75 seconds |
| Started | Jul 18 08:38:14 PM PDT 24 |
| Finished | Jul 18 08:48:49 PM PDT 24 |
| Peak memory | 614072 kb |
| Host | smart-8a3b9b60-aad1-4f47-85a1-119ae19a0390 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676249271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2676249271 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1818595828 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 5197786576 ps |
| CPU time | 607.59 seconds |
| Started | Jul 18 08:38:16 PM PDT 24 |
| Finished | Jul 18 08:48:25 PM PDT 24 |
| Peak memory | 611948 kb |
| Host | smart-36baee3d-fd3f-479f-9485-b41dcdb69d62 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818595828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.1818595828 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1493289939 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 4204737360 ps |
| CPU time | 565.85 seconds |
| Started | Jul 18 08:38:38 PM PDT 24 |
| Finished | Jul 18 08:48:05 PM PDT 24 |
| Peak memory | 612920 kb |
| Host | smart-8ff83b1a-6c6b-4e3f-980c-75cd91c6ed41 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493289939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1493289939 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2640412933 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2477398479 ps |
| CPU time | 198.53 seconds |
| Started | Jul 18 08:39:18 PM PDT 24 |
| Finished | Jul 18 08:42:38 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-99e2371e-3525-4f02-81a0-c2dffcff325c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640412933 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2640412933 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.931104714 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 3450671768 ps |
| CPU time | 542.63 seconds |
| Started | Jul 18 08:36:20 PM PDT 24 |
| Finished | Jul 18 08:45:23 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-90b1e0dc-b6b3-4c1a-be1b-d7d10b87fa0c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931104714 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.931104714 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2527163608 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 2585682945 ps |
| CPU time | 184.45 seconds |
| Started | Jul 18 08:38:44 PM PDT 24 |
| Finished | Jul 18 08:41:50 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-0ff7832f-916c-46b4-b4f3-0d8e8da2b609 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527163608 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2527163608 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3637750437 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4720373736 ps |
| CPU time | 555.36 seconds |
| Started | Jul 18 08:38:48 PM PDT 24 |
| Finished | Jul 18 08:48:04 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-5d9a6ee7-b1c8-46e6-8c72-b24d972f95c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637750437 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3637750437 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1819126498 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 5776253640 ps |
| CPU time | 616.8 seconds |
| Started | Jul 18 08:42:53 PM PDT 24 |
| Finished | Jul 18 08:53:11 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-6641b047-70ff-4d45-9cc7-80d3b02778da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819126498 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1819126498 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2680767369 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 4939478880 ps |
| CPU time | 512.42 seconds |
| Started | Jul 18 08:42:26 PM PDT 24 |
| Finished | Jul 18 08:51:00 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-da6eabd7-691d-4e57-a8dd-8d8566c3b329 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680767369 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2680767369 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2461968039 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 3493275810 ps |
| CPU time | 407.05 seconds |
| Started | Jul 18 08:35:34 PM PDT 24 |
| Finished | Jul 18 08:42:23 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-0c6b25b4-7428-4664-9a98-1cbd8f8378fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461968039 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.2461968039 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.201813090 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 10915562662 ps |
| CPU time | 1128.69 seconds |
| Started | Jul 18 08:42:40 PM PDT 24 |
| Finished | Jul 18 09:01:30 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-05f2e3bf-7349-4cf0-b125-6d735c7cdfe4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201813090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.201813090 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2313169676 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 2971116076 ps |
| CPU time | 401.15 seconds |
| Started | Jul 18 08:35:31 PM PDT 24 |
| Finished | Jul 18 08:42:13 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-bc30401f-d6ff-492e-8a52-f72d6f5e56fb |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313169676 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2313169676 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2741853373 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 4749486488 ps |
| CPU time | 559.73 seconds |
| Started | Jul 18 08:36:07 PM PDT 24 |
| Finished | Jul 18 08:45:28 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-999d722f-be82-411a-87ea-6911ee95800a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741853373 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2741853373 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2385791532 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 3611732912 ps |
| CPU time | 307.59 seconds |
| Started | Jul 18 08:39:31 PM PDT 24 |
| Finished | Jul 18 08:44:40 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-16c97ff7-4120-476f-80ee-4248f5c59df8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385791532 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2385791532 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.849753940 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 8864835536 ps |
| CPU time | 1938.1 seconds |
| Started | Jul 18 08:35:25 PM PDT 24 |
| Finished | Jul 18 09:07:45 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-8ff0deca-134e-4fe5-ad27-48354fca4eed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849753940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.849753940 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1971746956 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4149039592 ps |
| CPU time | 391.12 seconds |
| Started | Jul 18 08:34:40 PM PDT 24 |
| Finished | Jul 18 08:41:12 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-85acbafd-a785-4eaa-90a8-f3aa1b47e260 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19717 46956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1971746956 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.266833072 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3285968090 ps |
| CPU time | 301.37 seconds |
| Started | Jul 18 08:35:09 PM PDT 24 |
| Finished | Jul 18 08:40:12 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-565a7565-f630-4afb-9d3d-905f7210c836 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266833072 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.266833072 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2786354276 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 3114610818 ps |
| CPU time | 298.96 seconds |
| Started | Jul 18 08:39:55 PM PDT 24 |
| Finished | Jul 18 08:44:54 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-ef571da1-2121-432d-9277-3333db24b509 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786354276 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2786354276 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.156898154 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4929471870 ps |
| CPU time | 702.32 seconds |
| Started | Jul 18 08:29:27 PM PDT 24 |
| Finished | Jul 18 08:41:11 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-1718c074-794d-40b5-9174-d12858e1d682 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=156898154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.156898154 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.942835682 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4999919384 ps |
| CPU time | 1009.77 seconds |
| Started | Jul 18 08:34:42 PM PDT 24 |
| Finished | Jul 18 08:51:32 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-0bcaf4fd-727a-4721-a770-f3d95fa5f02b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942835682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_a uto_mode.942835682 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.149721348 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3019806380 ps |
| CPU time | 569.36 seconds |
| Started | Jul 18 08:35:10 PM PDT 24 |
| Finished | Jul 18 08:44:41 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-4e2ae011-cbee-474f-ad62-6356544a36aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149721348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.149721348 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.924653647 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 7146277120 ps |
| CPU time | 1175.18 seconds |
| Started | Jul 18 08:36:58 PM PDT 24 |
| Finished | Jul 18 08:56:34 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-52cc599e-0778-40c9-ac45-5973e4cd37ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=924653647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.924653647 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3516409884 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 3436619840 ps |
| CPU time | 687.8 seconds |
| Started | Jul 18 08:34:23 PM PDT 24 |
| Finished | Jul 18 08:45:51 PM PDT 24 |
| Peak memory | 616360 kb |
| Host | smart-4efff77c-f891-41d1-880f-42e34d83fd8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516409884 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3516409884 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.3341300180 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 10055903600 ps |
| CPU time | 2155.96 seconds |
| Started | Jul 18 08:34:32 PM PDT 24 |
| Finished | Jul 18 09:10:29 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-785e2b2b-c7b5-4305-b52c-37394c10e96e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341300180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3341300180 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1911364982 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 2668205240 ps |
| CPU time | 289.25 seconds |
| Started | Jul 18 08:34:16 PM PDT 24 |
| Finished | Jul 18 08:39:06 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-723854e3-ae8d-47d3-842b-29b5edcd9724 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19 11364982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1911364982 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2669779027 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 6596449044 ps |
| CPU time | 1280.25 seconds |
| Started | Jul 18 08:35:35 PM PDT 24 |
| Finished | Jul 18 08:56:56 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-cafd9ce5-c34e-4d2e-b6f4-f20f4e5be8c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2669779027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2669779027 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2362038799 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2182436248 ps |
| CPU time | 289.06 seconds |
| Started | Jul 18 08:34:48 PM PDT 24 |
| Finished | Jul 18 08:39:39 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-aa1d59cf-3a06-47da-9046-a9ae9007734e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362038799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.2362038799 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.4071813228 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2686297096 ps |
| CPU time | 497.22 seconds |
| Started | Jul 18 08:38:56 PM PDT 24 |
| Finished | Jul 18 08:47:14 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-115e74f5-1640-453a-8573-5fe90b6eeecf |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4071813228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.4071813228 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.1960493980 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3403362480 ps |
| CPU time | 320.95 seconds |
| Started | Jul 18 08:31:32 PM PDT 24 |
| Finished | Jul 18 08:36:54 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-eb77af75-01f6-4fe2-83fe-fb867b1fadea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960493980 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1960493980 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3619790978 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2217835892 ps |
| CPU time | 220.72 seconds |
| Started | Jul 18 08:29:50 PM PDT 24 |
| Finished | Jul 18 08:33:32 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-134fd7ff-cbf7-4548-9918-1104ecd63cc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619790978 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3619790978 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.3597179285 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 2979196760 ps |
| CPU time | 286.52 seconds |
| Started | Jul 18 08:31:14 PM PDT 24 |
| Finished | Jul 18 08:36:01 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-4bcfaaaf-eacc-4a74-9ad3-80ccf84b4eb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597179285 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.3597179285 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.1857374731 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 2540176072 ps |
| CPU time | 143.52 seconds |
| Started | Jul 18 08:28:55 PM PDT 24 |
| Finished | Jul 18 08:31:19 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-5b29dddf-1d40-4d47-901b-c4abc5a94164 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857374731 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.1857374731 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1359030432 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 60189808452 ps |
| CPU time | 11413.9 seconds |
| Started | Jul 18 08:31:17 PM PDT 24 |
| Finished | Jul 18 11:41:33 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-360f684b-bf37-48ee-8ac2-57f7b516eb63 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1359030432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.1359030432 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.3189804031 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 4878811790 ps |
| CPU time | 784.75 seconds |
| Started | Jul 18 08:39:38 PM PDT 24 |
| Finished | Jul 18 08:52:44 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-46b3c0e4-12f8-4cd5-a1bc-0610fbfbe978 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3189804031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.3189804031 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1647805885 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 6045903432 ps |
| CPU time | 1050.24 seconds |
| Started | Jul 18 08:31:52 PM PDT 24 |
| Finished | Jul 18 08:49:25 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-83ab7980-e953-41f8-8491-714b4f17368b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647805885 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.1647805885 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2196440916 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 6309751725 ps |
| CPU time | 1048.93 seconds |
| Started | Jul 18 08:36:39 PM PDT 24 |
| Finished | Jul 18 08:54:09 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-acc0cd83-6f78-45b0-9c9c-dcf318bf6acd |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196440916 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2196440916 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2317684585 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 6775399028 ps |
| CPU time | 1218.13 seconds |
| Started | Jul 18 08:39:03 PM PDT 24 |
| Finished | Jul 18 08:59:22 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-f57d52e9-95ad-4372-9a81-ba69aa1f7532 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317684585 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2317684585 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2239872085 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 5395198328 ps |
| CPU time | 1089.39 seconds |
| Started | Jul 18 08:30:58 PM PDT 24 |
| Finished | Jul 18 08:49:08 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-8ceb6f9a-cd0f-489b-8b10-27ee0651125f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239872085 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2239872085 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2355430623 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3880255730 ps |
| CPU time | 397.13 seconds |
| Started | Jul 18 08:32:12 PM PDT 24 |
| Finished | Jul 18 08:38:50 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-2f62a819-292b-446f-b35c-452f37cd52b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355430623 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2355430623 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1171703800 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 5772359270 ps |
| CPU time | 1107.96 seconds |
| Started | Jul 18 08:38:30 PM PDT 24 |
| Finished | Jul 18 08:57:00 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-239788d4-a123-4f01-b1f7-0dc4b3bba2cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171703800 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.1171703800 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2261785457 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4096162760 ps |
| CPU time | 695.53 seconds |
| Started | Jul 18 08:31:28 PM PDT 24 |
| Finished | Jul 18 08:43:04 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-e780870d-0234-4a34-ab39-4bc76ebab60a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261785457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2261785457 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.938697486 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 4283913413 ps |
| CPU time | 621.86 seconds |
| Started | Jul 18 08:32:20 PM PDT 24 |
| Finished | Jul 18 08:42:43 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-5cffa323-ede2-4e32-9f90-6abfae11f7e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=938697486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.938697486 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.452846632 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4311515003 ps |
| CPU time | 575.45 seconds |
| Started | Jul 18 08:39:33 PM PDT 24 |
| Finished | Jul 18 08:49:09 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-5e4fd29b-a043-446e-bb7a-001882f64afa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=452846632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.452846632 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1663718019 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 3093247516 ps |
| CPU time | 438.71 seconds |
| Started | Jul 18 08:39:33 PM PDT 24 |
| Finished | Jul 18 08:46:53 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-60f7cf26-436b-4754-a225-95f2be850187 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663718 019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1663718019 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.655430663 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 16919636110 ps |
| CPU time | 1520.21 seconds |
| Started | Jul 18 08:29:31 PM PDT 24 |
| Finished | Jul 18 08:54:53 PM PDT 24 |
| Peak memory | 611812 kb |
| Host | smart-f82167ad-8155-4263-9f9a-7e3e9883de0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655430663 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.655430663 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.308300457 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 26992569518 ps |
| CPU time | 1899.54 seconds |
| Started | Jul 18 08:37:37 PM PDT 24 |
| Finished | Jul 18 09:09:18 PM PDT 24 |
| Peak memory | 616344 kb |
| Host | smart-f8fc2828-5e99-4972-996c-886ce2cab2c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=308300457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.308300457 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1276109391 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2228357128 ps |
| CPU time | 182.96 seconds |
| Started | Jul 18 08:45:47 PM PDT 24 |
| Finished | Jul 18 08:48:52 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-a4787b1b-3e42-4e48-b703-7cb9f1a4dca6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1276109391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1276109391 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3967765744 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 4870285317 ps |
| CPU time | 503.22 seconds |
| Started | Jul 18 08:30:23 PM PDT 24 |
| Finished | Jul 18 08:38:48 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-21495601-a2c9-4c7a-8ff0-be11cfd0f16f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967765744 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3967765744 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.3793209943 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2530580071 ps |
| CPU time | 237.55 seconds |
| Started | Jul 18 08:40:25 PM PDT 24 |
| Finished | Jul 18 08:44:23 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-0928f90e-a59e-42ca-8cbd-d2fb42478667 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793209943 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3793209943 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.445586069 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2579938040 ps |
| CPU time | 276.46 seconds |
| Started | Jul 18 08:36:18 PM PDT 24 |
| Finished | Jul 18 08:40:55 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-4cda04ad-dcdc-476e-a604-03c73b42d035 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445586069 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.445586069 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3561574534 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3049157822 ps |
| CPU time | 289.8 seconds |
| Started | Jul 18 08:35:19 PM PDT 24 |
| Finished | Jul 18 08:40:10 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-55b5e25f-5b83-4406-9c87-5f4a46fb3899 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561574534 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.3561574534 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.169901831 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 2623967763 ps |
| CPU time | 258.77 seconds |
| Started | Jul 18 08:36:21 PM PDT 24 |
| Finished | Jul 18 08:40:40 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-512685a9-a99f-4ba5-9054-d4e89158f086 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169901831 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.169901831 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.476469590 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3208679106 ps |
| CPU time | 271.18 seconds |
| Started | Jul 18 08:40:09 PM PDT 24 |
| Finished | Jul 18 08:44:41 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-e6860411-550f-4833-b499-a184e7902840 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476469590 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.476469590 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.449606437 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 8486027770 ps |
| CPU time | 1618.8 seconds |
| Started | Jul 18 08:34:28 PM PDT 24 |
| Finished | Jul 18 09:01:28 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-1c5eff70-b3d2-4661-bf7e-1d06b9a1c309 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449606437 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.449606437 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2457594964 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2291088168 ps |
| CPU time | 332.69 seconds |
| Started | Jul 18 08:35:10 PM PDT 24 |
| Finished | Jul 18 08:40:44 PM PDT 24 |
| Peak memory | 609228 kb |
| Host | smart-e7c25642-23b6-4a18-83e8-2f5faf1495f2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457594964 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2457594964 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.4079501568 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2479456888 ps |
| CPU time | 335.39 seconds |
| Started | Jul 18 08:40:21 PM PDT 24 |
| Finished | Jul 18 08:45:57 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-9a92f69f-46a6-45ab-8779-e8c4f5d79fda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079501568 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.4079501568 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3902812677 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 3822537340 ps |
| CPU time | 637.87 seconds |
| Started | Jul 18 08:32:24 PM PDT 24 |
| Finished | Jul 18 08:43:04 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-29d24b0a-adb6-4533-be6b-d5976371724b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902812677 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.3902812677 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.8605870 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4800767006 ps |
| CPU time | 1035.17 seconds |
| Started | Jul 18 08:31:01 PM PDT 24 |
| Finished | Jul 18 08:48:18 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-d74adf7d-a808-4c37-957e-d6cb5af388ab |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8605870 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.8605870 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2239127690 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4607081692 ps |
| CPU time | 778.52 seconds |
| Started | Jul 18 08:29:55 PM PDT 24 |
| Finished | Jul 18 08:42:55 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-ab6ac441-d9c8-4377-980d-d25a14b6acd8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239127690 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2239127690 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.678235421 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4960342200 ps |
| CPU time | 894.91 seconds |
| Started | Jul 18 08:31:56 PM PDT 24 |
| Finished | Jul 18 08:46:52 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-376d8d97-bf04-4bd5-a328-982ec3038efd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678235421 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.678235421 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.4080600308 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 65146468221 ps |
| CPU time | 11543 seconds |
| Started | Jul 18 08:31:27 PM PDT 24 |
| Finished | Jul 18 11:43:53 PM PDT 24 |
| Peak memory | 624808 kb |
| Host | smart-1228d468-5bcd-4fda-ace6-c143348f5a91 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4080600308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.4080600308 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1561112865 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 7450169600 ps |
| CPU time | 1084.84 seconds |
| Started | Jul 18 08:36:19 PM PDT 24 |
| Finished | Jul 18 08:54:25 PM PDT 24 |
| Peak memory | 617696 kb |
| Host | smart-f2e11599-9f03-4b13-9c19-00a19fcfc3b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561 112865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1561112865 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3196625940 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 10827723993 ps |
| CPU time | 2034.51 seconds |
| Started | Jul 18 08:34:31 PM PDT 24 |
| Finished | Jul 18 09:08:26 PM PDT 24 |
| Peak memory | 616636 kb |
| Host | smart-9fdc5fed-c57f-474d-bd6c-0750e11b6387 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3196625940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.3196625940 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1263286955 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 7356563145 ps |
| CPU time | 1149.61 seconds |
| Started | Jul 18 08:38:22 PM PDT 24 |
| Finished | Jul 18 08:57:34 PM PDT 24 |
| Peak memory | 616712 kb |
| Host | smart-6a85778e-a04b-4eed-9392-bd0711240b35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1263286955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1263286955 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2150571398 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 8762225700 ps |
| CPU time | 1572.9 seconds |
| Started | Jul 18 08:37:14 PM PDT 24 |
| Finished | Jul 18 09:03:28 PM PDT 24 |
| Peak memory | 617704 kb |
| Host | smart-149eadc5-e225-4939-9d31-69aa79219adb |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2150571398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.2150571398 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3981269021 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 9292102948 ps |
| CPU time | 1460.17 seconds |
| Started | Jul 18 08:36:19 PM PDT 24 |
| Finished | Jul 18 09:00:40 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-49bb6408-cad3-4b37-9bc2-e178035513e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398126 9021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.3981269021 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.747948670 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 7630098104 ps |
| CPU time | 1165.9 seconds |
| Started | Jul 18 08:36:55 PM PDT 24 |
| Finished | Jul 18 08:56:22 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-2464bbf0-f3dc-4ac1-8fae-cb163e30dfda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74794 8670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.747948670 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1484250717 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 14232938850 ps |
| CPU time | 2889.27 seconds |
| Started | Jul 18 08:35:23 PM PDT 24 |
| Finished | Jul 18 09:23:34 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-07a48a8d-eee3-41b1-87eb-126d265eda1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842 50717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1484250717 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.3247905903 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2652473346 ps |
| CPU time | 201.33 seconds |
| Started | Jul 18 08:35:38 PM PDT 24 |
| Finished | Jul 18 08:38:59 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-97beda8f-2c65-47e3-b040-8b2711277a29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247905903 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.3247905903 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.4118543392 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 3220135988 ps |
| CPU time | 247.58 seconds |
| Started | Jul 18 08:36:10 PM PDT 24 |
| Finished | Jul 18 08:40:19 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-5d15567b-de96-4fe2-85ce-0562dc95c77f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118543392 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.4118543392 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1147976085 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 2657103064 ps |
| CPU time | 212.2 seconds |
| Started | Jul 18 08:35:27 PM PDT 24 |
| Finished | Jul 18 08:39:01 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-eb4729e1-a491-41a9-b573-dfedbe9a6167 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147976085 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.1147976085 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3645849057 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 3089556456 ps |
| CPU time | 343.03 seconds |
| Started | Jul 18 08:34:13 PM PDT 24 |
| Finished | Jul 18 08:39:56 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-787803ee-8293-446f-98e3-96e4d7191230 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645849057 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3645849057 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1998640171 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 2367870103 ps |
| CPU time | 269.55 seconds |
| Started | Jul 18 08:34:56 PM PDT 24 |
| Finished | Jul 18 08:39:27 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-430c2f06-9edd-472e-9ac5-8d25004896e6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998640171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1998640171 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3079974995 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2954169346 ps |
| CPU time | 302.55 seconds |
| Started | Jul 18 08:38:45 PM PDT 24 |
| Finished | Jul 18 08:43:49 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-cfe5170d-d5c4-4194-ac3a-45dd0fe56549 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30799749 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3079974995 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2951664390 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2505172120 ps |
| CPU time | 249.4 seconds |
| Started | Jul 18 08:41:32 PM PDT 24 |
| Finished | Jul 18 08:45:43 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-dd2d5a43-7126-4c46-8a68-22bbf781c18f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951664390 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2951664390 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1172581590 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3275163336 ps |
| CPU time | 321.21 seconds |
| Started | Jul 18 08:31:35 PM PDT 24 |
| Finished | Jul 18 08:36:57 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-fedecd5b-069a-4eb7-8588-9e124027da84 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172581590 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.1172581590 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4115270925 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5363848156 ps |
| CPU time | 549.96 seconds |
| Started | Jul 18 08:37:09 PM PDT 24 |
| Finished | Jul 18 08:46:20 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-6b2544a5-7a7e-4f19-8b71-076b97b83121 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4115270925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.4115270925 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.100537118 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3342282946 ps |
| CPU time | 350.27 seconds |
| Started | Jul 18 08:32:04 PM PDT 24 |
| Finished | Jul 18 08:37:54 PM PDT 24 |
| Peak memory | 621580 kb |
| Host | smart-194ca139-00c2-4add-beeb-dc739eb579b0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053711 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.100537118 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2843395063 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 6514458467 ps |
| CPU time | 388.59 seconds |
| Started | Jul 18 08:32:10 PM PDT 24 |
| Finished | Jul 18 08:38:40 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-206a11ed-f631-43fd-9a40-5e5b708c706f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843395063 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.2843395063 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2209328031 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2362921593 ps |
| CPU time | 110.14 seconds |
| Started | Jul 18 08:31:45 PM PDT 24 |
| Finished | Jul 18 08:33:36 PM PDT 24 |
| Peak memory | 616796 kb |
| Host | smart-91c78ace-fd28-4a36-97c9-e0962a86eaab |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2209328031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2209328031 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1817647671 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2307782250 ps |
| CPU time | 116.25 seconds |
| Started | Jul 18 08:31:31 PM PDT 24 |
| Finished | Jul 18 08:33:28 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-6aa8a5fc-cd4d-4f00-9867-294738c2c66d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817647671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1817647671 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.471646715 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 48401005348 ps |
| CPU time | 5225.61 seconds |
| Started | Jul 18 08:30:48 PM PDT 24 |
| Finished | Jul 18 09:57:55 PM PDT 24 |
| Peak memory | 620540 kb |
| Host | smart-3cbfa858-cfd1-44c9-9921-bc6f87786943 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471646715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.471646715 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1719804256 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 51845331959 ps |
| CPU time | 5796.14 seconds |
| Started | Jul 18 08:32:54 PM PDT 24 |
| Finished | Jul 18 10:09:32 PM PDT 24 |
| Peak memory | 620256 kb |
| Host | smart-dac19a0b-27bd-49ae-a0d4-c1fe53dac157 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719804256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1719804256 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1355139278 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 11514367110 ps |
| CPU time | 1176.18 seconds |
| Started | Jul 18 08:31:59 PM PDT 24 |
| Finished | Jul 18 08:51:36 PM PDT 24 |
| Peak memory | 620016 kb |
| Host | smart-c0a27579-2692-4f97-b3ee-7761c17293a6 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355139278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1355139278 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1104673909 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 48512554519 ps |
| CPU time | 6065.82 seconds |
| Started | Jul 18 08:31:46 PM PDT 24 |
| Finished | Jul 18 10:12:53 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-53542229-42f9-4dd2-ab28-5e847680589a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104673909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1104673909 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3370311369 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 32564963068 ps |
| CPU time | 2114.29 seconds |
| Started | Jul 18 08:33:00 PM PDT 24 |
| Finished | Jul 18 09:08:15 PM PDT 24 |
| Peak memory | 620424 kb |
| Host | smart-4678703d-fe23-41a8-b2ee-55375d3d7dfe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3370311369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3370311369 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1457628165 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 17092007240 ps |
| CPU time | 3235.87 seconds |
| Started | Jul 18 08:34:33 PM PDT 24 |
| Finished | Jul 18 09:28:30 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-6cdbae2b-62af-469e-a82f-ab73500cb201 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1457628165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.1457628165 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2515324473 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 18117578826 ps |
| CPU time | 3253.03 seconds |
| Started | Jul 18 08:33:29 PM PDT 24 |
| Finished | Jul 18 09:27:43 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-c257f964-2e7e-4570-a5ed-e2f5f5c71576 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2515324473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2515324473 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.439644913 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 24755625011 ps |
| CPU time | 3803.23 seconds |
| Started | Jul 18 08:38:16 PM PDT 24 |
| Finished | Jul 18 09:41:41 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-30172d6b-cd16-4b04-a17c-0474e2d1f5ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439644913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.439644913 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1658112036 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3155972400 ps |
| CPU time | 554.05 seconds |
| Started | Jul 18 08:32:42 PM PDT 24 |
| Finished | Jul 18 08:41:57 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-a20e5ccc-16bc-4227-af5b-203b788bf249 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658112036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1658112036 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.3501159127 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 6124726580 ps |
| CPU time | 817.35 seconds |
| Started | Jul 18 08:41:15 PM PDT 24 |
| Finished | Jul 18 08:54:54 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-5cf829b5-81a0-452c-821c-c055815a5463 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3501159127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3501159127 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.1388087909 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 8555415472 ps |
| CPU time | 1473.14 seconds |
| Started | Jul 18 08:39:49 PM PDT 24 |
| Finished | Jul 18 09:04:24 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-a87fcff9-9934-493b-b5a9-7ad2dc95f85b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388087909 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.1388087909 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.603964320 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 2764761313 ps |
| CPU time | 269.94 seconds |
| Started | Jul 18 08:31:42 PM PDT 24 |
| Finished | Jul 18 08:36:13 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-e5a8da10-98d9-4345-96c0-5cabf8a2401d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603964320 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.603964320 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1634720748 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 9129027040 ps |
| CPU time | 1484.93 seconds |
| Started | Jul 18 08:31:54 PM PDT 24 |
| Finished | Jul 18 08:56:40 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-1cbb07a6-ab85-4379-8584-2fc24a9d2564 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1634720748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1634720748 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.198902770 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 8394302992 ps |
| CPU time | 1166.67 seconds |
| Started | Jul 18 08:32:12 PM PDT 24 |
| Finished | Jul 18 08:51:39 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-97110970-3ab8-478e-a0d9-0bd9ed70a18c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=198902770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.198902770 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1360585756 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 8808126616 ps |
| CPU time | 1355.5 seconds |
| Started | Jul 18 08:31:50 PM PDT 24 |
| Finished | Jul 18 08:54:28 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-6d96504d-28eb-40e3-816a-1744179cefc6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1360585756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1360585756 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3194829302 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 4420561346 ps |
| CPU time | 641.79 seconds |
| Started | Jul 18 08:31:19 PM PDT 24 |
| Finished | Jul 18 08:42:01 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-d79c2d0f-9e36-4c7c-a360-eea14828adcd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3194829302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3194829302 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2443453125 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 2933652576 ps |
| CPU time | 207.86 seconds |
| Started | Jul 18 08:39:50 PM PDT 24 |
| Finished | Jul 18 08:43:19 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-3d6ba88b-ead2-4232-8b77-dbb004f44201 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443453125 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.2443453125 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.3258061966 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 3041986080 ps |
| CPU time | 256.79 seconds |
| Started | Jul 18 08:30:31 PM PDT 24 |
| Finished | Jul 18 08:34:49 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-4708b2f0-527e-40b1-94f0-96b3548ee8cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258061966 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.3258061966 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.31112137 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3473188432 ps |
| CPU time | 382.96 seconds |
| Started | Jul 18 08:36:44 PM PDT 24 |
| Finished | Jul 18 08:43:08 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-01da621f-44f6-4eb6-8c8b-164f28b548f9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112137 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_plic_sw_irq.31112137 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1896658734 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 4827345654 ps |
| CPU time | 718.92 seconds |
| Started | Jul 18 08:38:55 PM PDT 24 |
| Finished | Jul 18 08:50:55 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-938e49b3-e5d8-4179-acc3-5807ad67a856 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896658734 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1896658734 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.1678083596 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4914490004 ps |
| CPU time | 356.92 seconds |
| Started | Jul 18 08:39:29 PM PDT 24 |
| Finished | Jul 18 08:45:27 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-d966f375-e7cd-4b3b-9454-6e8ff7e43c3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678083596 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1678083596 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1072230007 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 10139858387 ps |
| CPU time | 1725.76 seconds |
| Started | Jul 18 08:32:41 PM PDT 24 |
| Finished | Jul 18 09:01:28 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-62a05f7b-ebb3-4998-9fea-55c8c67457f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072 230007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.1072230007 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.6191616 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 22160702366 ps |
| CPU time | 1862.98 seconds |
| Started | Jul 18 08:35:31 PM PDT 24 |
| Finished | Jul 18 09:06:34 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-315ff4ba-86dd-4059-8594-ae0c6ad90ea4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619 1616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.6191616 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.647491319 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 14521501030 ps |
| CPU time | 1605.72 seconds |
| Started | Jul 18 08:35:32 PM PDT 24 |
| Finished | Jul 18 09:02:19 PM PDT 24 |
| Peak memory | 611264 kb |
| Host | smart-317462db-28fb-411c-bbea-940f7716e2ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=647491319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.647491319 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3002268322 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 26483929924 ps |
| CPU time | 2001.86 seconds |
| Started | Jul 18 08:37:48 PM PDT 24 |
| Finished | Jul 18 09:11:11 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-5ade3362-1d0e-4e02-8870-dfd39fd3d0f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3002268322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3002268322 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.649240765 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 7419650200 ps |
| CPU time | 748.56 seconds |
| Started | Jul 18 08:31:22 PM PDT 24 |
| Finished | Jul 18 08:43:51 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-7b25dc40-f533-4458-ac2b-6e18c957901a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649240765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.649240765 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4090854736 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 7393269294 ps |
| CPU time | 389.76 seconds |
| Started | Jul 18 08:38:01 PM PDT 24 |
| Finished | Jul 18 08:44:32 PM PDT 24 |
| Peak memory | 616420 kb |
| Host | smart-d2cd5359-c341-4d05-a3ba-95658a3d967b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4090854736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4090854736 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.4192310690 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 9395028230 ps |
| CPU time | 578.09 seconds |
| Started | Jul 18 08:34:51 PM PDT 24 |
| Finished | Jul 18 08:44:30 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-b8b05f5d-829e-49f2-957a-9fc53e54184e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192310690 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.4192310690 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.477775403 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4139922910 ps |
| CPU time | 377.63 seconds |
| Started | Jul 18 08:31:59 PM PDT 24 |
| Finished | Jul 18 08:38:17 PM PDT 24 |
| Peak memory | 613064 kb |
| Host | smart-07ca1b22-0cdb-4fa0-80c9-55aeb42a20f9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=477775403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.477775403 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1350340863 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 9811796850 ps |
| CPU time | 1165.73 seconds |
| Started | Jul 18 08:32:23 PM PDT 24 |
| Finished | Jul 18 08:51:50 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-ec37711f-fb9c-40c5-ab44-f3e8dfb68a86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350340863 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1350340863 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3164148107 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 6879588960 ps |
| CPU time | 402.82 seconds |
| Started | Jul 18 08:36:10 PM PDT 24 |
| Finished | Jul 18 08:42:54 PM PDT 24 |
| Peak memory | 610456 kb |
| Host | smart-07308b2e-1211-4162-9ea4-d258213c3223 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164148107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3164148107 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3143907062 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 5115808048 ps |
| CPU time | 388.14 seconds |
| Started | Jul 18 08:32:31 PM PDT 24 |
| Finished | Jul 18 08:39:00 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-f1553391-9db6-4c3f-81d0-696352d5e887 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143907062 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.3143907062 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1876804070 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 28590464821 ps |
| CPU time | 2758.24 seconds |
| Started | Jul 18 08:32:34 PM PDT 24 |
| Finished | Jul 18 09:18:33 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-dfb901e2-a366-4ed0-8fbc-665afef99976 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1876804070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1876804070 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3099869422 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 19966255848 ps |
| CPU time | 1397.91 seconds |
| Started | Jul 18 08:37:13 PM PDT 24 |
| Finished | Jul 18 09:00:31 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-0b025887-bf3d-46ad-b596-65ae765d4c7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3099869422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3099869422 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.915985305 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 29683968615 ps |
| CPU time | 3756.51 seconds |
| Started | Jul 18 08:32:47 PM PDT 24 |
| Finished | Jul 18 09:35:25 PM PDT 24 |
| Peak memory | 612560 kb |
| Host | smart-3d6fa043-edcf-4473-9b82-00c94f379b33 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915985305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.915985305 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3373594301 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6685362968 ps |
| CPU time | 627.98 seconds |
| Started | Jul 18 08:37:47 PM PDT 24 |
| Finished | Jul 18 08:48:16 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-bcb1e913-32ec-4754-b2ca-cf098d6f8f90 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3373594301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3373594301 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1188619789 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3409398100 ps |
| CPU time | 319.85 seconds |
| Started | Jul 18 08:33:11 PM PDT 24 |
| Finished | Jul 18 08:38:32 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-b91d6bd1-b15b-4e5c-beca-a78cf8829810 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188619789 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.1188619789 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1321423402 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4746989782 ps |
| CPU time | 543.26 seconds |
| Started | Jul 18 08:33:21 PM PDT 24 |
| Finished | Jul 18 08:42:25 PM PDT 24 |
| Peak memory | 616528 kb |
| Host | smart-e1b48b63-7406-47ea-9065-6f1643ae32d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1321423402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.1321423402 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1523399355 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 5183378690 ps |
| CPU time | 402.71 seconds |
| Started | Jul 18 08:35:11 PM PDT 24 |
| Finished | Jul 18 08:41:54 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-f1d6ed95-8969-4542-892e-d3af596dd3b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15233993 55 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1523399355 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3846493603 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 6622559272 ps |
| CPU time | 488.67 seconds |
| Started | Jul 18 08:39:47 PM PDT 24 |
| Finished | Jul 18 08:47:56 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-11aae52f-e890-4ee8-bda6-a163803df4ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3846493603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3846493603 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4059361756 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 6428333042 ps |
| CPU time | 499.49 seconds |
| Started | Jul 18 08:40:23 PM PDT 24 |
| Finished | Jul 18 08:48:43 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-7f829cf9-a29f-4592-aa62-3bc11510b874 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059361756 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.4059361756 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2921360674 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 6080456760 ps |
| CPU time | 1012.49 seconds |
| Started | Jul 18 08:32:53 PM PDT 24 |
| Finished | Jul 18 08:49:46 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-dc5f79ef-c6bd-4854-a747-5fab22ea13ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921360674 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.2921360674 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2361733572 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4007374766 ps |
| CPU time | 540.5 seconds |
| Started | Jul 18 08:33:04 PM PDT 24 |
| Finished | Jul 18 08:42:05 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-2b38cc1d-b3de-46b3-ac49-f84c9821ee77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361733572 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2361733572 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2222548453 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 6519067110 ps |
| CPU time | 577.03 seconds |
| Started | Jul 18 08:39:21 PM PDT 24 |
| Finished | Jul 18 08:48:59 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-d62c1e1e-66f4-48ca-9735-1a4363f643c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222548453 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2222548453 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1347142454 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 3788053700 ps |
| CPU time | 478.11 seconds |
| Started | Jul 18 08:32:53 PM PDT 24 |
| Finished | Jul 18 08:40:53 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-03668243-78fd-4e43-9cdc-39967b7cd893 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134 7142454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.1347142454 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2003859603 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9591685309 ps |
| CPU time | 665.3 seconds |
| Started | Jul 18 08:41:18 PM PDT 24 |
| Finished | Jul 18 08:52:25 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-dcf17c81-ddad-4e66-aafc-f9a45b1abbc0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003859603 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2003859603 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.292605146 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 13658245408 ps |
| CPU time | 2094.15 seconds |
| Started | Jul 18 08:32:44 PM PDT 24 |
| Finished | Jul 18 09:07:39 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-7dbc0009-6e17-489f-99f6-c536717ea823 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=292605146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.292605146 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1575711130 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5383595520 ps |
| CPU time | 684.37 seconds |
| Started | Jul 18 08:32:45 PM PDT 24 |
| Finished | Jul 18 08:44:10 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-720054e7-356a-4aec-a8df-999c3f741407 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575711130 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.1575711130 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1603853408 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 5319843144 ps |
| CPU time | 842.56 seconds |
| Started | Jul 18 08:29:30 PM PDT 24 |
| Finished | Jul 18 08:43:34 PM PDT 24 |
| Peak memory | 641596 kb |
| Host | smart-9840c04e-cca7-423c-8d3f-1877abcd0c45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1603853408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.1603853408 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1372135960 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 3359809576 ps |
| CPU time | 212.42 seconds |
| Started | Jul 18 08:39:09 PM PDT 24 |
| Finished | Jul 18 08:42:42 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-43f85e45-3ff8-4437-bdb3-3760205038dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372135960 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1372135960 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1526678811 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 4369339892 ps |
| CPU time | 448.59 seconds |
| Started | Jul 18 08:32:45 PM PDT 24 |
| Finished | Jul 18 08:40:15 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-6b5cb222-da2b-4d29-97ed-1998b61e5f75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526678811 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1526678811 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2147822286 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3014995888 ps |
| CPU time | 281.61 seconds |
| Started | Jul 18 08:32:20 PM PDT 24 |
| Finished | Jul 18 08:37:03 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-b99fa4ab-fd91-464f-9b00-ece15b10347f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147822286 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.2147822286 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2086694991 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 2510435587 ps |
| CPU time | 296.19 seconds |
| Started | Jul 18 08:38:25 PM PDT 24 |
| Finished | Jul 18 08:43:23 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-6123689c-51ce-4c6a-b2fb-38dc972625ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086694991 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.2086694991 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2758857481 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2036738450 ps |
| CPU time | 127.13 seconds |
| Started | Jul 18 08:38:36 PM PDT 24 |
| Finished | Jul 18 08:40:44 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-03db3d1f-b6ca-4a4c-b018-dfc947d4a470 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758857481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2758857481 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1936450407 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4869577196 ps |
| CPU time | 965.63 seconds |
| Started | Jul 18 08:34:31 PM PDT 24 |
| Finished | Jul 18 08:50:37 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-8c9938a6-1b44-4621-b94b-35327e3a17d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19364 50407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1936450407 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.501860272 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 5871212924 ps |
| CPU time | 728.41 seconds |
| Started | Jul 18 08:41:10 PM PDT 24 |
| Finished | Jul 18 08:53:21 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-c4b6fbf2-5818-4e8c-a418-e7fbe07c6339 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=501860272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.501860272 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4137420123 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 5488333252 ps |
| CPU time | 568.97 seconds |
| Started | Jul 18 08:37:34 PM PDT 24 |
| Finished | Jul 18 08:47:03 PM PDT 24 |
| Peak memory | 623756 kb |
| Host | smart-7310c0c5-f1f5-4bfe-9b6e-ccfee5b1c669 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137420123 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.4137420123 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3613287432 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 5498900384 ps |
| CPU time | 396.64 seconds |
| Started | Jul 18 08:38:35 PM PDT 24 |
| Finished | Jul 18 08:45:12 PM PDT 24 |
| Peak memory | 619936 kb |
| Host | smart-5995d2d9-1791-4f74-a853-e315fbb792d1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613287432 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.3613287432 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3892654452 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 4060274088 ps |
| CPU time | 563.32 seconds |
| Started | Jul 18 08:39:29 PM PDT 24 |
| Finished | Jul 18 08:48:53 PM PDT 24 |
| Peak memory | 619180 kb |
| Host | smart-30eeae90-dffa-436d-9e78-664fcefe8367 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389265 4452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3892654452 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1404272378 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 3001019112 ps |
| CPU time | 307.81 seconds |
| Started | Jul 18 08:43:00 PM PDT 24 |
| Finished | Jul 18 08:48:09 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-7065c697-56c7-4f3e-aa44-0147145f89f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404272378 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_plic_smoketest.1404272378 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1459748081 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2931282346 ps |
| CPU time | 254.27 seconds |
| Started | Jul 18 08:32:51 PM PDT 24 |
| Finished | Jul 18 08:37:07 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-0c6b6686-2f7f-4c48-8237-bedb5e62df15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459748081 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1459748081 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2572733821 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2957303362 ps |
| CPU time | 299.06 seconds |
| Started | Jul 18 08:40:31 PM PDT 24 |
| Finished | Jul 18 08:45:31 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-5d04913e-528c-4bbf-ae3b-81a96d1a852b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572733821 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2572733821 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1554995140 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 3036783501 ps |
| CPU time | 254 seconds |
| Started | Jul 18 08:34:53 PM PDT 24 |
| Finished | Jul 18 08:39:08 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-4ae2cb45-fd71-47e5-a3cb-4c9ed0e555e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554995 140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1554995140 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1735685716 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3927535908 ps |
| CPU time | 402.48 seconds |
| Started | Jul 18 08:31:52 PM PDT 24 |
| Finished | Jul 18 08:38:36 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-8d910326-9ff2-4000-8f4f-862defeab8e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735685716 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.1735685716 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.528646843 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3034740520 ps |
| CPU time | 263.9 seconds |
| Started | Jul 18 08:29:49 PM PDT 24 |
| Finished | Jul 18 08:34:15 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-0a667a90-7d3c-442e-ba20-ebce81443689 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528646843 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.528646843 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1959143069 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 9464230794 ps |
| CPU time | 1208.09 seconds |
| Started | Jul 18 08:31:13 PM PDT 24 |
| Finished | Jul 18 08:51:22 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-85d8bd7c-d3f3-4eed-bb2e-9be1bd33a656 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959143069 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1959143069 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.463271068 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 7239784544 ps |
| CPU time | 552 seconds |
| Started | Jul 18 08:38:38 PM PDT 24 |
| Finished | Jul 18 08:47:51 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-15e52d33-06c2-4a07-9455-dfb001a856f3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463271068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.463271068 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.230954583 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 6654472702 ps |
| CPU time | 612.53 seconds |
| Started | Jul 18 08:41:38 PM PDT 24 |
| Finished | Jul 18 08:51:52 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-c2abd0f8-c01c-4624-be18-4e84dc9ff175 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230954583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.230954583 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3098607053 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5374013701 ps |
| CPU time | 674.09 seconds |
| Started | Jul 18 08:31:51 PM PDT 24 |
| Finished | Jul 18 08:43:07 PM PDT 24 |
| Peak memory | 624860 kb |
| Host | smart-593ed7d1-7f9a-4db7-aa6f-5be0c8138183 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098607053 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.3098607053 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.1563224406 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3512715266 ps |
| CPU time | 362.91 seconds |
| Started | Jul 18 08:31:20 PM PDT 24 |
| Finished | Jul 18 08:37:24 PM PDT 24 |
| Peak memory | 619284 kb |
| Host | smart-af24ac2c-b3b6-49b6-8220-2f27bfb1f49d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563224406 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.1563224406 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.986610336 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2995623232 ps |
| CPU time | 410.77 seconds |
| Started | Jul 18 08:30:12 PM PDT 24 |
| Finished | Jul 18 08:37:04 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-bd96b960-76b0-467f-bbed-11c26e65b7e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986610336 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.986610336 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3724726438 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 7644217470 ps |
| CPU time | 783.06 seconds |
| Started | Jul 18 08:36:32 PM PDT 24 |
| Finished | Jul 18 08:49:36 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-e3dbb47e-0d79-4032-9596-23032b88a90f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724726438 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3724726438 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.1460972692 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 5272586160 ps |
| CPU time | 641.65 seconds |
| Started | Jul 18 08:41:10 PM PDT 24 |
| Finished | Jul 18 08:51:55 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-1d36ae55-2e0f-44d6-8a04-ed8ebf932341 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460972692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.1460972692 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3142900781 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4207515617 ps |
| CPU time | 644.51 seconds |
| Started | Jul 18 08:36:06 PM PDT 24 |
| Finished | Jul 18 08:46:51 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-577bc4b2-74e0-4c89-8012-9d4f48170523 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142900781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3142900781 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4127890723 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4213780547 ps |
| CPU time | 529.74 seconds |
| Started | Jul 18 08:37:32 PM PDT 24 |
| Finished | Jul 18 08:46:23 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-64f05d10-9fca-40fa-a005-d32970c3ac87 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127890723 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4127890723 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.4275224329 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3083131224 ps |
| CPU time | 291.14 seconds |
| Started | Jul 18 08:39:26 PM PDT 24 |
| Finished | Jul 18 08:44:18 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-46bd514f-f060-46ee-96bc-85501665ffa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275224329 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.4275224329 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.631902581 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 20612244180 ps |
| CPU time | 2772.13 seconds |
| Started | Jul 18 08:41:20 PM PDT 24 |
| Finished | Jul 18 09:27:33 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-6ad171e2-f1e9-4d97-b0c8-c408f5896092 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631902581 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.631902581 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.415702987 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4711498925 ps |
| CPU time | 658.13 seconds |
| Started | Jul 18 08:33:11 PM PDT 24 |
| Finished | Jul 18 08:44:12 PM PDT 24 |
| Peak memory | 613664 kb |
| Host | smart-55320e9a-c19e-455f-88b5-f9f64cd3dbbe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415702987 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.415702987 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2234068500 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 2789751199 ps |
| CPU time | 307.94 seconds |
| Started | Jul 18 08:32:15 PM PDT 24 |
| Finished | Jul 18 08:37:25 PM PDT 24 |
| Peak memory | 612988 kb |
| Host | smart-37f7fb30-bad0-4227-a7cd-8afd73e86fb8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234068500 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2234068500 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3233312924 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3480513912 ps |
| CPU time | 429.06 seconds |
| Started | Jul 18 08:32:44 PM PDT 24 |
| Finished | Jul 18 08:39:54 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-4afa50a5-06ef-4bdd-a95a-619d792bf170 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233312924 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3233312924 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3804206049 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 22619010320 ps |
| CPU time | 1805.45 seconds |
| Started | Jul 18 08:33:00 PM PDT 24 |
| Finished | Jul 18 09:03:07 PM PDT 24 |
| Peak memory | 614460 kb |
| Host | smart-9ef92c9c-b3e7-49a6-98f0-c32b34e1ab60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38042060 49 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.3804206049 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.572854423 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 5564807996 ps |
| CPU time | 526.4 seconds |
| Started | Jul 18 08:33:20 PM PDT 24 |
| Finished | Jul 18 08:42:08 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-343a9241-6a73-40c2-a7ac-918e8e8dd9a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572854423 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.572854423 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2923535098 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 8293814980 ps |
| CPU time | 1750.92 seconds |
| Started | Jul 18 08:32:32 PM PDT 24 |
| Finished | Jul 18 09:01:44 PM PDT 24 |
| Peak memory | 619060 kb |
| Host | smart-6d9fea99-de9e-4b66-83ab-4a3c85c85733 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2923535098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2923535098 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.2879792184 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 2796546632 ps |
| CPU time | 286.37 seconds |
| Started | Jul 18 08:40:11 PM PDT 24 |
| Finished | Jul 18 08:44:58 PM PDT 24 |
| Peak memory | 616128 kb |
| Host | smart-541b496d-9bd0-4ee6-ae3b-7cb0ba90c70e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879792184 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.2879792184 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.387763611 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4616286962 ps |
| CPU time | 685.13 seconds |
| Started | Jul 18 08:30:03 PM PDT 24 |
| Finished | Jul 18 08:41:29 PM PDT 24 |
| Peak memory | 624052 kb |
| Host | smart-89e26d1f-2270-4e76-b9ca-20c1d5f0a41e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387763611 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.387763611 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1035480038 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4324520158 ps |
| CPU time | 775.89 seconds |
| Started | Jul 18 08:31:43 PM PDT 24 |
| Finished | Jul 18 08:44:40 PM PDT 24 |
| Peak memory | 622376 kb |
| Host | smart-7c09a6a6-7c0e-4f07-8393-7dfc9514d256 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035480038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1035480038 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.31903960 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 13641601754 ps |
| CPU time | 2049.34 seconds |
| Started | Jul 18 08:31:07 PM PDT 24 |
| Finished | Jul 18 09:05:17 PM PDT 24 |
| Peak memory | 624724 kb |
| Host | smart-9a204a1c-55de-456c-9ec1-c459baced00a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_a lt_clk_freq_low_speed.31903960 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2766973073 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 76938935680 ps |
| CPU time | 14150.1 seconds |
| Started | Jul 18 08:31:01 PM PDT 24 |
| Finished | Jul 19 12:26:53 AM PDT 24 |
| Peak memory | 636108 kb |
| Host | smart-b32e3ecd-e004-4856-951b-e87fc8d6150a |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2766973073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2766973073 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.100405923 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 4186031956 ps |
| CPU time | 822.42 seconds |
| Started | Jul 18 08:30:33 PM PDT 24 |
| Finished | Jul 18 08:44:17 PM PDT 24 |
| Peak memory | 623840 kb |
| Host | smart-9cd95af5-dc8a-4501-96f8-00dc43b973d8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100405923 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.100405923 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2702757611 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3631197854 ps |
| CPU time | 746.89 seconds |
| Started | Jul 18 08:30:15 PM PDT 24 |
| Finished | Jul 18 08:42:43 PM PDT 24 |
| Peak memory | 622516 kb |
| Host | smart-61c21c38-20e7-418a-bb2e-a067c500b3be |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702757611 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2702757611 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2290908175 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5019963296 ps |
| CPU time | 708.24 seconds |
| Started | Jul 18 08:30:20 PM PDT 24 |
| Finished | Jul 18 08:42:09 PM PDT 24 |
| Peak memory | 624060 kb |
| Host | smart-6899fdd3-41ca-4334-a545-93c7c2e7d78e |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290908175 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2290908175 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.982719485 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 5331057960 ps |
| CPU time | 490.67 seconds |
| Started | Jul 18 08:37:57 PM PDT 24 |
| Finished | Jul 18 08:46:08 PM PDT 24 |
| Peak memory | 620916 kb |
| Host | smart-ef7b548a-717e-40d1-8d10-44fd5a0f075c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=982719485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.982719485 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.5480469 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 10409195898 ps |
| CPU time | 1027.37 seconds |
| Started | Jul 18 08:38:59 PM PDT 24 |
| Finished | Jul 18 08:56:08 PM PDT 24 |
| Peak memory | 620940 kb |
| Host | smart-d0370635-d185-4712-8b87-2e06ca1c7889 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5480469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.5480469 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1124534710 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 15897764409 ps |
| CPU time | 3183.18 seconds |
| Started | Jul 18 08:42:12 PM PDT 24 |
| Finished | Jul 18 09:35:16 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-e77d3a44-033e-4def-8431-86ba2c558d86 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124534710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1124534710 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.3924702362 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 15764930726 ps |
| CPU time | 3265.77 seconds |
| Started | Jul 18 08:44:53 PM PDT 24 |
| Finished | Jul 18 09:39:20 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-d5f9661f-198c-44e6-a78f-4d75b03e13a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924702362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3924702362 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.456487628 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 15590325435 ps |
| CPU time | 3443.61 seconds |
| Started | Jul 18 08:42:52 PM PDT 24 |
| Finished | Jul 18 09:40:17 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-ea5053e5-80e1-4d41-99a3-7a3a02839174 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456487628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.456487628 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.246688922 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 14576168923 ps |
| CPU time | 3138.83 seconds |
| Started | Jul 18 08:43:53 PM PDT 24 |
| Finished | Jul 18 09:36:13 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-f5606fb6-4298-449f-95d9-302f41fb2262 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246688922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.246688922 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2253804240 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 10818981570 ps |
| CPU time | 2672.09 seconds |
| Started | Jul 18 08:44:49 PM PDT 24 |
| Finished | Jul 18 09:29:23 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-08e415bd-93ee-4282-8984-6ced88353943 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253804240 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.2253804240 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.265263205 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 14906384616 ps |
| CPU time | 3393.86 seconds |
| Started | Jul 18 08:44:21 PM PDT 24 |
| Finished | Jul 18 09:40:56 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-f3fd46c0-6402-4b30-a073-a7c3218edd92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265263205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.265263205 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2875649705 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 14704526390 ps |
| CPU time | 3127.42 seconds |
| Started | Jul 18 08:42:53 PM PDT 24 |
| Finished | Jul 18 09:35:02 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-3b56660d-afb0-41ac-8939-8997de1a7a09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875649705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.2875649705 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2754240204 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 14970464006 ps |
| CPU time | 3206.37 seconds |
| Started | Jul 18 08:44:36 PM PDT 24 |
| Finished | Jul 18 09:38:04 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-a164bc53-fd72-40df-8178-6df2d3f9d94a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754240204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2754240204 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.1007025573 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 25959784062 ps |
| CPU time | 6008.63 seconds |
| Started | Jul 18 08:45:17 PM PDT 24 |
| Finished | Jul 18 10:25:27 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-9e8e7c1b-362d-49a9-bc4d-af3f0b3582c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007025573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1007025573 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.619429565 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 14180750508 ps |
| CPU time | 3239.46 seconds |
| Started | Jul 18 08:44:07 PM PDT 24 |
| Finished | Jul 18 09:38:07 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-9c19ac96-6e27-4d8d-8a8f-c400eb716368 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619429565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shut down_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_s hutdown_exception_c.619429565 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1783662755 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 27412764659 ps |
| CPU time | 3308.61 seconds |
| Started | Jul 18 08:42:41 PM PDT 24 |
| Finished | Jul 18 09:37:51 PM PDT 24 |
| Peak memory | 611336 kb |
| Host | smart-960ba5ef-2776-4614-886e-688f59d19b56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783662755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1783662755 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.1260608332 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 14809553972 ps |
| CPU time | 3352.68 seconds |
| Started | Jul 18 08:44:33 PM PDT 24 |
| Finished | Jul 18 09:40:27 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-30ca3d2a-bcd6-4ace-af3f-13b8a5d96dc5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1260608332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.1260608332 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.941149182 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 16716439440 ps |
| CPU time | 4063.85 seconds |
| Started | Jul 18 08:44:52 PM PDT 24 |
| Finished | Jul 18 09:52:38 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-b8fc1635-6e95-4c1e-a4c1-29e62d15dac4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941149182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.941149182 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3413194551 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 4085188756 ps |
| CPU time | 483 seconds |
| Started | Jul 18 08:39:28 PM PDT 24 |
| Finished | Jul 18 08:47:31 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-71f8af8e-1225-4267-8875-ce71a74f10ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413194551 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3413194551 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3561884734 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 5382241092 ps |
| CPU time | 266.79 seconds |
| Started | Jul 18 08:41:00 PM PDT 24 |
| Finished | Jul 18 08:45:28 PM PDT 24 |
| Peak memory | 623884 kb |
| Host | smart-49f1ab39-6731-4383-a630-c77255fcfc04 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3561884734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3561884734 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.1038291323 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3091119375 ps |
| CPU time | 122.66 seconds |
| Started | Jul 18 08:39:01 PM PDT 24 |
| Finished | Jul 18 08:41:05 PM PDT 24 |
| Peak memory | 617984 kb |
| Host | smart-f603becb-d8cd-4b48-b909-3f7c6acc3972 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038291323 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1038291323 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825677374 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 4065312654 ps |
| CPU time | 378.69 seconds |
| Started | Jul 18 08:44:59 PM PDT 24 |
| Finished | Jul 18 08:51:18 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-3fae67fe-c8fa-40e4-bbba-8123863a815b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825677374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2825677374 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.723481898 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5574612880 ps |
| CPU time | 749.96 seconds |
| Started | Jul 18 08:52:19 PM PDT 24 |
| Finished | Jul 18 09:04:51 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-748dfa72-c3a4-468d-a068-a4f23516e1f0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 723481898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.723481898 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.624497964 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6563080720 ps |
| CPU time | 733.8 seconds |
| Started | Jul 18 08:53:20 PM PDT 24 |
| Finished | Jul 18 09:05:36 PM PDT 24 |
| Peak memory | 650224 kb |
| Host | smart-97e5f6f5-f193-41bd-9447-28325be199bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 624497964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.624497964 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.2009829353 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 6249399050 ps |
| CPU time | 622.26 seconds |
| Started | Jul 18 08:45:50 PM PDT 24 |
| Finished | Jul 18 08:56:14 PM PDT 24 |
| Peak memory | 616780 kb |
| Host | smart-2acfccd8-1841-4236-a11b-ca904e9d7a83 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2009829353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.2009829353 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1389684346 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5369627528 ps |
| CPU time | 503.06 seconds |
| Started | Jul 18 08:45:03 PM PDT 24 |
| Finished | Jul 18 08:53:27 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-aa3d2514-ace9-4edb-8ebf-e37fb10fdfe1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1389684346 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1389684346 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948520487 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3695061972 ps |
| CPU time | 367.62 seconds |
| Started | Jul 18 08:45:35 PM PDT 24 |
| Finished | Jul 18 08:51:43 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-cd415925-fba1-4a35-ad50-6470c9dac409 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948520487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3948520487 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1929225720 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4312233806 ps |
| CPU time | 586.79 seconds |
| Started | Jul 18 08:45:29 PM PDT 24 |
| Finished | Jul 18 08:55:17 PM PDT 24 |
| Peak memory | 648944 kb |
| Host | smart-4a4ec8c7-2a4f-4ff2-b7fa-b514d427f29f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929225720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1929225720 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3803787768 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 5484046176 ps |
| CPU time | 530.41 seconds |
| Started | Jul 18 08:46:22 PM PDT 24 |
| Finished | Jul 18 08:55:13 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-71d91745-ea39-442e-82b9-2bdc889de5cf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3803787768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3803787768 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820916726 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4343063480 ps |
| CPU time | 539.56 seconds |
| Started | Jul 18 08:47:24 PM PDT 24 |
| Finished | Jul 18 08:56:25 PM PDT 24 |
| Peak memory | 649100 kb |
| Host | smart-80f5ea6a-1e67-4c1c-88fe-5426532c9dcb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820916726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1820916726 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.910185655 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 4501006992 ps |
| CPU time | 439.83 seconds |
| Started | Jul 18 08:46:40 PM PDT 24 |
| Finished | Jul 18 08:54:00 PM PDT 24 |
| Peak memory | 648880 kb |
| Host | smart-074bb1f3-b179-41df-a7e4-4f608ae06991 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910185655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_s w_alert_handler_lpg_sleep_mode_alerts.910185655 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.2114687453 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5518921072 ps |
| CPU time | 676.83 seconds |
| Started | Jul 18 08:47:02 PM PDT 24 |
| Finished | Jul 18 08:58:22 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-e601b89e-813c-4f2a-90b5-f5d2d73fd807 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2114687453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.2114687453 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3960788082 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 3560632860 ps |
| CPU time | 446.67 seconds |
| Started | Jul 18 08:40:13 PM PDT 24 |
| Finished | Jul 18 08:47:40 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-0f682d53-1872-4e10-b563-48bcce62e76e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960788082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.3960788082 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.2980033872 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4616898890 ps |
| CPU time | 592.16 seconds |
| Started | Jul 18 08:40:55 PM PDT 24 |
| Finished | Jul 18 08:50:48 PM PDT 24 |
| Peak memory | 650032 kb |
| Host | smart-4dd433f0-29a9-4827-8b56-4bbc4c395da2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2980033872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.2980033872 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4292649812 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 8074709604 ps |
| CPU time | 611.34 seconds |
| Started | Jul 18 08:40:02 PM PDT 24 |
| Finished | Jul 18 08:50:15 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-1c680cbf-ffe1-4b57-8d86-6d1a6d32f559 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4292649812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4292649812 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2609027369 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 23150099936 ps |
| CPU time | 5137.61 seconds |
| Started | Jul 18 08:41:52 PM PDT 24 |
| Finished | Jul 18 10:07:32 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-0d178106-c64e-4b53-9bcc-5bac8b26f672 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609027369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2609027369 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1624761997 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4517287290 ps |
| CPU time | 658.94 seconds |
| Started | Jul 18 08:42:47 PM PDT 24 |
| Finished | Jul 18 08:53:47 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-4061e86a-f92a-4c88-9ce7-ec9f093df3fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1624761997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.1624761997 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.561813877 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 11780875933 ps |
| CPU time | 941.55 seconds |
| Started | Jul 18 08:40:47 PM PDT 24 |
| Finished | Jul 18 08:56:29 PM PDT 24 |
| Peak memory | 624600 kb |
| Host | smart-a1b6eccc-f2cc-44fc-bbe7-a7bce914663d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561813877 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.561813877 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.904414087 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3618284800 ps |
| CPU time | 666.19 seconds |
| Started | Jul 18 08:41:19 PM PDT 24 |
| Finished | Jul 18 08:52:28 PM PDT 24 |
| Peak memory | 623328 kb |
| Host | smart-4f988521-eecf-408e-81f3-244db2087f3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=904414087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.904414087 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.3406721392 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4522571182 ps |
| CPU time | 605.42 seconds |
| Started | Jul 18 08:39:57 PM PDT 24 |
| Finished | Jul 18 08:50:03 PM PDT 24 |
| Peak memory | 624176 kb |
| Host | smart-b0d12341-18af-4cbb-ad67-be761c391f69 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406721392 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.3406721392 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2168797111 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 4298202937 ps |
| CPU time | 515.87 seconds |
| Started | Jul 18 08:40:46 PM PDT 24 |
| Finished | Jul 18 08:49:24 PM PDT 24 |
| Peak memory | 624696 kb |
| Host | smart-9d112dd7-6e36-423f-803d-6384c929bfce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168797111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.2168797111 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1413999509 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5113447625 ps |
| CPU time | 620.66 seconds |
| Started | Jul 18 08:42:21 PM PDT 24 |
| Finished | Jul 18 08:52:43 PM PDT 24 |
| Peak memory | 618796 kb |
| Host | smart-35bd9e39-b892-42fd-8d81-def1b8c027fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413999509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1413999509 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3183090070 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 3807346100 ps |
| CPU time | 636.4 seconds |
| Started | Jul 18 08:39:56 PM PDT 24 |
| Finished | Jul 18 08:50:33 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-f4909846-921d-4b4d-bdbc-03db9d1a1957 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183090070 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.3183090070 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2773264405 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 4685739272 ps |
| CPU time | 614.02 seconds |
| Started | Jul 18 08:40:25 PM PDT 24 |
| Finished | Jul 18 08:50:40 PM PDT 24 |
| Peak memory | 624044 kb |
| Host | smart-6a12b581-7caa-4550-ae49-5ad674fa2dca |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773264405 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2773264405 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2275165686 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 4141016232 ps |
| CPU time | 631.22 seconds |
| Started | Jul 18 08:39:49 PM PDT 24 |
| Finished | Jul 18 08:50:22 PM PDT 24 |
| Peak memory | 622528 kb |
| Host | smart-e5d853cd-788a-4e73-b9a0-c453e191e742 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275165686 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2275165686 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.971017258 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 4028707607 ps |
| CPU time | 357.92 seconds |
| Started | Jul 18 08:40:05 PM PDT 24 |
| Finished | Jul 18 08:46:03 PM PDT 24 |
| Peak memory | 621816 kb |
| Host | smart-f5b504f9-6bfc-42d8-bcaa-d8b259994cc7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=971017258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.971017258 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3784421508 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2235472045 ps |
| CPU time | 150.45 seconds |
| Started | Jul 18 08:41:32 PM PDT 24 |
| Finished | Jul 18 08:44:03 PM PDT 24 |
| Peak memory | 621112 kb |
| Host | smart-81e1b751-cbc9-4fa7-aeca-7e942fe2fdec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784421508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3784421508 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2215013537 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3867157069 ps |
| CPU time | 342.25 seconds |
| Started | Jul 18 08:41:22 PM PDT 24 |
| Finished | Jul 18 08:47:05 PM PDT 24 |
| Peak memory | 620788 kb |
| Host | smart-e8a613ac-7148-417e-83f7-ec08349f8ea0 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215013537 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2215013537 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.2987392488 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5637476464 ps |
| CPU time | 614.05 seconds |
| Started | Jul 18 08:41:30 PM PDT 24 |
| Finished | Jul 18 08:51:45 PM PDT 24 |
| Peak memory | 622452 kb |
| Host | smart-791615fc-29ce-470a-9ea7-b157aa0a67c7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2987392488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.2987392488 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.689072699 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 4075585460 ps |
| CPU time | 362.46 seconds |
| Started | Jul 18 08:45:37 PM PDT 24 |
| Finished | Jul 18 08:51:40 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-1f2a02ad-3114-443a-a01d-4a4f18b58211 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689072699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.689072699 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.700955362 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6317134800 ps |
| CPU time | 768.64 seconds |
| Started | Jul 18 08:47:20 PM PDT 24 |
| Finished | Jul 18 09:00:10 PM PDT 24 |
| Peak memory | 650012 kb |
| Host | smart-94444123-f07b-4853-b11f-9b81ebd16ba8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 700955362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.700955362 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2552757204 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 3911682980 ps |
| CPU time | 401.67 seconds |
| Started | Jul 18 08:46:39 PM PDT 24 |
| Finished | Jul 18 08:53:22 PM PDT 24 |
| Peak memory | 648968 kb |
| Host | smart-a6fdd8c5-2842-4514-8ebf-53bebe966547 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552757204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2552757204 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3451392237 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4391574634 ps |
| CPU time | 506.26 seconds |
| Started | Jul 18 08:45:47 PM PDT 24 |
| Finished | Jul 18 08:54:15 PM PDT 24 |
| Peak memory | 650196 kb |
| Host | smart-af3ef5db-d8aa-4b5c-a90f-48f18abe3f14 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3451392237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3451392237 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.500758685 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 5842579976 ps |
| CPU time | 564.32 seconds |
| Started | Jul 18 08:48:13 PM PDT 24 |
| Finished | Jul 18 08:57:38 PM PDT 24 |
| Peak memory | 619672 kb |
| Host | smart-167c1e4a-7329-44b5-9d70-cf954310bbb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 500758685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.500758685 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3118424610 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 6330067280 ps |
| CPU time | 476.66 seconds |
| Started | Jul 18 08:41:59 PM PDT 24 |
| Finished | Jul 18 08:49:57 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-e9c8309f-3484-4db9-9eed-fe2ecae50d5f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3118424610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3118424610 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.841109206 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 29797572050 ps |
| CPU time | 5788.81 seconds |
| Started | Jul 18 08:42:45 PM PDT 24 |
| Finished | Jul 18 10:19:15 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-b190cd32-97d4-4dee-babf-41b6b551f480 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841109206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.841109206 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.3406604524 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 5456668240 ps |
| CPU time | 574.31 seconds |
| Started | Jul 18 08:41:57 PM PDT 24 |
| Finished | Jul 18 08:51:32 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-265b4388-a891-40ff-834b-57afc2e39898 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3406604524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3406604524 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.567771527 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 6870906078 ps |
| CPU time | 577.69 seconds |
| Started | Jul 18 08:40:37 PM PDT 24 |
| Finished | Jul 18 08:50:15 PM PDT 24 |
| Peak memory | 622480 kb |
| Host | smart-255f77fc-579b-43b9-a0aa-50dd2a3cfd0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567771527 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.567771527 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.369864610 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 7507934280 ps |
| CPU time | 1082.37 seconds |
| Started | Jul 18 08:42:21 PM PDT 24 |
| Finished | Jul 18 09:00:25 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-73805979-d97f-46fb-a03b-c485b37fea6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986461 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.369864610 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1399971381 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 8618148724 ps |
| CPU time | 1671.06 seconds |
| Started | Jul 18 08:40:50 PM PDT 24 |
| Finished | Jul 18 09:08:43 PM PDT 24 |
| Peak memory | 618836 kb |
| Host | smart-51e9cf26-2a90-4f61-9dbe-384bb1725fbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1399971381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.1399971381 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3582041742 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 3528444600 ps |
| CPU time | 564.32 seconds |
| Started | Jul 18 08:40:39 PM PDT 24 |
| Finished | Jul 18 08:50:04 PM PDT 24 |
| Peak memory | 622556 kb |
| Host | smart-59506dcb-4348-4757-97bd-3656ece47454 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582041742 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3582041742 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1481085360 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 4505149245 ps |
| CPU time | 628.69 seconds |
| Started | Jul 18 08:41:43 PM PDT 24 |
| Finished | Jul 18 08:52:12 PM PDT 24 |
| Peak memory | 623092 kb |
| Host | smart-b1fdd7d6-73b0-48eb-8a50-32a59b053054 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481085360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1481085360 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3506045851 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4048746102 ps |
| CPU time | 512.72 seconds |
| Started | Jul 18 08:45:48 PM PDT 24 |
| Finished | Jul 18 08:54:23 PM PDT 24 |
| Peak memory | 624684 kb |
| Host | smart-55c5e618-240f-4ec0-927b-711de42eb5a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506045851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3506045851 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2914221493 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 4393445240 ps |
| CPU time | 570.7 seconds |
| Started | Jul 18 08:41:52 PM PDT 24 |
| Finished | Jul 18 08:51:24 PM PDT 24 |
| Peak memory | 623756 kb |
| Host | smart-79b44ac4-a0d2-4228-951d-004d99041eef |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914221493 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2914221493 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1175222569 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 4179690312 ps |
| CPU time | 676.78 seconds |
| Started | Jul 18 08:41:17 PM PDT 24 |
| Finished | Jul 18 08:52:35 PM PDT 24 |
| Peak memory | 622524 kb |
| Host | smart-6180743d-66ff-401c-a240-7805f0f23006 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175222569 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1175222569 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.739318142 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2606933191 ps |
| CPU time | 171.99 seconds |
| Started | Jul 18 08:40:59 PM PDT 24 |
| Finished | Jul 18 08:43:52 PM PDT 24 |
| Peak memory | 620128 kb |
| Host | smart-57ab5b21-ba3c-4ade-826b-3ef757fa9158 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739318142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.739318142 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.641112912 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3371607320 ps |
| CPU time | 256.02 seconds |
| Started | Jul 18 08:40:59 PM PDT 24 |
| Finished | Jul 18 08:45:15 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-ac091111-9a7e-49c8-800d-21003b22b230 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641112912 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.641112912 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2314281166 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 5411229156 ps |
| CPU time | 490.78 seconds |
| Started | Jul 18 08:47:04 PM PDT 24 |
| Finished | Jul 18 08:55:17 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-0cc500ea-69e1-4ae9-8c39-a11f1d82c556 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2314281166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2314281166 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278239843 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4002516912 ps |
| CPU time | 347.23 seconds |
| Started | Jul 18 08:46:44 PM PDT 24 |
| Finished | Jul 18 08:52:32 PM PDT 24 |
| Peak memory | 648692 kb |
| Host | smart-25f95f95-2e4e-4076-b0df-90cf21c7f8ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278239843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1278239843 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270346591 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 3814120980 ps |
| CPU time | 367.16 seconds |
| Started | Jul 18 08:56:44 PM PDT 24 |
| Finished | Jul 18 09:02:52 PM PDT 24 |
| Peak memory | 649076 kb |
| Host | smart-60e89e04-c8b4-47d2-9270-fa47cfd527b9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270346591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4270346591 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1617481600 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4692694596 ps |
| CPU time | 532.05 seconds |
| Started | Jul 18 08:46:49 PM PDT 24 |
| Finished | Jul 18 08:55:42 PM PDT 24 |
| Peak memory | 649892 kb |
| Host | smart-4da66a17-ccaa-4d65-9fbf-3b6b5a40b7a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1617481600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1617481600 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3100903882 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 3861380960 ps |
| CPU time | 446.72 seconds |
| Started | Jul 18 08:47:24 PM PDT 24 |
| Finished | Jul 18 08:54:52 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-45df7a2f-f6ac-473b-b931-4b99f54b3c69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100903882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3100903882 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465537098 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3903354130 ps |
| CPU time | 393.12 seconds |
| Started | Jul 18 08:48:01 PM PDT 24 |
| Finished | Jul 18 08:54:36 PM PDT 24 |
| Peak memory | 648872 kb |
| Host | smart-39463337-7a27-413e-b738-36ef83e20100 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465537098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1465537098 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330154114 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 3934384800 ps |
| CPU time | 383.79 seconds |
| Started | Jul 18 08:47:45 PM PDT 24 |
| Finished | Jul 18 08:54:10 PM PDT 24 |
| Peak memory | 618788 kb |
| Host | smart-5f519395-66c9-49df-b842-da8b1b1c36b3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330154114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3330154114 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.670845062 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 5055570134 ps |
| CPU time | 607.27 seconds |
| Started | Jul 18 08:55:53 PM PDT 24 |
| Finished | Jul 18 09:06:01 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-372ff853-5b7c-4904-be06-89c6369a7719 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 670845062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.670845062 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3706984 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 4462841144 ps |
| CPU time | 580.44 seconds |
| Started | Jul 18 08:47:41 PM PDT 24 |
| Finished | Jul 18 08:57:22 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-f8cc7da1-d980-452f-ae1b-bd0b31adc197 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3706984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3706984 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1646786499 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 4205485800 ps |
| CPU time | 360.32 seconds |
| Started | Jul 18 08:43:44 PM PDT 24 |
| Finished | Jul 18 08:49:45 PM PDT 24 |
| Peak memory | 648648 kb |
| Host | smart-2af29f72-49c9-43ea-a6de-537f7af281b9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646786499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1646786499 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1617094326 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 18247444524 ps |
| CPU time | 3945.31 seconds |
| Started | Jul 18 08:42:08 PM PDT 24 |
| Finished | Jul 18 09:47:55 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-8fe91b02-180d-4dba-a30c-a0c88729f597 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617094326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1617094326 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.989675362 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5941018880 ps |
| CPU time | 651.74 seconds |
| Started | Jul 18 08:41:26 PM PDT 24 |
| Finished | Jul 18 08:52:19 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-42a7aecc-b383-4e18-af69-ad58432cfd8f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=989675362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.989675362 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.532423130 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4229233251 ps |
| CPU time | 414.24 seconds |
| Started | Jul 18 08:43:38 PM PDT 24 |
| Finished | Jul 18 08:50:33 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-1c37b0eb-688d-4994-a36a-95772bd7956f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532423130 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.532423130 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.419614961 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 3376475996 ps |
| CPU time | 577.8 seconds |
| Started | Jul 18 08:42:47 PM PDT 24 |
| Finished | Jul 18 08:52:28 PM PDT 24 |
| Peak memory | 618620 kb |
| Host | smart-6a382d68-c96e-45e7-8e02-38378d8d9ce9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=419614961 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.419614961 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2162296736 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 3285150184 ps |
| CPU time | 336.63 seconds |
| Started | Jul 18 08:47:29 PM PDT 24 |
| Finished | Jul 18 08:53:07 PM PDT 24 |
| Peak memory | 648524 kb |
| Host | smart-35b09c0e-a344-476f-88b8-085bad44613b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162296736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2162296736 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3934171258 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 4234124052 ps |
| CPU time | 432.49 seconds |
| Started | Jul 18 08:48:36 PM PDT 24 |
| Finished | Jul 18 08:55:50 PM PDT 24 |
| Peak memory | 648972 kb |
| Host | smart-e3e7f364-40dd-4ec8-a016-581ec4ad092c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934171258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3934171258 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.205060848 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3895201272 ps |
| CPU time | 455.81 seconds |
| Started | Jul 18 08:48:22 PM PDT 24 |
| Finished | Jul 18 08:55:59 PM PDT 24 |
| Peak memory | 648808 kb |
| Host | smart-cc830ce1-40a8-495b-81b8-687009a7dd32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205060848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_s w_alert_handler_lpg_sleep_mode_alerts.205060848 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.95930849 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 4654444800 ps |
| CPU time | 632.47 seconds |
| Started | Jul 18 08:48:54 PM PDT 24 |
| Finished | Jul 18 08:59:27 PM PDT 24 |
| Peak memory | 650060 kb |
| Host | smart-e5fcea2e-fd78-4889-83ad-238b94b5a99f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 95930849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.95930849 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.20487666 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 3161745828 ps |
| CPU time | 352.62 seconds |
| Started | Jul 18 08:47:29 PM PDT 24 |
| Finished | Jul 18 08:53:23 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-cf05e065-6614-4402-bcfd-4d7e5f1c08f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20487666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw _alert_handler_lpg_sleep_mode_alerts.20487666 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.3730647473 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 6038619698 ps |
| CPU time | 589.25 seconds |
| Started | Jul 18 08:48:29 PM PDT 24 |
| Finished | Jul 18 08:58:19 PM PDT 24 |
| Peak memory | 649920 kb |
| Host | smart-4a0184df-0054-4615-8bca-c0d6165dd830 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3730647473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.3730647473 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.2058310964 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 5154964928 ps |
| CPU time | 405.17 seconds |
| Started | Jul 18 08:47:54 PM PDT 24 |
| Finished | Jul 18 08:54:41 PM PDT 24 |
| Peak memory | 619664 kb |
| Host | smart-3b0c245e-e2af-43ae-9a46-09b54124953a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2058310964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2058310964 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262124903 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 3536374200 ps |
| CPU time | 382.1 seconds |
| Started | Jul 18 08:48:58 PM PDT 24 |
| Finished | Jul 18 08:55:21 PM PDT 24 |
| Peak memory | 648776 kb |
| Host | smart-dc3fb301-e676-486e-8ae6-e43630936f57 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262124903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3262124903 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.2833773167 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4918203360 ps |
| CPU time | 789.69 seconds |
| Started | Jul 18 08:47:51 PM PDT 24 |
| Finished | Jul 18 09:01:02 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-6e36c2e9-33ca-459b-90c8-4b6875fd6be9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2833773167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2833773167 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3219595184 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 5556945332 ps |
| CPU time | 491.84 seconds |
| Started | Jul 18 08:47:34 PM PDT 24 |
| Finished | Jul 18 08:55:46 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-a001829f-cb0a-463c-a71e-f737170c042a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3219595184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3219595184 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.682488606 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5054940208 ps |
| CPU time | 772.55 seconds |
| Started | Jul 18 08:47:55 PM PDT 24 |
| Finished | Jul 18 09:00:50 PM PDT 24 |
| Peak memory | 649736 kb |
| Host | smart-adcf2dd8-4535-4684-8f6c-b7e6cb80e3c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 682488606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.682488606 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2888461957 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4061248040 ps |
| CPU time | 357.18 seconds |
| Started | Jul 18 08:50:01 PM PDT 24 |
| Finished | Jul 18 08:55:59 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-13654ce7-410c-4bab-8f3f-d26ffd6d00c3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888461957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2888461957 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2952535957 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 4870582898 ps |
| CPU time | 616.22 seconds |
| Started | Jul 18 08:48:27 PM PDT 24 |
| Finished | Jul 18 08:58:44 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-bf7f06c8-98c5-4912-baf9-7b4fe4eb76bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2952535957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2952535957 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.925494377 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3408955624 ps |
| CPU time | 336.97 seconds |
| Started | Jul 18 08:43:06 PM PDT 24 |
| Finished | Jul 18 08:48:44 PM PDT 24 |
| Peak memory | 648776 kb |
| Host | smart-54575dff-cdba-4205-98af-ac09dbadd661 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925494377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.925494377 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1039852739 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 5432362052 ps |
| CPU time | 696.72 seconds |
| Started | Jul 18 08:41:16 PM PDT 24 |
| Finished | Jul 18 08:52:54 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-77da5a99-7c3a-4cba-bba6-46b59231d6c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1039852739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1039852739 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3478624094 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 19972890552 ps |
| CPU time | 4560.21 seconds |
| Started | Jul 18 08:43:33 PM PDT 24 |
| Finished | Jul 18 09:59:35 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-11e04003-5035-4c14-8a84-ca4129283c05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478624094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.3478624094 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2407176259 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 12427826644 ps |
| CPU time | 647.09 seconds |
| Started | Jul 18 08:42:44 PM PDT 24 |
| Finished | Jul 18 08:53:32 PM PDT 24 |
| Peak memory | 623596 kb |
| Host | smart-bc8893a0-4b2a-4c5e-963a-0ab7c924ace3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407176259 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2407176259 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1017279602 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3773421370 ps |
| CPU time | 457.12 seconds |
| Started | Jul 18 08:42:45 PM PDT 24 |
| Finished | Jul 18 08:50:24 PM PDT 24 |
| Peak memory | 617580 kb |
| Host | smart-3875fa8a-6e85-4673-ac4c-aef57bba12f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1017279602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1017279602 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335949693 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3713343400 ps |
| CPU time | 360.17 seconds |
| Started | Jul 18 08:49:00 PM PDT 24 |
| Finished | Jul 18 08:55:03 PM PDT 24 |
| Peak memory | 648600 kb |
| Host | smart-6fa2e3cf-4ff5-47d7-9b2a-8c2b52426ee9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335949693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2335949693 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.477038157 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5669205560 ps |
| CPU time | 602.27 seconds |
| Started | Jul 18 08:50:34 PM PDT 24 |
| Finished | Jul 18 09:00:38 PM PDT 24 |
| Peak memory | 650124 kb |
| Host | smart-598c76c7-e5aa-4437-a894-21003911ee53 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 477038157 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.477038157 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237822682 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 3758996496 ps |
| CPU time | 413 seconds |
| Started | Jul 18 08:47:39 PM PDT 24 |
| Finished | Jul 18 08:54:32 PM PDT 24 |
| Peak memory | 648868 kb |
| Host | smart-0de3f46c-ba71-40a6-8adf-526ebf42bfeb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237822682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1237822682 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2602650636 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4486269336 ps |
| CPU time | 572.82 seconds |
| Started | Jul 18 08:48:22 PM PDT 24 |
| Finished | Jul 18 08:57:56 PM PDT 24 |
| Peak memory | 649800 kb |
| Host | smart-c580fce9-ebc1-4851-bd9e-615864c50773 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2602650636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2602650636 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.456812433 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3663565794 ps |
| CPU time | 449.44 seconds |
| Started | Jul 18 08:48:29 PM PDT 24 |
| Finished | Jul 18 08:56:00 PM PDT 24 |
| Peak memory | 648924 kb |
| Host | smart-c5735db0-af98-4343-8e13-5e37bb3a2827 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456812433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_s w_alert_handler_lpg_sleep_mode_alerts.456812433 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.658428815 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4944722308 ps |
| CPU time | 576.76 seconds |
| Started | Jul 18 08:47:47 PM PDT 24 |
| Finished | Jul 18 08:57:25 PM PDT 24 |
| Peak memory | 650064 kb |
| Host | smart-57f79488-a47e-4eb7-86d7-f0eeda1116bc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 658428815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.658428815 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.77258045 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 4034132168 ps |
| CPU time | 331.45 seconds |
| Started | Jul 18 08:49:00 PM PDT 24 |
| Finished | Jul 18 08:54:34 PM PDT 24 |
| Peak memory | 649152 kb |
| Host | smart-e8764dca-bca8-4001-a7c0-f461e6ba9918 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77258045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw _alert_handler_lpg_sleep_mode_alerts.77258045 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.4217673379 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 5346960994 ps |
| CPU time | 532.74 seconds |
| Started | Jul 18 08:49:14 PM PDT 24 |
| Finished | Jul 18 08:58:08 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-1b769f88-c365-4f3c-9813-7a624c0224fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4217673379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.4217673379 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1945424911 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3403275278 ps |
| CPU time | 399.84 seconds |
| Started | Jul 18 08:49:08 PM PDT 24 |
| Finished | Jul 18 08:55:49 PM PDT 24 |
| Peak memory | 648600 kb |
| Host | smart-3ebafdce-475b-4280-a4bd-71bbcb307445 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945424911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1945424911 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.418241738 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 5950826580 ps |
| CPU time | 577.27 seconds |
| Started | Jul 18 08:48:29 PM PDT 24 |
| Finished | Jul 18 08:58:07 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-615fba8b-f8fa-429a-8bbb-d71b5e17a5d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 418241738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.418241738 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.688320663 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 3303338382 ps |
| CPU time | 324.58 seconds |
| Started | Jul 18 08:50:47 PM PDT 24 |
| Finished | Jul 18 08:56:16 PM PDT 24 |
| Peak memory | 648588 kb |
| Host | smart-f9da7cf6-646d-4241-9811-775babdebfff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688320663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_s w_alert_handler_lpg_sleep_mode_alerts.688320663 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2440938484 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 4165621784 ps |
| CPU time | 658.77 seconds |
| Started | Jul 18 08:48:19 PM PDT 24 |
| Finished | Jul 18 08:59:20 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-c48c3086-447f-4004-a5bc-1606adbbf954 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2440938484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2440938484 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.578943835 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6138172082 ps |
| CPU time | 592.26 seconds |
| Started | Jul 18 08:49:10 PM PDT 24 |
| Finished | Jul 18 08:59:03 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-5ad171b5-da3e-49e5-a495-112a3bf0bc0a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 578943835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.578943835 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932097806 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3758901272 ps |
| CPU time | 414.58 seconds |
| Started | Jul 18 08:51:25 PM PDT 24 |
| Finished | Jul 18 08:58:21 PM PDT 24 |
| Peak memory | 649124 kb |
| Host | smart-9d6905a8-64a4-4178-a52c-ac579b1a1910 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932097806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1932097806 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.55084293 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 3614026396 ps |
| CPU time | 427.97 seconds |
| Started | Jul 18 08:51:04 PM PDT 24 |
| Finished | Jul 18 08:58:14 PM PDT 24 |
| Peak memory | 648808 kb |
| Host | smart-1085e815-7b39-4448-8712-035588e91eff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55084293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw _alert_handler_lpg_sleep_mode_alerts.55084293 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.2619037522 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 6669760200 ps |
| CPU time | 685.8 seconds |
| Started | Jul 18 08:51:00 PM PDT 24 |
| Finished | Jul 18 09:02:28 PM PDT 24 |
| Peak memory | 649864 kb |
| Host | smart-505049b5-43de-48d9-8d6d-c8a7fe72934e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2619037522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2619037522 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.3924264298 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 5532053560 ps |
| CPU time | 666.71 seconds |
| Started | Jul 18 08:42:27 PM PDT 24 |
| Finished | Jul 18 08:53:35 PM PDT 24 |
| Peak memory | 649772 kb |
| Host | smart-292369a2-9282-4633-a1ff-350678d6907e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3924264298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.3924264298 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2358101505 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 15786108916 ps |
| CPU time | 3507.91 seconds |
| Started | Jul 18 08:43:53 PM PDT 24 |
| Finished | Jul 18 09:42:23 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-1fa76a2f-c020-474f-ae06-ecbbc5176d38 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358101505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.2358101505 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3253405760 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 12892623067 ps |
| CPU time | 1064.76 seconds |
| Started | Jul 18 08:43:13 PM PDT 24 |
| Finished | Jul 18 09:00:59 PM PDT 24 |
| Peak memory | 624792 kb |
| Host | smart-5f019824-bd84-49c2-92a2-c8ffe0bfb0d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253405760 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3253405760 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1357139924 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 13059321272 ps |
| CPU time | 2314.97 seconds |
| Started | Jul 18 08:41:41 PM PDT 24 |
| Finished | Jul 18 09:20:17 PM PDT 24 |
| Peak memory | 618492 kb |
| Host | smart-c2e11f2d-7454-4fb0-91ce-bbec0c5df0bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1357139924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.1357139924 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.491207526 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3567353760 ps |
| CPU time | 320.39 seconds |
| Started | Jul 18 08:48:34 PM PDT 24 |
| Finished | Jul 18 08:53:56 PM PDT 24 |
| Peak memory | 649380 kb |
| Host | smart-e7cef4fb-d006-465a-8bbf-341eb54200ed |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491207526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.491207526 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2720047380 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5490452800 ps |
| CPU time | 696.01 seconds |
| Started | Jul 18 08:51:16 PM PDT 24 |
| Finished | Jul 18 09:02:53 PM PDT 24 |
| Peak memory | 619728 kb |
| Host | smart-8d0fa850-8441-4b11-8636-97d807cc7e01 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2720047380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2720047380 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340126096 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 3968625136 ps |
| CPU time | 334.41 seconds |
| Started | Jul 18 08:49:52 PM PDT 24 |
| Finished | Jul 18 08:55:28 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-b439b795-2c71-43e1-83ee-8109cd7a67d3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340126096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2340126096 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3804141541 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 6256379660 ps |
| CPU time | 668.5 seconds |
| Started | Jul 18 08:48:59 PM PDT 24 |
| Finished | Jul 18 09:00:10 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-e2262756-60e0-4a14-8bf3-3ada966c8278 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3804141541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3804141541 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.374483020 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 3696200516 ps |
| CPU time | 330.12 seconds |
| Started | Jul 18 08:50:01 PM PDT 24 |
| Finished | Jul 18 08:55:32 PM PDT 24 |
| Peak memory | 648636 kb |
| Host | smart-7252c543-5e8f-4dd5-b0dc-d4a6508d8b60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374483020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_s w_alert_handler_lpg_sleep_mode_alerts.374483020 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.223593649 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6104799528 ps |
| CPU time | 606.54 seconds |
| Started | Jul 18 08:49:23 PM PDT 24 |
| Finished | Jul 18 08:59:30 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-2df6a587-c3dd-4dfc-afdb-278a97a44818 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 223593649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.223593649 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003931521 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3876752248 ps |
| CPU time | 403.42 seconds |
| Started | Jul 18 08:51:56 PM PDT 24 |
| Finished | Jul 18 08:58:41 PM PDT 24 |
| Peak memory | 649408 kb |
| Host | smart-dee87128-92c0-4af8-9b61-db7e823bf0c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003931521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1003931521 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570332714 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 4382647952 ps |
| CPU time | 397.42 seconds |
| Started | Jul 18 08:49:07 PM PDT 24 |
| Finished | Jul 18 08:55:46 PM PDT 24 |
| Peak memory | 649112 kb |
| Host | smart-e5b21516-4e89-433b-be0a-517be8ecccfe |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570332714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2570332714 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.36015680 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5379468168 ps |
| CPU time | 600.28 seconds |
| Started | Jul 18 08:49:10 PM PDT 24 |
| Finished | Jul 18 08:59:11 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-c145bf1a-0b64-4fb0-aa80-93515053f66a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 36015680 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.36015680 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3387707363 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 4504647718 ps |
| CPU time | 472.34 seconds |
| Started | Jul 18 08:52:16 PM PDT 24 |
| Finished | Jul 18 09:00:09 PM PDT 24 |
| Peak memory | 649424 kb |
| Host | smart-1b78fd32-653b-4b63-b745-cc586c51ea24 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387707363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3387707363 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.1669403956 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5813651760 ps |
| CPU time | 551.7 seconds |
| Started | Jul 18 08:49:41 PM PDT 24 |
| Finished | Jul 18 08:58:54 PM PDT 24 |
| Peak memory | 650160 kb |
| Host | smart-c9407b91-98fd-4ab0-8ffe-cf930748ca0d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1669403956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.1669403956 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312410569 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3494328956 ps |
| CPU time | 352 seconds |
| Started | Jul 18 08:50:55 PM PDT 24 |
| Finished | Jul 18 08:56:49 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-a93d5003-cb31-4e33-92ac-a4e271fca3d9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312410569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3312410569 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.28970148 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5267410200 ps |
| CPU time | 562.41 seconds |
| Started | Jul 18 08:51:17 PM PDT 24 |
| Finished | Jul 18 09:00:40 PM PDT 24 |
| Peak memory | 650180 kb |
| Host | smart-2f25af2d-815d-4c92-96a7-9065cd352342 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 28970148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.28970148 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1495524613 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 4359739832 ps |
| CPU time | 385.07 seconds |
| Started | Jul 18 08:50:16 PM PDT 24 |
| Finished | Jul 18 08:56:43 PM PDT 24 |
| Peak memory | 649076 kb |
| Host | smart-4dde8a9f-abc7-442e-a4a5-f4e7ad9d08ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495524613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1495524613 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1184473751 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 5355524700 ps |
| CPU time | 704.16 seconds |
| Started | Jul 18 08:49:25 PM PDT 24 |
| Finished | Jul 18 09:01:11 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-942db8de-91a6-4218-bc20-66e0d761b28b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1184473751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1184473751 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.351033381 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 4257563968 ps |
| CPU time | 387.89 seconds |
| Started | Jul 18 08:49:51 PM PDT 24 |
| Finished | Jul 18 08:56:19 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-beb8bc76-fb6e-45b1-9716-cb3c9344ff3d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 351033381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.351033381 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4089873445 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 3962276960 ps |
| CPU time | 340.24 seconds |
| Started | Jul 18 08:41:56 PM PDT 24 |
| Finished | Jul 18 08:47:37 PM PDT 24 |
| Peak memory | 649128 kb |
| Host | smart-f2497a48-55fa-4832-9682-26af19ac7705 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089873445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.4089873445 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1991131248 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 19711163900 ps |
| CPU time | 3881.4 seconds |
| Started | Jul 18 08:42:45 PM PDT 24 |
| Finished | Jul 18 09:47:27 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-1866b6d5-987a-48a0-894e-429852a1f428 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991131248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1991131248 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.611251736 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5345066684 ps |
| CPU time | 727.33 seconds |
| Started | Jul 18 08:43:01 PM PDT 24 |
| Finished | Jul 18 08:55:09 PM PDT 24 |
| Peak memory | 624760 kb |
| Host | smart-77159390-f0fa-4f62-affa-a979ce131534 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611251736 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.611251736 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3163658650 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 13761706040 ps |
| CPU time | 2007.18 seconds |
| Started | Jul 18 08:42:38 PM PDT 24 |
| Finished | Jul 18 09:16:07 PM PDT 24 |
| Peak memory | 619068 kb |
| Host | smart-803ae2a6-0f92-43ff-8a2d-2bfc0f9181d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3163658650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.3163658650 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020852669 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 3638986536 ps |
| CPU time | 394.73 seconds |
| Started | Jul 18 08:49:23 PM PDT 24 |
| Finished | Jul 18 08:55:59 PM PDT 24 |
| Peak memory | 648900 kb |
| Host | smart-e7694bd3-cfd7-4e83-b8b0-292642e05a99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020852669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1020852669 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.2175840214 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4910762870 ps |
| CPU time | 636.13 seconds |
| Started | Jul 18 08:50:13 PM PDT 24 |
| Finished | Jul 18 09:00:51 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-02d52a9c-cacc-4e89-bb99-7bd748d5ecaf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2175840214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.2175840214 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.807516203 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3741615400 ps |
| CPU time | 461.12 seconds |
| Started | Jul 18 08:50:51 PM PDT 24 |
| Finished | Jul 18 08:58:36 PM PDT 24 |
| Peak memory | 648816 kb |
| Host | smart-b7ad7a47-6b92-421e-8aef-714f5a7382f8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807516203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_s w_alert_handler_lpg_sleep_mode_alerts.807516203 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3554726804 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 4349840150 ps |
| CPU time | 476.26 seconds |
| Started | Jul 18 08:50:42 PM PDT 24 |
| Finished | Jul 18 08:58:40 PM PDT 24 |
| Peak memory | 650084 kb |
| Host | smart-165c494b-0009-497c-9303-65339f631d58 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3554726804 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3554726804 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.491283492 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3592779706 ps |
| CPU time | 353.26 seconds |
| Started | Jul 18 08:50:52 PM PDT 24 |
| Finished | Jul 18 08:56:48 PM PDT 24 |
| Peak memory | 648740 kb |
| Host | smart-06e856e4-9419-4969-a3ba-db8a4bb55085 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491283492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.491283492 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1953789402 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5120234050 ps |
| CPU time | 616.46 seconds |
| Started | Jul 18 08:50:39 PM PDT 24 |
| Finished | Jul 18 09:00:57 PM PDT 24 |
| Peak memory | 649976 kb |
| Host | smart-20a08b50-fda2-4565-8a9d-e1f4d484c75b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1953789402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1953789402 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799734877 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3847088888 ps |
| CPU time | 321.24 seconds |
| Started | Jul 18 08:50:54 PM PDT 24 |
| Finished | Jul 18 08:56:17 PM PDT 24 |
| Peak memory | 648860 kb |
| Host | smart-fee5f757-2c4c-4072-b4ad-cfbbfee3c00c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799734877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3799734877 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.3681228252 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 6238759040 ps |
| CPU time | 606.56 seconds |
| Started | Jul 18 08:49:48 PM PDT 24 |
| Finished | Jul 18 08:59:56 PM PDT 24 |
| Peak memory | 649820 kb |
| Host | smart-ba78a412-facb-4c65-b964-d9982a6076ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3681228252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.3681228252 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626126352 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4209796330 ps |
| CPU time | 351.84 seconds |
| Started | Jul 18 08:50:59 PM PDT 24 |
| Finished | Jul 18 08:56:52 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-deede681-2cff-4ea5-9dab-55dd5e42b0d2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626126352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1626126352 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.135454308 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 5351203120 ps |
| CPU time | 572.89 seconds |
| Started | Jul 18 08:49:14 PM PDT 24 |
| Finished | Jul 18 08:58:47 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-5c330fd8-41b3-4056-b5b6-5ba5be466c59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 135454308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.135454308 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543948679 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4256978008 ps |
| CPU time | 344.74 seconds |
| Started | Jul 18 08:49:43 PM PDT 24 |
| Finished | Jul 18 08:55:28 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-9325d04a-3fb9-4838-8d9d-4b46516da07e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543948679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2543948679 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890791447 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3867760644 ps |
| CPU time | 456.27 seconds |
| Started | Jul 18 08:51:08 PM PDT 24 |
| Finished | Jul 18 08:58:46 PM PDT 24 |
| Peak memory | 648576 kb |
| Host | smart-9d5848d9-2ce4-4c7a-9457-5df1f5231720 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890791447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1890791447 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.69218733 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 4998649534 ps |
| CPU time | 436.87 seconds |
| Started | Jul 18 08:49:40 PM PDT 24 |
| Finished | Jul 18 08:56:58 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-f5d0a4e8-cc73-433e-aa55-34ceb5c9a66d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 69218733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.69218733 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178191066 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4267315784 ps |
| CPU time | 298.8 seconds |
| Started | Jul 18 08:50:42 PM PDT 24 |
| Finished | Jul 18 08:55:43 PM PDT 24 |
| Peak memory | 648920 kb |
| Host | smart-d4d740fb-c8d0-408e-b754-553d6ec70db1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178191066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2178191066 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.1868656175 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5258477816 ps |
| CPU time | 489.12 seconds |
| Started | Jul 18 08:51:21 PM PDT 24 |
| Finished | Jul 18 08:59:31 PM PDT 24 |
| Peak memory | 650064 kb |
| Host | smart-49cb7cc9-7135-43dd-9ca2-354fd29b7dc9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1868656175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1868656175 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3605555685 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3387267720 ps |
| CPU time | 402.63 seconds |
| Started | Jul 18 08:51:42 PM PDT 24 |
| Finished | Jul 18 08:58:26 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-73458ab9-5418-41a8-8bf7-d8dca5e0b2c5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605555685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3605555685 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.1915553051 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 5498472790 ps |
| CPU time | 549.14 seconds |
| Started | Jul 18 08:51:18 PM PDT 24 |
| Finished | Jul 18 09:00:28 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-65499e12-678f-463f-a116-2f3179fb614a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1915553051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.1915553051 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2998800227 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3098894536 ps |
| CPU time | 352.71 seconds |
| Started | Jul 18 08:43:57 PM PDT 24 |
| Finished | Jul 18 08:49:51 PM PDT 24 |
| Peak memory | 648672 kb |
| Host | smart-80e09d7c-d172-4d14-bdec-c1b0fc501b2f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998800227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2998800227 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1458118802 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 6758112328 ps |
| CPU time | 834.99 seconds |
| Started | Jul 18 08:42:52 PM PDT 24 |
| Finished | Jul 18 08:56:48 PM PDT 24 |
| Peak memory | 650156 kb |
| Host | smart-5a283fe5-f5c2-49a0-8566-63495bb61590 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1458118802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1458118802 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.185606632 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 23766167922 ps |
| CPU time | 5009.71 seconds |
| Started | Jul 18 08:44:23 PM PDT 24 |
| Finished | Jul 18 10:07:55 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-fc08f6d6-7dea-4c93-a5cd-fd8c0090ce65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185606632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.185606632 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.180201810 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 13899175847 ps |
| CPU time | 986.86 seconds |
| Started | Jul 18 08:43:28 PM PDT 24 |
| Finished | Jul 18 08:59:56 PM PDT 24 |
| Peak memory | 624752 kb |
| Host | smart-c2b7d430-fbd9-4021-8d22-7d769789b3e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180201810 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.180201810 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3321426245 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 4452696090 ps |
| CPU time | 539.93 seconds |
| Started | Jul 18 08:43:27 PM PDT 24 |
| Finished | Jul 18 08:52:28 PM PDT 24 |
| Peak memory | 617808 kb |
| Host | smart-7fb89add-38a9-469c-9518-8fa735559aac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3321426245 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3321426245 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2530289684 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5701317504 ps |
| CPU time | 686.17 seconds |
| Started | Jul 18 08:51:01 PM PDT 24 |
| Finished | Jul 18 09:02:29 PM PDT 24 |
| Peak memory | 650312 kb |
| Host | smart-2a22f9a9-207a-4b83-8117-6cf7ccfc877f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2530289684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2530289684 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.3095123624 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 5532318204 ps |
| CPU time | 524.28 seconds |
| Started | Jul 18 08:50:46 PM PDT 24 |
| Finished | Jul 18 08:59:33 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-b8464965-f5b2-4cb3-a245-88ab91490838 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3095123624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.3095123624 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2201874860 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 4606316880 ps |
| CPU time | 659.94 seconds |
| Started | Jul 18 08:51:12 PM PDT 24 |
| Finished | Jul 18 09:02:13 PM PDT 24 |
| Peak memory | 616840 kb |
| Host | smart-24be4304-16e6-4248-82f0-deb776a50d22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2201874860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2201874860 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.369025123 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 4286055188 ps |
| CPU time | 557.43 seconds |
| Started | Jul 18 08:51:33 PM PDT 24 |
| Finished | Jul 18 09:00:52 PM PDT 24 |
| Peak memory | 649992 kb |
| Host | smart-2830e92d-d5a1-4173-8139-eed388ae93e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 369025123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.369025123 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.3583742286 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5626099112 ps |
| CPU time | 488.14 seconds |
| Started | Jul 18 08:49:31 PM PDT 24 |
| Finished | Jul 18 08:57:41 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-f3515786-a019-4ebb-ad84-18e440a392b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3583742286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3583742286 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.1885241586 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 5287224544 ps |
| CPU time | 649.54 seconds |
| Started | Jul 18 08:50:18 PM PDT 24 |
| Finished | Jul 18 09:01:09 PM PDT 24 |
| Peak memory | 649792 kb |
| Host | smart-3109b82c-bb08-4018-9727-be90cfd3ed5e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1885241586 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.1885241586 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.955988448 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4643983730 ps |
| CPU time | 581.07 seconds |
| Started | Jul 18 08:51:28 PM PDT 24 |
| Finished | Jul 18 09:01:11 PM PDT 24 |
| Peak memory | 649812 kb |
| Host | smart-356b3bac-85c4-4abe-864e-c075cb999880 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 955988448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.955988448 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3096595673 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 4010107610 ps |
| CPU time | 496.22 seconds |
| Started | Jul 18 08:51:09 PM PDT 24 |
| Finished | Jul 18 08:59:27 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-5c7bcc8c-a95d-472b-b004-8e91cdeeb812 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3096595673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3096595673 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3646443505 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 5413487146 ps |
| CPU time | 296.05 seconds |
| Started | Jul 18 08:43:45 PM PDT 24 |
| Finished | Jul 18 08:48:41 PM PDT 24 |
| Peak memory | 641868 kb |
| Host | smart-7bc2b8e5-78c3-490b-9ae5-db28e59628bb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646443505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.3646443505 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2481726563 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4229547359 ps |
| CPU time | 214.42 seconds |
| Started | Jul 18 08:44:05 PM PDT 24 |
| Finished | Jul 18 08:47:41 PM PDT 24 |
| Peak memory | 640992 kb |
| Host | smart-5761e18c-8298-4b2d-b8b6-22d879c09d06 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481726563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.2481726563 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1107348666 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4451040840 ps |
| CPU time | 223.01 seconds |
| Started | Jul 18 08:44:01 PM PDT 24 |
| Finished | Jul 18 08:47:45 PM PDT 24 |
| Peak memory | 641012 kb |
| Host | smart-5345e8a3-fd2e-46af-acfe-2a062e5ea92d |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107348666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1107348666 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1322016073 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4664288580 ps |
| CPU time | 314.18 seconds |
| Started | Jul 18 08:44:18 PM PDT 24 |
| Finished | Jul 18 08:49:33 PM PDT 24 |
| Peak memory | 657376 kb |
| Host | smart-76cc265c-d2a3-4fe0-b6f5-2b071406afe1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322016073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.1322016073 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2040208344 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 5639654297 ps |
| CPU time | 356.94 seconds |
| Started | Jul 18 08:43:59 PM PDT 24 |
| Finished | Jul 18 08:49:58 PM PDT 24 |
| Peak memory | 650920 kb |
| Host | smart-1fc62188-c7b2-46e8-9cb8-f6e239ff20a6 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040208344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2040208344 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.836086851 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5090059980 ps |
| CPU time | 344.4 seconds |
| Started | Jul 18 08:44:10 PM PDT 24 |
| Finished | Jul 18 08:49:56 PM PDT 24 |
| Peak memory | 657404 kb |
| Host | smart-8bd4f99e-9eeb-46cc-a939-dfa7c5ffcb5e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836086851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 7.chip_padctrl_attributes.836086851 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2393179602 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5432224465 ps |
| CPU time | 305.48 seconds |
| Started | Jul 18 08:44:00 PM PDT 24 |
| Finished | Jul 18 08:49:07 PM PDT 24 |
| Peak memory | 642476 kb |
| Host | smart-1c273192-a7ab-4530-a5c7-ee0c087a12cb |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393179602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.2393179602 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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