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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 95.29 93.64 95.33 94.46 97.53 99.62


Total test records in report: 2932
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T1235 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2846045839 Jul 18 08:15:01 PM PDT 24 Jul 18 08:21:47 PM PDT 24 5752565111 ps
T794 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.654764376 Jul 18 08:14:57 PM PDT 24 Jul 18 08:32:35 PM PDT 24 9694648060 ps
T1236 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3194001023 Jul 18 08:22:28 PM PDT 24 Jul 18 08:28:58 PM PDT 24 3795460946 ps
T1237 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2851010960 Jul 18 08:18:16 PM PDT 24 Jul 18 09:16:26 PM PDT 24 14896486804 ps
T806 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.544617063 Jul 18 08:44:44 PM PDT 24 Jul 18 08:50:36 PM PDT 24 3783861880 ps
T816 /workspace/coverage/default/79.chip_sw_all_escalation_resets.3489949688 Jul 18 08:50:59 PM PDT 24 Jul 18 09:01:12 PM PDT 24 5837578240 ps
T1238 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1119814691 Jul 18 08:17:18 PM PDT 24 Jul 18 08:22:48 PM PDT 24 3060152200 ps
T1239 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1911496953 Jul 18 08:34:34 PM PDT 24 Jul 18 08:40:20 PM PDT 24 4908614448 ps
T1240 /workspace/coverage/default/2.rom_e2e_asm_init_prod.3924702362 Jul 18 08:44:53 PM PDT 24 Jul 18 09:39:20 PM PDT 24 15764930726 ps
T419 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.322431773 Jul 18 08:29:29 PM PDT 24 Jul 18 08:56:20 PM PDT 24 21990693812 ps
T1241 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.1096415124 Jul 18 08:27:34 PM PDT 24 Jul 18 08:43:56 PM PDT 24 6919933160 ps
T1242 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2894848895 Jul 18 08:14:18 PM PDT 24 Jul 18 08:19:28 PM PDT 24 3240716564 ps
T1243 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.1647805885 Jul 18 08:31:52 PM PDT 24 Jul 18 08:49:25 PM PDT 24 6045903432 ps
T1244 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1876804070 Jul 18 08:32:34 PM PDT 24 Jul 18 09:18:33 PM PDT 24 28590464821 ps
T753 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.330064892 Jul 18 08:14:33 PM PDT 24 Jul 18 08:18:50 PM PDT 24 2653604004 ps
T1245 /workspace/coverage/default/1.rom_e2e_self_hash.4182976474 Jul 18 08:41:46 PM PDT 24 Jul 18 10:09:13 PM PDT 24 26075714952 ps
T1246 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.339433777 Jul 18 08:19:04 PM PDT 24 Jul 18 08:25:33 PM PDT 24 4807677672 ps
T1247 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.556537442 Jul 18 08:14:24 PM PDT 24 Jul 18 08:30:16 PM PDT 24 9715527704 ps
T202 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.780210942 Jul 18 08:17:55 PM PDT 24 Jul 18 08:30:05 PM PDT 24 6770895736 ps
T1248 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1894258935 Jul 18 08:18:39 PM PDT 24 Jul 18 08:23:17 PM PDT 24 3156357930 ps
T335 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3339179883 Jul 18 08:25:33 PM PDT 24 Jul 18 08:44:58 PM PDT 24 6171354544 ps
T1249 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.445569547 Jul 18 08:25:17 PM PDT 24 Jul 18 08:43:13 PM PDT 24 6411920456 ps
T1250 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1347142454 Jul 18 08:32:53 PM PDT 24 Jul 18 08:40:53 PM PDT 24 3788053700 ps
T1251 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1501005370 Jul 18 08:19:23 PM PDT 24 Jul 18 08:26:28 PM PDT 24 6111735610 ps
T818 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1389684346 Jul 18 08:45:03 PM PDT 24 Jul 18 08:53:27 PM PDT 24 5369627528 ps
T206 /workspace/coverage/default/0.chip_jtag_mem_access.3737612167 Jul 18 08:06:56 PM PDT 24 Jul 18 08:35:05 PM PDT 24 13807646089 ps
T1252 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2948170434 Jul 18 08:19:44 PM PDT 24 Jul 18 08:42:36 PM PDT 24 8034027642 ps
T1253 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1880675439 Jul 18 08:14:08 PM PDT 24 Jul 18 08:38:34 PM PDT 24 8837931895 ps
T367 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1886752522 Jul 18 08:33:06 PM PDT 24 Jul 18 08:40:05 PM PDT 24 3895501794 ps
T819 /workspace/coverage/default/31.chip_sw_all_escalation_resets.700955362 Jul 18 08:47:20 PM PDT 24 Jul 18 09:00:10 PM PDT 24 6317134800 ps
T1254 /workspace/coverage/default/1.chip_tap_straps_prod.1361240219 Jul 18 08:26:28 PM PDT 24 Jul 18 08:49:22 PM PDT 24 12841604914 ps
T1255 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.603964320 Jul 18 08:31:42 PM PDT 24 Jul 18 08:36:13 PM PDT 24 2764761313 ps
T271 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.547352010 Jul 18 08:20:20 PM PDT 24 Jul 18 08:31:25 PM PDT 24 4366088096 ps
T820 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1169962860 Jul 18 08:43:06 PM PDT 24 Jul 18 08:50:16 PM PDT 24 3734346200 ps
T804 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.374483020 Jul 18 08:50:01 PM PDT 24 Jul 18 08:55:32 PM PDT 24 3696200516 ps
T163 /workspace/coverage/default/1.chip_plic_all_irqs_10.3564902293 Jul 18 08:27:27 PM PDT 24 Jul 18 08:37:36 PM PDT 24 3444890656 ps
T449 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.727051997 Jul 18 08:18:12 PM PDT 24 Jul 18 09:07:04 PM PDT 24 34757172268 ps
T853 /workspace/coverage/default/97.chip_sw_all_escalation_resets.955988448 Jul 18 08:51:28 PM PDT 24 Jul 18 09:01:11 PM PDT 24 4643983730 ps
T1256 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.764622723 Jul 18 08:15:21 PM PDT 24 Jul 18 08:41:12 PM PDT 24 8276186930 ps
T1257 /workspace/coverage/default/0.chip_sw_power_idle_load.2495780153 Jul 18 08:23:20 PM PDT 24 Jul 18 08:38:05 PM PDT 24 4695410290 ps
T1258 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1350340863 Jul 18 08:32:23 PM PDT 24 Jul 18 08:51:50 PM PDT 24 9811796850 ps
T1259 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2407176259 Jul 18 08:42:44 PM PDT 24 Jul 18 08:53:32 PM PDT 24 12427826644 ps
T238 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2205817664 Jul 18 08:27:06 PM PDT 24 Jul 18 09:38:01 PM PDT 24 13346797648 ps
T850 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2889566888 Jul 18 08:46:01 PM PDT 24 Jul 18 08:54:50 PM PDT 24 3653808736 ps
T728 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3638622121 Jul 18 08:40:16 PM PDT 24 Jul 18 11:25:50 PM PDT 24 68796651368 ps
T1260 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.1074175276 Jul 18 08:13:30 PM PDT 24 Jul 18 11:37:41 PM PDT 24 64994632067 ps
T1261 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543948679 Jul 18 08:49:43 PM PDT 24 Jul 18 08:55:28 PM PDT 24 4256978008 ps
T1262 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2789210056 Jul 18 08:20:32 PM PDT 24 Jul 18 08:30:25 PM PDT 24 8614473330 ps
T36 /workspace/coverage/default/1.chip_sw_gpio.2879606770 Jul 18 08:19:36 PM PDT 24 Jul 18 08:27:30 PM PDT 24 4149986040 ps
T780 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1039852739 Jul 18 08:41:16 PM PDT 24 Jul 18 08:52:54 PM PDT 24 5432362052 ps
T241 /workspace/coverage/default/1.chip_sw_flash_init.3392341541 Jul 18 08:19:08 PM PDT 24 Jul 18 09:04:52 PM PDT 24 20295661796 ps
T1263 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2798694937 Jul 18 08:14:34 PM PDT 24 Jul 18 08:19:19 PM PDT 24 3614567848 ps
T336 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2669779027 Jul 18 08:35:35 PM PDT 24 Jul 18 08:56:56 PM PDT 24 6596449044 ps
T1264 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2736898379 Jul 18 08:14:44 PM PDT 24 Jul 18 08:43:01 PM PDT 24 10545503115 ps
T1265 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1431295212 Jul 18 08:16:24 PM PDT 24 Jul 18 08:24:41 PM PDT 24 4244221032 ps
T44 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.986610336 Jul 18 08:30:12 PM PDT 24 Jul 18 08:37:04 PM PDT 24 2995623232 ps
T1266 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.198440145 Jul 18 08:34:04 PM PDT 24 Jul 18 08:42:29 PM PDT 24 5557274336 ps
T1267 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1006981052 Jul 18 08:41:25 PM PDT 24 Jul 18 09:05:08 PM PDT 24 7483540776 ps
T868 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.491283492 Jul 18 08:50:52 PM PDT 24 Jul 18 08:56:48 PM PDT 24 3592779706 ps
T1268 /workspace/coverage/default/1.chip_sw_example_manufacturer.1403216015 Jul 18 08:16:29 PM PDT 24 Jul 18 08:19:37 PM PDT 24 2353884482 ps
T1269 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2043302316 Jul 18 08:13:50 PM PDT 24 Jul 18 11:54:40 PM PDT 24 79474317450 ps
T1270 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3596923620 Jul 18 08:44:09 PM PDT 24 Jul 18 08:50:11 PM PDT 24 5518084589 ps
T1271 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2541650809 Jul 18 08:31:40 PM PDT 24 Jul 18 08:35:56 PM PDT 24 2674246972 ps
T31 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2959120265 Jul 18 08:13:57 PM PDT 24 Jul 18 08:25:06 PM PDT 24 4167011644 ps
T1272 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.352633574 Jul 18 08:16:28 PM PDT 24 Jul 18 08:24:18 PM PDT 24 3945542316 ps
T887 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3804141541 Jul 18 08:48:59 PM PDT 24 Jul 18 09:00:10 PM PDT 24 6256379660 ps
T1273 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.841109206 Jul 18 08:42:45 PM PDT 24 Jul 18 10:19:15 PM PDT 24 29797572050 ps
T1274 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2883469166 Jul 18 08:28:48 PM PDT 24 Jul 18 08:36:06 PM PDT 24 5807058696 ps
T1275 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.631902581 Jul 18 08:41:20 PM PDT 24 Jul 18 09:27:33 PM PDT 24 20612244180 ps
T1276 /workspace/coverage/default/0.rom_e2e_self_hash.3970324451 Jul 18 08:28:24 PM PDT 24 Jul 18 10:07:20 PM PDT 24 26075515144 ps
T1277 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3141091534 Jul 18 08:23:28 PM PDT 24 Jul 18 09:16:42 PM PDT 24 14796659972 ps
T866 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1495524613 Jul 18 08:50:16 PM PDT 24 Jul 18 08:56:43 PM PDT 24 4359739832 ps
T1278 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2275165686 Jul 18 08:39:49 PM PDT 24 Jul 18 08:50:22 PM PDT 24 4141016232 ps
T1279 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2018872807 Jul 18 08:26:46 PM PDT 24 Jul 18 08:35:15 PM PDT 24 4729112437 ps
T1280 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4118883853 Jul 18 08:19:30 PM PDT 24 Jul 18 08:21:23 PM PDT 24 1925456887 ps
T1281 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1526678811 Jul 18 08:32:45 PM PDT 24 Jul 18 08:40:15 PM PDT 24 4369339892 ps
T1282 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2448430167 Jul 18 08:22:59 PM PDT 24 Jul 18 08:53:04 PM PDT 24 13456018406 ps
T855 /workspace/coverage/default/7.chip_sw_all_escalation_resets.3924264298 Jul 18 08:42:27 PM PDT 24 Jul 18 08:53:35 PM PDT 24 5532053560 ps
T815 /workspace/coverage/default/0.chip_sw_all_escalation_resets.311252287 Jul 18 08:12:56 PM PDT 24 Jul 18 08:26:11 PM PDT 24 6141074408 ps
T1283 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262124903 Jul 18 08:48:58 PM PDT 24 Jul 18 08:55:21 PM PDT 24 3536374200 ps
T1284 /workspace/coverage/default/2.chip_sw_uart_smoketest.2879792184 Jul 18 08:40:11 PM PDT 24 Jul 18 08:44:58 PM PDT 24 2796546632 ps
T1285 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2825677374 Jul 18 08:44:59 PM PDT 24 Jul 18 08:51:18 PM PDT 24 4065312654 ps
T1286 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2552757204 Jul 18 08:46:39 PM PDT 24 Jul 18 08:53:22 PM PDT 24 3911682980 ps
T1287 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1103135038 Jul 18 08:23:54 PM PDT 24 Jul 18 09:48:19 PM PDT 24 15018265530 ps
T1288 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.290209921 Jul 18 08:21:02 PM PDT 24 Jul 18 08:39:10 PM PDT 24 5900894541 ps
T1289 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1344087720 Jul 18 08:17:28 PM PDT 24 Jul 18 08:26:33 PM PDT 24 5029027542 ps
T100 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.491207526 Jul 18 08:48:34 PM PDT 24 Jul 18 08:53:56 PM PDT 24 3567353760 ps
T1290 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2855958134 Jul 18 08:29:28 PM PDT 24 Jul 18 08:34:56 PM PDT 24 2878150568 ps
T1291 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.611650164 Jul 18 08:21:05 PM PDT 24 Jul 18 08:30:14 PM PDT 24 5196711726 ps
T412 /workspace/coverage/default/0.chip_sw_usbdev_vbus.1275540896 Jul 18 08:14:36 PM PDT 24 Jul 18 08:18:30 PM PDT 24 3007875528 ps
T1292 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3713435294 Jul 18 08:16:45 PM PDT 24 Jul 18 08:29:24 PM PDT 24 3872764688 ps
T1293 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3139355216 Jul 18 08:16:29 PM PDT 24 Jul 18 08:21:13 PM PDT 24 2433158906 ps
T424 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.199015061 Jul 18 08:16:33 PM PDT 24 Jul 18 08:23:00 PM PDT 24 7858419628 ps
T1294 /workspace/coverage/default/2.chip_sw_flash_crash_alert.3189804031 Jul 18 08:39:38 PM PDT 24 Jul 18 08:52:44 PM PDT 24 4878811790 ps
T1295 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.796891143 Jul 18 08:23:06 PM PDT 24 Jul 18 10:07:24 PM PDT 24 23799465313 ps
T1296 /workspace/coverage/default/1.chip_sw_edn_auto_mode.417546011 Jul 18 08:22:37 PM PDT 24 Jul 18 08:39:41 PM PDT 24 4776732766 ps
T51 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2997795873 Jul 18 08:12:28 PM PDT 24 Jul 18 08:18:39 PM PDT 24 3821136799 ps
T78 /workspace/coverage/default/0.chip_sw_usbdev_pullup.185147822 Jul 18 08:13:53 PM PDT 24 Jul 18 08:20:24 PM PDT 24 3499071504 ps
T1297 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.532423130 Jul 18 08:43:38 PM PDT 24 Jul 18 08:50:33 PM PDT 24 4229233251 ps
T768 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1899701858 Jul 18 08:22:35 PM PDT 24 Jul 18 08:39:31 PM PDT 24 5126903858 ps
T1298 /workspace/coverage/default/1.chip_sw_kmac_entropy.3652067862 Jul 18 08:20:29 PM PDT 24 Jul 18 08:25:35 PM PDT 24 3523020520 ps
T398 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1613343246 Jul 18 08:27:35 PM PDT 24 Jul 18 08:30:09 PM PDT 24 2746472540 ps
T235 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.873020836 Jul 18 08:26:54 PM PDT 24 Jul 18 08:48:46 PM PDT 24 7797577666 ps
T1299 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1404272378 Jul 18 08:43:00 PM PDT 24 Jul 18 08:48:09 PM PDT 24 3001019112 ps
T332 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.292605146 Jul 18 08:32:44 PM PDT 24 Jul 18 09:07:39 PM PDT 24 13658245408 ps
T1300 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2461968039 Jul 18 08:35:34 PM PDT 24 Jul 18 08:42:23 PM PDT 24 3493275810 ps
T425 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3002268322 Jul 18 08:37:48 PM PDT 24 Jul 18 09:11:11 PM PDT 24 26483929924 ps
T1301 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1857582918 Jul 18 08:25:13 PM PDT 24 Jul 18 08:35:44 PM PDT 24 4588455582 ps
T331 /workspace/coverage/default/0.chip_plic_all_irqs_0.839783680 Jul 18 08:14:54 PM PDT 24 Jul 18 08:35:36 PM PDT 24 5409067240 ps
T1302 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3945168086 Jul 18 08:21:23 PM PDT 24 Jul 18 08:41:14 PM PDT 24 5186198206 ps
T374 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2286565122 Jul 18 08:16:18 PM PDT 24 Jul 18 08:22:59 PM PDT 24 5904788760 ps
T874 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2162296736 Jul 18 08:47:29 PM PDT 24 Jul 18 08:53:07 PM PDT 24 3285150184 ps
T1303 /workspace/coverage/default/24.chip_sw_all_escalation_resets.2009829353 Jul 18 08:45:50 PM PDT 24 Jul 18 08:56:14 PM PDT 24 6249399050 ps
T1304 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3381163726 Jul 18 08:22:22 PM PDT 24 Jul 18 08:25:38 PM PDT 24 2657916200 ps
T1305 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2601119870 Jul 18 08:29:26 PM PDT 24 Jul 18 08:34:51 PM PDT 24 2927273310 ps
T79 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3057445542 Jul 18 08:13:24 PM PDT 24 Jul 18 08:19:31 PM PDT 24 3952582872 ps
T1306 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3458113071 Jul 18 08:12:59 PM PDT 24 Jul 18 08:22:51 PM PDT 24 4095776040 ps
T1307 /workspace/coverage/default/1.chip_sw_uart_tx_rx.196202532 Jul 18 08:18:54 PM PDT 24 Jul 18 08:31:09 PM PDT 24 4825966568 ps
T770 /workspace/coverage/default/0.rom_raw_unlock.2180752952 Jul 18 08:18:59 PM PDT 24 Jul 18 08:24:34 PM PDT 24 6852439264 ps
T21 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3452884544 Jul 18 08:18:21 PM PDT 24 Jul 18 08:23:31 PM PDT 24 3315408717 ps
T1308 /workspace/coverage/default/0.rom_e2e_static_critical.727854304 Jul 18 08:23:33 PM PDT 24 Jul 18 09:45:25 PM PDT 24 16778500260 ps
T1309 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2843395063 Jul 18 08:32:10 PM PDT 24 Jul 18 08:38:40 PM PDT 24 6514458467 ps
T1310 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2861157871 Jul 18 08:16:43 PM PDT 24 Jul 18 08:58:07 PM PDT 24 11031747080 ps
T1311 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1416457050 Jul 18 08:21:34 PM PDT 24 Jul 18 08:45:52 PM PDT 24 8087191426 ps
T1312 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.979629730 Jul 18 08:14:21 PM PDT 24 Jul 18 08:33:26 PM PDT 24 6126061809 ps
T1313 /workspace/coverage/default/23.chip_sw_all_escalation_resets.1630920144 Jul 18 08:44:27 PM PDT 24 Jul 18 08:53:19 PM PDT 24 5388789190 ps
T1314 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2180875478 Jul 18 08:29:52 PM PDT 24 Jul 18 09:06:19 PM PDT 24 8753321572 ps
T1315 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3364916456 Jul 18 08:13:05 PM PDT 24 Jul 18 08:33:32 PM PDT 24 5933579882 ps
T1316 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3080378071 Jul 18 08:28:19 PM PDT 24 Jul 18 09:05:52 PM PDT 24 11709441920 ps
T172 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.4115270925 Jul 18 08:37:09 PM PDT 24 Jul 18 08:46:20 PM PDT 24 5363848156 ps
T1317 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1963057220 Jul 18 08:27:44 PM PDT 24 Jul 18 08:47:08 PM PDT 24 5212082268 ps
T726 /workspace/coverage/default/2.chip_sw_edn_boot_mode.149721348 Jul 18 08:35:10 PM PDT 24 Jul 18 08:44:41 PM PDT 24 3019806380 ps
T1318 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1658112036 Jul 18 08:32:42 PM PDT 24 Jul 18 08:41:57 PM PDT 24 3155972400 ps
T1319 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3902812677 Jul 18 08:32:24 PM PDT 24 Jul 18 08:43:04 PM PDT 24 3822537340 ps
T885 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278239843 Jul 18 08:46:44 PM PDT 24 Jul 18 08:52:32 PM PDT 24 4002516912 ps
T1320 /workspace/coverage/default/0.chip_sw_gpio_smoketest.1046279580 Jul 18 08:17:15 PM PDT 24 Jul 18 08:21:52 PM PDT 24 3061871749 ps
T861 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932097806 Jul 18 08:51:25 PM PDT 24 Jul 18 08:58:21 PM PDT 24 3758901272 ps
T1321 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3945710099 Jul 18 08:16:33 PM PDT 24 Jul 18 09:09:41 PM PDT 24 27970637892 ps
T1322 /workspace/coverage/default/0.chip_sw_hmac_oneshot.3392490426 Jul 18 08:14:55 PM PDT 24 Jul 18 08:21:29 PM PDT 24 3648927640 ps
T1323 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2773264405 Jul 18 08:40:25 PM PDT 24 Jul 18 08:50:40 PM PDT 24 4685739272 ps
T1324 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3321426245 Jul 18 08:43:27 PM PDT 24 Jul 18 08:52:28 PM PDT 24 4452696090 ps
T863 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1825660523 Jul 18 08:45:09 PM PDT 24 Jul 18 08:58:46 PM PDT 24 6538843024 ps
T1325 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.201813090 Jul 18 08:42:40 PM PDT 24 Jul 18 09:01:30 PM PDT 24 10915562662 ps
T873 /workspace/coverage/default/60.chip_sw_all_escalation_resets.477038157 Jul 18 08:50:34 PM PDT 24 Jul 18 09:00:38 PM PDT 24 5669205560 ps
T1326 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.330459217 Jul 18 08:23:30 PM PDT 24 Jul 18 08:33:05 PM PDT 24 4847725798 ps
T1327 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1634720748 Jul 18 08:31:54 PM PDT 24 Jul 18 08:56:40 PM PDT 24 9129027040 ps
T1328 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3572427001 Jul 18 08:42:07 PM PDT 24 Jul 19 12:05:06 AM PDT 24 255211063064 ps
T1329 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1481085360 Jul 18 08:41:43 PM PDT 24 Jul 18 08:52:12 PM PDT 24 4505149245 ps
T864 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2530289684 Jul 18 08:51:01 PM PDT 24 Jul 18 09:02:29 PM PDT 24 5701317504 ps
T1330 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2234068500 Jul 18 08:32:15 PM PDT 24 Jul 18 08:37:25 PM PDT 24 2789751199 ps
T1331 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4249078907 Jul 18 08:19:10 PM PDT 24 Jul 18 11:54:20 PM PDT 24 78426789622 ps
T69 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3328845115 Jul 18 08:17:07 PM PDT 24 Jul 18 08:19:25 PM PDT 24 2245994074 ps
T1332 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3169167172 Jul 18 08:15:18 PM PDT 24 Jul 18 08:24:34 PM PDT 24 5815442177 ps
T1333 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.948998197 Jul 18 08:12:15 PM PDT 24 Jul 18 08:15:33 PM PDT 24 3363065744 ps
T1334 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.1422207801 Jul 18 08:20:31 PM PDT 24 Jul 18 08:30:05 PM PDT 24 5374693350 ps
T1335 /workspace/coverage/default/0.chip_sw_coremark.1809509380 Jul 18 08:14:38 PM PDT 24 Jul 19 12:18:22 AM PDT 24 71280804104 ps
T376 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1256922794 Jul 18 08:50:18 PM PDT 24 Jul 18 08:58:47 PM PDT 24 4630568948 ps
T1336 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4248035838 Jul 18 08:15:47 PM PDT 24 Jul 18 08:26:02 PM PDT 24 4903024104 ps
T1337 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3269775595 Jul 18 08:20:30 PM PDT 24 Jul 18 08:22:31 PM PDT 24 1865101868 ps
T1338 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1034851545 Jul 18 08:24:28 PM PDT 24 Jul 18 10:29:41 PM PDT 24 23519707240 ps
T1339 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2806219109 Jul 18 08:14:10 PM PDT 24 Jul 18 08:22:50 PM PDT 24 3921793993 ps
T1340 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.308300457 Jul 18 08:37:37 PM PDT 24 Jul 18 09:09:18 PM PDT 24 26992569518 ps
T1341 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3881843447 Jul 18 08:13:34 PM PDT 24 Jul 18 08:32:17 PM PDT 24 11504327528 ps
T1342 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2255809763 Jul 18 08:33:18 PM PDT 24 Jul 18 08:36:42 PM PDT 24 2819280881 ps
T1343 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.680111158 Jul 18 08:14:55 PM PDT 24 Jul 18 08:23:50 PM PDT 24 6359991870 ps
T247 /workspace/coverage/default/2.chip_sw_flash_init.655430663 Jul 18 08:29:31 PM PDT 24 Jul 18 08:54:53 PM PDT 24 16919636110 ps
T167 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2058310964 Jul 18 08:47:54 PM PDT 24 Jul 18 08:54:41 PM PDT 24 5154964928 ps
T1344 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3603522877 Jul 18 08:32:59 PM PDT 24 Jul 18 08:48:58 PM PDT 24 7412151400 ps
T148 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3652375451 Jul 18 08:28:25 PM PDT 24 Jul 18 09:32:43 PM PDT 24 27396934683 ps
T1345 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2496611407 Jul 18 08:35:17 PM PDT 24 Jul 18 09:04:52 PM PDT 24 7396000976 ps
T32 /workspace/coverage/default/0.chip_sw_usbdev_config_host.3323787902 Jul 18 08:13:50 PM PDT 24 Jul 18 08:40:50 PM PDT 24 8481001248 ps
T248 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1294623344 Jul 18 08:14:15 PM PDT 24 Jul 18 09:55:47 PM PDT 24 48057529509 ps
T1346 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3830353223 Jul 18 08:20:59 PM PDT 24 Jul 18 08:27:44 PM PDT 24 4123779940 ps
T1347 /workspace/coverage/default/1.chip_sw_aes_idle.3022128381 Jul 18 08:22:35 PM PDT 24 Jul 18 08:26:37 PM PDT 24 3060583168 ps
T1348 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1856277526 Jul 18 08:15:47 PM PDT 24 Jul 18 08:26:20 PM PDT 24 7240436266 ps
T821 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3519326663 Jul 18 08:15:47 PM PDT 24 Jul 18 08:22:58 PM PDT 24 4072511194 ps
T1349 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3018144185 Jul 18 08:26:48 PM PDT 24 Jul 18 09:08:00 PM PDT 24 13114326584 ps
T1350 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.742430605 Jul 18 08:22:06 PM PDT 24 Jul 18 09:26:34 PM PDT 24 14610004700 ps
T1351 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1147976085 Jul 18 08:35:27 PM PDT 24 Jul 18 08:39:01 PM PDT 24 2657103064 ps
T370 /workspace/coverage/default/2.chip_sw_hmac_enc.445586069 Jul 18 08:36:18 PM PDT 24 Jul 18 08:40:55 PM PDT 24 2579938040 ps
T1352 /workspace/coverage/default/0.rom_e2e_asm_init_rma.66495768 Jul 18 08:19:04 PM PDT 24 Jul 18 09:26:09 PM PDT 24 15125806571 ps
T1353 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3121818205 Jul 18 08:14:19 PM PDT 24 Jul 18 09:13:11 PM PDT 24 16965440480 ps
T1354 /workspace/coverage/default/1.chip_sw_aes_smoketest.75487658 Jul 18 08:29:42 PM PDT 24 Jul 18 08:35:02 PM PDT 24 3536554092 ps
T1355 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.4115033047 Jul 18 08:15:50 PM PDT 24 Jul 18 08:19:58 PM PDT 24 2809516984 ps
T1356 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1445115483 Jul 18 08:17:26 PM PDT 24 Jul 18 08:27:21 PM PDT 24 4532573992 ps
T1357 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2925554940 Jul 18 08:24:51 PM PDT 24 Jul 18 10:21:46 PM PDT 24 23568002165 ps
T138 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1523399355 Jul 18 08:35:11 PM PDT 24 Jul 18 08:41:54 PM PDT 24 5183378690 ps
T1358 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3963739409 Jul 18 08:15:11 PM PDT 24 Jul 18 08:39:00 PM PDT 24 9443733302 ps
T1359 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3422634097 Jul 18 08:21:27 PM PDT 24 Jul 18 08:26:02 PM PDT 24 2497680956 ps
T754 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.4110267090 Jul 18 08:19:52 PM PDT 24 Jul 18 08:24:18 PM PDT 24 3499766310 ps
T1360 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3143405 Jul 18 08:19:05 PM PDT 24 Jul 18 09:29:32 PM PDT 24 15624712124 ps
T800 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890791447 Jul 18 08:51:08 PM PDT 24 Jul 18 08:58:46 PM PDT 24 3867760644 ps
T1361 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3341300180 Jul 18 08:34:32 PM PDT 24 Jul 18 09:10:29 PM PDT 24 10055903600 ps
T63 /workspace/coverage/default/1.chip_sw_alert_test.846345271 Jul 18 08:21:39 PM PDT 24 Jul 18 08:27:02 PM PDT 24 2953498570 ps
T1362 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1719804256 Jul 18 08:32:54 PM PDT 24 Jul 18 10:09:32 PM PDT 24 51845331959 ps
T1363 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3613287432 Jul 18 08:38:35 PM PDT 24 Jul 18 08:45:12 PM PDT 24 5498900384 ps
T48 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2284261238 Jul 18 08:17:04 PM PDT 24 Jul 18 08:25:40 PM PDT 24 5882753962 ps
T1364 /workspace/coverage/default/1.chip_sival_flash_info_access.4016861997 Jul 18 08:18:03 PM PDT 24 Jul 18 08:24:39 PM PDT 24 3747642298 ps
T1365 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3196625940 Jul 18 08:34:31 PM PDT 24 Jul 18 09:08:26 PM PDT 24 10827723993 ps
T1366 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.733148549 Jul 18 08:27:30 PM PDT 24 Jul 18 08:36:31 PM PDT 24 5430850284 ps
T1367 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270346591 Jul 18 08:56:44 PM PDT 24 Jul 18 09:02:52 PM PDT 24 3814120980 ps
T1368 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1393304873 Jul 18 08:20:07 PM PDT 24 Jul 18 09:49:59 PM PDT 24 24185499560 ps
T880 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3424544681 Jul 18 08:46:59 PM PDT 24 Jul 18 08:52:44 PM PDT 24 3614794700 ps
T1369 /workspace/coverage/default/2.chip_sw_aes_entropy.2628547340 Jul 18 08:37:36 PM PDT 24 Jul 18 08:42:14 PM PDT 24 2613906856 ps
T1370 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2471944799 Jul 18 08:17:36 PM PDT 24 Jul 18 08:23:57 PM PDT 24 3443101420 ps
T1371 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.419614961 Jul 18 08:42:47 PM PDT 24 Jul 18 08:52:28 PM PDT 24 3376475996 ps
T1372 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2443453125 Jul 18 08:39:50 PM PDT 24 Jul 18 08:43:19 PM PDT 24 2933652576 ps
T840 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2884728861 Jul 18 08:44:04 PM PDT 24 Jul 18 08:52:38 PM PDT 24 5239531956 ps
T70 /workspace/coverage/default/4.chip_tap_straps_rma.641112912 Jul 18 08:40:59 PM PDT 24 Jul 18 08:45:15 PM PDT 24 3371607320 ps
T841 /workspace/coverage/default/75.chip_sw_all_escalation_resets.1669403956 Jul 18 08:49:41 PM PDT 24 Jul 18 08:58:54 PM PDT 24 5813651760 ps
T1373 /workspace/coverage/default/2.chip_sw_aes_enc.605519702 Jul 18 08:33:31 PM PDT 24 Jul 18 08:39:51 PM PDT 24 3147000600 ps
T849 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1809251308 Jul 18 08:42:51 PM PDT 24 Jul 18 08:54:31 PM PDT 24 5273623080 ps
T1374 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.619429565 Jul 18 08:44:07 PM PDT 24 Jul 18 09:38:07 PM PDT 24 14180750508 ps
T1375 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3212463471 Jul 18 08:13:46 PM PDT 24 Jul 18 08:15:26 PM PDT 24 1993270698 ps
T1376 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3582041742 Jul 18 08:40:39 PM PDT 24 Jul 18 08:50:04 PM PDT 24 3528444600 ps
T1377 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2786354276 Jul 18 08:39:55 PM PDT 24 Jul 18 08:44:54 PM PDT 24 3114610818 ps
T1378 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2905559446 Jul 18 08:15:05 PM PDT 24 Jul 18 08:29:25 PM PDT 24 7407773012 ps
T867 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237822682 Jul 18 08:47:39 PM PDT 24 Jul 18 08:54:32 PM PDT 24 3758996496 ps
T1379 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1267741513 Jul 18 08:28:15 PM PDT 24 Jul 18 09:05:00 PM PDT 24 20914806443 ps
T1380 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1818595828 Jul 18 08:38:16 PM PDT 24 Jul 18 08:48:25 PM PDT 24 5197786576 ps
T1381 /workspace/coverage/default/2.chip_sw_aes_masking_off.3769177613 Jul 18 08:40:22 PM PDT 24 Jul 18 08:44:24 PM PDT 24 2885754539 ps
T1382 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2068045808 Jul 18 08:14:31 PM PDT 24 Jul 18 11:16:54 PM PDT 24 59464398552 ps
T1383 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2685878351 Jul 18 08:13:02 PM PDT 24 Jul 18 08:23:58 PM PDT 24 4100940476 ps
T802 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.185137478 Jul 18 08:48:43 PM PDT 24 Jul 18 08:54:32 PM PDT 24 4148374456 ps
T1384 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3907981526 Jul 18 08:33:36 PM PDT 24 Jul 18 08:41:47 PM PDT 24 7463672500 ps
T1385 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3304424566 Jul 18 08:19:54 PM PDT 24 Jul 18 08:44:58 PM PDT 24 23125161470 ps
T139 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2813096293 Jul 18 08:26:02 PM PDT 24 Jul 18 08:34:12 PM PDT 24 5417932744 ps
T1386 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2172396771 Jul 18 08:35:31 PM PDT 24 Jul 18 08:45:03 PM PDT 24 6682968470 ps
T1387 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1922019373 Jul 18 08:17:13 PM PDT 24 Jul 18 08:24:29 PM PDT 24 3823689728 ps
T1388 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1170544895 Jul 18 08:22:00 PM PDT 24 Jul 18 08:41:12 PM PDT 24 8139243490 ps
T1389 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4039656828 Jul 18 08:32:41 PM PDT 24 Jul 18 08:37:10 PM PDT 24 3579751128 ps
T155 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2674169595 Jul 18 08:13:15 PM PDT 24 Jul 18 08:57:47 PM PDT 24 11953259150 ps
T1390 /workspace/coverage/default/0.chip_sw_aes_idle.2138000011 Jul 18 08:14:09 PM PDT 24 Jul 18 08:19:22 PM PDT 24 2085878472 ps
T1391 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2759145879 Jul 18 08:14:37 PM PDT 24 Jul 18 08:19:40 PM PDT 24 2424576896 ps
T1392 /workspace/coverage/default/1.chip_sw_aes_masking_off.3716148293 Jul 18 08:21:49 PM PDT 24 Jul 18 08:27:31 PM PDT 24 2705389201 ps
T1393 /workspace/coverage/default/20.chip_sw_all_escalation_resets.1153051919 Jul 18 08:44:18 PM PDT 24 Jul 18 08:51:29 PM PDT 24 4411770848 ps
T1394 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2245603964 Jul 18 08:21:12 PM PDT 24 Jul 18 08:31:00 PM PDT 24 4544203031 ps
T1395 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1807829502 Jul 18 08:23:30 PM PDT 24 Jul 18 08:38:25 PM PDT 24 8279788128 ps
T1396 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3506045851 Jul 18 08:45:48 PM PDT 24 Jul 18 08:54:23 PM PDT 24 4048746102 ps
T1397 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3670275800 Jul 18 08:22:28 PM PDT 24 Jul 18 08:27:32 PM PDT 24 2392374954 ps
T1398 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.208297281 Jul 18 08:16:09 PM PDT 24 Jul 18 08:44:57 PM PDT 24 9328877461 ps
T1399 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1184473751 Jul 18 08:49:25 PM PDT 24 Jul 18 09:01:11 PM PDT 24 5355524700 ps
T1400 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.180201810 Jul 18 08:43:28 PM PDT 24 Jul 18 08:59:56 PM PDT 24 13899175847 ps
T1401 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2741853373 Jul 18 08:36:07 PM PDT 24 Jul 18 08:45:28 PM PDT 24 4749486488 ps
T1402 /workspace/coverage/default/86.chip_sw_all_escalation_resets.69218733 Jul 18 08:49:40 PM PDT 24 Jul 18 08:56:58 PM PDT 24 4998649534 ps
T377 /workspace/coverage/default/33.chip_sw_all_escalation_resets.4048872517 Jul 18 08:46:15 PM PDT 24 Jul 18 08:54:19 PM PDT 24 5535003760 ps
T1403 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2005904121 Jul 18 08:14:16 PM PDT 24 Jul 18 08:44:47 PM PDT 24 21550632596 ps
T851 /workspace/coverage/default/47.chip_sw_all_escalation_resets.670845062 Jul 18 08:55:53 PM PDT 24 Jul 18 09:06:01 PM PDT 24 5055570134 ps
T80 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2440083114 Jul 18 08:12:57 PM PDT 24 Jul 18 10:14:12 PM PDT 24 31871990782 ps
T1404 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1663718019 Jul 18 08:39:33 PM PDT 24 Jul 18 08:46:53 PM PDT 24 3093247516 ps
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