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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.41 92.69 82.60 90.58 94.43 97.53 84.65


Total test records in report: 1018
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T310 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3943186387 Jul 19 06:41:40 PM PDT 24 Jul 19 06:50:20 PM PDT 24 4742425200 ps
T577 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2671751737 Jul 19 06:50:19 PM PDT 24 Jul 19 07:17:14 PM PDT 24 10725280843 ps
T276 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.398832125 Jul 19 06:49:43 PM PDT 24 Jul 19 07:00:24 PM PDT 24 6498845980 ps
T431 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.921575548 Jul 19 06:58:21 PM PDT 24 Jul 19 07:13:24 PM PDT 24 4993307281 ps
T578 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4018007098 Jul 19 06:53:21 PM PDT 24 Jul 19 06:56:48 PM PDT 24 2210290555 ps
T56 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1817621183 Jul 19 06:45:06 PM PDT 24 Jul 19 07:50:04 PM PDT 24 14820542514 ps
T579 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.884611865 Jul 19 06:44:53 PM PDT 24 Jul 19 06:59:38 PM PDT 24 5404984106 ps
T481 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.535250727 Jul 19 07:09:15 PM PDT 24 Jul 19 07:15:57 PM PDT 24 3180109640 ps
T580 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2533572986 Jul 19 06:55:19 PM PDT 24 Jul 19 07:13:56 PM PDT 24 6001359578 ps
T84 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.533018120 Jul 19 07:00:29 PM PDT 24 Jul 19 07:55:45 PM PDT 24 16737973607 ps
T253 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.2931187884 Jul 19 06:53:08 PM PDT 24 Jul 19 10:07:55 PM PDT 24 63284697473 ps
T374 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3278356701 Jul 19 07:09:39 PM PDT 24 Jul 19 07:16:12 PM PDT 24 3538973500 ps
T581 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2429403871 Jul 19 06:58:00 PM PDT 24 Jul 19 07:02:09 PM PDT 24 2486513160 ps
T229 /workspace/coverage/default/1.chip_plic_all_irqs_0.3256851836 Jul 19 06:46:09 PM PDT 24 Jul 19 07:04:53 PM PDT 24 5997020044 ps
T582 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2531393603 Jul 19 06:59:51 PM PDT 24 Jul 19 07:09:04 PM PDT 24 4454682750 ps
T48 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.880418069 Jul 19 06:42:38 PM PDT 24 Jul 19 06:49:39 PM PDT 24 6187178000 ps
T204 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2598548865 Jul 19 06:46:51 PM PDT 24 Jul 19 06:55:42 PM PDT 24 9055610542 ps
T583 /workspace/coverage/default/1.chip_tap_straps_rma.1054873356 Jul 19 06:48:51 PM PDT 24 Jul 19 06:52:01 PM PDT 24 3474802272 ps
T392 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2490313478 Jul 19 07:00:35 PM PDT 24 Jul 19 07:05:44 PM PDT 24 2227070451 ps
T584 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3578778704 Jul 19 06:48:07 PM PDT 24 Jul 19 06:55:24 PM PDT 24 4095450800 ps
T390 /workspace/coverage/default/1.chip_sival_flash_info_access.685773333 Jul 19 06:43:04 PM PDT 24 Jul 19 06:48:51 PM PDT 24 3160552548 ps
T489 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422948120 Jul 19 07:04:51 PM PDT 24 Jul 19 07:13:18 PM PDT 24 3644668660 ps
T461 /workspace/coverage/default/70.chip_sw_all_escalation_resets.236193874 Jul 19 07:11:05 PM PDT 24 Jul 19 07:21:54 PM PDT 24 4866136488 ps
T184 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3277349194 Jul 19 06:40:57 PM PDT 24 Jul 19 08:24:41 PM PDT 24 46303295570 ps
T398 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4187787297 Jul 19 06:58:17 PM PDT 24 Jul 19 07:03:00 PM PDT 24 3262847903 ps
T585 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.224385236 Jul 19 07:02:48 PM PDT 24 Jul 19 07:09:33 PM PDT 24 3111425160 ps
T82 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3056151656 Jul 19 06:56:56 PM PDT 24 Jul 19 07:17:13 PM PDT 24 5708683832 ps
T586 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2432056919 Jul 19 06:40:55 PM PDT 24 Jul 19 07:01:06 PM PDT 24 13911609038 ps
T482 /workspace/coverage/default/87.chip_sw_all_escalation_resets.199533931 Jul 19 07:14:13 PM PDT 24 Jul 19 07:25:16 PM PDT 24 4949673162 ps
T166 /workspace/coverage/default/2.rom_raw_unlock.2241896264 Jul 19 07:00:26 PM PDT 24 Jul 19 07:04:59 PM PDT 24 6463041051 ps
T460 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.664451224 Jul 19 07:05:54 PM PDT 24 Jul 19 07:11:40 PM PDT 24 3258843244 ps
T9 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2988204626 Jul 19 06:58:55 PM PDT 24 Jul 19 07:26:51 PM PDT 24 26057210552 ps
T587 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.793768004 Jul 19 06:58:01 PM PDT 24 Jul 19 07:08:46 PM PDT 24 6550765130 ps
T588 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3383714376 Jul 19 07:04:17 PM PDT 24 Jul 19 07:39:51 PM PDT 24 8998384620 ps
T449 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3759982099 Jul 19 06:54:39 PM PDT 24 Jul 19 06:57:44 PM PDT 24 2490854651 ps
T325 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1471957838 Jul 19 06:43:12 PM PDT 24 Jul 19 06:49:59 PM PDT 24 3996363780 ps
T589 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1505650238 Jul 19 06:56:45 PM PDT 24 Jul 19 07:00:07 PM PDT 24 2733850122 ps
T590 /workspace/coverage/default/1.chip_sw_kmac_entropy.2850971062 Jul 19 06:42:16 PM PDT 24 Jul 19 06:47:03 PM PDT 24 2761684368 ps
T195 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.224272947 Jul 19 06:38:05 PM PDT 24 Jul 19 08:35:24 PM PDT 24 45144590500 ps
T457 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3188277407 Jul 19 07:10:52 PM PDT 24 Jul 19 07:17:18 PM PDT 24 3604921154 ps
T284 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.253759411 Jul 19 06:52:47 PM PDT 24 Jul 19 06:56:49 PM PDT 24 3266021316 ps
T299 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3838868254 Jul 19 06:47:29 PM PDT 24 Jul 19 08:45:45 PM PDT 24 24106695704 ps
T591 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3051782274 Jul 19 06:57:21 PM PDT 24 Jul 19 07:05:46 PM PDT 24 6538782889 ps
T375 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302870110 Jul 19 07:08:41 PM PDT 24 Jul 19 07:15:35 PM PDT 24 3729834456 ps
T474 /workspace/coverage/default/93.chip_sw_all_escalation_resets.641711386 Jul 19 07:11:29 PM PDT 24 Jul 19 07:21:25 PM PDT 24 5203655248 ps
T592 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1784373603 Jul 19 06:41:50 PM PDT 24 Jul 19 06:59:46 PM PDT 24 5670737482 ps
T479 /workspace/coverage/default/0.chip_sw_edn_kat.3730972360 Jul 19 06:39:19 PM PDT 24 Jul 19 06:48:56 PM PDT 24 3417684188 ps
T388 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2380698835 Jul 19 06:54:47 PM PDT 24 Jul 19 07:07:59 PM PDT 24 4687281703 ps
T593 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.231773560 Jul 19 06:39:22 PM PDT 24 Jul 19 06:51:46 PM PDT 24 8969504952 ps
T594 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3657786843 Jul 19 06:42:46 PM PDT 24 Jul 19 06:47:15 PM PDT 24 3080243966 ps
T189 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1518631848 Jul 19 06:49:50 PM PDT 24 Jul 19 06:54:34 PM PDT 24 3072988194 ps
T227 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1717369429 Jul 19 07:14:20 PM PDT 24 Jul 19 07:24:17 PM PDT 24 4590630524 ps
T425 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4104573107 Jul 19 07:03:16 PM PDT 24 Jul 19 07:14:26 PM PDT 24 3753918344 ps
T426 /workspace/coverage/default/1.chip_tap_straps_dev.440174316 Jul 19 06:49:39 PM PDT 24 Jul 19 07:23:38 PM PDT 24 18147565456 ps
T427 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334557720 Jul 19 06:45:17 PM PDT 24 Jul 19 06:52:27 PM PDT 24 3513942250 ps
T428 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.23224300 Jul 19 06:41:54 PM PDT 24 Jul 19 06:47:01 PM PDT 24 3031789179 ps
T429 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.753539999 Jul 19 06:43:26 PM PDT 24 Jul 19 06:52:42 PM PDT 24 5388691980 ps
T341 /workspace/coverage/default/1.chip_sw_flash_init.1277975233 Jul 19 06:40:10 PM PDT 24 Jul 19 07:19:18 PM PDT 24 22219696328 ps
T275 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2173551397 Jul 19 06:55:33 PM PDT 24 Jul 19 07:06:35 PM PDT 24 4936528400 ps
T37 /workspace/coverage/default/2.chip_sw_gpio.3647046582 Jul 19 06:54:22 PM PDT 24 Jul 19 07:03:58 PM PDT 24 4889086824 ps
T363 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.826876293 Jul 19 06:45:06 PM PDT 24 Jul 19 07:07:21 PM PDT 24 8691368556 ps
T262 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3537680296 Jul 19 07:07:55 PM PDT 24 Jul 19 07:15:23 PM PDT 24 3525143272 ps
T595 /workspace/coverage/default/1.chip_sw_aes_entropy.62878365 Jul 19 06:45:40 PM PDT 24 Jul 19 06:49:58 PM PDT 24 2890594140 ps
T596 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3299340994 Jul 19 06:40:07 PM PDT 24 Jul 19 06:43:02 PM PDT 24 2727733104 ps
T243 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2358652797 Jul 19 06:42:56 PM PDT 24 Jul 19 07:17:28 PM PDT 24 8098824020 ps
T287 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3069867509 Jul 19 06:43:17 PM PDT 24 Jul 19 06:54:59 PM PDT 24 5886698400 ps
T389 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4062231667 Jul 19 06:40:30 PM PDT 24 Jul 19 06:52:45 PM PDT 24 4817082134 ps
T597 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2649339021 Jul 19 07:03:29 PM PDT 24 Jul 19 07:31:31 PM PDT 24 7982243040 ps
T288 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2680513282 Jul 19 07:08:34 PM PDT 24 Jul 19 07:19:02 PM PDT 24 5436931768 ps
T233 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3026935172 Jul 19 06:40:33 PM PDT 24 Jul 19 07:06:53 PM PDT 24 13209591094 ps
T598 /workspace/coverage/default/0.chip_sw_aes_smoketest.1228095483 Jul 19 06:40:13 PM PDT 24 Jul 19 06:45:04 PM PDT 24 2870246080 ps
T226 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3492662585 Jul 19 06:44:54 PM PDT 24 Jul 19 10:12:03 PM PDT 24 255205825048 ps
T599 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.848020492 Jul 19 06:53:24 PM PDT 24 Jul 19 07:03:54 PM PDT 24 4477487110 ps
T354 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.348261250 Jul 19 06:47:19 PM PDT 24 Jul 19 06:56:49 PM PDT 24 18078119380 ps
T505 /workspace/coverage/default/88.chip_sw_all_escalation_resets.4009513218 Jul 19 07:10:11 PM PDT 24 Jul 19 07:18:02 PM PDT 24 4704580402 ps
T600 /workspace/coverage/default/0.rom_e2e_asm_init_rma.2302281923 Jul 19 06:49:36 PM PDT 24 Jul 19 07:55:22 PM PDT 24 14910935697 ps
T38 /workspace/coverage/default/1.chip_sw_gpio.637468281 Jul 19 06:47:39 PM PDT 24 Jul 19 06:55:25 PM PDT 24 4167642880 ps
T202 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1182572261 Jul 19 06:40:43 PM PDT 24 Jul 19 07:28:04 PM PDT 24 31915975255 ps
T29 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4131755134 Jul 19 06:41:47 PM PDT 24 Jul 19 06:50:28 PM PDT 24 4395255286 ps
T601 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2536318611 Jul 19 06:44:59 PM PDT 24 Jul 19 08:03:32 PM PDT 24 14380271184 ps
T602 /workspace/coverage/default/1.rom_e2e_static_critical.383035431 Jul 19 07:03:22 PM PDT 24 Jul 19 08:14:00 PM PDT 24 17291036456 ps
T603 /workspace/coverage/default/2.chip_sw_edn_kat.589156530 Jul 19 06:58:03 PM PDT 24 Jul 19 07:11:44 PM PDT 24 3399382740 ps
T255 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2316268276 Jul 19 06:55:29 PM PDT 24 Jul 19 07:07:58 PM PDT 24 5434417571 ps
T269 /workspace/coverage/default/1.chip_sw_plic_sw_irq.1124476363 Jul 19 06:46:44 PM PDT 24 Jul 19 06:50:13 PM PDT 24 2261823316 ps
T604 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2630685547 Jul 19 06:48:07 PM PDT 24 Jul 19 07:38:41 PM PDT 24 10943161386 ps
T85 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3879634470 Jul 19 06:39:08 PM PDT 24 Jul 19 07:56:12 PM PDT 24 26005728887 ps
T462 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2846773116 Jul 19 07:09:02 PM PDT 24 Jul 19 07:20:18 PM PDT 24 5036236118 ps
T605 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2968230896 Jul 19 06:48:18 PM PDT 24 Jul 19 06:57:38 PM PDT 24 5207476940 ps
T64 /workspace/coverage/default/0.chip_jtag_csr_rw.552193988 Jul 19 06:31:28 PM PDT 24 Jul 19 06:58:08 PM PDT 24 10537695960 ps
T111 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3270179782 Jul 19 06:42:42 PM PDT 24 Jul 19 06:48:12 PM PDT 24 3603602625 ps
T606 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2689295884 Jul 19 06:54:51 PM PDT 24 Jul 19 07:17:12 PM PDT 24 5312714608 ps
T117 /workspace/coverage/default/2.chip_jtag_csr_rw.1792809725 Jul 19 06:51:27 PM PDT 24 Jul 19 07:09:52 PM PDT 24 9363328010 ps
T607 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3676934308 Jul 19 06:39:07 PM PDT 24 Jul 19 06:43:27 PM PDT 24 3087997519 ps
T376 /workspace/coverage/default/4.chip_sw_uart_tx_rx.1972590350 Jul 19 07:04:38 PM PDT 24 Jul 19 07:16:30 PM PDT 24 3497780420 ps
T358 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.697051588 Jul 19 06:38:42 PM PDT 24 Jul 19 06:49:26 PM PDT 24 3754543592 ps
T205 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2364930201 Jul 19 06:59:27 PM PDT 24 Jul 19 07:05:06 PM PDT 24 2366376880 ps
T466 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590274255 Jul 19 07:09:12 PM PDT 24 Jul 19 07:15:55 PM PDT 24 4089867880 ps
T454 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1239278733 Jul 19 07:07:58 PM PDT 24 Jul 19 07:17:06 PM PDT 24 5044691602 ps
T176 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1214682039 Jul 19 06:40:34 PM PDT 24 Jul 19 06:48:27 PM PDT 24 4278431658 ps
T608 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2303319130 Jul 19 06:55:20 PM PDT 24 Jul 19 07:34:44 PM PDT 24 35633297424 ps
T609 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2457681530 Jul 19 07:06:59 PM PDT 24 Jul 19 08:14:33 PM PDT 24 15648499420 ps
T36 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.622553416 Jul 19 06:55:31 PM PDT 24 Jul 19 07:02:28 PM PDT 24 3385821250 ps
T413 /workspace/coverage/default/86.chip_sw_all_escalation_resets.3818373254 Jul 19 07:14:06 PM PDT 24 Jul 19 07:23:36 PM PDT 24 4523790040 ps
T610 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1171812822 Jul 19 06:46:55 PM PDT 24 Jul 19 07:50:17 PM PDT 24 13944739108 ps
T127 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2967296666 Jul 19 07:04:08 PM PDT 24 Jul 19 07:13:43 PM PDT 24 5481524592 ps
T135 /workspace/coverage/default/0.chip_sw_aes_enc.4259247720 Jul 19 06:42:01 PM PDT 24 Jul 19 06:47:11 PM PDT 24 3074924044 ps
T136 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2139222005 Jul 19 06:43:56 PM PDT 24 Jul 19 06:57:26 PM PDT 24 4955100116 ps
T133 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.660748518 Jul 19 07:07:56 PM PDT 24 Jul 19 07:15:05 PM PDT 24 3895496264 ps
T137 /workspace/coverage/default/0.chip_tap_straps_dev.809811459 Jul 19 06:41:05 PM PDT 24 Jul 19 06:43:54 PM PDT 24 3073879940 ps
T138 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1372448239 Jul 19 07:01:47 PM PDT 24 Jul 19 07:10:22 PM PDT 24 3103828200 ps
T139 /workspace/coverage/default/1.chip_sw_example_flash.4134881436 Jul 19 06:41:03 PM PDT 24 Jul 19 06:43:53 PM PDT 24 2945136430 ps
T140 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3762785602 Jul 19 07:04:30 PM PDT 24 Jul 19 07:15:44 PM PDT 24 5000068542 ps
T141 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031565725 Jul 19 07:06:13 PM PDT 24 Jul 19 07:14:08 PM PDT 24 4229274120 ps
T142 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2014736738 Jul 19 07:10:27 PM PDT 24 Jul 19 07:17:51 PM PDT 24 3703665416 ps
T240 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2839223969 Jul 19 06:54:37 PM PDT 24 Jul 19 07:09:15 PM PDT 24 5185845544 ps
T539 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1648334229 Jul 19 07:08:03 PM PDT 24 Jul 19 07:12:48 PM PDT 24 3919721400 ps
T169 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115889355 Jul 19 07:08:54 PM PDT 24 Jul 19 07:15:01 PM PDT 24 3496319888 ps
T471 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3190820702 Jul 19 07:04:54 PM PDT 24 Jul 19 07:15:49 PM PDT 24 5579413968 ps
T611 /workspace/coverage/default/1.chip_sw_uart_smoketest.3545043458 Jul 19 06:52:45 PM PDT 24 Jul 19 06:57:39 PM PDT 24 2903991916 ps
T311 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3183971675 Jul 19 06:44:08 PM PDT 24 Jul 19 06:50:31 PM PDT 24 3935987486 ps
T612 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.879460536 Jul 19 06:56:55 PM PDT 24 Jul 19 08:08:59 PM PDT 24 19047253446 ps
T529 /workspace/coverage/default/67.chip_sw_all_escalation_resets.472496839 Jul 19 07:11:12 PM PDT 24 Jul 19 07:21:58 PM PDT 24 5164961152 ps
T463 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741445742 Jul 19 07:11:28 PM PDT 24 Jul 19 07:17:45 PM PDT 24 3591852500 ps
T613 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3607305014 Jul 19 06:45:20 PM PDT 24 Jul 19 08:08:52 PM PDT 24 15032328948 ps
T614 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.480300533 Jul 19 06:50:09 PM PDT 24 Jul 19 08:07:13 PM PDT 24 14589515320 ps
T615 /workspace/coverage/default/0.rom_e2e_smoke.2661822056 Jul 19 06:47:26 PM PDT 24 Jul 19 08:04:44 PM PDT 24 15567989058 ps
T616 /workspace/coverage/default/0.chip_sw_kmac_smoketest.4003501636 Jul 19 06:41:08 PM PDT 24 Jul 19 06:45:43 PM PDT 24 3167560316 ps
T617 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4100048087 Jul 19 07:03:17 PM PDT 24 Jul 19 07:30:43 PM PDT 24 9432159639 ps
T618 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1456842833 Jul 19 07:10:56 PM PDT 24 Jul 19 07:17:20 PM PDT 24 3475377600 ps
T450 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1449644392 Jul 19 06:57:25 PM PDT 24 Jul 19 06:59:22 PM PDT 24 1945249467 ps
T619 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3880060129 Jul 19 06:45:05 PM PDT 24 Jul 19 07:50:31 PM PDT 24 14260029260 ps
T620 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1605813467 Jul 19 06:42:04 PM PDT 24 Jul 19 06:51:56 PM PDT 24 4091598494 ps
T206 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1246525182 Jul 19 06:56:53 PM PDT 24 Jul 19 07:07:44 PM PDT 24 9600101182 ps
T621 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3768096802 Jul 19 07:01:34 PM PDT 24 Jul 19 07:11:44 PM PDT 24 6138767265 ps
T622 /workspace/coverage/default/1.chip_sw_example_rom.4131123801 Jul 19 06:46:24 PM PDT 24 Jul 19 06:48:16 PM PDT 24 2189727016 ps
T623 /workspace/coverage/default/0.chip_tap_straps_prod.2680033258 Jul 19 06:43:32 PM PDT 24 Jul 19 07:03:42 PM PDT 24 10781556612 ps
T624 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4272768432 Jul 19 06:40:12 PM PDT 24 Jul 19 06:49:45 PM PDT 24 6442002080 ps
T472 /workspace/coverage/default/42.chip_sw_all_escalation_resets.460270837 Jul 19 07:07:52 PM PDT 24 Jul 19 07:19:14 PM PDT 24 4363430222 ps
T280 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2930368768 Jul 19 06:43:28 PM PDT 24 Jul 19 08:40:47 PM PDT 24 24296644040 ps
T239 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.421118965 Jul 19 06:39:34 PM PDT 24 Jul 19 06:46:56 PM PDT 24 4083733776 ps
T625 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1656574601 Jul 19 06:52:41 PM PDT 24 Jul 19 07:19:44 PM PDT 24 9343666450 ps
T626 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.63715599 Jul 19 06:39:48 PM PDT 24 Jul 19 07:48:01 PM PDT 24 18628084486 ps
T485 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4084854581 Jul 19 07:06:50 PM PDT 24 Jul 19 07:12:58 PM PDT 24 3797530630 ps
T490 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.385432254 Jul 19 06:42:21 PM PDT 24 Jul 19 06:48:55 PM PDT 24 3291270720 ps
T395 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3454214659 Jul 19 06:56:54 PM PDT 24 Jul 19 07:03:34 PM PDT 24 3382811952 ps
T451 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1127877894 Jul 19 06:41:52 PM PDT 24 Jul 19 06:43:59 PM PDT 24 2568655224 ps
T326 /workspace/coverage/default/1.chip_sw_power_sleep_load.3969123024 Jul 19 06:52:57 PM PDT 24 Jul 19 07:04:41 PM PDT 24 10195576944 ps
T627 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1431097363 Jul 19 06:53:07 PM PDT 24 Jul 19 07:00:59 PM PDT 24 3440941092 ps
T628 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1164898388 Jul 19 07:08:57 PM PDT 24 Jul 19 07:17:00 PM PDT 24 3385287692 ps
T270 /workspace/coverage/default/0.chip_sw_power_sleep_load.2314943249 Jul 19 06:39:21 PM PDT 24 Jul 19 06:46:42 PM PDT 24 4615485236 ps
T143 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1276891368 Jul 19 06:40:05 PM PDT 24 Jul 19 07:12:37 PM PDT 24 23002008914 ps
T629 /workspace/coverage/default/1.chip_sw_example_concurrency.2897595198 Jul 19 06:40:52 PM PDT 24 Jul 19 06:43:51 PM PDT 24 2385386344 ps
T630 /workspace/coverage/default/0.chip_tap_straps_rma.3530968151 Jul 19 06:39:40 PM PDT 24 Jul 19 06:43:04 PM PDT 24 2762411054 ps
T467 /workspace/coverage/default/21.chip_sw_all_escalation_resets.361036854 Jul 19 07:05:21 PM PDT 24 Jul 19 07:13:17 PM PDT 24 4844999292 ps
T414 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.700897323 Jul 19 07:08:32 PM PDT 24 Jul 19 07:14:07 PM PDT 24 3316278928 ps
T631 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.603496039 Jul 19 06:59:50 PM PDT 24 Jul 19 07:12:25 PM PDT 24 5901334617 ps
T632 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.4225848807 Jul 19 06:46:05 PM PDT 24 Jul 19 07:13:37 PM PDT 24 7533563190 ps
T487 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.979850943 Jul 19 07:09:37 PM PDT 24 Jul 19 07:17:13 PM PDT 24 3554149720 ps
T633 /workspace/coverage/default/2.rom_e2e_smoke.2631773179 Jul 19 07:08:02 PM PDT 24 Jul 19 08:04:56 PM PDT 24 14706426220 ps
T478 /workspace/coverage/default/41.chip_sw_all_escalation_resets.250292028 Jul 19 07:08:18 PM PDT 24 Jul 19 07:21:16 PM PDT 24 6059354936 ps
T634 /workspace/coverage/default/0.chip_sw_example_flash.151080391 Jul 19 06:38:21 PM PDT 24 Jul 19 06:42:38 PM PDT 24 2865309166 ps
T635 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1353810179 Jul 19 07:05:33 PM PDT 24 Jul 19 07:17:19 PM PDT 24 4348952560 ps
T447 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2317565489 Jul 19 06:39:42 PM PDT 24 Jul 19 06:49:08 PM PDT 24 4771075478 ps
T636 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.515286327 Jul 19 06:39:36 PM PDT 24 Jul 19 07:35:48 PM PDT 24 12568790120 ps
T637 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1281580364 Jul 19 06:58:20 PM PDT 24 Jul 19 07:28:39 PM PDT 24 9331530428 ps
T491 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4085533151 Jul 19 07:05:24 PM PDT 24 Jul 19 07:13:01 PM PDT 24 3368673580 ps
T638 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2264817075 Jul 19 06:56:53 PM PDT 24 Jul 19 08:11:09 PM PDT 24 15549383240 ps
T639 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.163261238 Jul 19 07:05:56 PM PDT 24 Jul 19 07:17:00 PM PDT 24 5831930377 ps
T640 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1519709905 Jul 19 06:43:39 PM PDT 24 Jul 19 06:53:59 PM PDT 24 4134672152 ps
T641 /workspace/coverage/default/1.rom_e2e_smoke.6577281 Jul 19 06:57:23 PM PDT 24 Jul 19 08:06:57 PM PDT 24 15235263736 ps
T642 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.408288092 Jul 19 06:55:18 PM PDT 24 Jul 19 07:00:11 PM PDT 24 3167307541 ps
T643 /workspace/coverage/default/1.chip_sw_edn_sw_mode.1347472814 Jul 19 06:45:21 PM PDT 24 Jul 19 07:11:10 PM PDT 24 6577911976 ps
T13 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2481333563 Jul 19 06:41:38 PM PDT 24 Jul 19 06:48:44 PM PDT 24 4987531940 ps
T644 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.876220114 Jul 19 06:45:19 PM PDT 24 Jul 19 07:01:00 PM PDT 24 7263607984 ps
T171 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3313816361 Jul 19 06:42:43 PM PDT 24 Jul 19 06:47:28 PM PDT 24 2966457729 ps
T645 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3530398983 Jul 19 07:04:26 PM PDT 24 Jul 19 07:22:08 PM PDT 24 8637999241 ps
T221 /workspace/coverage/default/0.chip_jtag_mem_access.3868305883 Jul 19 06:31:21 PM PDT 24 Jul 19 06:54:10 PM PDT 24 13618617564 ps
T254 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3987414974 Jul 19 06:40:46 PM PDT 24 Jul 19 09:37:18 PM PDT 24 57016060256 ps
T646 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.367401289 Jul 19 06:38:43 PM PDT 24 Jul 19 06:56:14 PM PDT 24 6064971470 ps
T330 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.663757734 Jul 19 06:55:56 PM PDT 24 Jul 19 07:03:39 PM PDT 24 3964066722 ps
T647 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2324124389 Jul 19 06:41:25 PM PDT 24 Jul 19 06:54:44 PM PDT 24 3879749408 ps
T648 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.652693529 Jul 19 06:55:46 PM PDT 24 Jul 19 07:11:16 PM PDT 24 5342878290 ps
T649 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3672233017 Jul 19 06:58:14 PM PDT 24 Jul 19 07:02:03 PM PDT 24 2781414488 ps
T237 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.787662383 Jul 19 06:41:37 PM PDT 24 Jul 19 06:55:51 PM PDT 24 5190203850 ps
T53 /workspace/coverage/default/1.chip_sw_spi_device_tpm.692613251 Jul 19 06:41:13 PM PDT 24 Jul 19 06:47:56 PM PDT 24 3638243905 ps
T525 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2820777608 Jul 19 07:11:14 PM PDT 24 Jul 19 07:22:33 PM PDT 24 5137577150 ps
T650 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4221382232 Jul 19 06:40:55 PM PDT 24 Jul 19 06:44:39 PM PDT 24 2668593407 ps
T651 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3397197373 Jul 19 07:02:46 PM PDT 24 Jul 19 07:07:47 PM PDT 24 3470059159 ps
T532 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108955999 Jul 19 07:08:44 PM PDT 24 Jul 19 07:14:11 PM PDT 24 4174864850 ps
T652 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2188432975 Jul 19 07:04:06 PM PDT 24 Jul 19 07:38:25 PM PDT 24 8741337464 ps
T653 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3730249287 Jul 19 06:38:52 PM PDT 24 Jul 19 06:47:29 PM PDT 24 9942316173 ps
T409 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3468797537 Jul 19 06:59:59 PM PDT 24 Jul 19 07:12:00 PM PDT 24 6245005700 ps
T654 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2733502597 Jul 19 06:47:46 PM PDT 24 Jul 19 07:48:33 PM PDT 24 20522161811 ps
T655 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2973237808 Jul 19 06:45:38 PM PDT 24 Jul 19 07:08:17 PM PDT 24 7823044060 ps
T656 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1507367367 Jul 19 06:40:09 PM PDT 24 Jul 19 06:44:37 PM PDT 24 2592088088 ps
T512 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3228176915 Jul 19 07:11:02 PM PDT 24 Jul 19 07:20:32 PM PDT 24 4348337256 ps
T657 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.92839639 Jul 19 06:41:00 PM PDT 24 Jul 19 06:58:08 PM PDT 24 6465079830 ps
T339 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3868826360 Jul 19 06:50:09 PM PDT 24 Jul 19 07:22:50 PM PDT 24 25555905757 ps
T658 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3326860475 Jul 19 06:39:27 PM PDT 24 Jul 19 06:44:02 PM PDT 24 2870861564 ps
T128 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.783067399 Jul 19 07:08:57 PM PDT 24 Jul 19 07:15:16 PM PDT 24 3329819172 ps
T659 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2009559060 Jul 19 06:53:26 PM PDT 24 Jul 19 07:06:12 PM PDT 24 4935571628 ps
T660 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3885058724 Jul 19 06:39:42 PM PDT 24 Jul 19 06:59:38 PM PDT 24 5676202752 ps
T661 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1156486551 Jul 19 06:40:17 PM PDT 24 Jul 19 07:00:20 PM PDT 24 6865368959 ps
T134 /workspace/coverage/default/45.chip_sw_all_escalation_resets.1327903404 Jul 19 07:07:45 PM PDT 24 Jul 19 07:17:51 PM PDT 24 5865250942 ps
T662 /workspace/coverage/default/1.chip_sw_csrng_kat_test.1567349305 Jul 19 06:47:42 PM PDT 24 Jul 19 06:52:41 PM PDT 24 2766760104 ps
T483 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.187216194 Jul 19 06:40:40 PM PDT 24 Jul 19 06:52:00 PM PDT 24 4843259864 ps
T407 /workspace/coverage/default/7.chip_sw_all_escalation_resets.946892940 Jul 19 07:04:05 PM PDT 24 Jul 19 07:12:30 PM PDT 24 6226375672 ps
T663 /workspace/coverage/default/2.chip_tap_straps_prod.1362974746 Jul 19 06:59:50 PM PDT 24 Jul 19 07:29:42 PM PDT 24 17431370924 ps
T162 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.17635516 Jul 19 06:59:55 PM PDT 24 Jul 19 07:23:56 PM PDT 24 13410408912 ps
T664 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2781659636 Jul 19 06:44:52 PM PDT 24 Jul 19 06:55:01 PM PDT 24 8452991160 ps
T665 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.436363926 Jul 19 06:53:47 PM PDT 24 Jul 19 07:14:15 PM PDT 24 8854444550 ps
T94 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2908158092 Jul 19 06:46:27 PM PDT 24 Jul 19 07:07:04 PM PDT 24 8975009852 ps
T531 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690797726 Jul 19 07:06:23 PM PDT 24 Jul 19 07:14:48 PM PDT 24 4140714060 ps
T190 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.116655921 Jul 19 06:40:43 PM PDT 24 Jul 19 06:52:55 PM PDT 24 7199604563 ps
T666 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1148143643 Jul 19 06:47:25 PM PDT 24 Jul 19 06:56:33 PM PDT 24 7200626560 ps
T362 /workspace/coverage/default/0.chip_sw_pattgen_ios.2903724442 Jul 19 06:42:14 PM PDT 24 Jul 19 06:47:50 PM PDT 24 2791355400 ps
T667 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.713498727 Jul 19 06:59:32 PM PDT 24 Jul 19 07:05:53 PM PDT 24 2837347760 ps
T668 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2827316284 Jul 19 06:40:58 PM PDT 24 Jul 19 07:16:00 PM PDT 24 9572219450 ps
T669 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.871956431 Jul 19 06:57:10 PM PDT 24 Jul 19 07:10:33 PM PDT 24 5272188468 ps
T670 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2347407324 Jul 19 07:08:24 PM PDT 24 Jul 19 07:11:09 PM PDT 24 2344430676 ps
T384 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3498545566 Jul 19 07:00:31 PM PDT 24 Jul 19 07:09:29 PM PDT 24 4002649960 ps
T365 /workspace/coverage/default/1.rom_raw_unlock.2159377866 Jul 19 06:57:33 PM PDT 24 Jul 19 07:02:27 PM PDT 24 4556510935 ps
T671 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2646574234 Jul 19 06:43:12 PM PDT 24 Jul 19 07:05:12 PM PDT 24 8106672668 ps
T357 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2822577417 Jul 19 06:40:46 PM PDT 24 Jul 19 07:18:43 PM PDT 24 11370460682 ps
T672 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4058076639 Jul 19 06:51:46 PM PDT 24 Jul 19 06:56:50 PM PDT 24 2160109284 ps
T157 /workspace/coverage/default/2.chip_plic_all_irqs_20.2340719258 Jul 19 06:58:35 PM PDT 24 Jul 19 07:11:07 PM PDT 24 4841353694 ps
T673 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3073304762 Jul 19 06:56:00 PM PDT 24 Jul 19 07:06:10 PM PDT 24 4387083028 ps
T343 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3578801826 Jul 19 06:39:47 PM PDT 24 Jul 19 06:48:18 PM PDT 24 5251989700 ps
T513 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277518861 Jul 19 07:07:47 PM PDT 24 Jul 19 07:15:02 PM PDT 24 3430136920 ps
T674 /workspace/coverage/default/0.chip_sw_coremark.298796539 Jul 19 06:42:23 PM PDT 24 Jul 19 11:23:55 PM PDT 24 71716842464 ps
T191 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3761100646 Jul 19 07:01:00 PM PDT 24 Jul 19 07:06:44 PM PDT 24 2618149904 ps
T675 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1481434918 Jul 19 06:39:51 PM PDT 24 Jul 19 06:48:59 PM PDT 24 7334525495 ps
T439 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1846285550 Jul 19 07:00:40 PM PDT 24 Jul 19 07:05:55 PM PDT 24 5967322656 ps
T676 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.870693960 Jul 19 06:44:47 PM PDT 24 Jul 19 06:50:13 PM PDT 24 2725919756 ps
T677 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1814867630 Jul 19 06:40:32 PM PDT 24 Jul 19 06:47:27 PM PDT 24 4059513800 ps
T129 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1794592604 Jul 19 06:43:57 PM PDT 24 Jul 19 07:08:44 PM PDT 24 12285033070 ps
T502 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824238013 Jul 19 07:09:23 PM PDT 24 Jul 19 07:16:02 PM PDT 24 3972388180 ps
T678 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.434535696 Jul 19 06:53:55 PM PDT 24 Jul 19 07:01:20 PM PDT 24 3429374024 ps
T679 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1373410928 Jul 19 07:04:01 PM PDT 24 Jul 19 08:28:04 PM PDT 24 18199203380 ps
T10 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2776115431 Jul 19 06:54:36 PM PDT 24 Jul 19 07:01:50 PM PDT 24 3944697548 ps
T468 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826436229 Jul 19 07:11:04 PM PDT 24 Jul 19 07:18:14 PM PDT 24 3779194352 ps
T680 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1413730515 Jul 19 06:43:21 PM PDT 24 Jul 19 06:52:53 PM PDT 24 7342380670 ps
T452 /workspace/coverage/default/0.rom_volatile_raw_unlock.3929046924 Jul 19 06:44:07 PM PDT 24 Jul 19 06:46:16 PM PDT 24 2272957294 ps
T196 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1340813246 Jul 19 06:57:08 PM PDT 24 Jul 19 07:05:27 PM PDT 24 4402028496 ps
T681 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4072271864 Jul 19 06:55:47 PM PDT 24 Jul 19 07:05:49 PM PDT 24 9763252080 ps
T238 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3673782469 Jul 19 06:53:48 PM PDT 24 Jul 19 07:05:18 PM PDT 24 4516570530 ps
T682 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2702177633 Jul 19 06:40:53 PM PDT 24 Jul 19 06:54:26 PM PDT 24 5048778634 ps
T519 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310819662 Jul 19 07:08:09 PM PDT 24 Jul 19 07:14:04 PM PDT 24 3480693752 ps
T114 /workspace/coverage/default/0.chip_plic_all_irqs_10.1408567926 Jul 19 06:41:05 PM PDT 24 Jul 19 06:51:44 PM PDT 24 4107999900 ps
T683 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3370131840 Jul 19 06:40:49 PM PDT 24 Jul 19 07:00:47 PM PDT 24 7357979000 ps
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