| T833 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1053724898 |
|
|
Jul 19 06:41:43 PM PDT 24 |
Jul 19 07:05:13 PM PDT 24 |
6213977200 ps |
| T834 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1518794801 |
|
|
Jul 19 06:39:29 PM PDT 24 |
Jul 19 06:42:01 PM PDT 24 |
2491515579 ps |
| T835 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.229734399 |
|
|
Jul 19 07:06:30 PM PDT 24 |
Jul 19 07:13:17 PM PDT 24 |
3219228500 ps |
| T836 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1345536886 |
|
|
Jul 19 06:59:15 PM PDT 24 |
Jul 19 07:07:31 PM PDT 24 |
4511202122 ps |
| T837 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3609470935 |
|
|
Jul 19 06:44:39 PM PDT 24 |
Jul 19 07:47:40 PM PDT 24 |
24757706060 ps |
| T838 |
/workspace/coverage/default/1.chip_sw_aes_enc.3209218132 |
|
|
Jul 19 06:44:27 PM PDT 24 |
Jul 19 06:48:50 PM PDT 24 |
3184735920 ps |
| T839 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3645883293 |
|
|
Jul 19 06:41:11 PM PDT 24 |
Jul 19 06:46:34 PM PDT 24 |
2725529446 ps |
| T271 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2352296712 |
|
|
Jul 19 06:41:48 PM PDT 24 |
Jul 19 06:45:50 PM PDT 24 |
3374189350 ps |
| T440 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.3863432810 |
|
|
Jul 19 06:39:06 PM PDT 24 |
Jul 19 07:59:54 PM PDT 24 |
18609792850 ps |
| T840 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1529094377 |
|
|
Jul 19 06:40:25 PM PDT 24 |
Jul 19 07:44:18 PM PDT 24 |
17017222144 ps |
| T841 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4179470587 |
|
|
Jul 19 07:05:29 PM PDT 24 |
Jul 19 07:14:38 PM PDT 24 |
3493103668 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.910643892 |
|
|
Jul 19 07:01:12 PM PDT 24 |
Jul 19 07:08:31 PM PDT 24 |
4561459188 ps |
| T842 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4080611101 |
|
|
Jul 19 06:44:33 PM PDT 24 |
Jul 19 07:40:13 PM PDT 24 |
13611175928 ps |
| T8 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.264697710 |
|
|
Jul 19 06:49:07 PM PDT 24 |
Jul 19 06:56:22 PM PDT 24 |
3915955108 ps |
| T843 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.3767813398 |
|
|
Jul 19 07:06:35 PM PDT 24 |
Jul 19 08:10:12 PM PDT 24 |
28654493659 ps |
| T222 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2307705140 |
|
|
Jul 19 06:41:01 PM PDT 24 |
Jul 19 07:18:44 PM PDT 24 |
11862818232 ps |
| T844 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.341199644 |
|
|
Jul 19 06:56:57 PM PDT 24 |
Jul 19 07:24:08 PM PDT 24 |
8209546000 ps |
| T845 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.538931718 |
|
|
Jul 19 06:55:15 PM PDT 24 |
Jul 19 07:14:32 PM PDT 24 |
5957578752 ps |
| T355 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.122660678 |
|
|
Jul 19 07:01:24 PM PDT 24 |
Jul 19 07:10:25 PM PDT 24 |
4728655700 ps |
| T846 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1911796517 |
|
|
Jul 19 06:56:37 PM PDT 24 |
Jul 19 07:01:14 PM PDT 24 |
3199570400 ps |
| T528 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.461485061 |
|
|
Jul 19 07:11:48 PM PDT 24 |
Jul 19 07:23:42 PM PDT 24 |
5629614288 ps |
| T847 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.140815112 |
|
|
Jul 19 06:42:56 PM PDT 24 |
Jul 19 06:53:39 PM PDT 24 |
4817271282 ps |
| T25 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1297082909 |
|
|
Jul 19 06:54:24 PM PDT 24 |
Jul 19 07:02:03 PM PDT 24 |
3156203638 ps |
| T848 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2067997602 |
|
|
Jul 19 07:02:39 PM PDT 24 |
Jul 19 07:09:29 PM PDT 24 |
8007823360 ps |
| T849 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1476154224 |
|
|
Jul 19 06:49:36 PM PDT 24 |
Jul 19 07:55:24 PM PDT 24 |
15441474809 ps |
| T476 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4177430575 |
|
|
Jul 19 07:00:09 PM PDT 24 |
Jul 19 07:21:03 PM PDT 24 |
10975786832 ps |
| T850 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2923137104 |
|
|
Jul 19 06:42:04 PM PDT 24 |
Jul 19 06:52:41 PM PDT 24 |
6850042174 ps |
| T851 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1545362856 |
|
|
Jul 19 07:03:47 PM PDT 24 |
Jul 19 08:12:42 PM PDT 24 |
14912759193 ps |
| T852 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3187883141 |
|
|
Jul 19 06:55:19 PM PDT 24 |
Jul 19 07:13:22 PM PDT 24 |
9021902760 ps |
| T853 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4255561249 |
|
|
Jul 19 06:46:38 PM PDT 24 |
Jul 19 07:32:26 PM PDT 24 |
29055514467 ps |
| T854 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4108331050 |
|
|
Jul 19 06:51:27 PM PDT 24 |
Jul 19 07:14:18 PM PDT 24 |
5553656128 ps |
| T281 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1501247122 |
|
|
Jul 19 06:49:44 PM PDT 24 |
Jul 19 08:40:26 PM PDT 24 |
23013690890 ps |
| T855 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1658557677 |
|
|
Jul 19 06:54:19 PM PDT 24 |
Jul 19 07:00:30 PM PDT 24 |
2672639710 ps |
| T856 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2620856193 |
|
|
Jul 19 06:48:28 PM PDT 24 |
Jul 19 07:05:59 PM PDT 24 |
7584409694 ps |
| T857 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2079634595 |
|
|
Jul 19 06:58:05 PM PDT 24 |
Jul 19 07:08:47 PM PDT 24 |
4754621964 ps |
| T858 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1017618966 |
|
|
Jul 19 06:47:33 PM PDT 24 |
Jul 19 06:55:07 PM PDT 24 |
5541075144 ps |
| T859 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.151726048 |
|
|
Jul 19 06:46:01 PM PDT 24 |
Jul 19 06:52:59 PM PDT 24 |
3465723886 ps |
| T860 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2844147527 |
|
|
Jul 19 06:52:42 PM PDT 24 |
Jul 19 10:06:32 PM PDT 24 |
59792840984 ps |
| T861 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483378360 |
|
|
Jul 19 06:41:29 PM PDT 24 |
Jul 19 06:48:58 PM PDT 24 |
3609762752 ps |
| T862 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3472081122 |
|
|
Jul 19 07:00:55 PM PDT 24 |
Jul 19 07:05:11 PM PDT 24 |
3116805320 ps |
| T863 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.924890459 |
|
|
Jul 19 06:50:13 PM PDT 24 |
Jul 19 07:46:34 PM PDT 24 |
15469131790 ps |
| T864 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1710798567 |
|
|
Jul 19 06:46:36 PM PDT 24 |
Jul 19 07:45:24 PM PDT 24 |
11227297313 ps |
| T865 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3338284080 |
|
|
Jul 19 06:39:48 PM PDT 24 |
Jul 19 07:05:01 PM PDT 24 |
7795648365 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3888903076 |
|
|
Jul 19 06:43:55 PM PDT 24 |
Jul 19 06:48:14 PM PDT 24 |
2941856680 ps |
| T96 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3971507346 |
|
|
Jul 19 07:02:45 PM PDT 24 |
Jul 19 07:12:52 PM PDT 24 |
5860174242 ps |
| T866 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3620665229 |
|
|
Jul 19 07:00:16 PM PDT 24 |
Jul 19 07:08:25 PM PDT 24 |
4850094020 ps |
| T441 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1916637772 |
|
|
Jul 19 06:39:57 PM PDT 24 |
Jul 19 06:45:17 PM PDT 24 |
2766979517 ps |
| T867 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1195200008 |
|
|
Jul 19 07:04:16 PM PDT 24 |
Jul 19 08:02:51 PM PDT 24 |
14687657304 ps |
| T868 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3115901202 |
|
|
Jul 19 06:57:02 PM PDT 24 |
Jul 19 07:14:20 PM PDT 24 |
6017755168 ps |
| T869 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3723058612 |
|
|
Jul 19 06:59:29 PM PDT 24 |
Jul 19 07:32:30 PM PDT 24 |
25703711123 ps |
| T126 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.879031190 |
|
|
Jul 19 06:39:12 PM PDT 24 |
Jul 19 06:45:19 PM PDT 24 |
2954901992 ps |
| T870 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1146570818 |
|
|
Jul 19 06:56:52 PM PDT 24 |
Jul 19 07:28:18 PM PDT 24 |
7244978024 ps |
| T871 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.797783739 |
|
|
Jul 19 06:47:11 PM PDT 24 |
Jul 19 06:50:31 PM PDT 24 |
3055587412 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3771813713 |
|
|
Jul 19 06:40:10 PM PDT 24 |
Jul 19 06:48:28 PM PDT 24 |
5862862168 ps |
| T872 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.520040550 |
|
|
Jul 19 06:42:15 PM PDT 24 |
Jul 19 07:01:45 PM PDT 24 |
4471138272 ps |
| T873 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1949754521 |
|
|
Jul 19 07:03:43 PM PDT 24 |
Jul 19 07:18:28 PM PDT 24 |
12178139352 ps |
| T874 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.753249538 |
|
|
Jul 19 06:42:25 PM PDT 24 |
Jul 19 07:00:37 PM PDT 24 |
8526114906 ps |
| T875 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1338288186 |
|
|
Jul 19 06:57:45 PM PDT 24 |
Jul 19 08:08:28 PM PDT 24 |
15220935789 ps |
| T876 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2694562694 |
|
|
Jul 19 07:02:23 PM PDT 24 |
Jul 19 07:08:58 PM PDT 24 |
4182260438 ps |
| T498 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2727742502 |
|
|
Jul 19 07:08:21 PM PDT 24 |
Jul 19 07:22:55 PM PDT 24 |
5312328928 ps |
| T511 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.908791605 |
|
|
Jul 19 07:07:18 PM PDT 24 |
Jul 19 07:17:58 PM PDT 24 |
5175279760 ps |
| T497 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2287838322 |
|
|
Jul 19 07:13:58 PM PDT 24 |
Jul 19 07:22:43 PM PDT 24 |
4868230568 ps |
| T464 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.4149122537 |
|
|
Jul 19 07:06:22 PM PDT 24 |
Jul 19 07:14:38 PM PDT 24 |
3786742456 ps |
| T492 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.137932889 |
|
|
Jul 19 07:12:50 PM PDT 24 |
Jul 19 07:23:52 PM PDT 24 |
6042109020 ps |
| T877 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2254333570 |
|
|
Jul 19 06:59:08 PM PDT 24 |
Jul 19 07:11:56 PM PDT 24 |
6213801800 ps |
| T878 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3102578086 |
|
|
Jul 19 06:40:12 PM PDT 24 |
Jul 19 07:07:28 PM PDT 24 |
7158281452 ps |
| T879 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2049335216 |
|
|
Jul 19 06:57:13 PM PDT 24 |
Jul 19 07:02:04 PM PDT 24 |
2955734320 ps |
| T453 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.930477082 |
|
|
Jul 19 07:09:14 PM PDT 24 |
Jul 19 07:18:01 PM PDT 24 |
3958175954 ps |
| T880 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2260135385 |
|
|
Jul 19 06:46:07 PM PDT 24 |
Jul 19 07:35:11 PM PDT 24 |
34030622400 ps |
| T172 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2611539745 |
|
|
Jul 19 06:54:34 PM PDT 24 |
Jul 19 06:57:33 PM PDT 24 |
2509949753 ps |
| T423 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4131015662 |
|
|
Jul 19 07:03:40 PM PDT 24 |
Jul 19 07:08:47 PM PDT 24 |
3165114382 ps |
| T881 |
/workspace/coverage/default/0.chip_sw_aes_idle.1722813986 |
|
|
Jul 19 06:42:12 PM PDT 24 |
Jul 19 06:47:41 PM PDT 24 |
3058244704 ps |
| T533 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557181797 |
|
|
Jul 19 07:09:30 PM PDT 24 |
Jul 19 07:16:53 PM PDT 24 |
3806624410 ps |
| T882 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.557758195 |
|
|
Jul 19 06:42:22 PM PDT 24 |
Jul 19 06:51:52 PM PDT 24 |
5231517160 ps |
| T883 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.3974109255 |
|
|
Jul 19 06:41:01 PM PDT 24 |
Jul 19 06:47:07 PM PDT 24 |
3425678920 ps |
| T116 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1326306033 |
|
|
Jul 19 06:58:39 PM PDT 24 |
Jul 19 07:08:28 PM PDT 24 |
4501985500 ps |
| T884 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2873137642 |
|
|
Jul 19 06:44:43 PM PDT 24 |
Jul 19 06:58:33 PM PDT 24 |
10298399356 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2980359240 |
|
|
Jul 19 06:44:22 PM PDT 24 |
Jul 19 06:53:46 PM PDT 24 |
5415365542 ps |
| T885 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2195779023 |
|
|
Jul 19 06:42:46 PM PDT 24 |
Jul 19 06:53:41 PM PDT 24 |
3970083020 ps |
| T886 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2707637861 |
|
|
Jul 19 06:52:57 PM PDT 24 |
Jul 19 06:57:19 PM PDT 24 |
3009565362 ps |
| T887 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2464224108 |
|
|
Jul 19 06:41:01 PM PDT 24 |
Jul 19 08:17:04 PM PDT 24 |
27561918504 ps |
| T888 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1757651100 |
|
|
Jul 19 06:56:55 PM PDT 24 |
Jul 19 07:03:09 PM PDT 24 |
3738849362 ps |
| T889 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1232450531 |
|
|
Jul 19 06:40:33 PM PDT 24 |
Jul 19 07:37:34 PM PDT 24 |
33972669178 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3524725469 |
|
|
Jul 19 06:48:15 PM PDT 24 |
Jul 19 06:57:10 PM PDT 24 |
5850792360 ps |
| T890 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4203373865 |
|
|
Jul 19 06:41:29 PM PDT 24 |
Jul 19 07:30:14 PM PDT 24 |
33292720743 ps |
| T475 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3320378298 |
|
|
Jul 19 07:07:37 PM PDT 24 |
Jul 19 07:17:50 PM PDT 24 |
5807658648 ps |
| T891 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2537776617 |
|
|
Jul 19 06:44:18 PM PDT 24 |
Jul 19 07:11:05 PM PDT 24 |
7083777032 ps |
| T892 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.212739980 |
|
|
Jul 19 06:40:47 PM PDT 24 |
Jul 19 06:44:00 PM PDT 24 |
2335908850 ps |
| T893 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3930880916 |
|
|
Jul 19 07:00:24 PM PDT 24 |
Jul 19 07:04:43 PM PDT 24 |
2108761060 ps |
| T894 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2925808513 |
|
|
Jul 19 06:57:06 PM PDT 24 |
Jul 19 07:17:52 PM PDT 24 |
7371242448 ps |
| T118 |
/workspace/coverage/default/1.chip_sw_alert_test.4006042875 |
|
|
Jul 19 06:44:40 PM PDT 24 |
Jul 19 06:50:42 PM PDT 24 |
3288417080 ps |
| T47 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2195259268 |
|
|
Jul 19 06:40:21 PM PDT 24 |
Jul 19 06:46:22 PM PDT 24 |
3303622094 ps |
| T895 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3259116574 |
|
|
Jul 19 07:03:33 PM PDT 24 |
Jul 19 08:21:06 PM PDT 24 |
15949864109 ps |
| T896 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.167658605 |
|
|
Jul 19 06:38:44 PM PDT 24 |
Jul 19 06:44:22 PM PDT 24 |
2773924968 ps |
| T897 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1601373472 |
|
|
Jul 19 06:45:12 PM PDT 24 |
Jul 19 07:58:24 PM PDT 24 |
15234578928 ps |
| T898 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.187137926 |
|
|
Jul 19 06:43:37 PM PDT 24 |
Jul 19 07:13:25 PM PDT 24 |
11001416236 ps |
| T899 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.698266109 |
|
|
Jul 19 06:58:39 PM PDT 24 |
Jul 19 07:11:32 PM PDT 24 |
8952803524 ps |
| T97 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2110547800 |
|
|
Jul 19 07:08:42 PM PDT 24 |
Jul 19 07:22:07 PM PDT 24 |
6039149552 ps |
| T900 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.252444062 |
|
|
Jul 19 06:46:08 PM PDT 24 |
Jul 19 08:09:17 PM PDT 24 |
18349295816 ps |
| T901 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1830578575 |
|
|
Jul 19 07:05:10 PM PDT 24 |
Jul 19 07:29:35 PM PDT 24 |
8281886892 ps |
| T902 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1734797105 |
|
|
Jul 19 06:57:38 PM PDT 24 |
Jul 19 07:22:11 PM PDT 24 |
22079178410 ps |
| T346 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124170358 |
|
|
Jul 19 07:10:08 PM PDT 24 |
Jul 19 07:17:54 PM PDT 24 |
4616806878 ps |
| T903 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3767127106 |
|
|
Jul 19 07:05:06 PM PDT 24 |
Jul 19 07:36:42 PM PDT 24 |
8544835250 ps |
| T904 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2645426075 |
|
|
Jul 19 06:40:22 PM PDT 24 |
Jul 19 08:01:20 PM PDT 24 |
17769567396 ps |
| T905 |
/workspace/coverage/default/0.chip_sw_flash_init.2724954819 |
|
|
Jul 19 06:40:18 PM PDT 24 |
Jul 19 07:15:49 PM PDT 24 |
18425486250 ps |
| T906 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2638878343 |
|
|
Jul 19 06:53:05 PM PDT 24 |
Jul 19 07:00:20 PM PDT 24 |
5826371624 ps |
| T907 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3365438713 |
|
|
Jul 19 06:42:27 PM PDT 24 |
Jul 19 07:07:18 PM PDT 24 |
12177018089 ps |
| T908 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3029865815 |
|
|
Jul 19 07:00:33 PM PDT 24 |
Jul 19 07:38:40 PM PDT 24 |
27230194035 ps |
| T909 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1753143125 |
|
|
Jul 19 06:44:01 PM PDT 24 |
Jul 19 07:58:41 PM PDT 24 |
15762379074 ps |
| T910 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2164145497 |
|
|
Jul 19 06:48:40 PM PDT 24 |
Jul 19 07:01:52 PM PDT 24 |
7190326990 ps |
| T323 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4211241545 |
|
|
Jul 19 06:42:34 PM PDT 24 |
Jul 19 06:47:53 PM PDT 24 |
2755689360 ps |
| T911 |
/workspace/coverage/default/2.chip_sw_example_rom.2883625755 |
|
|
Jul 19 06:53:55 PM PDT 24 |
Jul 19 06:56:16 PM PDT 24 |
3004581518 ps |
| T912 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.877778305 |
|
|
Jul 19 06:57:30 PM PDT 24 |
Jul 19 07:10:36 PM PDT 24 |
6334629436 ps |
| T913 |
/workspace/coverage/default/1.rom_e2e_self_hash.1735332116 |
|
|
Jul 19 06:57:19 PM PDT 24 |
Jul 19 08:42:20 PM PDT 24 |
25759472648 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2483831428 |
|
|
Jul 19 06:42:20 PM PDT 24 |
Jul 19 06:48:32 PM PDT 24 |
4362187062 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2051566729 |
|
|
Jul 19 06:39:20 PM PDT 24 |
Jul 19 06:47:50 PM PDT 24 |
4134531600 ps |
| T914 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2937792457 |
|
|
Jul 19 06:39:10 PM PDT 24 |
Jul 19 08:24:38 PM PDT 24 |
49578493012 ps |
| T915 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581394307 |
|
|
Jul 19 07:05:21 PM PDT 24 |
Jul 19 07:12:39 PM PDT 24 |
4159847442 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_aes_idle.821726238 |
|
|
Jul 19 06:43:22 PM PDT 24 |
Jul 19 06:48:26 PM PDT 24 |
3005743476 ps |
| T917 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3636605102 |
|
|
Jul 19 06:40:29 PM PDT 24 |
Jul 19 08:14:40 PM PDT 24 |
45870552105 ps |
| T918 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.997904542 |
|
|
Jul 19 07:04:48 PM PDT 24 |
Jul 19 07:39:06 PM PDT 24 |
13173709640 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.340844964 |
|
|
Jul 19 06:40:19 PM PDT 24 |
Jul 19 11:15:29 PM PDT 24 |
77749665308 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4022793813 |
|
|
Jul 19 06:41:05 PM PDT 24 |
Jul 19 06:56:48 PM PDT 24 |
5011730576 ps |
| T920 |
/workspace/coverage/default/0.rom_keymgr_functest.2918727612 |
|
|
Jul 19 06:41:43 PM PDT 24 |
Jul 19 06:53:33 PM PDT 24 |
5785339444 ps |
| T921 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1765193508 |
|
|
Jul 19 06:51:00 PM PDT 24 |
Jul 19 06:56:42 PM PDT 24 |
3403757135 ps |
| T504 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1229673525 |
|
|
Jul 19 07:09:53 PM PDT 24 |
Jul 19 07:20:12 PM PDT 24 |
5167841234 ps |
| T922 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.672142819 |
|
|
Jul 19 07:02:44 PM PDT 24 |
Jul 19 07:45:32 PM PDT 24 |
11299377898 ps |
| T923 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.294082405 |
|
|
Jul 19 06:58:13 PM PDT 24 |
Jul 19 07:03:29 PM PDT 24 |
3327544040 ps |
| T924 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.673848394 |
|
|
Jul 19 06:41:32 PM PDT 24 |
Jul 19 06:45:00 PM PDT 24 |
2536154440 ps |
| T925 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1728821826 |
|
|
Jul 19 07:09:28 PM PDT 24 |
Jul 19 07:20:40 PM PDT 24 |
5423158020 ps |
| T926 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.193806949 |
|
|
Jul 19 06:37:30 PM PDT 24 |
Jul 19 06:48:28 PM PDT 24 |
3922808024 ps |
| T927 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.922775995 |
|
|
Jul 19 06:44:44 PM PDT 24 |
Jul 19 08:57:56 PM PDT 24 |
24764540316 ps |
| T928 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.3360168530 |
|
|
Jul 19 06:52:21 PM PDT 24 |
Jul 19 06:56:15 PM PDT 24 |
3057324781 ps |
| T929 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.870522220 |
|
|
Jul 19 06:39:32 PM PDT 24 |
Jul 19 06:49:13 PM PDT 24 |
5618462840 ps |
| T113 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3458436826 |
|
|
Jul 19 06:40:49 PM PDT 24 |
Jul 19 06:51:47 PM PDT 24 |
4750063555 ps |
| T930 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.733196551 |
|
|
Jul 19 06:39:35 PM PDT 24 |
Jul 19 07:45:46 PM PDT 24 |
19986936117 ps |
| T931 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4206409800 |
|
|
Jul 19 06:44:52 PM PDT 24 |
Jul 19 06:49:44 PM PDT 24 |
2844108814 ps |
| T493 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.200437499 |
|
|
Jul 19 07:08:34 PM PDT 24 |
Jul 19 07:17:34 PM PDT 24 |
4824875250 ps |
| T432 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.705929918 |
|
|
Jul 19 06:51:29 PM PDT 24 |
Jul 19 08:31:28 PM PDT 24 |
35277939551 ps |
| T932 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4230994909 |
|
|
Jul 19 06:46:59 PM PDT 24 |
Jul 19 07:57:02 PM PDT 24 |
15216280990 ps |
| T933 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2891574492 |
|
|
Jul 19 07:02:34 PM PDT 24 |
Jul 19 07:11:22 PM PDT 24 |
4465229048 ps |
| T12 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2177159147 |
|
|
Jul 19 06:42:23 PM PDT 24 |
Jul 19 06:46:02 PM PDT 24 |
3050275452 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.749748733 |
|
|
Jul 19 07:09:38 PM PDT 24 |
Jul 19 07:12:58 PM PDT 24 |
2871155400 ps |
| T935 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2437629740 |
|
|
Jul 19 06:48:11 PM PDT 24 |
Jul 19 06:49:52 PM PDT 24 |
1980419833 ps |
| T936 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1938138185 |
|
|
Jul 19 06:50:04 PM PDT 24 |
Jul 19 08:12:18 PM PDT 24 |
15643868108 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_power_idle_load.2653262919 |
|
|
Jul 19 06:45:34 PM PDT 24 |
Jul 19 06:59:39 PM PDT 24 |
4817346602 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.4002516320 |
|
|
Jul 19 06:58:14 PM PDT 24 |
Jul 19 07:03:01 PM PDT 24 |
2742852160 ps |
| T939 |
/workspace/coverage/default/4.chip_tap_straps_prod.1668375806 |
|
|
Jul 19 07:02:15 PM PDT 24 |
Jul 19 07:25:00 PM PDT 24 |
12649655102 ps |
| T540 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.590951 |
|
|
Jul 19 07:11:04 PM PDT 24 |
Jul 19 07:17:22 PM PDT 24 |
3955460324 ps |
| T443 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2177882666 |
|
|
Jul 19 06:58:45 PM PDT 24 |
Jul 19 07:07:57 PM PDT 24 |
7594373240 ps |
| T940 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3099435455 |
|
|
Jul 19 06:45:01 PM PDT 24 |
Jul 19 07:03:24 PM PDT 24 |
6099855880 ps |
| T93 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1893775481 |
|
|
Jul 19 06:58:35 PM PDT 24 |
Jul 19 07:07:05 PM PDT 24 |
5651476266 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.799675423 |
|
|
Jul 19 06:40:11 PM PDT 24 |
Jul 19 06:44:42 PM PDT 24 |
2972131272 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2413861692 |
|
|
Jul 19 06:55:35 PM PDT 24 |
Jul 19 07:00:04 PM PDT 24 |
3482955798 ps |
| T942 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1573695 |
|
|
Jul 19 06:54:57 PM PDT 24 |
Jul 19 07:01:01 PM PDT 24 |
2908408080 ps |
| T119 |
/workspace/coverage/default/0.chip_sw_alert_test.2107876674 |
|
|
Jul 19 06:41:44 PM PDT 24 |
Jul 19 06:48:32 PM PDT 24 |
2947649778 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1466700612 |
|
|
Jul 19 06:55:42 PM PDT 24 |
Jul 19 07:03:22 PM PDT 24 |
6625171400 ps |
| T944 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.558797607 |
|
|
Jul 19 07:07:29 PM PDT 24 |
Jul 19 07:16:09 PM PDT 24 |
4146462324 ps |
| T945 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1141621823 |
|
|
Jul 19 06:56:38 PM PDT 24 |
Jul 19 08:04:23 PM PDT 24 |
15369071546 ps |
| T542 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2406956326 |
|
|
Jul 19 07:09:45 PM PDT 24 |
Jul 19 07:20:20 PM PDT 24 |
4642690896 ps |
| T946 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560267897 |
|
|
Jul 19 07:05:51 PM PDT 24 |
Jul 19 07:13:01 PM PDT 24 |
3830748126 ps |
| T947 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1918462543 |
|
|
Jul 19 07:11:34 PM PDT 24 |
Jul 19 07:21:08 PM PDT 24 |
5337507848 ps |
| T503 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.4241449323 |
|
|
Jul 19 07:07:30 PM PDT 24 |
Jul 19 07:17:41 PM PDT 24 |
6004791434 ps |
| T948 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3539643806 |
|
|
Jul 19 06:47:32 PM PDT 24 |
Jul 19 08:23:51 PM PDT 24 |
24097649376 ps |
| T301 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.65919364 |
|
|
Jul 19 07:00:57 PM PDT 24 |
Jul 19 07:13:22 PM PDT 24 |
5546736928 ps |
| T949 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3684477307 |
|
|
Jul 19 06:44:13 PM PDT 24 |
Jul 19 06:47:59 PM PDT 24 |
2885302520 ps |
| T950 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2046693360 |
|
|
Jul 19 06:41:22 PM PDT 24 |
Jul 19 06:47:50 PM PDT 24 |
6325812831 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1719869334 |
|
|
Jul 19 06:43:45 PM PDT 24 |
Jul 19 06:47:30 PM PDT 24 |
2717657424 ps |
| T417 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1331941619 |
|
|
Jul 19 07:11:43 PM PDT 24 |
Jul 19 07:21:47 PM PDT 24 |
6114277070 ps |
| T952 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.4140585203 |
|
|
Jul 19 06:39:55 PM PDT 24 |
Jul 19 06:44:14 PM PDT 24 |
2856674898 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.580589083 |
|
|
Jul 19 06:43:19 PM PDT 24 |
Jul 19 06:48:14 PM PDT 24 |
3137472913 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.384683167 |
|
|
Jul 19 06:56:35 PM PDT 24 |
Jul 19 07:07:52 PM PDT 24 |
18917945388 ps |
| T954 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.577351049 |
|
|
Jul 19 06:55:17 PM PDT 24 |
Jul 19 07:05:29 PM PDT 24 |
3598923600 ps |
| T506 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3516341477 |
|
|
Jul 19 07:07:53 PM PDT 24 |
Jul 19 07:19:50 PM PDT 24 |
4852522048 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3636642330 |
|
|
Jul 19 06:59:12 PM PDT 24 |
Jul 19 07:04:08 PM PDT 24 |
3049795226 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.953125380 |
|
|
Jul 19 06:46:07 PM PDT 24 |
Jul 19 06:50:22 PM PDT 24 |
2566071640 ps |
| T500 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130544359 |
|
|
Jul 19 07:12:09 PM PDT 24 |
Jul 19 07:18:32 PM PDT 24 |
3785164520 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2794580672 |
|
|
Jul 19 06:40:18 PM PDT 24 |
Jul 19 07:01:28 PM PDT 24 |
7623979672 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1900778298 |
|
|
Jul 19 06:41:06 PM PDT 24 |
Jul 19 06:46:23 PM PDT 24 |
2588901208 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1734080523 |
|
|
Jul 19 06:57:32 PM PDT 24 |
Jul 19 07:49:03 PM PDT 24 |
20161806100 ps |
| T436 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3487692278 |
|
|
Jul 19 06:56:47 PM PDT 24 |
Jul 19 07:06:37 PM PDT 24 |
2676757636 ps |
| T960 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1159258035 |
|
|
Jul 19 06:43:10 PM PDT 24 |
Jul 19 06:54:42 PM PDT 24 |
4310125000 ps |
| T961 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.523730294 |
|
|
Jul 19 06:52:13 PM PDT 24 |
Jul 19 06:56:18 PM PDT 24 |
3352959620 ps |
| T448 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.619138810 |
|
|
Jul 19 06:59:25 PM PDT 24 |
Jul 19 07:13:55 PM PDT 24 |
6024802511 ps |
| T230 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3044616381 |
|
|
Jul 19 07:00:20 PM PDT 24 |
Jul 19 07:19:58 PM PDT 24 |
5621824112 ps |
| T962 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.665901405 |
|
|
Jul 19 06:39:38 PM PDT 24 |
Jul 19 06:47:42 PM PDT 24 |
4827463150 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1335262550 |
|
|
Jul 19 06:47:45 PM PDT 24 |
Jul 19 07:00:05 PM PDT 24 |
4759542576 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3979102016 |
|
|
Jul 19 07:00:17 PM PDT 24 |
Jul 19 07:06:22 PM PDT 24 |
3978280391 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_edn_kat.3137254178 |
|
|
Jul 19 06:45:53 PM PDT 24 |
Jul 19 06:56:58 PM PDT 24 |
3324400888 ps |
| T966 |
/workspace/coverage/default/2.chip_sw_aes_enc.1753787785 |
|
|
Jul 19 06:55:35 PM PDT 24 |
Jul 19 07:00:36 PM PDT 24 |
3198632760 ps |
| T367 |
/workspace/coverage/default/2.chip_jtag_mem_access.559673313 |
|
|
Jul 19 06:51:24 PM PDT 24 |
Jul 19 07:15:04 PM PDT 24 |
13855262600 ps |
| T347 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.4187020626 |
|
|
Jul 19 07:10:48 PM PDT 24 |
Jul 19 07:20:21 PM PDT 24 |
5675702528 ps |
| T967 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1898044795 |
|
|
Jul 19 07:06:33 PM PDT 24 |
Jul 19 08:10:44 PM PDT 24 |
15721376206 ps |
| T968 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2413728963 |
|
|
Jul 19 06:43:09 PM PDT 24 |
Jul 19 06:55:16 PM PDT 24 |
4075443504 ps |
| T969 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1919639419 |
|
|
Jul 19 07:03:39 PM PDT 24 |
Jul 19 08:11:39 PM PDT 24 |
16090870626 ps |
| T970 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2723351108 |
|
|
Jul 19 07:03:16 PM PDT 24 |
Jul 19 07:10:59 PM PDT 24 |
6292498848 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.87147234 |
|
|
Jul 19 06:38:45 PM PDT 24 |
Jul 19 06:55:04 PM PDT 24 |
6527820640 ps |
| T359 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.153820282 |
|
|
Jul 19 06:54:34 PM PDT 24 |
Jul 19 07:23:14 PM PDT 24 |
10451490422 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3858224896 |
|
|
Jul 19 06:40:13 PM PDT 24 |
Jul 19 06:43:53 PM PDT 24 |
2523106904 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3758802897 |
|
|
Jul 19 06:42:16 PM PDT 24 |
Jul 19 06:49:28 PM PDT 24 |
3780015812 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3773969328 |
|
|
Jul 19 06:46:33 PM PDT 24 |
Jul 19 06:50:55 PM PDT 24 |
3233213904 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2544475169 |
|
|
Jul 19 06:53:24 PM PDT 24 |
Jul 19 07:04:37 PM PDT 24 |
4620858000 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_aes_idle.3826403330 |
|
|
Jul 19 06:57:56 PM PDT 24 |
Jul 19 07:02:50 PM PDT 24 |
2650900336 ps |
| T324 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.371003956 |
|
|
Jul 19 06:42:15 PM PDT 24 |
Jul 19 06:45:50 PM PDT 24 |
2840283002 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.357631435 |
|
|
Jul 19 07:00:47 PM PDT 24 |
Jul 19 07:09:20 PM PDT 24 |
3268042828 ps |
| T978 |
/workspace/coverage/default/3.chip_tap_straps_prod.3317761973 |
|
|
Jul 19 07:01:00 PM PDT 24 |
Jul 19 07:08:57 PM PDT 24 |
5210951060 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1536491107 |
|
|
Jul 19 06:59:42 PM PDT 24 |
Jul 19 07:08:18 PM PDT 24 |
6291823220 ps |
| T980 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.553228416 |
|
|
Jul 19 07:07:21 PM PDT 24 |
Jul 19 07:14:18 PM PDT 24 |
4050569600 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.844483876 |
|
|
Jul 19 06:54:39 PM PDT 24 |
Jul 19 07:07:19 PM PDT 24 |
4286170596 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.437501845 |
|
|
Jul 19 06:40:45 PM PDT 24 |
Jul 19 07:14:51 PM PDT 24 |
25876158768 ps |
| T348 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076723001 |
|
|
Jul 19 07:11:51 PM PDT 24 |
Jul 19 07:19:08 PM PDT 24 |
4254823280 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_power_idle_load.900112359 |
|
|
Jul 19 07:01:59 PM PDT 24 |
Jul 19 07:15:17 PM PDT 24 |
4271998302 ps |
| T984 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.902018092 |
|
|
Jul 19 07:10:55 PM PDT 24 |
Jul 19 07:15:50 PM PDT 24 |
4004074352 ps |
| T418 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.298336833 |
|
|
Jul 19 07:08:12 PM PDT 24 |
Jul 19 07:18:54 PM PDT 24 |
5852278734 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.829401923 |
|
|
Jul 19 06:55:32 PM PDT 24 |
Jul 19 07:08:06 PM PDT 24 |
4423433940 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1066232553 |
|
|
Jul 19 06:48:57 PM PDT 24 |
Jul 19 06:56:45 PM PDT 24 |
5172822882 ps |
| T987 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.566260055 |
|
|
Jul 19 07:02:31 PM PDT 24 |
Jul 19 07:40:14 PM PDT 24 |
12651701910 ps |
| T988 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.269677592 |
|
|
Jul 19 07:10:06 PM PDT 24 |
Jul 19 07:16:18 PM PDT 24 |
3654565644 ps |
| T368 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3077750375 |
|
|
Jul 19 06:40:08 PM PDT 24 |
Jul 19 07:28:30 PM PDT 24 |
24631815376 ps |
| T536 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1304706598 |
|
|
Jul 19 07:12:15 PM PDT 24 |
Jul 19 07:23:18 PM PDT 24 |
5381947260 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.462093681 |
|
|
Jul 19 06:45:11 PM PDT 24 |
Jul 19 06:50:19 PM PDT 24 |
5773567944 ps |
| T989 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.638022901 |
|
|
Jul 19 06:58:07 PM PDT 24 |
Jul 19 07:45:29 PM PDT 24 |
11572429030 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4086365900 |
|
|
Jul 19 06:43:48 PM PDT 24 |
Jul 19 06:52:59 PM PDT 24 |
3824340568 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.143152891 |
|
|
Jul 19 06:52:42 PM PDT 24 |
Jul 19 06:57:03 PM PDT 24 |
2841919872 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3847686359 |
|
|
Jul 19 06:39:24 PM PDT 24 |
Jul 19 07:27:01 PM PDT 24 |
28620876877 ps |
| T993 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4216658615 |
|
|
Jul 19 07:02:12 PM PDT 24 |
Jul 19 07:14:50 PM PDT 24 |
4387492843 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.3865657711 |
|
|
Jul 19 07:01:41 PM PDT 24 |
Jul 19 07:07:55 PM PDT 24 |
3409996588 ps |
| T995 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.350527338 |
|
|
Jul 19 07:02:09 PM PDT 24 |
Jul 19 07:05:40 PM PDT 24 |
2897054632 ps |
| T996 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.665008934 |
|
|
Jul 19 07:03:13 PM PDT 24 |
Jul 19 07:09:58 PM PDT 24 |
4851600588 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3315151442 |
|
|
Jul 19 06:45:50 PM PDT 24 |
Jul 19 06:52:39 PM PDT 24 |
3394722040 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_example_concurrency.4212308783 |
|
|
Jul 19 06:38:53 PM PDT 24 |
Jul 19 06:43:11 PM PDT 24 |
2600390616 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2879896386 |
|
|
Jul 19 06:40:30 PM PDT 24 |
Jul 19 06:48:47 PM PDT 24 |
3747452095 ps |
| T999 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.15508149 |
|
|
Jul 19 07:04:05 PM PDT 24 |
Jul 19 07:32:01 PM PDT 24 |
8273482738 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1244698856 |
|
|
Jul 19 06:43:59 PM PDT 24 |
Jul 19 06:48:00 PM PDT 24 |
2805958460 ps |
| T1001 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4221333305 |
|
|
Jul 19 06:58:57 PM PDT 24 |
Jul 19 07:21:48 PM PDT 24 |
7068223588 ps |
| T1002 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3464259131 |
|
|
Jul 19 06:49:56 PM PDT 24 |
Jul 19 07:56:46 PM PDT 24 |
14449168072 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3264228901 |
|
|
Jul 19 06:41:20 PM PDT 24 |
Jul 19 06:52:45 PM PDT 24 |
4304548520 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4154487082 |
|
|
Jul 19 06:40:21 PM PDT 24 |
Jul 19 06:42:06 PM PDT 24 |
2483337726 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_hmac_enc.3366637450 |
|
|
Jul 19 06:57:46 PM PDT 24 |
Jul 19 07:03:32 PM PDT 24 |
3143223332 ps |
| T252 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1508179040 |
|
|
Jul 19 06:45:06 PM PDT 24 |
Jul 19 06:58:48 PM PDT 24 |
7201752056 ps |
| T1006 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2077842796 |
|
|
Jul 19 07:10:04 PM PDT 24 |
Jul 19 07:17:19 PM PDT 24 |
3814244760 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3699194260 |
|
|
Jul 19 06:40:58 PM PDT 24 |
Jul 19 06:45:26 PM PDT 24 |
3097662833 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2087382251 |
|
|
Jul 19 06:42:36 PM PDT 24 |
Jul 19 06:44:33 PM PDT 24 |
2822598159 ps |
| T1009 |
/workspace/coverage/default/2.rom_e2e_self_hash.1842774592 |
|
|
Jul 19 07:05:49 PM PDT 24 |
Jul 19 09:01:42 PM PDT 24 |
26453338680 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2358503144 |
|
|
Jul 19 07:01:48 PM PDT 24 |
Jul 19 07:10:13 PM PDT 24 |
5055462090 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2404250943 |
|
|
Jul 19 06:58:07 PM PDT 24 |
Jul 19 07:28:48 PM PDT 24 |
8347001256 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_example_flash.1044641139 |
|
|
Jul 19 06:53:28 PM PDT 24 |
Jul 19 06:56:57 PM PDT 24 |
2772986152 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4273394769 |
|
|
Jul 19 06:47:39 PM PDT 24 |
Jul 19 06:56:03 PM PDT 24 |
6853912066 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1742618078 |
|
|
Jul 19 06:54:21 PM PDT 24 |
Jul 19 07:06:39 PM PDT 24 |
4840132488 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.823998675 |
|
|
Jul 19 06:43:44 PM PDT 24 |
Jul 19 07:15:56 PM PDT 24 |
23078996000 ps |