Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.41	92.69	82.60	90.58		94.43	97.53	84.65

Total test records in report: 1018

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T98	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2599857358			Jul 19 07:01:20 PM PDT 24	Jul 19 07:59:04 PM PDT 24	22248986769 ps
T15	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.545897794			Jul 19 06:47:36 PM PDT 24	Jul 19 07:20:45 PM PDT 24	24499323460 ps
T1015	/workspace/coverage/default/1.rom_keymgr_functest.1962668283			Jul 19 06:52:14 PM PDT 24	Jul 19 06:58:39 PM PDT 24	3959952790 ps
T1016	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3756283691			Jul 19 07:00:54 PM PDT 24	Jul 19 07:09:57 PM PDT 24	5402107816 ps
T537	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.998460690			Jul 19 07:06:42 PM PDT 24	Jul 19 07:14:31 PM PDT 24	4366545928 ps
T120	/workspace/coverage/default/2.chip_sw_alert_test.2147152339			Jul 19 06:56:08 PM PDT 24	Jul 19 07:01:59 PM PDT 24	3338744752 ps
T1017	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3063872867			Jul 19 07:02:11 PM PDT 24	Jul 19 07:11:00 PM PDT 24	5865529688 ps
T1018	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4234134641			Jul 19 06:45:10 PM PDT 24	Jul 19 08:03:16 PM PDT 24	24982657576 ps
T40	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.425971458			Jul 19 04:48:43 PM PDT 24	Jul 19 04:52:53 PM PDT 24	4782586165 ps
T41	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3547711923			Jul 19 04:48:50 PM PDT 24	Jul 19 04:52:53 PM PDT 24	5241144085 ps
T42	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.250181597			Jul 19 04:48:43 PM PDT 24	Jul 19 04:53:54 PM PDT 24	5551571340 ps
T249	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3150757964			Jul 19 04:48:44 PM PDT 24	Jul 19 04:52:24 PM PDT 24	5498134860 ps
T245	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.568917921			Jul 19 04:48:49 PM PDT 24	Jul 19 04:53:28 PM PDT 24	5589113635 ps
T246	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3728004525			Jul 19 04:48:40 PM PDT 24	Jul 19 04:55:12 PM PDT 24	5400777908 ps
T200	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1363544344			Jul 19 04:48:40 PM PDT 24	Jul 19 04:52:25 PM PDT 24	3895258445 ps
T201	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1663843576			Jul 19 04:48:47 PM PDT 24	Jul 19 04:53:20 PM PDT 24	4620193558 ps
T247	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.451408801			Jul 19 04:48:51 PM PDT 24	Jul 19 04:53:55 PM PDT 24	4886873120 ps
T248	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.772270036			Jul 19 04:48:46 PM PDT 24	Jul 19 04:53:36 PM PDT 24	5235191500 ps

Test location	/workspace/coverage/default/61.chip_sw_all_escalation_resets.897063511
Short name	T20
Test name
Test status
Simulation time	6071977796 ps
CPU time	603.08 seconds
Started	Jul 19 07:08:47 PM PDT 24
Finished	Jul 19 07:18:54 PM PDT 24
Peak memory	650004 kb
Host	smart-d5bf85ac-9f2b-435e-a538-a920ab1bd513
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 897063511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.897063511
Directory	/workspace/61.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_jtag_csr_rw.1448946453
Short name	T1
Test name
Test status
Simulation time	12925959835 ps
CPU time	1525.91 seconds
Started	Jul 19 06:40:55 PM PDT 24
Finished	Jul 19 07:06:23 PM PDT 24
Peak memory	607988 kb
Host	smart-aec53ede-b8e3-46ae-8999-562f03e39b1a
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448946453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1448946453
Directory	/workspace/1.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_0.3514453211
Short name	T228
Test name
Test status
Simulation time	6206966238 ps
CPU time	1366.23 seconds
Started	Jul 19 06:41:05 PM PDT 24
Finished	Jul 19 07:03:53 PM PDT 24
Peak memory	610144 kb
Host	smart-75a3cffd-2c00-407e-843d-f10ed690b149
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514453211 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3514453211
Directory	/workspace/0.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.425971458
Short name	T40
Test name
Test status
Simulation time	4782586165 ps
CPU time	233.51 seconds
Started	Jul 19 04:48:43 PM PDT 24
Finished	Jul 19 04:52:53 PM PDT 24
Peak memory	657436 kb
Host	smart-3d7eb6ad-95a9-4e00-8267-1db45d8d893b
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425971458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.425971458
Directory	/workspace/3.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_test.4006042875
Short name	T118
Test name
Test status
Simulation time	3288417080 ps
CPU time	361.4 seconds
Started	Jul 19 06:44:40 PM PDT 24
Finished	Jul 19 06:50:42 PM PDT 24
Peak memory	609592 kb
Host	smart-4115003d-6f6e-4943-b4c9-88fb7bb3df54
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006042875 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.4006042875
Directory	/workspace/1.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1095795370
Short name	T108
Test name
Test status
Simulation time	3398596437 ps
CPU time	287.61 seconds
Started	Jul 19 06:45:04 PM PDT 24
Finished	Jul 19 06:49:53 PM PDT 24
Peak memory	609680 kb
Host	smart-ee19d26c-50be-4668-97be-e3960eac4ed6
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1095795370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1095795370
Directory	/workspace/1.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1930292941
Short name	T213
Test name
Test status
Simulation time	14157799680 ps
CPU time	4263.7 seconds
Started	Jul 19 06:39:40 PM PDT 24
Finished	Jul 19 07:50:45 PM PDT 24
Peak memory	609688 kb
Host	smart-f8c264b4-c9a3-4540-a551-26ee3485a250
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302 92941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1930292941
Directory	/workspace/0.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_jtag_csr_rw.1792809725
Short name	T117
Test name
Test status
Simulation time	9363328010 ps
CPU time	1102.4 seconds
Started	Jul 19 06:51:27 PM PDT 24
Finished	Jul 19 07:09:52 PM PDT 24
Peak memory	603900 kb
Host	smart-f154fcf6-2e48-4f3a-afd1-4b22529f8a8d
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792809725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1792809725
Directory	/workspace/2.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1319711536
Short name	T106
Test name
Test status
Simulation time	46527378235 ps
CPU time	5218.25 seconds
Started	Jul 19 06:56:03 PM PDT 24
Finished	Jul 19 08:23:08 PM PDT 24
Peak memory	620252 kb
Host	smart-90e866de-8f80-429b-9e07-2a0039d47a73
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319711536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1319711536
Directory	/workspace/2.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1883919176
Short name	T54
Test name
Test status
Simulation time	14356399963 ps
CPU time	4342.35 seconds
Started	Jul 19 06:45:01 PM PDT 24
Finished	Jul 19 07:57:25 PM PDT 24
Peak memory	609472 kb
Host	smart-ba57ba0a-6f52-45cf-9d09-94df6afe7d09
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883919176 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1883919176
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.517252666
Short name	T24
Test name
Test status
Simulation time	2724440521 ps
CPU time	246.09 seconds
Started	Jul 19 06:40:00 PM PDT 24
Finished	Jul 19 06:44:07 PM PDT 24
Peak memory	609808 kb
Host	smart-1a50f548-604e-47dd-bd5f-82f9f59923e1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5172 52666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.517252666
Directory	/workspace/0.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265402335
Short name	T72
Test name
Test status
Simulation time	3865920616 ps
CPU time	334.42 seconds
Started	Jul 19 07:06:44 PM PDT 24
Finished	Jul 19 07:12:20 PM PDT 24
Peak memory	648584 kb
Host	smart-5daa40ba-071e-4f9d-b769-8c802953d4a0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265402335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2265402335
Directory	/workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_20.2340719258
Short name	T157
Test name
Test status
Simulation time	4841353694 ps
CPU time	751.54 seconds
Started	Jul 19 06:58:35 PM PDT 24
Finished	Jul 19 07:11:07 PM PDT 24
Peak memory	610004 kb
Host	smart-f8966f91-e534-44c1-aa36-ecd75054d0f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340719258 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2340719258
Directory	/workspace/2.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4211241545
Short name	T323
Test name
Test status
Simulation time	2755689360 ps
CPU time	318.54 seconds
Started	Jul 19 06:42:34 PM PDT 24
Finished	Jul 19 06:47:53 PM PDT 24
Peak memory	609288 kb
Host	smart-6569b498-33d1-4314-99ad-c0cc855de30a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4211241545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.4211241545
Directory	/workspace/0.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1729631170
Short name	T3
Test name
Test status
Simulation time	24346883780 ps
CPU time	1677.02 seconds
Started	Jul 19 07:00:59 PM PDT 24
Finished	Jul 19 07:29:02 PM PDT 24
Peak memory	610808 kb
Host	smart-132f1e7a-6330-48f2-9fb9-43a99d2a36ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1729631170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1729631170
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio_smoketest.50334111
Short name	T6
Test name
Test status
Simulation time	2426831796 ps
CPU time	326.17 seconds
Started	Jul 19 06:40:05 PM PDT 24
Finished	Jul 19 06:45:32 PM PDT 24
Peak memory	609952 kb
Host	smart-5dc3bb8a-4825-4f97-a212-a8e0f3e5d63b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50334111 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_gpio_smoketest.50334111
Directory	/workspace/0.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1251061379
Short name	T83
Test name
Test status
Simulation time	7449811440 ps
CPU time	1543 seconds
Started	Jul 19 06:44:30 PM PDT 24
Finished	Jul 19 07:10:13 PM PDT 24
Peak memory	610708 kb
Host	smart-e78788f5-f4fe-441c-aea7-bb0fc6e49733
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1251061379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1251061379
Directory	/workspace/1.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_10.1408567926
Short name	T114
Test name
Test status
Simulation time	4107999900 ps
CPU time	638.57 seconds
Started	Jul 19 06:41:05 PM PDT 24
Finished	Jul 19 06:51:44 PM PDT 24
Peak memory	609808 kb
Host	smart-0368b992-8a12-4a48-b9fb-145c17a59231
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408567926 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1408567926
Directory	/workspace/0.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1794592604
Short name	T129
Test name
Test status
Simulation time	12285033070 ps
CPU time	1486.28 seconds
Started	Jul 19 06:43:57 PM PDT 24
Finished	Jul 19 07:08:44 PM PDT 24
Peak memory	610416 kb
Host	smart-9669baa1-d566-4491-8850-be34d2462844
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794592604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.1794592604
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.389505439
Short name	T165
Test name
Test status
Simulation time	58052561356 ps
CPU time	11154.9 seconds
Started	Jul 19 06:43:08 PM PDT 24
Finished	Jul 19 09:49:05 PM PDT 24
Peak memory	624728 kb
Host	smart-0edea351-5079-4e57-a69b-76d6371bbe11
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=389505439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.389505439
Directory	/workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1656531459
Short name	T293
Test name
Test status
Simulation time	5857195164 ps
CPU time	524.56 seconds
Started	Jul 19 06:40:16 PM PDT 24
Finished	Jul 19 06:49:01 PM PDT 24
Peak memory	610272 kb
Host	smart-291bd76a-05de-43d6-b4b0-288903470474
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656531459 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.1656531459
Directory	/workspace/0.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3613257595
Short name	T34
Test name
Test status
Simulation time	2785972424 ps
CPU time	343.57 seconds
Started	Jul 19 06:43:54 PM PDT 24
Finished	Jul 19 06:49:39 PM PDT 24
Peak memory	609372 kb
Host	smart-445e12da-ed17-4515-b52a-08563c58420f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613257595 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3613257595
Directory	/workspace/0.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.344710409
Short name	T43
Test name
Test status
Simulation time	5178881520 ps
CPU time	794.75 seconds
Started	Jul 19 06:42:18 PM PDT 24
Finished	Jul 19 06:55:35 PM PDT 24
Peak memory	619408 kb
Host	smart-b9c6771e-2332-49c9-af2a-f2bc5f917c95
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=344710409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.344710409
Directory	/workspace/0.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/0.chip_jtag_csr_rw.552193988
Short name	T64
Test name
Test status
Simulation time	10537695960 ps
CPU time	1599.09 seconds
Started	Jul 19 06:31:28 PM PDT 24
Finished	Jul 19 06:58:08 PM PDT 24
Peak memory	604044 kb
Host	smart-c20f4980-0d61-4df7-9c03-e836a08cc704
User	root
Command	/workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552193988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.ch ip_jtag_csr_rw.552193988
Directory	/workspace/0.chip_jtag_csr_rw/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2980359240
Short name	T92
Test name
Test status
Simulation time	5415365542 ps
CPU time	563.23 seconds
Started	Jul 19 06:44:22 PM PDT 24
Finished	Jul 19 06:53:46 PM PDT 24
Peak memory	609312 kb
Host	smart-754b31eb-58c1-446f-92c3-9e6a4d9e5862
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29803592 40 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2980359240
Directory	/workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2745636743
Short name	T18
Test name
Test status
Simulation time	5040655609 ps
CPU time	702.41 seconds
Started	Jul 19 06:45:11 PM PDT 24
Finished	Jul 19 06:56:54 PM PDT 24
Peak memory	624756 kb
Host	smart-99ca2a69-72da-4e98-93e8-022db8bcf24b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745636743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2745636743
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.4162767126
Short name	T182
Test name
Test status
Simulation time	44916708796 ps
CPU time	4933.46 seconds
Started	Jul 19 06:53:12 PM PDT 24
Finished	Jul 19 08:15:27 PM PDT 24
Peak memory	619796 kb
Host	smart-442564a5-3f38-44a3-a424-705a1d9a0d88
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4162767126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.4162767126
Directory	/workspace/2.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3892948486
Short name	T45
Test name
Test status
Simulation time	2502549754 ps
CPU time	408.64 seconds
Started	Jul 19 06:53:50 PM PDT 24
Finished	Jul 19 07:00:51 PM PDT 24
Peak memory	610168 kb
Host	smart-85c1e1e0-4803-4541-b33a-b8d4ce6c735b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892948486 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3892948486
Directory	/workspace/2.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1297082909
Short name	T25
Test name
Test status
Simulation time	3156203638 ps
CPU time	394.08 seconds
Started	Jul 19 06:54:24 PM PDT 24
Finished	Jul 19 07:02:03 PM PDT 24
Peak memory	609272 kb
Host	smart-a0e0af77-726f-4d1b-b90b-dabdabd22c08
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297 082909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.1297082909
Directory	/workspace/2.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2776115431
Short name	T10
Test name
Test status
Simulation time	3944697548 ps
CPU time	366.74 seconds
Started	Jul 19 06:54:36 PM PDT 24
Finished	Jul 19 07:01:50 PM PDT 24
Peak memory	610036 kb
Host	smart-c3a6c16b-94bc-410b-9e2b-eb7820f0214f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776115431 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2776115431
Directory	/workspace/2.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2366467584
Short name	T260
Test name
Test status
Simulation time	4844176648 ps
CPU time	542.92 seconds
Started	Jul 19 06:52:21 PM PDT 24
Finished	Jul 19 07:01:24 PM PDT 24
Peak memory	650144 kb
Host	smart-5ce5ed7c-dc09-45d0-9fb0-0f2b46204aa8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2366467584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2366467584
Directory	/workspace/2.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3182960238
Short name	T404
Test name
Test status
Simulation time	4665517784 ps
CPU time	608.24 seconds
Started	Jul 19 07:07:40 PM PDT 24
Finished	Jul 19 07:17:50 PM PDT 24
Peak memory	650012 kb
Host	smart-c7075cc7-addb-42a4-bfbb-2f74e17ebb4a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3182960238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.3182960238
Directory	/workspace/40.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1455749416
Short name	T21
Test name
Test status
Simulation time	4414900490 ps
CPU time	496.74 seconds
Started	Jul 19 06:41:50 PM PDT 24
Finished	Jul 19 06:50:08 PM PDT 24
Peak memory	610608 kb
Host	smart-b13f548a-dbf0-4864-b816-526a6061963b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14 55749416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1455749416
Directory	/workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.580589083
Short name	T26
Test name
Test status
Simulation time	3137472913 ps
CPU time	294.38 seconds
Started	Jul 19 06:43:19 PM PDT 24
Finished	Jul 19 06:48:14 PM PDT 24
Peak memory	609868 kb
Host	smart-9ff3aa50-5a2e-4712-a511-7970833ceae6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5805 89083 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.580589083
Directory	/workspace/1.chip_sw_sleep_pin_mio_dio_val/latest

Test location	/workspace/coverage/default/90.chip_sw_all_escalation_resets.1828002156
Short name	T277
Test name
Test status
Simulation time	6128194384 ps
CPU time	619.35 seconds
Started	Jul 19 07:11:27 PM PDT 24
Finished	Jul 19 07:21:59 PM PDT 24
Peak memory	649984 kb
Host	smart-189a9fe0-571d-45a8-a8ac-eadb66aba64a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1828002156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.1828002156
Directory	/workspace/90.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/45.chip_sw_all_escalation_resets.1327903404
Short name	T134
Test name
Test status
Simulation time	5865250942 ps
CPU time	605.13 seconds
Started	Jul 19 07:07:45 PM PDT 24
Finished	Jul 19 07:17:51 PM PDT 24
Peak memory	650628 kb
Host	smart-34e887ad-594b-4b31-baee-b21e5a1df8bb
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1327903404 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1327903404
Directory	/workspace/45.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3771813713
Short name	T177
Test name
Test status
Simulation time	5862862168 ps
CPU time	496.7 seconds
Started	Jul 19 06:40:10 PM PDT 24
Finished	Jul 19 06:48:28 PM PDT 24
Peak memory	619648 kb
Host	smart-ade3927f-e5c8-40bc-9655-43936d71bc9d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3771813713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.3771813713
Directory	/workspace/0.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3821377379
Short name	T199
Test name
Test status
Simulation time	5852026592 ps
CPU time	605.62 seconds
Started	Jul 19 06:41:35 PM PDT 24
Finished	Jul 19 06:51:41 PM PDT 24
Peak memory	610564 kb
Host	smart-14b6f434-6f6b-4cce-bd44-0e5384068edc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3821377379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3821377379
Directory	/workspace/1.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.224272947
Short name	T195
Test name
Test status
Simulation time	45144590500 ps
CPU time	7037.33 seconds
Started	Jul 19 06:38:05 PM PDT 24
Finished	Jul 19 08:35:24 PM PDT 24
Peak memory	623024 kb
Host	smart-5a5431e7-5fe9-4d67-9d1f-774b22ba67ff
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=224272947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.224272947
Directory	/workspace/0.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2395489892
Short name	T79
Test name
Test status
Simulation time	13725979280 ps
CPU time	3437.59 seconds
Started	Jul 19 07:08:42 PM PDT 24
Finished	Jul 19 08:06:05 PM PDT 24
Peak memory	610248 kb
Host	smart-03016d6e-b510-4977-b20b-c94ccde48349
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395489892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.2395489892
Directory	/workspace/3.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/68.chip_sw_all_escalation_resets.328861689
Short name	T198
Test name
Test status
Simulation time	3874081928 ps
CPU time	536.72 seconds
Started	Jul 19 07:09:05 PM PDT 24
Finished	Jul 19 07:18:11 PM PDT 24
Peak memory	649412 kb
Host	smart-a5533827-42f5-4b1e-bccd-f4c31d48b36b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 328861689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.328861689
Directory	/workspace/68.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2481333563
Short name	T13
Test name
Test status
Simulation time	4987531940 ps
CPU time	424.3 seconds
Started	Jul 19 06:41:38 PM PDT 24
Finished	Jul 19 06:48:44 PM PDT 24
Peak memory	610648 kb
Host	smart-cebb46c4-d347-4d7e-8795-16a71598f677
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481333563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2481333563
Directory	/workspace/0.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1663843576
Short name	T201
Test name
Test status
Simulation time	4620193558 ps
CPU time	257.83 seconds
Started	Jul 19 04:48:47 PM PDT 24
Finished	Jul 19 04:53:20 PM PDT 24
Peak memory	649152 kb
Host	smart-cc0a11c8-9dfc-47ba-8b36-ec0c226f2a34
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663843576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.1663843576
Directory	/workspace/6.chip_padctrl_attributes/latest

Test location	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2680513282
Short name	T288
Test name
Test status
Simulation time	5436931768 ps
CPU time	626.79 seconds
Started	Jul 19 07:08:34 PM PDT 24
Finished	Jul 19 07:19:02 PM PDT 24
Peak memory	650108 kb
Host	smart-6e4041ed-28a7-4e37-9e72-f1ffef4967b8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2680513282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2680513282
Directory	/workspace/23.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/59.chip_sw_all_escalation_resets.2067679377
Short name	T107
Test name
Test status
Simulation time	6031298150 ps
CPU time	645.89 seconds
Started	Jul 19 07:10:43 PM PDT 24
Finished	Jul 19 07:21:32 PM PDT 24
Peak memory	650128 kb
Host	smart-1c58d9e9-5fbe-492e-a028-a28e75f46fda
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2067679377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2067679377
Directory	/workspace/59.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4131755134
Short name	T29
Test name
Test status
Simulation time	4395255286 ps
CPU time	520.34 seconds
Started	Jul 19 06:41:47 PM PDT 24
Finished	Jul 19 06:50:28 PM PDT 24
Peak memory	624820 kb
Host	smart-131dab6d-67ea-48d5-b0c0-8034c4c2e631
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131755134 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.4131755134
Directory	/workspace/0.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675158095
Short name	T19
Test name
Test status
Simulation time	4191597468 ps
CPU time	410.3 seconds
Started	Jul 19 07:09:55 PM PDT 24
Finished	Jul 19 07:16:48 PM PDT 24
Peak memory	648584 kb
Host	smart-7d1590d0-4348-40aa-ab84-4018b0fcd3ec
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675158095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3675158095
Directory	/workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/36.chip_sw_all_escalation_resets.577975387
Short name	T526
Test name
Test status
Simulation time	4613300460 ps
CPU time	508.2 seconds
Started	Jul 19 07:06:32 PM PDT 24
Finished	Jul 19 07:15:01 PM PDT 24
Peak memory	650188 kb
Host	smart-38e8afe9-3094-400b-963c-d0602cfd85f7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 577975387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.577975387
Directory	/workspace/36.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/66.chip_sw_all_escalation_resets.2187935910
Short name	T207
Test name
Test status
Simulation time	5121910880 ps
CPU time	637.74 seconds
Started	Jul 19 07:11:33 PM PDT 24
Finished	Jul 19 07:22:21 PM PDT 24
Peak memory	649868 kb
Host	smart-254317a3-06c4-4a3f-8eb4-facbf84e2887
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2187935910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2187935910
Directory	/workspace/66.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_all_escalation_resets.348761848
Short name	T146
Test name
Test status
Simulation time	5103801992 ps
CPU time	549.77 seconds
Started	Jul 19 07:09:58 PM PDT 24
Finished	Jul 19 07:19:10 PM PDT 24
Peak memory	649792 kb
Host	smart-e87c3b1d-d870-4686-b135-1e3238ecb154
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 348761848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.348761848
Directory	/workspace/75.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2491542396
Short name	T193
Test name
Test status
Simulation time	5472968272 ps
CPU time	770.59 seconds
Started	Jul 19 07:08:54 PM PDT 24
Finished	Jul 19 07:21:48 PM PDT 24
Peak memory	649908 kb
Host	smart-259a7eb0-23ba-415c-9f1c-6b212b210757
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2491542396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.2491542396
Directory	/workspace/39.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2365704985
Short name	T486
Test name
Test status
Simulation time	5520979466 ps
CPU time	670.91 seconds
Started	Jul 19 07:07:12 PM PDT 24
Finished	Jul 19 07:18:24 PM PDT 24
Peak memory	649916 kb
Host	smart-7a46a605-1b10-4cb8-95a0-7340e8f3fcf8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2365704985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.2365704985
Directory	/workspace/16.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743561453
Short name	T71
Test name
Test status
Simulation time	3768875918 ps
CPU time	443.62 seconds
Started	Jul 19 07:09:30 PM PDT 24
Finished	Jul 19 07:17:06 PM PDT 24
Peak memory	648780 kb
Host	smart-97c4cfbf-edeb-4cf9-a208-2214f57fd424
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743561453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3743561453
Directory	/workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2334557720
Short name	T427
Test name
Test status
Simulation time	3513942250 ps
CPU time	428.89 seconds
Started	Jul 19 06:45:17 PM PDT 24
Finished	Jul 19 06:52:27 PM PDT 24
Peak memory	648912 kb
Host	smart-7d40ac49-9e3a-43d2-94af-d6ceae588242
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334557720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.2334557720
Directory	/workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1335262550
Short name	T963
Test name
Test status
Simulation time	4759542576 ps
CPU time	739.24 seconds
Started	Jul 19 06:47:45 PM PDT 24
Finished	Jul 19 07:00:05 PM PDT 24
Peak memory	649964 kb
Host	smart-c5bb7d8c-b800-4e27-b7b7-95b38685d07e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1335262550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1335262550
Directory	/workspace/1.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560267897
Short name	T946
Test name
Test status
Simulation time	3830748126 ps
CPU time	429.67 seconds
Started	Jul 19 07:05:51 PM PDT 24
Finished	Jul 19 07:13:01 PM PDT 24
Peak memory	648904 kb
Host	smart-b14f0729-037f-43a4-b87c-b9d73a7f1e66
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560267897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3560267897
Directory	/workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1971409254
Short name	T437
Test name
Test status
Simulation time	6188985732 ps
CPU time	781.77 seconds
Started	Jul 19 07:06:58 PM PDT 24
Finished	Jul 19 07:20:02 PM PDT 24
Peak memory	649752 kb
Host	smart-f6dac03c-a87b-49eb-8473-b60cc997199d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1971409254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1971409254
Directory	/workspace/11.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4237102201
Short name	T373
Test name
Test status
Simulation time	4875669664 ps
CPU time	614.96 seconds
Started	Jul 19 07:06:36 PM PDT 24
Finished	Jul 19 07:16:52 PM PDT 24
Peak memory	649808 kb
Host	smart-555f2b17-b179-4e0e-bef9-89ce97aaf72b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4237102201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.4237102201
Directory	/workspace/12.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426143957
Short name	T415
Test name
Test status
Simulation time	3951588690 ps
CPU time	382.23 seconds
Started	Jul 19 07:05:07 PM PDT 24
Finished	Jul 19 07:11:30 PM PDT 24
Peak memory	648812 kb
Host	smart-4625e74c-82f8-4fe9-ba5d-8c8c7cdc9cdc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426143957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1426143957
Directory	/workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/13.chip_sw_all_escalation_resets.4044272371
Short name	T518
Test name
Test status
Simulation time	6015586902 ps
CPU time	658.07 seconds
Started	Jul 19 07:04:04 PM PDT 24
Finished	Jul 19 07:15:02 PM PDT 24
Peak memory	649988 kb
Host	smart-5be7b114-18df-42b8-91f2-aa8c75ce7ab6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4044272371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.4044272371
Directory	/workspace/13.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2806405632
Short name	T477
Test name
Test status
Simulation time	4157800810 ps
CPU time	405.58 seconds
Started	Jul 19 07:07:21 PM PDT 24
Finished	Jul 19 07:14:12 PM PDT 24
Peak memory	648572 kb
Host	smart-83da0854-3528-4738-9ff4-f68ad08fcf4d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806405632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2806405632
Directory	/workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/14.chip_sw_all_escalation_resets.678816535
Short name	T289
Test name
Test status
Simulation time	4287726990 ps
CPU time	438.89 seconds
Started	Jul 19 07:05:59 PM PDT 24
Finished	Jul 19 07:13:19 PM PDT 24
Peak memory	649972 kb
Host	smart-4e3016d0-158d-4f28-8ae1-f689b7267a09
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 678816535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.678816535
Directory	/workspace/14.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/15.chip_sw_all_escalation_resets.3411933467
Short name	T430
Test name
Test status
Simulation time	6098076792 ps
CPU time	698.96 seconds
Started	Jul 19 07:04:51 PM PDT 24
Finished	Jul 19 07:16:31 PM PDT 24
Peak memory	649740 kb
Host	smart-20aa3a37-ab81-4e2b-bfdd-38d29d45b85c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3411933467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.3411933467
Directory	/workspace/15.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3779651895
Short name	T401
Test name
Test status
Simulation time	3820684588 ps
CPU time	375.75 seconds
Started	Jul 19 07:05:06 PM PDT 24
Finished	Jul 19 07:11:23 PM PDT 24
Peak memory	649060 kb
Host	smart-95c7079e-6b76-4163-8713-121af0168914
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779651895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3779651895
Directory	/workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2394636195
Short name	T496
Test name
Test status
Simulation time	3302434804 ps
CPU time	388.83 seconds
Started	Jul 19 07:06:54 PM PDT 24
Finished	Jul 19 07:13:24 PM PDT 24
Peak memory	648896 kb
Host	smart-6875737b-ed7c-44fe-991c-daa80bc488bc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394636195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2394636195
Directory	/workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690797726
Short name	T531
Test name
Test status
Simulation time	4140714060 ps
CPU time	503.96 seconds
Started	Jul 19 07:06:23 PM PDT 24
Finished	Jul 19 07:14:48 PM PDT 24
Peak memory	648788 kb
Host	smart-af682ddc-d56d-459c-b4b2-9567e5726d30
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690797726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1690797726
Directory	/workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/18.chip_sw_all_escalation_resets.4149122537
Short name	T464
Test name
Test status
Simulation time	3786742456 ps
CPU time	494.4 seconds
Started	Jul 19 07:06:22 PM PDT 24
Finished	Jul 19 07:14:38 PM PDT 24
Peak memory	649488 kb
Host	smart-6dbbe4f4-79cd-45c9-855e-63344f645841
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4149122537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.4149122537
Directory	/workspace/18.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.558797607
Short name	T944
Test name
Test status
Simulation time	4146462324 ps
CPU time	514.38 seconds
Started	Jul 19 07:07:29 PM PDT 24
Finished	Jul 19 07:16:09 PM PDT 24
Peak memory	648808 kb
Host	smart-5c54fded-1e9a-40cd-8b38-268d1c755c69
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558797607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_s w_alert_handler_lpg_sleep_mode_alerts.558797607
Directory	/workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/19.chip_sw_all_escalation_resets.3190820702
Short name	T471
Test name
Test status
Simulation time	5579413968 ps
CPU time	653.55 seconds
Started	Jul 19 07:04:54 PM PDT 24
Finished	Jul 19 07:15:49 PM PDT 24
Peak memory	649732 kb
Host	smart-5ca87462-008d-45b1-8c12-2cdb9151dd2e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3190820702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3190820702
Directory	/workspace/19.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.663757734
Short name	T330
Test name
Test status
Simulation time	3964066722 ps
CPU time	451.12 seconds
Started	Jul 19 06:55:56 PM PDT 24
Finished	Jul 19 07:03:39 PM PDT 24
Peak memory	648808 kb
Host	smart-34f261d4-b154-4040-b29c-0169fbb7660d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663757734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _alert_handler_lpg_sleep_mode_alerts.663757734
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2366285314
Short name	T514
Test name
Test status
Simulation time	4067289520 ps
CPU time	409.66 seconds
Started	Jul 19 07:08:41 PM PDT 24
Finished	Jul 19 07:15:36 PM PDT 24
Peak memory	648976 kb
Host	smart-8a3bb891-0c90-4fa5-b2c2-1e4a441329c3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366285314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2366285314
Directory	/workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3542557095
Short name	T480
Test name
Test status
Simulation time	4136606650 ps
CPU time	432.25 seconds
Started	Jul 19 07:05:15 PM PDT 24
Finished	Jul 19 07:12:29 PM PDT 24
Peak memory	648616 kb
Host	smart-c32da729-dd9f-45ff-91e5-4163de6013f0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542557095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3542557095
Directory	/workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2310819662
Short name	T519
Test name
Test status
Simulation time	3480693752 ps
CPU time	353.67 seconds
Started	Jul 19 07:08:09 PM PDT 24
Finished	Jul 19 07:14:04 PM PDT 24
Peak memory	648528 kb
Host	smart-2ba8b36b-a134-4640-9e5e-16a429cbb039
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310819662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2310819662
Directory	/workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.664451224
Short name	T460
Test name
Test status
Simulation time	3258843244 ps
CPU time	345.45 seconds
Started	Jul 19 07:05:54 PM PDT 24
Finished	Jul 19 07:11:40 PM PDT 24
Peak memory	648596 kb
Host	smart-37877071-5d8e-415f-a19c-3edbe18e4b20
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664451224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.664451224
Directory	/workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2693698622
Short name	T273
Test name
Test status
Simulation time	5829126396 ps
CPU time	685.58 seconds
Started	Jul 19 07:05:47 PM PDT 24
Finished	Jul 19 07:17:14 PM PDT 24
Peak memory	650244 kb
Host	smart-e718f061-77e6-4299-bc4a-8344209265a6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2693698622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2693698622
Directory	/workspace/27.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663919648
Short name	T527
Test name
Test status
Simulation time	4289990868 ps
CPU time	411.37 seconds
Started	Jul 19 07:05:57 PM PDT 24
Finished	Jul 19 07:12:50 PM PDT 24
Peak memory	649120 kb
Host	smart-8caec997-c9d5-4bcc-8feb-0aa3d9133050
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663919648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1663919648
Directory	/workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.475222130
Short name	T372
Test name
Test status
Simulation time	4070419088 ps
CPU time	504.2 seconds
Started	Jul 19 07:06:32 PM PDT 24
Finished	Jul 19 07:14:57 PM PDT 24
Peak memory	648772 kb
Host	smart-431efbcd-3586-4133-8875-0cffcef50408
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475222130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_s w_alert_handler_lpg_sleep_mode_alerts.475222130
Directory	/workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/31.chip_sw_all_escalation_resets.2293404381
Short name	T455
Test name
Test status
Simulation time	4977128272 ps
CPU time	889.84 seconds
Started	Jul 19 07:06:34 PM PDT 24
Finished	Jul 19 07:21:26 PM PDT 24
Peak memory	650076 kb
Host	smart-39844f52-4e40-4083-95b8-7e009e2d7ac6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2293404381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2293404381
Directory	/workspace/31.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.660748518
Short name	T133
Test name
Test status
Simulation time	3895496264 ps
CPU time	428.06 seconds
Started	Jul 19 07:07:56 PM PDT 24
Finished	Jul 19 07:15:05 PM PDT 24
Peak memory	649368 kb
Host	smart-7c230ebb-6e50-43e7-99f6-942d1eef0024
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660748518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_s w_alert_handler_lpg_sleep_mode_alerts.660748518
Directory	/workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1557181797
Short name	T533
Test name
Test status
Simulation time	3806624410 ps
CPU time	430.37 seconds
Started	Jul 19 07:09:30 PM PDT 24
Finished	Jul 19 07:16:53 PM PDT 24
Peak memory	648724 kb
Host	smart-7138c21f-7689-4d11-9a5c-e5882dd79710
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557181797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1557181797
Directory	/workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2180657938
Short name	T748
Test name
Test status
Simulation time	4510443190 ps
CPU time	556.09 seconds
Started	Jul 19 07:06:03 PM PDT 24
Finished	Jul 19 07:15:20 PM PDT 24
Peak memory	649836 kb
Host	smart-7aba6476-cfe0-408a-90f7-6ebdce911b6f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2180657938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2180657938
Directory	/workspace/33.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.998460690
Short name	T537
Test name
Test status
Simulation time	4366545928 ps
CPU time	467.99 seconds
Started	Jul 19 07:06:42 PM PDT 24
Finished	Jul 19 07:14:31 PM PDT 24
Peak memory	649052 kb
Host	smart-cbd637e1-574c-468e-a8bb-896cdac672cd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998460690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_s w_alert_handler_lpg_sleep_mode_alerts.998460690
Directory	/workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2338121666
Short name	T469
Test name
Test status
Simulation time	4872076276 ps
CPU time	575.07 seconds
Started	Jul 19 07:07:21 PM PDT 24
Finished	Jul 19 07:17:01 PM PDT 24
Peak memory	649832 kb
Host	smart-5d018168-2e5a-4651-8a27-6b8b801c03e4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2338121666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2338121666
Directory	/workspace/35.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2302870110
Short name	T375
Test name
Test status
Simulation time	3729834456 ps
CPU time	410.7 seconds
Started	Jul 19 07:08:41 PM PDT 24
Finished	Jul 19 07:15:35 PM PDT 24
Peak memory	648472 kb
Host	smart-80371039-1e2e-4c4c-8dcd-1ce1c98f2ac4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302870110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2302870110
Directory	/workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3320378298
Short name	T475
Test name
Test status
Simulation time	5807658648 ps
CPU time	610.64 seconds
Started	Jul 19 07:07:37 PM PDT 24
Finished	Jul 19 07:17:50 PM PDT 24
Peak memory	649904 kb
Host	smart-1f15cf79-95f0-4f02-bc23-15d28a2d9042
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3320378298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.3320378298
Directory	/workspace/43.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1648334229
Short name	T539
Test name
Test status
Simulation time	3919721400 ps
CPU time	284.4 seconds
Started	Jul 19 07:08:03 PM PDT 24
Finished	Jul 19 07:12:48 PM PDT 24
Peak memory	648568 kb
Host	smart-9672c3c6-eb66-4f2b-bfec-faa96dacad9d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648334229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1648334229
Directory	/workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3537680296
Short name	T262
Test name
Test status
Simulation time	3525143272 ps
CPU time	447.33 seconds
Started	Jul 19 07:07:55 PM PDT 24
Finished	Jul 19 07:15:23 PM PDT 24
Peak memory	648968 kb
Host	smart-b96b4f97-ab27-482f-a1fa-f0f8c3537788
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537680296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3537680296
Directory	/workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2964164641
Short name	T458
Test name
Test status
Simulation time	4307008058 ps
CPU time	563.96 seconds
Started	Jul 19 07:09:29 PM PDT 24
Finished	Jul 19 07:19:08 PM PDT 24
Peak memory	650148 kb
Host	smart-53981476-c124-4662-bb54-8c6e4adcf262
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2964164641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2964164641
Directory	/workspace/47.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2846773116
Short name	T462
Test name
Test status
Simulation time	5036236118 ps
CPU time	668.14 seconds
Started	Jul 19 07:09:02 PM PDT 24
Finished	Jul 19 07:20:18 PM PDT 24
Peak memory	649852 kb
Host	smart-a2f4a46a-878b-45df-999a-eb1b9e84be4d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2846773116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2846773116
Directory	/workspace/48.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2014736738
Short name	T142
Test name
Test status
Simulation time	3703665416 ps
CPU time	440.33 seconds
Started	Jul 19 07:10:27 PM PDT 24
Finished	Jul 19 07:17:51 PM PDT 24
Peak memory	648768 kb
Host	smart-ac7fff19-f2dd-4116-bd93-6b045d6818af
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014736738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2014736738
Directory	/workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2861979553
Short name	T501
Test name
Test status
Simulation time	6047460014 ps
CPU time	758.47 seconds
Started	Jul 19 07:13:14 PM PDT 24
Finished	Jul 19 07:25:56 PM PDT 24
Peak memory	650220 kb
Host	smart-616bc6a0-d3ce-468c-844d-485fb455e811
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2861979553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2861979553
Directory	/workspace/49.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2751167640
Short name	T435
Test name
Test status
Simulation time	4911198500 ps
CPU time	836.67 seconds
Started	Jul 19 07:04:03 PM PDT 24
Finished	Jul 19 07:18:01 PM PDT 24
Peak memory	650096 kb
Host	smart-414dc18d-7fae-4bee-8c68-e6230f1de396
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2751167640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2751167640
Directory	/workspace/5.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386604172
Short name	T522
Test name
Test status
Simulation time	3169145580 ps
CPU time	351.96 seconds
Started	Jul 19 07:14:02 PM PDT 24
Finished	Jul 19 07:19:56 PM PDT 24
Peak memory	648788 kb
Host	smart-cafc5058-9e81-4f72-b7f7-29a05f935442
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386604172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2386604172
Directory	/workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.269677592
Short name	T988
Test name
Test status
Simulation time	3654565644 ps
CPU time	370.88 seconds
Started	Jul 19 07:10:06 PM PDT 24
Finished	Jul 19 07:16:18 PM PDT 24
Peak memory	648804 kb
Host	smart-b2a95fb6-57c8-405b-a8ea-f59d85ae526a
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269677592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.269677592
Directory	/workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1824238013
Short name	T502
Test name
Test status
Simulation time	3972388180 ps
CPU time	383.38 seconds
Started	Jul 19 07:09:23 PM PDT 24
Finished	Jul 19 07:16:02 PM PDT 24
Peak memory	648908 kb
Host	smart-58fc9c16-d98a-4cbc-84f4-2affad1b7c98
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824238013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1824238013
Directory	/workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3516341477
Short name	T506
Test name
Test status
Simulation time	4852522048 ps
CPU time	715.88 seconds
Started	Jul 19 07:07:53 PM PDT 24
Finished	Jul 19 07:19:50 PM PDT 24
Peak memory	649860 kb
Host	smart-2ba7c704-2041-474c-931d-58ceb728dec6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3516341477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.3516341477
Directory	/workspace/53.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1229673525
Short name	T504
Test name
Test status
Simulation time	5167841234 ps
CPU time	617.65 seconds
Started	Jul 19 07:09:53 PM PDT 24
Finished	Jul 19 07:20:12 PM PDT 24
Peak memory	649836 kb
Host	smart-13c583c8-f47b-4699-a32f-a629cf44a671
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1229673525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.1229673525
Directory	/workspace/54.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/57.chip_sw_all_escalation_resets.3447555678
Short name	T509
Test name
Test status
Simulation time	5838897936 ps
CPU time	697.89 seconds
Started	Jul 19 07:10:57 PM PDT 24
Finished	Jul 19 07:22:39 PM PDT 24
Peak memory	650000 kb
Host	smart-87aaa6d8-4059-4172-8880-a148cd10193f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3447555678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3447555678
Directory	/workspace/57.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.479937528
Short name	T148
Test name
Test status
Simulation time	3799434342 ps
CPU time	463.85 seconds
Started	Jul 19 07:03:57 PM PDT 24
Finished	Jul 19 07:11:42 PM PDT 24
Peak memory	648728 kb
Host	smart-5896faed-58bd-47ab-9984-7221f8b3130b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479937528 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.479937528
Directory	/workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/60.chip_sw_all_escalation_resets.2911373543
Short name	T290
Test name
Test status
Simulation time	5058402952 ps
CPU time	515.32 seconds
Started	Jul 19 07:11:19 PM PDT 24
Finished	Jul 19 07:20:10 PM PDT 24
Peak memory	650196 kb
Host	smart-ddad6e65-36f3-49b4-878e-1e277a72164a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2911373543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2911373543
Directory	/workspace/60.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134057863
Short name	T406
Test name
Test status
Simulation time	3729329412 ps
CPU time	426.43 seconds
Started	Jul 19 07:10:32 PM PDT 24
Finished	Jul 19 07:17:39 PM PDT 24
Peak memory	648532 kb
Host	smart-bc0d1c65-29ef-41ac-9ab3-a45a46dbc2b5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134057863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2134057863
Directory	/workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.930477082
Short name	T453
Test name
Test status
Simulation time	3958175954 ps
CPU time	513.4 seconds
Started	Jul 19 07:09:14 PM PDT 24
Finished	Jul 19 07:18:01 PM PDT 24
Peak memory	648772 kb
Host	smart-62ac2a48-742c-494a-a735-d63537483e2c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930477082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.930477082
Directory	/workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1441725777
Short name	T499
Test name
Test status
Simulation time	3957487390 ps
CPU time	345.45 seconds
Started	Jul 19 07:09:37 PM PDT 24
Finished	Jul 19 07:15:32 PM PDT 24
Peak memory	649032 kb
Host	smart-fedc4418-af1c-40da-b1ad-80b75d9aeb31
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441725777 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1441725777
Directory	/workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2826664155
Short name	T393
Test name
Test status
Simulation time	5302644060 ps
CPU time	599.79 seconds
Started	Jul 19 07:09:53 PM PDT 24
Finished	Jul 19 07:19:55 PM PDT 24
Peak memory	650004 kb
Host	smart-4c9a7bc1-54e5-4745-bc29-00fb8038bc18
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2826664155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.2826664155
Directory	/workspace/72.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3819859945
Short name	T278
Test name
Test status
Simulation time	3513271460 ps
CPU time	416.95 seconds
Started	Jul 19 07:10:03 PM PDT 24
Finished	Jul 19 07:17:01 PM PDT 24
Peak memory	648764 kb
Host	smart-89968eea-a648-483e-a988-e5fc34f59702
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819859945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3819859945
Directory	/workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2257155005
Short name	T242
Test name
Test status
Simulation time	5521060020 ps
CPU time	567.01 seconds
Started	Jul 19 07:10:46 PM PDT 24
Finished	Jul 19 07:20:15 PM PDT 24
Peak memory	650020 kb
Host	smart-f2b32652-166c-4590-b326-a6ad94adf8b8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2257155005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.2257155005
Directory	/workspace/76.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4085533151
Short name	T491
Test name
Test status
Simulation time	3368673580 ps
CPU time	453.06 seconds
Started	Jul 19 07:05:24 PM PDT 24
Finished	Jul 19 07:13:01 PM PDT 24
Peak memory	648484 kb
Host	smart-25b5789f-c526-407b-af86-0020c43c2dff
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085533151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.4085533151
Directory	/workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741445742
Short name	T463
Test name
Test status
Simulation time	3591852500 ps
CPU time	365.03 seconds
Started	Jul 19 07:11:28 PM PDT 24
Finished	Jul 19 07:17:45 PM PDT 24
Peak memory	648480 kb
Host	smart-ef80625f-181b-4e46-b0a5-bf274e168025
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741445742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2741445742
Directory	/workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/98.chip_sw_all_escalation_resets.1304706598
Short name	T536
Test name
Test status
Simulation time	5381947260 ps
CPU time	662.39 seconds
Started	Jul 19 07:12:15 PM PDT 24
Finished	Jul 19 07:23:18 PM PDT 24
Peak memory	649756 kb
Host	smart-d3a975e4-6944-4427-8998-0175b7598c95
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1304706598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.1304706598
Directory	/workspace/98.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.4255979778
Short name	T23
Test name
Test status
Simulation time	3528650664 ps
CPU time	270.59 seconds
Started	Jul 19 06:55:31 PM PDT 24
Finished	Jul 19 07:00:35 PM PDT 24
Peak memory	621032 kb
Host	smart-11bce26a-067e-420f-909e-6ffc25192552
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559797 78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.4255979778
Directory	/workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1501691385
Short name	T300
Test name
Test status
Simulation time	5464322540 ps
CPU time	615.24 seconds
Started	Jul 19 06:55:26 PM PDT 24
Finished	Jul 19 07:06:19 PM PDT 24
Peak memory	610612 kb
Host	smart-6d0360d3-0b43-4835-b7bb-4e74c62d4008
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1501691385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1501691385
Directory	/workspace/2.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_plic_sw_irq.2432576621
Short name	T187
Test name
Test status
Simulation time	2672302568 ps
CPU time	225.53 seconds
Started	Jul 19 06:59:57 PM PDT 24
Finished	Jul 19 07:03:48 PM PDT 24
Peak memory	609764 kb
Host	smart-bbe29122-1e02-4b96-a644-635dac4081de
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432576621 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2432576621
Directory	/workspace/2.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1478816040
Short name	T183
Test name
Test status
Simulation time	43690200556 ps
CPU time	5671.2 seconds
Started	Jul 19 06:41:20 PM PDT 24
Finished	Jul 19 08:15:52 PM PDT 24
Peak memory	621688 kb
Host	smart-d8ee8c68-9d0c-487a-9c27-616129e98c4c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1478816040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1478816040
Directory	/workspace/1.chip_sw_flash_rma_unlocked/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1942604870
Short name	T90
Test name
Test status
Simulation time	8882232072 ps
CPU time	954.04 seconds
Started	Jul 19 06:40:46 PM PDT 24
Finished	Jul 19 06:56:41 PM PDT 24
Peak memory	609384 kb
Host	smart-421a7308-2e3c-4cd7-9b12-ce7fd2829333
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19426048 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1942604870
Directory	/workspace/0.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_rma.337291762
Short name	T100
Test name
Test status
Simulation time	5947124207 ps
CPU time	546.56 seconds
Started	Jul 19 06:57:42 PM PDT 24
Finished	Jul 19 07:06:49 PM PDT 24
Peak memory	620932 kb
Host	smart-d67608bc-d027-4950-ab28-e1c88e097c22
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337291762 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.337291762
Directory	/workspace/2.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_0.3044616381
Short name	T230
Test name
Test status
Simulation time	5621824112 ps
CPU time	1176.51 seconds
Started	Jul 19 07:00:20 PM PDT 24
Finished	Jul 19 07:19:58 PM PDT 24
Peak memory	610044 kb
Host	smart-ce2690e7-bbaa-47d4-9782-5649c91cce3f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044616381 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3044616381
Directory	/workspace/2.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.836723708
Short name	T554
Test name
Test status
Simulation time	3550277197 ps
CPU time	294.28 seconds
Started	Jul 19 06:39:29 PM PDT 24
Finished	Jul 19 06:44:24 PM PDT 24
Peak memory	609300 kb
Host	smart-ed361dd9-9d27-4210-bdc0-477205f0c258
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836723708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.836723708
Directory	/workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.880418069
Short name	T48
Test name
Test status
Simulation time	6187178000 ps
CPU time	420.86 seconds
Started	Jul 19 06:42:38 PM PDT 24
Finished	Jul 19 06:49:39 PM PDT 24
Peak memory	610344 kb
Host	smart-3b693df7-816b-4214-a459-4d02ab58ba27
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880418069 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.880418069
Directory	/workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.559197298
Short name	T17
Test name
Test status
Simulation time	5076038136 ps
CPU time	551.15 seconds
Started	Jul 19 06:42:08 PM PDT 24
Finished	Jul 19 06:51:20 PM PDT 24
Peak memory	610720 kb
Host	smart-406d348c-df57-4762-995e-1988f876e764
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559197298 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.559197298
Directory	/workspace/1.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1420140499
Short name	T16
Test name
Test status
Simulation time	3617449960 ps
CPU time	253.36 seconds
Started	Jul 19 06:55:09 PM PDT 24
Finished	Jul 19 07:00:14 PM PDT 24
Peak memory	609284 kb
Host	smart-9cc057cc-2a43-43c0-95e6-38fe6cc9ec12
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420140499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.1420140499
Directory	/workspace/2.chip_sw_sleep_pin_wake/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.266604229
Short name	T266
Test name
Test status
Simulation time	3451340536 ps
CPU time	256.04 seconds
Started	Jul 19 06:38:53 PM PDT 24
Finished	Jul 19 06:43:10 PM PDT 24
Peak memory	609376 kb
Host	smart-19e0311b-22ae-47db-b928-d9a879696803
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266604229 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.266604229
Directory	/workspace/0.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.515286327
Short name	T636
Test name
Test status
Simulation time	12568790120 ps
CPU time	3370.35 seconds
Started	Jul 19 06:39:36 PM PDT 24
Finished	Jul 19 07:35:48 PM PDT 24
Peak memory	618436 kb
Host	smart-1d7856a0-28cf-45eb-8d42-e71889b26a38
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=515286327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.515286327
Directory	/workspace/0.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1914338045
Short name	T32
Test name
Test status
Simulation time	31832109828 ps
CPU time	7610.14 seconds
Started	Jul 19 06:40:54 PM PDT 24
Finished	Jul 19 08:47:46 PM PDT 24
Peak memory	610204 kb
Host	smart-be47d7cf-ba82-429c-b02b-2e5da8e2d99b
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1914338045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1914338045
Directory	/workspace/0.chip_sw_usbdev_pincfg/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.304653059
Short name	T223
Test name
Test status
Simulation time	32954858515 ps
CPU time	2796.63 seconds
Started	Jul 19 06:41:55 PM PDT 24
Finished	Jul 19 07:28:33 PM PDT 24
Peak memory	621176 kb
Host	smart-ee5ee4fb-fd1a-45eb-9ad5-8b296d94b746
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304653059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_ test_unlocked0.304653059
Directory	/workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1496350253
Short name	T75
Test name
Test status
Simulation time	4630162836 ps
CPU time	651.62 seconds
Started	Jul 19 06:41:00 PM PDT 24
Finished	Jul 19 06:51:53 PM PDT 24
Peak memory	610904 kb
Host	smart-ffef819e-e05e-4237-a6a3-f1506cb3d52c
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496350253 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1496350253
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_plic_all_irqs_20.3147483604
Short name	T158
Test name
Test status
Simulation time	4944139628 ps
CPU time	731.09 seconds
Started	Jul 19 06:44:10 PM PDT 24
Finished	Jul 19 06:56:22 PM PDT 24
Peak memory	609996 kb
Host	smart-e0248749-c618-4763-910c-313fd581c813
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147483604 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.3147483604
Directory	/workspace/0.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/28.chip_sw_all_escalation_resets.621140095
Short name	T122
Test name
Test status
Simulation time	4504707604 ps
CPU time	479.48 seconds
Started	Jul 19 07:05:43 PM PDT 24
Finished	Jul 19 07:13:43 PM PDT 24
Peak memory	610780 kb
Host	smart-07995871-dda3-4dff-9039-ae335fa808cc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 621140095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.621140095
Directory	/workspace/28.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_0.3256851836
Short name	T229
Test name
Test status
Simulation time	5997020044 ps
CPU time	1123.4 seconds
Started	Jul 19 06:46:09 PM PDT 24
Finished	Jul 19 07:04:53 PM PDT 24
Peak memory	610076 kb
Host	smart-f91573aa-ad6f-4530-af5b-c886df550025
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256851836 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3256851836
Directory	/workspace/1.chip_plic_all_irqs_0/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3879634470
Short name	T85
Test name
Test status
Simulation time	26005728887 ps
CPU time	4621.6 seconds
Started	Jul 19 06:39:08 PM PDT 24
Finished	Jul 19 07:56:12 PM PDT 24
Peak memory	610500 kb
Host	smart-080b3987-8785-4aa8-83a1-59d8c0449eed
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879634470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.3879634470
Directory	/workspace/0.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2967072299
Short name	T95
Test name
Test status
Simulation time	5000750328 ps
CPU time	644.26 seconds
Started	Jul 19 06:58:03 PM PDT 24
Finished	Jul 19 07:08:48 PM PDT 24
Peak memory	609412 kb
Host	smart-bb57eed1-80c1-4596-8e5f-16f4d6d8b18d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29670722 99 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2967072299
Directory	/workspace/2.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio.637468281
Short name	T38
Test name
Test status
Simulation time	4167642880 ps
CPU time	464.54 seconds
Started	Jul 19 06:47:39 PM PDT 24
Finished	Jul 19 06:55:25 PM PDT 24
Peak memory	610208 kb
Host	smart-f759e776-e027-4658-8df5-e07725e91944
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637468281 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.637468281
Directory	/workspace/1.chip_sw_gpio/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_20.3620639251
Short name	T159
Test name
Test status
Simulation time	4318850868 ps
CPU time	726.34 seconds
Started	Jul 19 06:47:34 PM PDT 24
Finished	Jul 19 06:59:41 PM PDT 24
Peak memory	610064 kb
Host	smart-e634508b-3d6e-4dcf-b20b-94466f455aa4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620639251 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.3620639251
Directory	/workspace/1.chip_plic_all_irqs_20/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3768127434
Short name	T70
Test name
Test status
Simulation time	24024083233 ps
CPU time	2592.71 seconds
Started	Jul 19 06:42:50 PM PDT 24
Finished	Jul 19 07:26:03 PM PDT 24
Peak memory	610988 kb
Host	smart-9a9c81bb-4526-4653-97cb-8d1bcb8ea46d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3768127434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3768127434
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3313816361
Short name	T171
Test name
Test status
Simulation time	2966457729 ps
CPU time	283.82 seconds
Started	Jul 19 06:42:43 PM PDT 24
Finished	Jul 19 06:47:28 PM PDT 24
Peak memory	622600 kb
Host	smart-a71dc712-b84d-4237-8f42-f293f94478e8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313816361 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3313816361
Directory	/workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init.1277975233
Short name	T341
Test name
Test status
Simulation time	22219696328 ps
CPU time	2346.89 seconds
Started	Jul 19 06:40:10 PM PDT 24
Finished	Jul 19 07:19:18 PM PDT 24
Peak memory	612580 kb
Host	smart-449deb3c-5086-4d99-a973-64366a66076d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277975233 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1277975233
Directory	/workspace/1.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_tpm.319950697
Short name	T52
Test name
Test status
Simulation time	3139811699 ps
CPU time	357.9 seconds
Started	Jul 19 06:41:32 PM PDT 24
Finished	Jul 19 06:47:31 PM PDT 24
Peak memory	619412 kb
Host	smart-c964e9f3-da3f-4dd8-a67e-9b08619365c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319950697 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.319950697
Directory	/workspace/0.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3051782274
Short name	T591
Test name
Test status
Simulation time	6538782889 ps
CPU time	503.97 seconds
Started	Jul 19 06:57:21 PM PDT 24
Finished	Jul 19 07:05:46 PM PDT 24
Peak memory	622460 kb
Host	smart-a713b2d4-ef56-4613-b670-3a1464f7e968
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051782274 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3051782274
Directory	/workspace/2.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2988204626
Short name	T9
Test name
Test status
Simulation time	26057210552 ps
CPU time	1675.29 seconds
Started	Jul 19 06:58:55 PM PDT 24
Finished	Jul 19 07:26:51 PM PDT 24
Peak memory	610816 kb
Host	smart-cd704549-b2e9-4aa7-89b6-9c117948cc48
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2988204626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2988204626
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.116655921
Short name	T190
Test name
Test status
Simulation time	7199604563 ps
CPU time	730.64 seconds
Started	Jul 19 06:40:43 PM PDT 24
Finished	Jul 19 06:52:55 PM PDT 24
Peak memory	610272 kb
Host	smart-4b7bf966-67a8-4082-8050-f9f366a6d257
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116655921 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.116655921
Directory	/workspace/0.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.888204540
Short name	T361
Test name
Test status
Simulation time	4220307960 ps
CPU time	817.62 seconds
Started	Jul 19 06:41:19 PM PDT 24
Finished	Jul 19 06:54:58 PM PDT 24
Peak memory	622516 kb
Host	smart-e305881f-ace9-4e25-9bf3-8a658044e373
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888204540 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.888204540
Directory	/workspace/0.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_plic_all_irqs_10.1326306033
Short name	T116
Test name
Test status
Simulation time	4501985500 ps
CPU time	588.05 seconds
Started	Jul 19 06:58:39 PM PDT 24
Finished	Jul 19 07:08:28 PM PDT 24
Peak memory	610032 kb
Host	smart-2b37e9da-cbc5-472f-bedf-4ac60bb529da
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326306033 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1326306033
Directory	/workspace/2.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3088098437
Short name	T104
Test name
Test status
Simulation time	3722136910 ps
CPU time	670.73 seconds
Started	Jul 19 06:42:24 PM PDT 24
Finished	Jul 19 06:53:36 PM PDT 24
Peak memory	613996 kb
Host	smart-2be66adf-c846-4b57-b829-36c71dbcf03d
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088098437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3088098437
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_irq.3454214659
Short name	T395
Test name
Test status
Simulation time	3382811952 ps
CPU time	398.95 seconds
Started	Jul 19 06:56:54 PM PDT 24
Finished	Jul 19 07:03:34 PM PDT 24
Peak memory	609300 kb
Host	smart-2f1be68e-c760-45bc-8df6-bf8a65b3fb13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454214659 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3454214659
Directory	/workspace/2.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2317565489
Short name	T447
Test name
Test status
Simulation time	4771075478 ps
CPU time	565.51 seconds
Started	Jul 19 06:39:42 PM PDT 24
Finished	Jul 19 06:49:08 PM PDT 24
Peak memory	624156 kb
Host	smart-66c1b5d3-8444-4ff9-84bd-d6383b6a4636
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317565489 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2317565489
Directory	/workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pattgen_ios.2903724442
Short name	T362
Test name
Test status
Simulation time	2791355400 ps
CPU time	335.09 seconds
Started	Jul 19 06:42:14 PM PDT 24
Finished	Jul 19 06:47:50 PM PDT 24
Peak memory	610316 kb
Host	smart-ef58785f-fdf4-4b38-bc67-e5433a54e55e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903724442 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2903724442
Directory	/workspace/0.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3137329920
Short name	T386
Test name
Test status
Simulation time	4401817464 ps
CPU time	690.15 seconds
Started	Jul 19 07:01:24 PM PDT 24
Finished	Jul 19 07:12:57 PM PDT 24
Peak memory	609960 kb
Host	smart-48dcdace-36ac-4c76-8c47-42f3e4481d39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3137329920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3137329920
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3026935172
Short name	T233
Test name
Test status
Simulation time	13209591094 ps
CPU time	1579 seconds
Started	Jul 19 06:40:33 PM PDT 24
Finished	Jul 19 07:06:53 PM PDT 24
Peak memory	610736 kb
Host	smart-5a17d249-be54-46dd-8562-1af837eb251d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3026935172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3026935172
Directory	/workspace/0.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_entropy.2850971062
Short name	T590
Test name
Test status
Simulation time	2761684368 ps
CPU time	286.61 seconds
Started	Jul 19 06:42:16 PM PDT 24
Finished	Jul 19 06:47:03 PM PDT 24
Peak memory	609716 kb
Host	smart-3f8f9a7a-64af-4bfd-995c-3b3f2e32d4bf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850971062 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2850971062
Directory	/workspace/1.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3589682656
Short name	T121
Test name
Test status
Simulation time	3535365036 ps
CPU time	541.51 seconds
Started	Jul 19 06:41:05 PM PDT 24
Finished	Jul 19 06:50:07 PM PDT 24
Peak memory	609300 kb
Host	smart-57c88d8c-0fa7-49fd-9bf2-05ed959e4dce
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358968 2656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.3589682656
Directory	/workspace/0.chip_sw_usbdev_aon_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_app_rom.3326860475
Short name	T658
Test name
Test status
Simulation time	2870861564 ps
CPU time	274.29 seconds
Started	Jul 19 06:39:27 PM PDT 24
Finished	Jul 19 06:44:02 PM PDT 24
Peak memory	609728 kb
Host	smart-3d54687a-9003-4aee-b6ed-54a92dfa20f8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326860475 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3326860475
Directory	/workspace/0.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.358021744
Short name	T381
Test name
Test status
Simulation time	7755016936 ps
CPU time	1780.65 seconds
Started	Jul 19 06:39:05 PM PDT 24
Finished	Jul 19 07:08:47 PM PDT 24
Peak memory	610204 kb
Host	smart-694c987a-345c-496f-bd18-b87528c89991
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=358021744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.358021744
Directory	/workspace/0.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.183390105
Short name	T7
Test name
Test status
Simulation time	5170965092 ps
CPU time	431.36 seconds
Started	Jul 19 06:43:44 PM PDT 24
Finished	Jul 19 06:50:55 PM PDT 24
Peak memory	620156 kb
Host	smart-6cd8f28c-87e6-433a-b1cd-77bb13fc2a64
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 83390105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.183390105
Directory	/workspace/0.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_power_sleep_load.2314943249
Short name	T270
Test name
Test status
Simulation time	4615485236 ps
CPU time	439.88 seconds
Started	Jul 19 06:39:21 PM PDT 24
Finished	Jul 19 06:46:42 PM PDT 24
Peak memory	609364 kb
Host	smart-8ab49142-665e-413f-8ede-81c257700a72
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314943249 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2314943249
Directory	/workspace/0.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.4022793813
Short name	T241
Test name
Test status
Simulation time	5011730576 ps
CPU time	942.69 seconds
Started	Jul 19 06:41:05 PM PDT 24
Finished	Jul 19 06:56:48 PM PDT 24
Peak memory	609560 kb
Host	smart-66511b88-726c-47c6-92e1-275247b9c2f6
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022793813 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.4022793813
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_jtag_mem_access.3868305883
Short name	T221
Test name
Test status
Simulation time	13618617564 ps
CPU time	1368.66 seconds
Started	Jul 19 06:31:21 PM PDT 24
Finished	Jul 19 06:54:10 PM PDT 24
Peak memory	607844 kb
Host	smart-494e3dd0-54b8-4827-85c6-b8337bc7ea72
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868305883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 868305883
Directory	/workspace/0.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2783942379
Short name	T123
Test name
Test status
Simulation time	2723988817 ps
CPU time	231.62 seconds
Started	Jul 19 06:42:13 PM PDT 24
Finished	Jul 19 06:46:05 PM PDT 24
Peak memory	621312 kb
Host	smart-28c963a6-f9c9-46db-8f2e-c120d5f8f10f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783942379 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.2783942379
Directory	/workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4103695206
Short name	T410
Test name
Test status
Simulation time	5550020276 ps
CPU time	550.47 seconds
Started	Jul 19 06:45:12 PM PDT 24
Finished	Jul 19 06:54:23 PM PDT 24
Peak memory	611016 kb
Host	smart-578437d3-e790-42fe-9bed-f334c741d87d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4103695206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.4103695206
Directory	/workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx.888897505
Short name	T263
Test name
Test status
Simulation time	4060312928 ps
CPU time	795.89 seconds
Started	Jul 19 06:42:52 PM PDT 24
Finished	Jul 19 06:56:09 PM PDT 24
Peak memory	623784 kb
Host	smart-99a05f6a-2671-4e3e-a86f-527540cd35f5
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888897505 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.888897505
Directory	/workspace/0.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.786818540
Short name	T383
Test name
Test status
Simulation time	4337085292 ps
CPU time	445.33 seconds
Started	Jul 19 06:48:15 PM PDT 24
Finished	Jul 19 06:55:41 PM PDT 24
Peak memory	609872 kb
Host	smart-a6a5302b-8a0a-48cf-b6c1-2a098d38d03f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786818540 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.786818540
Directory	/workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1481434918
Short name	T675
Test name
Test status
Simulation time	7334525495 ps
CPU time	547.05 seconds
Started	Jul 19 06:39:51 PM PDT 24
Finished	Jul 19 06:48:59 PM PDT 24
Peak memory	609600 kb
Host	smart-2c075496-9010-4e30-a837-c7927a57b527
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481434918 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.1481434918
Directory	/workspace/0.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2781659636
Short name	T664
Test name
Test status
Simulation time	8452991160 ps
CPU time	608.98 seconds
Started	Jul 19 06:44:52 PM PDT 24
Finished	Jul 19 06:55:01 PM PDT 24
Peak memory	610472 kb
Host	smart-5070b595-7741-444c-b862-96a084e1786e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781659636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.2781659636
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1696749420
Short name	T208
Test name
Test status
Simulation time	2574064048 ps
CPU time	234.02 seconds
Started	Jul 19 06:44:12 PM PDT 24
Finished	Jul 19 06:48:07 PM PDT 24
Peak memory	609812 kb
Host	smart-9e585cf6-09cd-44cf-8214-1bec1eb7135f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696749420 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1696749420
Directory	/workspace/1.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2723351108
Short name	T970
Test name
Test status
Simulation time	6292498848 ps
CPU time	462.62 seconds
Started	Jul 19 07:03:16 PM PDT 24
Finished	Jul 19 07:10:59 PM PDT 24
Peak memory	609376 kb
Host	smart-9b3cc62e-d106-4f6d-90a5-e1fdd03f4006
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2723351108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2723351108
Directory	/workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_dev.440174316
Short name	T426
Test name
Test status
Simulation time	18147565456 ps
CPU time	2038.41 seconds
Started	Jul 19 06:49:39 PM PDT 24
Finished	Jul 19 07:23:38 PM PDT 24
Peak memory	620972 kb
Host	smart-062e98f5-2d37-4bf2-84e5-7dcd56c8618a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=440174316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.440174316
Directory	/workspace/1.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.193806949
Short name	T926
Test name
Test status
Simulation time	3922808024 ps
CPU time	657.13 seconds
Started	Jul 19 06:37:30 PM PDT 24
Finished	Jul 19 06:48:28 PM PDT 24
Peak memory	609852 kb
Host	smart-30ecd4bd-4484-4fe9-9861-fa22701223df
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=193806949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.193806949
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.421118965
Short name	T239
Test name
Test status
Simulation time	4083733776 ps
CPU time	441.14 seconds
Started	Jul 19 06:39:34 PM PDT 24
Finished	Jul 19 06:46:56 PM PDT 24
Peak memory	609576 kb
Host	smart-0e01d854-8686-448a-bbd5-329fc9deb1ae
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421118965 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.421118965
Directory	/workspace/0.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio.3647046582
Short name	T37
Test name
Test status
Simulation time	4889086824 ps
CPU time	511.76 seconds
Started	Jul 19 06:54:22 PM PDT 24
Finished	Jul 19 07:03:58 PM PDT 24
Peak memory	610000 kb
Host	smart-08899f66-d32c-493c-a579-c7ab8495f66e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647046582 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3647046582
Directory	/workspace/2.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1735007279
Short name	T78
Test name
Test status
Simulation time	18593207836 ps
CPU time	723.41 seconds
Started	Jul 19 06:42:02 PM PDT 24
Finished	Jul 19 06:54:06 PM PDT 24
Peak memory	619224 kb
Host	smart-f8d993e2-06db-4a2e-9f08-56b77324caa3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1735007279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1735007279
Directory	/workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.252444062
Short name	T900
Test name
Test status
Simulation time	18349295816 ps
CPU time	4988.67 seconds
Started	Jul 19 06:46:08 PM PDT 24
Finished	Jul 19 08:09:17 PM PDT 24
Peak memory	610008 kb
Host	smart-e6cb8f0c-66f3-45fb-9809-60895e10e4ad
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252444062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.252444062
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2822577417
Short name	T357
Test name
Test status
Simulation time	11370460682 ps
CPU time	2275.31 seconds
Started	Jul 19 06:40:46 PM PDT 24
Finished	Jul 19 07:18:43 PM PDT 24
Peak memory	624180 kb
Host	smart-bc4c91d6-a1a2-4d11-a67c-b77114c70d50
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2822577417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.2822577417
Directory	/workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2447696343
Short name	T734
Test name
Test status
Simulation time	5567078420 ps
CPU time	808.83 seconds
Started	Jul 19 06:42:42 PM PDT 24
Finished	Jul 19 06:56:12 PM PDT 24
Peak memory	609376 kb
Host	smart-b58ba521-6973-48b1-b38a-ff51cf95ac05
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447696343 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.2447696343
Directory	/workspace/0.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.753249538
Short name	T874
Test name
Test status
Simulation time	8526114906 ps
CPU time	1091.07 seconds
Started	Jul 19 06:42:25 PM PDT 24
Finished	Jul 19 07:00:37 PM PDT 24
Peak memory	616820 kb
Host	smart-97a62ede-163e-4173-87a9-1aedd2aedd79
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753249538 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.753249538
Directory	/workspace/0.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2234777843
Short name	T331
Test name
Test status
Simulation time	6438948648 ps
CPU time	1512 seconds
Started	Jul 19 06:40:36 PM PDT 24
Finished	Jul 19 07:05:50 PM PDT 24
Peak memory	611184 kb
Host	smart-d5fe521e-bb5c-4754-a6ce-c36187abdcc0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223477 7843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.2234777843
Directory	/workspace/0.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2051566729
Short name	T180
Test name
Test status
Simulation time	4134531600 ps
CPU time	509.2 seconds
Started	Jul 19 06:39:20 PM PDT 24
Finished	Jul 19 06:47:50 PM PDT 24
Peak memory	610452 kb
Host	smart-ccc86798-bf67-4e04-a60a-423ef71d93d8
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2051566729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.2051566729
Directory	/workspace/0.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2432056919
Short name	T586
Test name
Test status
Simulation time	13911609038 ps
CPU time	1210.47 seconds
Started	Jul 19 06:40:55 PM PDT 24
Finished	Jul 19 07:01:06 PM PDT 24
Peak memory	624716 kb
Host	smart-388f3b93-dd87-4c6c-8780-f9f0fe0887fb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432056919 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.2432056919
Directory	/workspace/0.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2937792457
Short name	T914
Test name
Test status
Simulation time	49578493012 ps
CPU time	6326.69 seconds
Started	Jul 19 06:39:10 PM PDT 24
Finished	Jul 19 08:24:38 PM PDT 24
Peak memory	620464 kb
Host	smart-e14cfe07-026f-4d73-95a1-0e048eb7e860
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937792457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2937792457
Directory	/workspace/0.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4272768432
Short name	T624
Test name
Test status
Simulation time	6442002080 ps
CPU time	573.01 seconds
Started	Jul 19 06:40:12 PM PDT 24
Finished	Jul 19 06:49:45 PM PDT 24
Peak memory	616096 kb
Host	smart-76a05340-56f8-4b3b-aad6-098e810b72a0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4272768432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4272768432
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.705929918
Short name	T432
Test name
Test status
Simulation time	35277939551 ps
CPU time	5997.09 seconds
Started	Jul 19 06:51:29 PM PDT 24
Finished	Jul 19 08:31:28 PM PDT 24
Peak memory	609432 kb
Host	smart-49e2c434-2c3d-4e5f-9ea8-7b40556d0f56
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=705929918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.705929918
Directory	/workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_sleep_load.3969123024
Short name	T326
Test name
Test status
Simulation time	10195576944 ps
CPU time	703.2 seconds
Started	Jul 19 06:52:57 PM PDT 24
Finished	Jul 19 07:04:41 PM PDT 24
Peak memory	610784 kb
Host	smart-f55caaea-feb9-4375-baea-1b8283e2d1c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969123024 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3969123024
Directory	/workspace/1.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2611539745
Short name	T172
Test name
Test status
Simulation time	2509949753 ps
CPU time	110.82 seconds
Started	Jul 19 06:54:34 PM PDT 24
Finished	Jul 19 06:57:33 PM PDT 24
Peak memory	620560 kb
Host	smart-1b3cb209-d557-43a9-bf40-13680e25b118
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611539745 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2611539745
Directory	/workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3315151442
Short name	T385
Test name
Test status
Simulation time	3394722040 ps
CPU time	408.89 seconds
Started	Jul 19 06:45:50 PM PDT 24
Finished	Jul 19 06:52:39 PM PDT 24
Peak memory	609528 kb
Host	smart-5f13c3f5-686f-429f-8f5c-393e277c5d9d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315151442 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.3315151442
Directory	/workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3051703210
Short name	T285
Test name
Test status
Simulation time	4436608276 ps
CPU time	777.53 seconds
Started	Jul 19 06:39:52 PM PDT 24
Finished	Jul 19 06:52:50 PM PDT 24
Peak memory	609372 kb
Host	smart-fbbe22e7-34d9-4817-9029-b2b00be7a3cb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30517 03210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3051703210
Directory	/workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_plic_all_irqs_10.488542953
Short name	T115
Test name
Test status
Simulation time	4036365000 ps
CPU time	611.93 seconds
Started	Jul 19 06:47:06 PM PDT 24
Finished	Jul 19 06:57:18 PM PDT 24
Peak memory	609716 kb
Host	smart-5cb45448-c2ff-4c6c-8eba-5a66ecb84ceb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488542953 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.488542953
Directory	/workspace/1.chip_plic_all_irqs_10/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_boot_mode.567677080
Short name	T80
Test name
Test status
Simulation time	3340803832 ps
CPU time	624.36 seconds
Started	Jul 19 06:41:13 PM PDT 24
Finished	Jul 19 06:51:37 PM PDT 24
Peak memory	609920 kb
Host	smart-483d1c01-eb7b-499e-84c1-3113cbb3c4a4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567677080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.567677080
Directory	/workspace/0.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.63715599
Short name	T626
Test name
Test status
Simulation time	18628084486 ps
CPU time	4091.74 seconds
Started	Jul 19 06:39:48 PM PDT 24
Finished	Jul 19 07:48:01 PM PDT 24
Peak memory	610196 kb
Host	smart-75176357-9665-47be-ac7a-dc27108895fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=63715599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.63715599
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/0.rom_raw_unlock.174527983
Short name	T366
Test name
Test status
Simulation time	6670093401 ps
CPU time	294.01 seconds
Started	Jul 19 06:42:34 PM PDT 24
Finished	Jul 19 06:47:29 PM PDT 24
Peak memory	623472 kb
Host	smart-08ca410e-c00c-4f69-8da7-867f4cda56d8
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=174527983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.174527983
Directory	/workspace/0.rom_raw_unlock/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4131015662
Short name	T423
Test name
Test status
Simulation time	3165114382 ps
CPU time	304.38 seconds
Started	Jul 19 07:03:40 PM PDT 24
Finished	Jul 19 07:08:47 PM PDT 24
Peak memory	609292 kb
Host	smart-3365c71b-5d4d-46e8-9261-d67823606edc
User	root
Command	/workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131015662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.4131015662
Directory	/workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3381331535
Short name	T197
Test name
Test status
Simulation time	4338759680 ps
CPU time	515.85 seconds
Started	Jul 19 06:42:01 PM PDT 24
Finished	Jul 19 06:50:38 PM PDT 24
Peak memory	609708 kb
Host	smart-c30d502a-0a11-48ce-b707-2e3ddbead419
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813 31535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.3381331535
Directory	/workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/0.chip_sival_flash_info_access.1512303238
Short name	T265
Test name
Test status
Simulation time	2791554880 ps
CPU time	344.92 seconds
Started	Jul 19 06:38:17 PM PDT 24
Finished	Jul 19 06:44:03 PM PDT 24
Peak memory	609284 kb
Host	smart-dbec2936-e603-43a0-9c5f-33cb7da3dd51
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1512303238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1512303238
Directory	/workspace/0.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc.4259247720
Short name	T135
Test name
Test status
Simulation time	3074924044 ps
CPU time	308.78 seconds
Started	Jul 19 06:42:01 PM PDT 24
Finished	Jul 19 06:47:11 PM PDT 24
Peak memory	609480 kb
Host	smart-85d5c5e9-af17-41e1-9d77-91a8f28cd904
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259247720 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.4259247720
Directory	/workspace/0.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4221382232
Short name	T650
Test name
Test status
Simulation time	2668593407 ps
CPU time	223.04 seconds
Started	Jul 19 06:40:55 PM PDT 24
Finished	Jul 19 06:44:39 PM PDT 24
Peak memory	609664 kb
Host	smart-9f4a7def-88fa-4a05-9c42-adb96b06325c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221 382232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.4221382232
Directory	/workspace/0.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_entropy.160870424
Short name	T817
Test name
Test status
Simulation time	3012536200 ps
CPU time	247.93 seconds
Started	Jul 19 06:39:03 PM PDT 24
Finished	Jul 19 06:43:12 PM PDT 24
Peak memory	609640 kb
Host	smart-c0c777d0-2898-4543-9615-3bcd2a7500f0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160870424 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.160870424
Directory	/workspace/0.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_idle.1722813986
Short name	T881
Test name
Test status
Simulation time	3058244704 ps
CPU time	328.96 seconds
Started	Jul 19 06:42:12 PM PDT 24
Finished	Jul 19 06:47:41 PM PDT 24
Peak memory	609600 kb
Host	smart-ad2bda7f-acdf-44a8-9306-ffad83dec6bb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722813986 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1722813986
Directory	/workspace/0.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_masking_off.3352682687
Short name	T689
Test name
Test status
Simulation time	3099103235 ps
CPU time	312.58 seconds
Started	Jul 19 06:42:41 PM PDT 24
Finished	Jul 19 06:47:55 PM PDT 24
Peak memory	609348 kb
Host	smart-b4163ce9-629d-46b3-b751-d92ee3f5f832
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352682687 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.3352682687
Directory	/workspace/0.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/0.chip_sw_aes_smoketest.1228095483
Short name	T598
Test name
Test status
Simulation time	2870246080 ps
CPU time	290.19 seconds
Started	Jul 19 06:40:13 PM PDT 24
Finished	Jul 19 06:45:04 PM PDT 24
Peak memory	609768 kb
Host	smart-6f33795b-f8a3-4859-bba3-e2fe57cd7e93
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228095483 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.1228095483
Directory	/workspace/0.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3270179782
Short name	T111
Test name
Test status
Simulation time	3603602625 ps
CPU time	330.62 seconds
Started	Jul 19 06:42:42 PM PDT 24
Finished	Jul 19 06:48:12 PM PDT 24
Peak memory	609444 kb
Host	smart-eef29fdd-0755-49aa-869c-1cd1f6501d1e
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3270179782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.3270179782
Directory	/workspace/0.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1664047488
Short name	T156
Test name
Test status
Simulation time	9201917246 ps
CPU time	2186.24 seconds
Started	Jul 19 06:42:27 PM PDT 24
Finished	Jul 19 07:18:55 PM PDT 24
Peak memory	609884 kb
Host	smart-45927272-bd3a-48fd-a806-ef1121b21d96
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1664047488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1664047488
Directory	/workspace/0.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.40870161
Short name	T110
Test name
Test status
Simulation time	6459580012 ps
CPU time	1690.31 seconds
Started	Jul 19 06:40:32 PM PDT 24
Finished	Jul 19 07:08:44 PM PDT 24
Peak memory	609776 kb
Host	smart-97f81b2a-6f6d-4208-8a60-aaa6f1d6ca80
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_toggle.40870161
Directory	/workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.385432254
Short name	T490
Test name
Test status
Simulation time	3291270720 ps
CPU time	393.45 seconds
Started	Jul 19 06:42:21 PM PDT 24
Finished	Jul 19 06:48:55 PM PDT 24
Peak memory	648796 kb
Host	smart-56c6757d-9834-4c85-8795-e2c4046847ed
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385432254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _alert_handler_lpg_sleep_mode_alerts.385432254
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1212224062
Short name	T412
Test name
Test status
Simulation time	10336897480 ps
CPU time	1415.38 seconds
Started	Jul 19 06:39:39 PM PDT 24
Finished	Jul 19 07:03:15 PM PDT 24
Peak memory	610736 kb
Host	smart-182be8e9-46fd-47a3-b901-d0ae6b78558b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212224062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1212224062
Directory	/workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.384746527
Short name	T793
Test name
Test status
Simulation time	7705309880 ps
CPU time	1215.29 seconds
Started	Jul 19 06:40:26 PM PDT 24
Finished	Jul 19 07:00:42 PM PDT 24
Peak memory	609304 kb
Host	smart-f6923f39-e410-4db3-9d35-8cd6e6115c12
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=384746527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.384746527
Directory	/workspace/0.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.187216194
Short name	T483
Test name
Test status
Simulation time	4843259864 ps
CPU time	679.07 seconds
Started	Jul 19 06:40:40 PM PDT 24
Finished	Jul 19 06:52:00 PM PDT 24
Peak memory	609892 kb
Host	smart-f5b97536-e7ff-4cfd-8fa3-491538e551bd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=187216194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.187216194
Directory	/workspace/0.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3661840376
Short name	T465
Test name
Test status
Simulation time	255717343370 ps
CPU time	13818.9 seconds
Started	Jul 19 06:39:43 PM PDT 24
Finished	Jul 19 10:30:04 PM PDT 24
Peak memory	610512 kb
Host	smart-af6f5c44-b704-4b1e-a588-a45ba4a7f069
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3661840376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3661840376
Directory	/workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/0.chip_sw_alert_test.2107876674
Short name	T119
Test name
Test status
Simulation time	2947649778 ps
CPU time	408.24 seconds
Started	Jul 19 06:41:44 PM PDT 24
Finished	Jul 19 06:48:32 PM PDT 24
Peak memory	609800 kb
Host	smart-4b0217fe-39ce-4afe-8766-39e13d4f9c63
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107876674 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2107876674
Directory	/workspace/0.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_irq.2068025238
Short name	T700
Test name
Test status
Simulation time	4296564930 ps
CPU time	416.1 seconds
Started	Jul 19 06:42:12 PM PDT 24
Finished	Jul 19 06:49:10 PM PDT 24
Peak memory	610044 kb
Host	smart-b6d63c56-c357-4a02-bd40-acce5b426da4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068025238 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2068025238
Directory	/workspace/0.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3951796693
Short name	T568
Test name
Test status
Simulation time	7405627418 ps
CPU time	418.95 seconds
Started	Jul 19 06:40:54 PM PDT 24
Finished	Jul 19 06:47:53 PM PDT 24
Peak memory	609344 kb
Host	smart-9e9d7425-1f9f-453f-af44-8b2811600293
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3951796693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3951796693
Directory	/workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3657786843
Short name	T594
Test name
Test status
Simulation time	3080243966 ps
CPU time	267.89 seconds
Started	Jul 19 06:42:46 PM PDT 24
Finished	Jul 19 06:47:15 PM PDT 24
Peak memory	609408 kb
Host	smart-c53c3783-29a7-468a-a23b-2292160b61bc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657786843 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.3657786843
Directory	/workspace/0.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.305440904
Short name	T314
Test name
Test status
Simulation time	9703182416 ps
CPU time	816.17 seconds
Started	Jul 19 06:43:28 PM PDT 24
Finished	Jul 19 06:57:05 PM PDT 24
Peak memory	610224 kb
Host	smart-2ab5b6d7-4ca9-47dd-851e-3dd32a64dcf2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 305440904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.305440904
Directory	/workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1495085433
Short name	T319
Test name
Test status
Simulation time	5034679150 ps
CPU time	647.01 seconds
Started	Jul 19 06:42:22 PM PDT 24
Finished	Jul 19 06:53:10 PM PDT 24
Peak memory	610256 kb
Host	smart-bb59bb83-a3d6-4e8a-9de7-12405a9db29d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1495085433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.1495085433
Directory	/workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2873137642
Short name	T884
Test name
Test status
Simulation time	10298399356 ps
CPU time	828.15 seconds
Started	Jul 19 06:44:43 PM PDT 24
Finished	Jul 19 06:58:33 PM PDT 24
Peak memory	622240 kb
Host	smart-e2a944fe-f356-49ba-9f4d-d3bcb243b881
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2873137642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2873137642
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2195779023
Short name	T885
Test name
Test status
Simulation time	3970083020 ps
CPU time	653.62 seconds
Started	Jul 19 06:42:46 PM PDT 24
Finished	Jul 19 06:53:41 PM PDT 24
Peak memory	614044 kb
Host	smart-e35ae548-7622-4694-bb1b-1e78a399aa6b
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195779023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2195779023
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2413728963
Short name	T968
Test name
Test status
Simulation time	4075443504 ps
CPU time	725.58 seconds
Started	Jul 19 06:43:09 PM PDT 24
Finished	Jul 19 06:55:16 PM PDT 24
Peak memory	612808 kb
Host	smart-b7e6bce1-a5c5-42d0-92cd-64d50f14096c
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413728963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2413728963
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1159258035
Short name	T960
Test name
Test status
Simulation time	4310125000 ps
CPU time	690.63 seconds
Started	Jul 19 06:43:10 PM PDT 24
Finished	Jul 19 06:54:42 PM PDT 24
Peak memory	612788 kb
Host	smart-67a0a773-a324-4f83-af27-1c4257d97b7e
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159258035 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1159258035
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3124864763
Short name	T708
Test name
Test status
Simulation time	4725021240 ps
CPU time	629.95 seconds
Started	Jul 19 06:42:52 PM PDT 24
Finished	Jul 19 06:53:22 PM PDT 24
Peak memory	614032 kb
Host	smart-f022837e-8608-459d-8a2d-b8f78f8eae16
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124864763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3124864763
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2702177633
Short name	T682
Test name
Test status
Simulation time	5048778634 ps
CPU time	812.04 seconds
Started	Jul 19 06:40:53 PM PDT 24
Finished	Jul 19 06:54:26 PM PDT 24
Peak memory	611664 kb
Host	smart-2e6e88e2-9af7-466f-8a0b-d680cd20ff6a
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702177633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2702177633
Directory	/workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3699194260
Short name	T1007
Test name
Test status
Simulation time	3097662833 ps
CPU time	267.86 seconds
Started	Jul 19 06:40:58 PM PDT 24
Finished	Jul 19 06:45:26 PM PDT 24
Peak memory	609716 kb
Host	smart-3f9b76ca-cb3d-4a71-8385-9a826a4ab896
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699194260 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.3699194260
Directory	/workspace/0.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3758802897
Short name	T973
Test name
Test status
Simulation time	3780015812 ps
CPU time	431.48 seconds
Started	Jul 19 06:42:16 PM PDT 24
Finished	Jul 19 06:49:28 PM PDT 24
Peak memory	609408 kb
Host	smart-c7beb84b-b16e-49c1-b7ad-4cd29dfdf24c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758802897 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.3758802897
Directory	/workspace/0.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1028705891
Short name	T153
Test name
Test status
Simulation time	3040644685 ps
CPU time	201.74 seconds
Started	Jul 19 06:39:37 PM PDT 24
Finished	Jul 19 06:43:00 PM PDT 24
Peak memory	609780 kb
Host	smart-3244d70e-381c-4f7e-83a3-e101d08d977d
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028705891 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.1028705891
Directory	/workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1314473589
Short name	T209
Test name
Test status
Simulation time	5077000520 ps
CPU time	712.71 seconds
Started	Jul 19 06:41:40 PM PDT 24
Finished	Jul 19 06:53:33 PM PDT 24
Peak memory	610380 kb
Host	smart-4b9203d9-c18c-4f7b-acc3-ef16d24be6e3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314473589 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1314473589
Directory	/workspace/0.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3936516169
Short name	T218
Test name
Test status
Simulation time	4344397040 ps
CPU time	512.01 seconds
Started	Jul 19 06:40:46 PM PDT 24
Finished	Jul 19 06:49:19 PM PDT 24
Peak memory	610376 kb
Host	smart-ee26576d-a039-45fc-b129-10ab7b9e428e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936516169 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.3936516169
Directory	/workspace/0.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1814867630
Short name	T677
Test name
Test status
Simulation time	4059513800 ps
CPU time	413.7 seconds
Started	Jul 19 06:40:32 PM PDT 24
Finished	Jul 19 06:47:27 PM PDT 24
Peak memory	610004 kb
Host	smart-1cf64e1e-8b55-4233-9471-2b659ad68959
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814867630 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.1814867630
Directory	/workspace/0.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3309280292
Short name	T217
Test name
Test status
Simulation time	5727381520 ps
CPU time	635.15 seconds
Started	Jul 19 06:43:14 PM PDT 24
Finished	Jul 19 06:53:51 PM PDT 24
Peak memory	610384 kb
Host	smart-2fc2f66a-1cb6-422c-b85a-9f8add5a5618
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309280292 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3309280292
Directory	/workspace/0.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.680474768
Short name	T802
Test name
Test status
Simulation time	10665495440 ps
CPU time	1385.7 seconds
Started	Jul 19 06:40:45 PM PDT 24
Finished	Jul 19 07:03:51 PM PDT 24
Peak memory	610164 kb
Host	smart-bb3902e3-211f-4ec0-bed0-1e1b0b44ee39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680474768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.680474768
Directory	/workspace/0.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1028206398
Short name	T762
Test name
Test status
Simulation time	3055798344 ps
CPU time	461.34 seconds
Started	Jul 19 06:39:32 PM PDT 24
Finished	Jul 19 06:47:14 PM PDT 24
Peak memory	609352 kb
Host	smart-13af1197-940f-4e47-b8e2-0e758a2d033b
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028206398 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1028206398
Directory	/workspace/0.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.140815112
Short name	T847
Test name
Test status
Simulation time	4817271282 ps
CPU time	642 seconds
Started	Jul 19 06:42:56 PM PDT 24
Finished	Jul 19 06:53:39 PM PDT 24
Peak memory	610188 kb
Host	smart-297581a3-1e69-4725-b4de-6dca1e9ff1e2
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140815112 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.140815112
Directory	/workspace/0.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.421291369
Short name	T559
Test name
Test status
Simulation time	2849533960 ps
CPU time	258.34 seconds
Started	Jul 19 06:41:22 PM PDT 24
Finished	Jul 19 06:45:41 PM PDT 24
Peak memory	609272 kb
Host	smart-46201e5b-87e6-421d-9bf0-f76dc5427831
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421291369 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_clkmgr_smoketest.421291369
Directory	/workspace/0.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_coremark.298796539
Short name	T674
Test name
Test status
Simulation time	71716842464 ps
CPU time	16888.7 seconds
Started	Jul 19 06:42:23 PM PDT 24
Finished	Jul 19 11:23:55 PM PDT 24
Peak memory	610348 kb
Host	smart-6d3eb8d7-c2fc-4aee-9a62-a04e72b72ea8
User	root
Command	/workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=298796539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.298796539
Directory	/workspace/0.chip_sw_coremark/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2645426075
Short name	T904
Test name
Test status
Simulation time	17769567396 ps
CPU time	4856.78 seconds
Started	Jul 19 06:40:22 PM PDT 24
Finished	Jul 19 08:01:20 PM PDT 24
Peak memory	610028 kb
Host	smart-ac1a4209-379a-4d28-a5e4-86f2418f8915
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645426075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2645426075
Directory	/workspace/0.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_kat_test.465456586
Short name	T685
Test name
Test status
Simulation time	3129294200 ps
CPU time	293.71 seconds
Started	Jul 19 06:45:09 PM PDT 24
Finished	Jul 19 06:50:04 PM PDT 24
Peak memory	609248 kb
Host	smart-e026f2cb-14f1-4d28-8d23-bdaed9c2159d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465456586 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.465456586
Directory	/workspace/0.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2713560614
Short name	T712
Test name
Test status
Simulation time	6774825065 ps
CPU time	761.7 seconds
Started	Jul 19 06:44:35 PM PDT 24
Finished	Jul 19 06:57:17 PM PDT 24
Peak memory	610744 kb
Host	smart-830cf9cc-0766-4a44-9b48-1bdfb70e8491
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713560614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2713560614
Directory	/workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/0.chip_sw_csrng_smoketest.3858224896
Short name	T972
Test name
Test status
Simulation time	2523106904 ps
CPU time	218.86 seconds
Started	Jul 19 06:40:13 PM PDT 24
Finished	Jul 19 06:43:53 PM PDT 24
Peak memory	609796 kb
Host	smart-293c3565-51a5-4baf-bd78-b28720cef845
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858224896 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.3858224896
Directory	/workspace/0.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1529096063
Short name	T282
Test name
Test status
Simulation time	5821521716 ps
CPU time	430.92 seconds
Started	Jul 19 06:36:36 PM PDT 24
Finished	Jul 19 06:43:47 PM PDT 24
Peak memory	610788 kb
Host	smart-1d13a9f8-4891-4d86-be6b-8bd69a37bc26
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1529096063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1529096063
Directory	/workspace/0.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_auto_mode.520040550
Short name	T872
Test name
Test status
Simulation time	4471138272 ps
CPU time	1168.56 seconds
Started	Jul 19 06:42:15 PM PDT 24
Finished	Jul 19 07:01:45 PM PDT 24
Peak memory	610132 kb
Host	smart-f13ddb30-ad59-4c94-a2ed-ab764c02ebb6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520040550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.520040550
Directory	/workspace/0.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.367401289
Short name	T646
Test name
Test status
Simulation time	6064971470 ps
CPU time	1050.12 seconds
Started	Jul 19 06:38:43 PM PDT 24
Finished	Jul 19 06:56:14 PM PDT 24
Peak memory	610756 kb
Host	smart-56cca2ea-b6b3-41da-a974-ecc61d8d7f20
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=367401289 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.367401289
Directory	/workspace/0.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3338284080
Short name	T865
Test name
Test status
Simulation time	7795648365 ps
CPU time	1512.24 seconds
Started	Jul 19 06:39:48 PM PDT 24
Finished	Jul 19 07:05:01 PM PDT 24
Peak memory	610516 kb
Host	smart-26f83327-c5c0-4bcd-a5e1-d81ebd777a10
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338284080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3338284080
Directory	/workspace/0.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/0.chip_sw_edn_kat.3730972360
Short name	T479
Test name
Test status
Simulation time	3417684188 ps
CPU time	576.6 seconds
Started	Jul 19 06:39:19 PM PDT 24
Finished	Jul 19 06:48:56 PM PDT 24
Peak memory	615096 kb
Host	smart-5d5c2668-9e85-46bc-890a-6d6838a7dfaa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730972360 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3730972360
Directory	/workspace/0.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2038144624
Short name	T545
Test name
Test status
Simulation time	2981423140 ps
CPU time	334.33 seconds
Started	Jul 19 06:40:45 PM PDT 24
Finished	Jul 19 06:46:21 PM PDT 24
Peak memory	609712 kb
Host	smart-60e22f23-31bc-4f7d-a954-beb70fded3f4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20 38144624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.2038144624
Directory	/workspace/0.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.4206409800
Short name	T931
Test name
Test status
Simulation time	2844108814 ps
CPU time	290.72 seconds
Started	Jul 19 06:44:52 PM PDT 24
Finished	Jul 19 06:49:44 PM PDT 24
Peak memory	609556 kb
Host	smart-f08b6d1c-c48c-4ac7-b3fa-7ace0810958c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206409800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.4206409800
Directory	/workspace/0.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3450473666
Short name	T787
Test name
Test status
Simulation time	3716267746 ps
CPU time	400.7 seconds
Started	Jul 19 06:43:00 PM PDT 24
Finished	Jul 19 06:49:41 PM PDT 24
Peak memory	609736 kb
Host	smart-c6a55d85-7e2e-4474-bfad-7f1cfe7bc99c
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3450473666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3450473666
Directory	/workspace/0.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_example_concurrency.4212308783
Short name	T997
Test name
Test status
Simulation time	2600390616 ps
CPU time	257.93 seconds
Started	Jul 19 06:38:53 PM PDT 24
Finished	Jul 19 06:43:11 PM PDT 24
Peak memory	609360 kb
Host	smart-50d2e1b3-ba41-44bb-9caf-04ffaa5fedb2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212308783 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4212308783
Directory	/workspace/0.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/0.chip_sw_example_flash.151080391
Short name	T634
Test name
Test status
Simulation time	2865309166 ps
CPU time	256.82 seconds
Started	Jul 19 06:38:21 PM PDT 24
Finished	Jul 19 06:42:38 PM PDT 24
Peak memory	609648 kb
Host	smart-2f7db078-d322-430c-9744-b7320dd29c32
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151080391 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.151080391
Directory	/workspace/0.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/0.chip_sw_example_manufacturer.2887812916
Short name	T724
Test name
Test status
Simulation time	2709070264 ps
CPU time	216.58 seconds
Started	Jul 19 06:42:23 PM PDT 24
Finished	Jul 19 06:46:01 PM PDT 24
Peak memory	609344 kb
Host	smart-3762595f-943f-4da8-bec5-98523311ee14
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887812916 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2887812916
Directory	/workspace/0.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/0.chip_sw_example_rom.40059686
Short name	T821
Test name
Test status
Simulation time	2433787632 ps
CPU time	141.93 seconds
Started	Jul 19 06:37:59 PM PDT 24
Finished	Jul 19 06:40:22 PM PDT 24
Peak memory	609324 kb
Host	smart-5b060918-c081-4489-aa94-3e5e179eb945
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40059686 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_example_rom.40059686
Directory	/workspace/0.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3987414974
Short name	T254
Test name
Test status
Simulation time	57016060256 ps
CPU time	10590.6 seconds
Started	Jul 19 06:40:46 PM PDT 24
Finished	Jul 19 09:37:18 PM PDT 24
Peak memory	624728 kb
Host	smart-5921bc47-25d5-4911-862a-497e8777607c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3987414974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3987414974
Directory	/workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3137962461
Short name	T776
Test name
Test status
Simulation time	5156804998 ps
CPU time	684.58 seconds
Started	Jul 19 06:44:28 PM PDT 24
Finished	Jul 19 06:55:53 PM PDT 24
Peak memory	610992 kb
Host	smart-3fd968a0-56d8-42e4-ac91-32516060c23f
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3137962461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.3137962461
Directory	/workspace/0.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.3885058724
Short name	T660
Test name
Test status
Simulation time	5676202752 ps
CPU time	1193.78 seconds
Started	Jul 19 06:39:42 PM PDT 24
Finished	Jul 19 06:59:38 PM PDT 24
Peak memory	609276 kb
Host	smart-13a541ee-9bde-4aa3-aba3-906166803a9e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885058724 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3885058724
Directory	/workspace/0.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3051141773
Short name	T561
Test name
Test status
Simulation time	6788449504 ps
CPU time	1244.48 seconds
Started	Jul 19 06:42:19 PM PDT 24
Finished	Jul 19 07:03:04 PM PDT 24
Peak memory	609260 kb
Host	smart-520efd31-30de-48b8-a3d8-ddd6f57a3bba
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051141773 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3051141773
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1156486551
Short name	T661
Test name
Test status
Simulation time	6865368959 ps
CPU time	1202.21 seconds
Started	Jul 19 06:40:17 PM PDT 24
Finished	Jul 19 07:00:20 PM PDT 24
Peak memory	609300 kb
Host	smart-1699741d-18ee-4114-9d5e-da3ae24fb360
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156486551 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1156486551
Directory	/workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.92839639
Short name	T657
Test name
Test status
Simulation time	6465079830 ps
CPU time	1026.7 seconds
Started	Jul 19 06:41:00 PM PDT 24
Finished	Jul 19 06:58:08 PM PDT 24
Peak memory	609380 kb
Host	smart-dfc47058-a312-4a8e-ba08-6fd8d2fb647a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92839639 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.92839639
Directory	/workspace/0.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3459509881
Short name	T394
Test name
Test status
Simulation time	3034902336 ps
CPU time	415.52 seconds
Started	Jul 19 06:39:23 PM PDT 24
Finished	Jul 19 06:46:19 PM PDT 24
Peak memory	609556 kb
Host	smart-bf465b50-0cbe-4cde-ad6e-3d68b45942a6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459509881 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3459509881
Directory	/workspace/0.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3578801826
Short name	T343
Test name
Test status
Simulation time	5251989700 ps
CPU time	511.02 seconds
Started	Jul 19 06:39:47 PM PDT 24
Finished	Jul 19 06:48:18 PM PDT 24
Peak memory	609692 kb
Host	smart-32a0ff16-e6fb-4188-a052-21bde98f05b4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35 78801826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.3578801826
Directory	/workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2156907205
Short name	T422
Test name
Test status
Simulation time	5589731610 ps
CPU time	1179.7 seconds
Started	Jul 19 06:41:48 PM PDT 24
Finished	Jul 19 07:01:28 PM PDT 24
Peak memory	609876 kb
Host	smart-89629618-5114-42ce-be8a-ee71955c505a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156907205 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2156907205
Directory	/workspace/0.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2340085214
Short name	T397
Test name
Test status
Simulation time	3977327032 ps
CPU time	628.12 seconds
Started	Jul 19 06:41:47 PM PDT 24
Finished	Jul 19 06:52:16 PM PDT 24
Peak memory	609608 kb
Host	smart-8d4b1120-cbff-4f38-8798-2f33d59d07aa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340085214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.2340085214
Directory	/workspace/0.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4062231667
Short name	T389
Test name
Test status
Simulation time	4817082134 ps
CPU time	733.76 seconds
Started	Jul 19 06:40:30 PM PDT 24
Finished	Jul 19 06:52:45 PM PDT 24
Peak memory	610152 kb
Host	smart-196ee277-f5ec-4211-b971-ac033c362efb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4062231667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4062231667
Directory	/workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.870693960
Short name	T676
Test name
Test status
Simulation time	2725919756 ps
CPU time	325.43 seconds
Started	Jul 19 06:44:47 PM PDT 24
Finished	Jul 19 06:50:13 PM PDT 24
Peak memory	609372 kb
Host	smart-4c9f908e-7c5c-43c2-a85d-738081a55df0
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8706939 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.870693960
Directory	/workspace/0.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init.2724954819
Short name	T905
Test name
Test status
Simulation time	18425486250 ps
CPU time	2130.21 seconds
Started	Jul 19 06:40:18 PM PDT 24
Finished	Jul 19 07:15:49 PM PDT 24
Peak memory	613408 kb
Host	smart-21d5badc-21be-4196-9cae-d8e7787da6af
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724954819 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2724954819
Directory	/workspace/0.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4077654769
Short name	T814
Test name
Test status
Simulation time	19013809178 ps
CPU time	2018.96 seconds
Started	Jul 19 06:38:38 PM PDT 24
Finished	Jul 19 07:12:18 PM PDT 24
Peak memory	614440 kb
Host	smart-f81b7c4d-d829-474a-8cb5-80a37af4b85b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4077654769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.4077654769
Directory	/workspace/0.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.797783739
Short name	T871
Test name
Test status
Simulation time	3055587412 ps
CPU time	199.73 seconds
Started	Jul 19 06:47:11 PM PDT 24
Finished	Jul 19 06:50:31 PM PDT 24
Peak memory	609408 kb
Host	smart-9d617111-a2e3-43f6-ac00-65406025d139
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=797783739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.797783739
Directory	/workspace/0.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_gpio.1822100903
Short name	T39
Test name
Test status
Simulation time	4750274536 ps
CPU time	519.95 seconds
Started	Jul 19 06:40:26 PM PDT 24
Finished	Jul 19 06:49:06 PM PDT 24
Peak memory	610016 kb
Host	smart-f1e9d0ec-18f3-4f07-ab91-9bc7dd14c976
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822100903 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.1822100903
Directory	/workspace/0.chip_sw_gpio/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc.2932788997
Short name	T211
Test name
Test status
Simulation time	2794103744 ps
CPU time	332.49 seconds
Started	Jul 19 06:43:03 PM PDT 24
Finished	Jul 19 06:48:36 PM PDT 24
Peak memory	609680 kb
Host	smart-e6299a14-2c40-4f5d-a7dd-cf07d824e749
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932788997 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2932788997
Directory	/workspace/0.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.799675423
Short name	T941
Test name
Test status
Simulation time	2972131272 ps
CPU time	269.68 seconds
Started	Jul 19 06:40:11 PM PDT 24
Finished	Jul 19 06:44:42 PM PDT 24
Peak memory	609768 kb
Host	smart-6dcde217-07a9-4538-bf34-5518dfb616ad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799675423 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.799675423
Directory	/workspace/0.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3676934308
Short name	T607
Test name
Test status
Simulation time	3087997519 ps
CPU time	259.63 seconds
Started	Jul 19 06:39:07 PM PDT 24
Finished	Jul 19 06:43:27 PM PDT 24
Peak memory	609772 kb
Host	smart-6f774027-8b61-4a32-a21a-efd36ead93a6
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676934308 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.3676934308
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2300731070
Short name	T789
Test name
Test status
Simulation time	2744331807 ps
CPU time	228.93 seconds
Started	Jul 19 06:40:45 PM PDT 24
Finished	Jul 19 06:44:35 PM PDT 24
Peak memory	609792 kb
Host	smart-34201acc-7f32-4321-adbb-6fd24b9f4910
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300731070 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2300731070
Directory	/workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_multistream.3966749478
Short name	T309
Test name
Test status
Simulation time	7943736360 ps
CPU time	2099.41 seconds
Started	Jul 19 06:43:28 PM PDT 24
Finished	Jul 19 07:18:29 PM PDT 24
Peak memory	610092 kb
Host	smart-cc2c3bf5-a8ba-430a-b0e9-839353259b9d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966749478 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.3966749478
Directory	/workspace/0.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_oneshot.3196508321
Short name	T691
Test name
Test status
Simulation time	3168112216 ps
CPU time	406.37 seconds
Started	Jul 19 06:43:55 PM PDT 24
Finished	Jul 19 06:50:42 PM PDT 24
Peak memory	609860 kb
Host	smart-cebe0754-4493-43f1-b2a7-b78cc97d7d2f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196508321 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3196508321
Directory	/workspace/0.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1406763562
Short name	T807
Test name
Test status
Simulation time	3623619864 ps
CPU time	369.65 seconds
Started	Jul 19 06:42:29 PM PDT 24
Finished	Jul 19 06:48:40 PM PDT 24
Peak memory	609796 kb
Host	smart-8d1ddd25-e596-4bee-b24a-cdaa7b21f601
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406763562 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1406763562
Directory	/workspace/0.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.691747845
Short name	T232
Test name
Test status
Simulation time	4198121560 ps
CPU time	840.82 seconds
Started	Jul 19 06:44:33 PM PDT 24
Finished	Jul 19 06:58:34 PM PDT 24
Peak memory	609484 kb
Host	smart-293aa02b-6960-4835-a266-5a38e17a8a31
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691747845 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.691747845
Directory	/workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3157404993
Short name	T830
Test name
Test status
Simulation time	63918678364 ps
CPU time	13091.9 seconds
Started	Jul 19 06:41:34 PM PDT 24
Finished	Jul 19 10:19:48 PM PDT 24
Peak memory	624768 kb
Host	smart-9ab88944-ac3e-4d92-9f45-2152b19b6267
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3157404993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3157404993
Directory	/workspace/0.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.409046494
Short name	T714
Test name
Test status
Simulation time	10365202289 ps
CPU time	2237.65 seconds
Started	Jul 19 06:44:29 PM PDT 24
Finished	Jul 19 07:21:48 PM PDT 24
Peak memory	617684 kb
Host	smart-67b076c4-cb5c-45e6-b191-29e8df54bc1d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=409046494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.409046494
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2674230504
Short name	T736
Test name
Test status
Simulation time	7916755136 ps
CPU time	1256.4 seconds
Started	Jul 19 06:43:24 PM PDT 24
Finished	Jul 19 07:04:21 PM PDT 24
Peak memory	617404 kb
Host	smart-a73325c5-d03d-4691-828a-f307f0578548
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2674230504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2674230504
Directory	/workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.87147234
Short name	T971
Test name
Test status
Simulation time	6527820640 ps
CPU time	977.95 seconds
Started	Jul 19 06:38:45 PM PDT 24
Finished	Jul 19 06:55:04 PM PDT 24
Peak memory	617944 kb
Host	smart-104f7504-ae1a-47b0-b52e-8c827eec358a
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=87147234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.87147234
Directory	/workspace/0.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3102357681
Short name	T214
Test name
Test status
Simulation time	9578884760 ps
CPU time	1411.64 seconds
Started	Jul 19 06:38:41 PM PDT 24
Finished	Jul 19 07:02:14 PM PDT 24
Peak memory	610712 kb
Host	smart-2839337a-8bcc-43cf-8e5e-1789922c5f29
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31023 57681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.3102357681
Directory	/workspace/0.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_entropy.702139046
Short name	T713
Test name
Test status
Simulation time	2531227420 ps
CPU time	349.39 seconds
Started	Jul 19 06:39:58 PM PDT 24
Finished	Jul 19 06:45:49 PM PDT 24
Peak memory	609764 kb
Host	smart-e1ce56d3-8a56-47aa-9a43-3d536beb0169
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702139046 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.702139046
Directory	/workspace/0.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_idle.3081350403
Short name	T548
Test name
Test status
Simulation time	2507124170 ps
CPU time	226.41 seconds
Started	Jul 19 06:42:35 PM PDT 24
Finished	Jul 19 06:46:22 PM PDT 24
Peak memory	609628 kb
Host	smart-6c044fb3-cd92-4186-9811-77c8fe91d478
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081350403 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3081350403
Directory	/workspace/0.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3645883293
Short name	T839
Test name
Test status
Simulation time	2725529446 ps
CPU time	322.25 seconds
Started	Jul 19 06:41:11 PM PDT 24
Finished	Jul 19 06:46:34 PM PDT 24
Peak memory	609264 kb
Host	smart-20ae1a82-1843-40db-bf4e-2d216bbbc03a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645883293 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3645883293
Directory	/workspace/0.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.167658605
Short name	T896
Test name
Test status
Simulation time	2773924968 ps
CPU time	337.89 seconds
Started	Jul 19 06:38:44 PM PDT 24
Finished	Jul 19 06:44:22 PM PDT 24
Peak memory	609664 kb
Host	smart-173abfa3-f05a-4498-a8fc-236d19aaed45
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167658605 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.167658605
Directory	/workspace/0.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1507367367
Short name	T656
Test name
Test status
Simulation time	2592088088 ps
CPU time	267.45 seconds
Started	Jul 19 06:40:09 PM PDT 24
Finished	Jul 19 06:44:37 PM PDT 24
Peak memory	609356 kb
Host	smart-705d07ae-3919-4a03-880e-35e1ff73c2b1
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507367367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1507367367
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.898234852
Short name	T74
Test name
Test status
Simulation time	3485981499 ps
CPU time	244.58 seconds
Started	Jul 19 06:41:10 PM PDT 24
Finished	Jul 19 06:45:15 PM PDT 24
Peak memory	609648 kb
Host	smart-bf5da46d-f04d-4aca-b0af-ea1ebf53f284
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89823485 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.898234852
Directory	/workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_kmac_smoketest.4003501636
Short name	T616
Test name
Test status
Simulation time	3167560316 ps
CPU time	273.6 seconds
Started	Jul 19 06:41:08 PM PDT 24
Finished	Jul 19 06:45:43 PM PDT 24
Peak memory	609728 kb
Host	smart-93b54f00-346c-423c-b855-1d9b8c8cbfe1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003501636 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.4003501636
Directory	/workspace/0.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.857251475
Short name	T320
Test name
Test status
Simulation time	2768074950 ps
CPU time	229.87 seconds
Started	Jul 19 06:38:36 PM PDT 24
Finished	Jul 19 06:42:26 PM PDT 24
Peak memory	609728 kb
Host	smart-6694a834-eb5f-431f-b5c6-8712d7008f99
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857251475 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.857251475
Directory	/workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.830912797
Short name	T185
Test name
Test status
Simulation time	2788702477 ps
CPU time	134.61 seconds
Started	Jul 19 06:39:54 PM PDT 24
Finished	Jul 19 06:42:10 PM PDT 24
Peak memory	620036 kb
Host	smart-259b2ab7-002b-4735-9956-f1b79368e0f2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83091279 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.830912797
Directory	/workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1127877894
Short name	T451
Test name
Test status
Simulation time	2568655224 ps
CPU time	126.7 seconds
Started	Jul 19 06:41:52 PM PDT 24
Finished	Jul 19 06:43:59 PM PDT 24
Peak memory	619980 kb
Host	smart-ba20101d-f2e1-48b8-a406-d3d840a25813
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127877894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1127877894
Directory	/workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.23224300
Short name	T428
Test name
Test status
Simulation time	3031789179 ps
CPU time	304.87 seconds
Started	Jul 19 06:41:54 PM PDT 24
Finished	Jul 19 06:47:01 PM PDT 24
Peak memory	621028 kb
Host	smart-f4bb26c7-cc14-4d64-93ca-e210948c3bae
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23224300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.23224300
Directory	/workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1518794801
Short name	T834
Test name
Test status
Simulation time	2491515579 ps
CPU time	150.91 seconds
Started	Jul 19 06:39:29 PM PDT 24
Finished	Jul 19 06:42:01 PM PDT 24
Peak memory	620500 kb
Host	smart-a265ab8f-d724-4120-af7c-41bba1962bf9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1518794801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1518794801
Directory	/workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.4154487082
Short name	T1004
Test name
Test status
Simulation time	2483337726 ps
CPU time	104.71 seconds
Started	Jul 19 06:40:21 PM PDT 24
Finished	Jul 19 06:42:06 PM PDT 24
Peak memory	616724 kb
Host	smart-6f3b1cf4-4825-49dd-803b-845a9c11f72c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=4154487082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.4154487082
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4083336123
Short name	T174
Test name
Test status
Simulation time	1905525389 ps
CPU time	110.01 seconds
Started	Jul 19 06:41:36 PM PDT 24
Finished	Jul 19 06:43:27 PM PDT 24
Peak memory	617704 kb
Host	smart-3fd0ab27-7241-40f0-9cba-153351ffcfd8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083336123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4083336123
Directory	/workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.926534766
Short name	T813
Test name
Test status
Simulation time	47560419957 ps
CPU time	5660.51 seconds
Started	Jul 19 06:42:57 PM PDT 24
Finished	Jul 19 08:17:18 PM PDT 24
Peak memory	620188 kb
Host	smart-75cedf80-0756-4808-992d-42f0213c5f10
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926534766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_dev.926534766
Directory	/workspace/0.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2922184403
Short name	T173
Test name
Test status
Simulation time	11309765678 ps
CPU time	1023.31 seconds
Started	Jul 19 06:39:17 PM PDT 24
Finished	Jul 19 06:56:21 PM PDT 24
Peak memory	618792 kb
Host	smart-3dfbf36f-0239-4b4d-8225-6dd36d27f07a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922184403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2922184403
Directory	/workspace/0.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3277349194
Short name	T184
Test name
Test status
Simulation time	46303295570 ps
CPU time	6222.15 seconds
Started	Jul 19 06:40:57 PM PDT 24
Finished	Jul 19 08:24:41 PM PDT 24
Peak memory	620156 kb
Host	smart-c24b7b97-4347-417f-8f47-6afb20cf2ce6
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277349194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3277349194
Directory	/workspace/0.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.4263810308
Short name	T810
Test name
Test status
Simulation time	26307670880 ps
CPU time	2449.76 seconds
Started	Jul 19 06:38:57 PM PDT 24
Finished	Jul 19 07:19:48 PM PDT 24
Peak memory	619700 kb
Host	smart-3e2acfd1-5256-4ae9-a1e7-fc858feb8afe
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4263810308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.4263810308
Directory	/workspace/0.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1529094377
Short name	T840
Test name
Test status
Simulation time	17017222144 ps
CPU time	3832.26 seconds
Started	Jul 19 06:40:25 PM PDT 24
Finished	Jul 19 07:44:18 PM PDT 24
Peak memory	610276 kb
Host	smart-2c539eaf-8cf1-41b7-9496-edcbbc8ed053
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1529094377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1529094377
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4234134641
Short name	T1018
Test name
Test status
Simulation time	24982657576 ps
CPU time	4684.47 seconds
Started	Jul 19 06:45:10 PM PDT 24
Finished	Jul 19 08:03:16 PM PDT 24
Peak memory	610236 kb
Host	smart-287b5055-f5ca-4f67-9496-70fee1065646
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234134641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.4234134641
Directory	/workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4002216213
Short name	T784
Test name
Test status
Simulation time	3509974360 ps
CPU time	427.75 seconds
Started	Jul 19 06:39:54 PM PDT 24
Finished	Jul 19 06:47:02 PM PDT 24
Peak memory	609528 kb
Host	smart-a9525fc1-991b-43c0-b85a-018db6077a3b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002216213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.4002216213
Directory	/workspace/0.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_randomness.3930052939
Short name	T302
Test name
Test status
Simulation time	6389277300 ps
CPU time	855.64 seconds
Started	Jul 19 06:40:55 PM PDT 24
Finished	Jul 19 06:55:12 PM PDT 24
Peak memory	610224 kb
Host	smart-1b18fbc9-13d4-4262-bf1e-82c36b7f75fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3930052939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3930052939
Directory	/workspace/0.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2827316284
Short name	T668
Test name
Test status
Simulation time	9572219450 ps
CPU time	2101.39 seconds
Started	Jul 19 06:40:58 PM PDT 24
Finished	Jul 19 07:16:00 PM PDT 24
Peak memory	610268 kb
Host	smart-813b09c2-43f5-42f2-ab1b-45653628987c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827316284 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2827316284
Directory	/workspace/0.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2464224108
Short name	T887
Test name
Test status
Simulation time	27561918504 ps
CPU time	5761.18 seconds
Started	Jul 19 06:41:01 PM PDT 24
Finished	Jul 19 08:17:04 PM PDT 24
Peak memory	610280 kb
Host	smart-6730710a-280c-4056-8de5-d2de181a9afc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246422 4108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2464224108
Directory	/workspace/0.chip_sw_otp_ctrl_dai_lock/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1935979009
Short name	T707
Test name
Test status
Simulation time	3168292090 ps
CPU time	327.49 seconds
Started	Jul 19 06:38:56 PM PDT 24
Finished	Jul 19 06:44:24 PM PDT 24
Peak memory	609856 kb
Host	smart-1ffd1135-15e6-4caf-b9d5-24026a15c278
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935979009 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1935979009
Directory	/workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1214682039
Short name	T176
Test name
Test status
Simulation time	4278431658 ps
CPU time	471.17 seconds
Started	Jul 19 06:40:34 PM PDT 24
Finished	Jul 19 06:48:27 PM PDT 24
Peak memory	610684 kb
Host	smart-fc84aac6-9874-47f6-9574-7eebaf3be530
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1214682039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1214682039
Directory	/workspace/0.chip_sw_otp_ctrl_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2794580672
Short name	T957
Test name
Test status
Simulation time	7623979672 ps
CPU time	1268.96 seconds
Started	Jul 19 06:40:18 PM PDT 24
Finished	Jul 19 07:01:28 PM PDT 24
Peak memory	610540 kb
Host	smart-37623823-d400-4c77-8195-4abf789a3826
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2794580672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2794580672
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1053724898
Short name	T833
Test name
Test status
Simulation time	6213977200 ps
CPU time	1409.39 seconds
Started	Jul 19 06:41:43 PM PDT 24
Finished	Jul 19 07:05:13 PM PDT 24
Peak memory	610316 kb
Host	smart-c30c1347-4cf3-4ef9-be38-1d8f855a10f1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1053724898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.1053724898
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3978671099
Short name	T803
Test name
Test status
Simulation time	7446671610 ps
CPU time	1506.09 seconds
Started	Jul 19 06:38:31 PM PDT 24
Finished	Jul 19 07:03:38 PM PDT 24
Peak memory	610496 kb
Host	smart-164f9ec9-3b92-4101-94cb-f07774e79549
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3978671099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.3978671099
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2324124389
Short name	T647
Test name
Test status
Simulation time	3879749408 ps
CPU time	798.27 seconds
Started	Jul 19 06:41:25 PM PDT 24
Finished	Jul 19 06:54:44 PM PDT 24
Peak memory	609812 kb
Host	smart-dc23d16e-9637-460e-b921-150ed806009a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2324124389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2324124389
Directory	/workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.279799431
Short name	T405
Test name
Test status
Simulation time	3065354894 ps
CPU time	224.78 seconds
Started	Jul 19 06:42:06 PM PDT 24
Finished	Jul 19 06:45:51 PM PDT 24
Peak memory	609272 kb
Host	smart-9cf49e3f-09cf-4748-9e65-ddaaeb308b56
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279799431 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.279799431
Directory	/workspace/0.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2352296712
Short name	T271
Test name
Test status
Simulation time	3374189350 ps
CPU time	240.74 seconds
Started	Jul 19 06:41:48 PM PDT 24
Finished	Jul 19 06:45:50 PM PDT 24
Peak memory	609764 kb
Host	smart-a548b2d9-6138-4cd2-9a1e-0afb952dc715
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352296712 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2352296712
Directory	/workspace/0.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_power_idle_load.2653262919
Short name	T937
Test name
Test status
Simulation time	4817346602 ps
CPU time	844.11 seconds
Started	Jul 19 06:45:34 PM PDT 24
Finished	Jul 19 06:59:39 PM PDT 24
Peak memory	610100 kb
Host	smart-f6ba79e5-2462-44ff-b348-47a3c2a3c3af
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653262919 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.2653262919
Directory	/workspace/0.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3126818698
Short name	T761
Test name
Test status
Simulation time	12200644077 ps
CPU time	1621.91 seconds
Started	Jul 19 06:42:58 PM PDT 24
Finished	Jul 19 07:10:00 PM PDT 24
Peak memory	611264 kb
Host	smart-ae2a2968-ee9f-4084-ad6f-2c6ddd2864b7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126 818698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3126818698
Directory	/workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4203373865
Short name	T890
Test name
Test status
Simulation time	33292720743 ps
CPU time	2923.42 seconds
Started	Jul 19 06:41:29 PM PDT 24
Finished	Jul 19 07:30:14 PM PDT 24
Peak memory	610492 kb
Host	smart-3ceab6e8-14e8-4fe9-a327-8a9b94c551c2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420 3373865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.4203373865
Directory	/workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1276891368
Short name	T143
Test name
Test status
Simulation time	23002008914 ps
CPU time	1951.38 seconds
Started	Jul 19 06:40:05 PM PDT 24
Finished	Jul 19 07:12:37 PM PDT 24
Peak memory	610508 kb
Host	smart-97b1858c-6eb3-4c11-ab02-e00e4bad721f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1276891368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1276891368
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.231773560
Short name	T593
Test name
Test status
Simulation time	8969504952 ps
CPU time	743.59 seconds
Started	Jul 19 06:39:22 PM PDT 24
Finished	Jul 19 06:51:46 PM PDT 24
Peak memory	610712 kb
Host	smart-2f280376-7408-49b0-adbc-c5d39d2b09ab
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231773560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.231773560
Directory	/workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.665901405
Short name	T962
Test name
Test status
Simulation time	4827463150 ps
CPU time	483.43 seconds
Started	Jul 19 06:39:38 PM PDT 24
Finished	Jul 19 06:47:42 PM PDT 24
Peak memory	616376 kb
Host	smart-8e74d8f4-8700-4fb7-aef7-0dbc3998f654
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=665901405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.665901405
Directory	/workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3365438713
Short name	T907
Test name
Test status
Simulation time	12177018089 ps
CPU time	1488.65 seconds
Started	Jul 19 06:42:27 PM PDT 24
Finished	Jul 19 07:07:18 PM PDT 24
Peak memory	611288 kb
Host	smart-207f58d6-145a-48ce-9d0b-e7a12ee8fcad
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365438713 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3365438713
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2037618150
Short name	T144
Test name
Test status
Simulation time	8075231318 ps
CPU time	398.6 seconds
Started	Jul 19 06:41:52 PM PDT 24
Finished	Jul 19 06:48:31 PM PDT 24
Peak memory	610360 kb
Host	smart-c4d86527-ed71-4f20-908f-407944693df6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037618150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2037618150
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2923137104
Short name	T850
Test name
Test status
Simulation time	6850042174 ps
CPU time	636.26 seconds
Started	Jul 19 06:42:04 PM PDT 24
Finished	Jul 19 06:52:41 PM PDT 24
Peak memory	609760 kb
Host	smart-9866b0de-989d-41e6-a926-76da546a3ed5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923137104 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2923137104
Directory	/workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3847686359
Short name	T992
Test name
Test status
Simulation time	28620876877 ps
CPU time	2855.18 seconds
Started	Jul 19 06:39:24 PM PDT 24
Finished	Jul 19 07:27:01 PM PDT 24
Peak memory	611284 kb
Host	smart-de701e3f-417e-4a57-b8f1-864f3c77432c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3847686359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3847686359
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.545897794
Short name	T15
Test name
Test status
Simulation time	24499323460 ps
CPU time	1988.08 seconds
Started	Jul 19 06:47:36 PM PDT 24
Finished	Jul 19 07:20:45 PM PDT 24
Peak memory	610580 kb
Host	smart-4be16572-6c80-4133-9a01-839276a5a47e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=545897794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.545897794
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1232450531
Short name	T889
Test name
Test status
Simulation time	33972669178 ps
CPU time	3418.76 seconds
Started	Jul 19 06:40:33 PM PDT 24
Finished	Jul 19 07:37:34 PM PDT 24
Peak memory	611732 kb
Host	smart-e8e3001c-d988-4ee1-8935-317a1dbef80d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232450531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1232450531
Directory	/workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.753539999
Short name	T429
Test name
Test status
Simulation time	5388691980 ps
CPU time	553.93 seconds
Started	Jul 19 06:43:26 PM PDT 24
Finished	Jul 19 06:52:42 PM PDT 24
Peak memory	617560 kb
Host	smart-29afe65c-03aa-4818-8e44-e252a859fe1d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=753539999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.753539999
Directory	/workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.184364283
Short name	T89
Test name
Test status
Simulation time	4996160242 ps
CPU time	361.84 seconds
Started	Jul 19 06:46:09 PM PDT 24
Finished	Jul 19 06:52:12 PM PDT 24
Peak memory	610252 kb
Host	smart-b46d1827-d3c7-4e32-abef-ee890bb9c7ff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=184364283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.184364283
Directory	/workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2888513200
Short name	T567
Test name
Test status
Simulation time	5526640996 ps
CPU time	450.13 seconds
Started	Jul 19 06:45:11 PM PDT 24
Finished	Jul 19 06:52:41 PM PDT 24
Peak memory	610104 kb
Host	smart-93130f2f-9e38-4d65-9d0e-4b52f172d6ae
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888513200 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.2888513200
Directory	/workspace/0.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3102578086
Short name	T878
Test name
Test status
Simulation time	7158281452 ps
CPU time	1635.73 seconds
Started	Jul 19 06:40:12 PM PDT 24
Finished	Jul 19 07:07:28 PM PDT 24
Peak memory	609848 kb
Host	smart-635ecb43-43e4-4282-ad90-fabd8fa578c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102578086 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.3102578086
Directory	/workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1745533841
Short name	T769
Test name
Test status
Simulation time	4571707910 ps
CPU time	384.97 seconds
Started	Jul 19 06:39:26 PM PDT 24
Finished	Jul 19 06:45:52 PM PDT 24
Peak memory	610352 kb
Host	smart-57116fc2-51ae-4790-8eef-93d3257df978
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745533841 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1745533841
Directory	/workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.866957266
Short name	T804
Test name
Test status
Simulation time	5227012720 ps
CPU time	518.58 seconds
Started	Jul 19 06:44:49 PM PDT 24
Finished	Jul 19 06:53:28 PM PDT 24
Peak memory	610128 kb
Host	smart-9088de22-2676-4dbc-8172-126101840b7b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866957266 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.866957266
Directory	/workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2925978446
Short name	T192
Test name
Test status
Simulation time	3712377798 ps
CPU time	489.42 seconds
Started	Jul 19 06:37:49 PM PDT 24
Finished	Jul 19 06:45:58 PM PDT 24
Peak memory	609296 kb
Host	smart-09cf2a1b-59f5-4607-a72c-54d53e5b4a81
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292 5978446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2925978446
Directory	/workspace/0.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3730249287
Short name	T653
Test name
Test status
Simulation time	9942316173 ps
CPU time	516.15 seconds
Started	Jul 19 06:38:52 PM PDT 24
Finished	Jul 19 06:47:29 PM PDT 24
Peak memory	624736 kb
Host	smart-c8ee287d-82b4-4d99-bb1e-329a3bb9cd15
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730249287 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3730249287
Directory	/workspace/0.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2684920884
Short name	T408
Test name
Test status
Simulation time	6104982680 ps
CPU time	668.19 seconds
Started	Jul 19 06:40:31 PM PDT 24
Finished	Jul 19 06:51:40 PM PDT 24
Peak memory	641548 kb
Host	smart-09e0794c-1981-47a9-b0c0-ec847de769fe
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2684920884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2684920884
Directory	/workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1900778298
Short name	T958
Test name
Test status
Simulation time	2588901208 ps
CPU time	316.2 seconds
Started	Jul 19 06:41:06 PM PDT 24
Finished	Jul 19 06:46:23 PM PDT 24
Peak memory	609776 kb
Host	smart-722da330-b21b-4eab-a5b2-24934862acdf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900778298 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1900778298
Directory	/workspace/0.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.870522220
Short name	T929
Test name
Test status
Simulation time	5618462840 ps
CPU time	580.45 seconds
Started	Jul 19 06:39:32 PM PDT 24
Finished	Jul 19 06:49:13 PM PDT 24
Peak memory	610244 kb
Host	smart-c772cff1-d07e-4c15-89aa-f9329e8f41f4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870522220 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.870522220
Directory	/workspace/0.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1719869334
Short name	T951
Test name
Test status
Simulation time	2717657424 ps
CPU time	225.23 seconds
Started	Jul 19 06:43:45 PM PDT 24
Finished	Jul 19 06:47:30 PM PDT 24
Peak memory	609668 kb
Host	smart-192d6390-38db-4616-9ad5-8f81ef436288
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719869334 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1719869334
Directory	/workspace/0.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.371003956
Short name	T324
Test name
Test status
Simulation time	2840283002 ps
CPU time	214.28 seconds
Started	Jul 19 06:42:15 PM PDT 24
Finished	Jul 19 06:45:50 PM PDT 24
Peak memory	609664 kb
Host	smart-91d31f4b-6b98-421b-8147-973edc85dfe2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371003956 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.371003956
Directory	/workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2633372503
Short name	T296
Test name
Test status
Simulation time	5305157072 ps
CPU time	1187.7 seconds
Started	Jul 19 06:41:10 PM PDT 24
Finished	Jul 19 07:00:59 PM PDT 24
Peak memory	609832 kb
Host	smart-9012b06e-6da3-4e02-800f-3d7cc334804f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2633372503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.2633372503
Directory	/workspace/0.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2679160977
Short name	T798
Test name
Test status
Simulation time	6567897764 ps
CPU time	469.3 seconds
Started	Jul 19 06:45:10 PM PDT 24
Finished	Jul 19 06:53:01 PM PDT 24
Peak memory	620288 kb
Host	smart-ab453b17-5dc5-485c-baac-974449f5657a
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679160977 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.2679160977
Directory	/workspace/0.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483378360
Short name	T861
Test name
Test status
Simulation time	3609762752 ps
CPU time	447.84 seconds
Started	Jul 19 06:41:29 PM PDT 24
Finished	Jul 19 06:48:58 PM PDT 24
Peak memory	620124 kb
Host	smart-9e8a3c8e-6fc5-4f1a-bad8-8bd584890b9e
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348337 8360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3483378360
Directory	/workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1244698856
Short name	T1000
Test name
Test status
Simulation time	2805958460 ps
CPU time	238.44 seconds
Started	Jul 19 06:43:59 PM PDT 24
Finished	Jul 19 06:48:00 PM PDT 24
Peak memory	609912 kb
Host	smart-52d273c5-cddd-4139-9cc0-b8a2031aca60
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244698856 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1244698856
Directory	/workspace/0.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4140585203
Short name	T952
Test name
Test status
Simulation time	2856674898 ps
CPU time	258.03 seconds
Started	Jul 19 06:39:55 PM PDT 24
Finished	Jul 19 06:44:14 PM PDT 24
Peak memory	609356 kb
Host	smart-d8b4cbfb-fdd9-413d-9330-5e7b5f652c19
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140585203 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.4140585203
Directory	/workspace/0.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.212739980
Short name	T892
Test name
Test status
Simulation time	2335908850 ps
CPU time	192.44 seconds
Started	Jul 19 06:40:47 PM PDT 24
Finished	Jul 19 06:44:00 PM PDT 24
Peak memory	609628 kb
Host	smart-8d7958eb-508b-40ba-84e5-98046febfc47
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212739980 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_smoketest.212739980
Directory	/workspace/0.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1212702374
Short name	T65
Test name
Test status
Simulation time	2955293238 ps
CPU time	289.83 seconds
Started	Jul 19 06:43:49 PM PDT 24
Finished	Jul 19 06:48:39 PM PDT 24
Peak memory	609528 kb
Host	smart-41a46170-3306-4e0b-84be-da01414649e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212702 374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1212702374
Directory	/workspace/0.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2483831428
Short name	T11
Test name
Test status
Simulation time	4362187062 ps
CPU time	370.45 seconds
Started	Jul 19 06:42:20 PM PDT 24
Finished	Jul 19 06:48:32 PM PDT 24
Peak memory	609336 kb
Host	smart-fbddec84-4529-45b8-9efa-50659658b045
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483831428 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.2483831428
Directory	/workspace/0.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2852914888
Short name	T820
Test name
Test status
Simulation time	7673145152 ps
CPU time	1143.4 seconds
Started	Jul 19 06:37:40 PM PDT 24
Finished	Jul 19 06:56:45 PM PDT 24
Peak memory	610668 kb
Host	smart-b7cbab84-920d-4226-b553-23242074617a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852914888 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2852914888
Directory	/workspace/0.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3784059074
Short name	T550
Test name
Test status
Simulation time	7837652830 ps
CPU time	844.21 seconds
Started	Jul 19 06:41:37 PM PDT 24
Finished	Jul 19 06:55:42 PM PDT 24
Peak memory	610392 kb
Host	smart-2270f692-cbac-4388-9879-a4e7f96e3f73
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784059074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.3784059074
Directory	/workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2663930879
Short name	T27
Test name
Test status
Simulation time	5873524401 ps
CPU time	636.25 seconds
Started	Jul 19 06:43:12 PM PDT 24
Finished	Jul 19 06:53:50 PM PDT 24
Peak memory	624868 kb
Host	smart-ec860698-a94d-4172-8b94-ab6109d7cdbb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663930879 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.2663930879
Directory	/workspace/0.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2195259268
Short name	T47
Test name
Test status
Simulation time	3303622094 ps
CPU time	360.5 seconds
Started	Jul 19 06:40:21 PM PDT 24
Finished	Jul 19 06:46:22 PM PDT 24
Peak memory	610276 kb
Host	smart-6c0a5b87-544b-4f7f-945f-75091b72a18b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195259268 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2195259268
Directory	/workspace/0.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3943186387
Short name	T310
Test name
Test status
Simulation time	4742425200 ps
CPU time	519.51 seconds
Started	Jul 19 06:41:40 PM PDT 24
Finished	Jul 19 06:50:20 PM PDT 24
Peak memory	610848 kb
Host	smart-fb4e1f58-4b91-4b50-9715-084eaa3fbd9e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943186387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.3943186387
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3634041505
Short name	T822
Test name
Test status
Simulation time	4087304908 ps
CPU time	726.08 seconds
Started	Jul 19 06:44:36 PM PDT 24
Finished	Jul 19 06:56:44 PM PDT 24
Peak memory	609668 kb
Host	smart-2cd92cf6-beaf-4f4c-8e81-b34588089118
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634041505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3634041505
Directory	/workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.673848394
Short name	T924
Test name
Test status
Simulation time	2536154440 ps
CPU time	207.22 seconds
Started	Jul 19 06:41:32 PM PDT 24
Finished	Jul 19 06:45:00 PM PDT 24
Peak memory	609276 kb
Host	smart-8e4ff61b-8e13-4096-9be8-07bb50015869
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673848394 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.673848394
Directory	/workspace/0.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.733196551
Short name	T930
Test name
Test status
Simulation time	19986936117 ps
CPU time	3969.69 seconds
Started	Jul 19 06:39:35 PM PDT 24
Finished	Jul 19 07:45:46 PM PDT 24
Peak memory	610452 kb
Host	smart-d9da6a0f-7d18-4e67-b6ea-adca91b03d8b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733196551 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.733196551
Directory	/workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1823934784
Short name	T257
Test name
Test status
Simulation time	4739945819 ps
CPU time	781.04 seconds
Started	Jul 19 06:42:59 PM PDT 24
Finished	Jul 19 06:56:04 PM PDT 24
Peak memory	613568 kb
Host	smart-0fb3ebe4-a240-4ad6-a528-4ca6ed919dbc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823934784 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.1823934784
Directory	/workspace/0.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1275796379
Short name	T259
Test name
Test status
Simulation time	2702854415 ps
CPU time	426.06 seconds
Started	Jul 19 06:42:26 PM PDT 24
Finished	Jul 19 06:49:34 PM PDT 24
Peak memory	612740 kb
Host	smart-43cc908f-d889-4986-8094-c490e9a46020
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275796379 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1275796379
Directory	/workspace/0.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.437501845
Short name	T982
Test name
Test status
Simulation time	25876158768 ps
CPU time	2044.06 seconds
Started	Jul 19 06:40:45 PM PDT 24
Finished	Jul 19 07:14:51 PM PDT 24
Peak memory	613944 kb
Host	smart-37d15176-0bb4-4ccb-9f0e-7b35c6a991e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43750184 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.437501845
Directory	/workspace/0.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_smoketest.3974109255
Short name	T883
Test name
Test status
Simulation time	3425678920 ps
CPU time	365.43 seconds
Started	Jul 19 06:41:01 PM PDT 24
Finished	Jul 19 06:47:07 PM PDT 24
Peak memory	615824 kb
Host	smart-33d9d97f-4ab1-4baa-adae-fe236073d21d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974109255 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.3974109255
Directory	/workspace/0.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3660359798
Short name	T553
Test name
Test status
Simulation time	8509933127 ps
CPU time	2084.54 seconds
Started	Jul 19 06:42:07 PM PDT 24
Finished	Jul 19 07:16:53 PM PDT 24
Peak memory	623060 kb
Host	smart-14655ab6-f4fe-4b64-bcc4-8acd71c40f27
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660359798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.3660359798
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2879896386
Short name	T998
Test name
Test status
Simulation time	3747452095 ps
CPU time	495.9 seconds
Started	Jul 19 06:40:30 PM PDT 24
Finished	Jul 19 06:48:47 PM PDT 24
Peak memory	624692 kb
Host	smart-9d65e335-36dc-4037-8ab3-c4245786119f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879896386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2879896386
Directory	/workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.340844964
Short name	T919
Test name
Test status
Simulation time	77749665308 ps
CPU time	16507.7 seconds
Started	Jul 19 06:40:19 PM PDT 24
Finished	Jul 19 11:15:29 PM PDT 24
Peak memory	635056 kb
Host	smart-356b97bb-4971-4258-9251-e637691dfff6
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=340844964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.340844964
Directory	/workspace/0.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.697051588
Short name	T358
Test name
Test status
Simulation time	3754543592 ps
CPU time	642.84 seconds
Started	Jul 19 06:38:42 PM PDT 24
Finished	Jul 19 06:49:26 PM PDT 24
Peak memory	622420 kb
Host	smart-3c6d3b89-3f69-49b1-83c7-c0db4dba85b7
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697051588 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.697051588
Directory	/workspace/0.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3264228901
Short name	T1003
Test name
Test status
Simulation time	4304548520 ps
CPU time	684.16 seconds
Started	Jul 19 06:41:20 PM PDT 24
Finished	Jul 19 06:52:45 PM PDT 24
Peak memory	624068 kb
Host	smart-29660880-fff3-46e1-885e-7c5360d9552b
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264228901 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3264228901
Directory	/workspace/0.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1916637772
Short name	T441
Test name
Test status
Simulation time	2766979517 ps
CPU time	319.12 seconds
Started	Jul 19 06:39:57 PM PDT 24
Finished	Jul 19 06:45:17 PM PDT 24
Peak memory	609892 kb
Host	smart-18de4112-f0a1-45a1-966a-e37aae016c40
User	root
Command	/workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916637772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.1916637772
Directory	/workspace/0.chip_sw_usb_ast_clk_calib/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1429081725
Short name	T5
Test name
Test status
Simulation time	7789140358 ps
CPU time	2014.97 seconds
Started	Jul 19 06:38:53 PM PDT 24
Finished	Jul 19 07:12:29 PM PDT 24
Peak memory	609280 kb
Host	smart-147d41af-ab18-469e-ba48-9acc75df1031
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14290 81725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.1429081725
Directory	/workspace/0.chip_sw_usbdev_config_host/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_dpi.1270309102
Short name	T786
Test name
Test status
Simulation time	11842493024 ps
CPU time	2674.78 seconds
Started	Jul 19 06:38:18 PM PDT 24
Finished	Jul 19 07:22:54 PM PDT 24
Peak memory	610136 kb
Host	smart-87596e09-b316-4432-aefe-2938cf512f81
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1270309102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.1270309102
Directory	/workspace/0.chip_sw_usbdev_dpi/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_pullup.879031190
Short name	T126
Test name
Test status
Simulation time	2954901992 ps
CPU time	366.61 seconds
Started	Jul 19 06:39:12 PM PDT 24
Finished	Jul 19 06:45:19 PM PDT 24
Peak memory	609276 kb
Host	smart-61cf66a3-f2da-4770-b5a5-775c45d4b3cc
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879031190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.879031190
Directory	/workspace/0.chip_sw_usbdev_pullup/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1139497594
Short name	T33
Test name
Test status
Simulation time	3261286584 ps
CPU time	596.89 seconds
Started	Jul 19 06:40:10 PM PDT 24
Finished	Jul 19 06:50:07 PM PDT 24
Peak memory	609284 kb
Host	smart-4f86d04b-a83a-4d1c-81f1-a717351fc799
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113949759 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.1139497594
Directory	/workspace/0.chip_sw_usbdev_setuprx/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_stream.3863432810
Short name	T440
Test name
Test status
Simulation time	18609792850 ps
CPU time	4846.91 seconds
Started	Jul 19 06:39:06 PM PDT 24
Finished	Jul 19 07:59:54 PM PDT 24
Peak memory	610196 kb
Host	smart-cc007888-75a0-42f3-862d-60939255c9a2
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3863432810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3863432810
Directory	/workspace/0.chip_sw_usbdev_stream/latest

Test location	/workspace/coverage/default/0.chip_sw_usbdev_vbus.3299340994
Short name	T596
Test name
Test status
Simulation time	2727733104 ps
CPU time	175.03 seconds
Started	Jul 19 06:40:07 PM PDT 24
Finished	Jul 19 06:43:02 PM PDT 24
Peak memory	609276 kb
Host	smart-f361a0c3-d63c-47ab-a6d6-d0b014231c04
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299340994 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3299340994
Directory	/workspace/0.chip_sw_usbdev_vbus/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_dev.809811459
Short name	T137
Test name
Test status
Simulation time	3073879940 ps
CPU time	167.32 seconds
Started	Jul 19 06:41:05 PM PDT 24
Finished	Jul 19 06:43:54 PM PDT 24
Peak memory	621160 kb
Host	smart-263db4a0-1156-49f9-8737-91b3795aafd3
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=809811459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.809811459
Directory	/workspace/0.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_prod.2680033258
Short name	T623
Test name
Test status
Simulation time	10781556612 ps
CPU time	1208.96 seconds
Started	Jul 19 06:43:32 PM PDT 24
Finished	Jul 19 07:03:42 PM PDT 24
Peak memory	631472 kb
Host	smart-186aeb0e-737f-4d8b-a7d4-3d0a0c55c7a2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680033258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2680033258
Directory	/workspace/0.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_rma.3530968151
Short name	T630
Test name
Test status
Simulation time	2762411054 ps
CPU time	201.65 seconds
Started	Jul 19 06:39:40 PM PDT 24
Finished	Jul 19 06:43:04 PM PDT 24
Peak memory	620696 kb
Host	smart-ec722d43-9a11-4509-8606-690ecfe85948
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530968151 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.3530968151
Directory	/workspace/0.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2469499128
Short name	T99
Test name
Test status
Simulation time	5593393709 ps
CPU time	493.08 seconds
Started	Jul 19 06:43:49 PM PDT 24
Finished	Jul 19 06:52:04 PM PDT 24
Peak memory	620900 kb
Host	smart-74ee7258-440f-4ddc-ad48-b4806bea45da
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469499128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2469499128
Directory	/workspace/0.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_dev.924890459
Short name	T863
Test name
Test status
Simulation time	15469131790 ps
CPU time	3380.43 seconds
Started	Jul 19 06:50:13 PM PDT 24
Finished	Jul 19 07:46:34 PM PDT 24
Peak memory	610204 kb
Host	smart-86a0f606-e0ae-4144-b44d-d7176bdf2010
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924890459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_dev.924890459
Directory	/workspace/0.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod.1476154224
Short name	T849
Test name
Test status
Simulation time	15441474809 ps
CPU time	3947.16 seconds
Started	Jul 19 06:49:36 PM PDT 24
Finished	Jul 19 07:55:24 PM PDT 24
Peak memory	610312 kb
Host	smart-b2788f08-62c7-443a-8a81-ef691a880c04
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476154224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1476154224
Directory	/workspace/0.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3503993848
Short name	T774
Test name
Test status
Simulation time	15811493413 ps
CPU time	4464.61 seconds
Started	Jul 19 06:45:37 PM PDT 24
Finished	Jul 19 08:00:02 PM PDT 24
Peak memory	609632 kb
Host	smart-891ba5c1-dd5d-4cf1-bc8a-de693b152030
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503993848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3503993848
Directory	/workspace/0.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_rma.2302281923
Short name	T600
Test name
Test status
Simulation time	14910935697 ps
CPU time	3945.14 seconds
Started	Jul 19 06:49:36 PM PDT 24
Finished	Jul 19 07:55:22 PM PDT 24
Peak memory	610432 kb
Host	smart-291f0dcd-8053-4744-af6f-375c5ef71ea5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302281923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.2302281923
Directory	/workspace/0.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1710798567
Short name	T864
Test name
Test status
Simulation time	11227297313 ps
CPU time	3527.05 seconds
Started	Jul 19 06:46:36 PM PDT 24
Finished	Jul 19 07:45:24 PM PDT 24
Peak memory	609656 kb
Host	smart-d629c639-e815-44d7-834a-34b0c76ae6f7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710798567 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.1710798567
Directory	/workspace/0.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.922775995
Short name	T927
Test name
Test status
Simulation time	24764540316 ps
CPU time	7990.93 seconds
Started	Jul 19 06:44:44 PM PDT 24
Finished	Jul 19 08:57:56 PM PDT 24
Peak memory	609408 kb
Host	smart-2f4f15bb-9efb-4482-a0f6-b664f3a24c8b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=922775995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.922775995
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2930368768
Short name	T280
Test name
Test status
Simulation time	24296644040 ps
CPU time	7037.53 seconds
Started	Jul 19 06:43:28 PM PDT 24
Finished	Jul 19 08:40:47 PM PDT 24
Peak memory	609456 kb
Host	smart-b06cbd4e-51a8-495e-add1-04ab1fd50032
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2930368768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2930368768
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3533203238
Short name	T279
Test name
Test status
Simulation time	24170750528 ps
CPU time	6506.28 seconds
Started	Jul 19 06:45:37 PM PDT 24
Finished	Jul 19 08:34:04 PM PDT 24
Peak memory	609928 kb
Host	smart-72ff35b6-cbc3-4e95-8897-91f3a4bdedb3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3533203238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3533203238
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1501247122
Short name	T281
Test name
Test status
Simulation time	23013690890 ps
CPU time	6639.82 seconds
Started	Jul 19 06:49:44 PM PDT 24
Finished	Jul 19 08:40:26 PM PDT 24
Peak memory	610084 kb
Host	smart-22c1d078-be66-4a2a-9009-0c2d8325b44e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1501247122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1501247122
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2862851561
Short name	T419
Test name
Test status
Simulation time	15462262828 ps
CPU time	4450.33 seconds
Started	Jul 19 06:47:05 PM PDT 24
Finished	Jul 19 08:01:17 PM PDT 24
Peak memory	609424 kb
Host	smart-b7d02074-afbc-46af-b092-bd8f28461ba6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2862851561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2862851561
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1938138185
Short name	T936
Test name
Test status
Simulation time	15643868108 ps
CPU time	4933.06 seconds
Started	Jul 19 06:50:04 PM PDT 24
Finished	Jul 19 08:12:18 PM PDT 24
Peak memory	609424 kb
Host	smart-fd82a783-e96b-463f-b3c6-ca9df1305a0b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1938138185 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1938138185
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1601373472
Short name	T897
Test name
Test status
Simulation time	15234578928 ps
CPU time	4391.43 seconds
Started	Jul 19 06:45:12 PM PDT 24
Finished	Jul 19 07:58:24 PM PDT 24
Peak memory	609424 kb
Host	smart-10c04b9d-3b06-46f4-8f6d-8f6beaf9cf76
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1601373472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1601373472
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2536318611
Short name	T601
Test name
Test status
Simulation time	14380271184 ps
CPU time	4712.43 seconds
Started	Jul 19 06:44:59 PM PDT 24
Finished	Jul 19 08:03:32 PM PDT 24
Peak memory	610016 kb
Host	smart-82be93e4-7f31-41cb-9eb4-ef419bd9e2e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2536318611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2536318611
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2630685547
Short name	T604
Test name
Test status
Simulation time	10943161386 ps
CPU time	3032.35 seconds
Started	Jul 19 06:48:07 PM PDT 24
Finished	Jul 19 07:38:41 PM PDT 24
Peak memory	609496 kb
Host	smart-04d11a32-4261-4f16-8263-2c756fda9211
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630685547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2630685547
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2984480608
Short name	T160
Test name
Test status
Simulation time	15222259232 ps
CPU time	4968.18 seconds
Started	Jul 19 06:47:36 PM PDT 24
Finished	Jul 19 08:10:26 PM PDT 24
Peak memory	609420 kb
Host	smart-0ea64fde-ddb7-4196-b9e8-cbf9808cfe37
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984480608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2984480608
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1417411075
Short name	T688
Test name
Test status
Simulation time	15610293296 ps
CPU time	3841.04 seconds
Started	Jul 19 06:48:54 PM PDT 24
Finished	Jul 19 07:52:56 PM PDT 24
Peak memory	609440 kb
Host	smart-8fcf246b-cd7d-4c0b-af31-b03dd636ec44
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417411075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1417411075
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1753143125
Short name	T909
Test name
Test status
Simulation time	15762379074 ps
CPU time	4479.57 seconds
Started	Jul 19 06:44:01 PM PDT 24
Finished	Jul 19 07:58:41 PM PDT 24
Peak memory	609420 kb
Host	smart-9756bd35-2dff-497a-9eb6-e7b1f99af8e4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175314 3125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1753143125
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4230994909
Short name	T932
Test name
Test status
Simulation time	15216280990 ps
CPU time	4202.24 seconds
Started	Jul 19 06:46:59 PM PDT 24
Finished	Jul 19 07:57:02 PM PDT 24
Peak memory	610024 kb
Host	smart-086c2aa4-77e0-4152-a2d4-b4410051c75f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230994909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4230994909
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3262806032
Short name	T716
Test name
Test status
Simulation time	11259137512 ps
CPU time	3336.85 seconds
Started	Jul 19 06:46:32 PM PDT 24
Finished	Jul 19 07:42:10 PM PDT 24
Peak memory	610304 kb
Host	smart-69efad7f-845b-4df5-ac3f-c180fe2e82cb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3262806032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3262806032
Directory	/workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2307705140
Short name	T222
Test name
Test status
Simulation time	11862818232 ps
CPU time	2261.27 seconds
Started	Jul 19 06:41:01 PM PDT 24
Finished	Jul 19 07:18:44 PM PDT 24
Peak memory	623784 kb
Host	smart-060ef533-fc3e-4c37-97ec-3592000b314b
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077 05140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2307705140
Directory	/workspace/0.rom_e2e_jtag_debug_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1669411224
Short name	T63
Test name
Test status
Simulation time	12697627390 ps
CPU time	2246.06 seconds
Started	Jul 19 06:42:05 PM PDT 24
Finished	Jul 19 07:19:32 PM PDT 24
Peak memory	624188 kb
Host	smart-7c4cf770-20f7-4259-b081-1a7b7e025cc8
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16694 11224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1669411224
Directory	/workspace/0.rom_e2e_jtag_debug_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1182572261
Short name	T202
Test name
Test status
Simulation time	31915975255 ps
CPU time	2839.06 seconds
Started	Jul 19 06:40:43 PM PDT 24
Finished	Jul 19 07:28:04 PM PDT 24
Peak memory	621120 kb
Host	smart-8f1de3cc-5683-4785-8fc8-f993a1d7011f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1182572261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1182572261
Directory	/workspace/0.rom_e2e_jtag_inject_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3077750375
Short name	T368
Test name
Test status
Simulation time	24631815376 ps
CPU time	2900.67 seconds
Started	Jul 19 06:40:08 PM PDT 24
Finished	Jul 19 07:28:30 PM PDT 24
Peak memory	620232 kb
Host	smart-6229bdc8-64af-4e12-9d75-da44d7e220e9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3077750375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3077750375
Directory	/workspace/0.rom_e2e_jtag_inject_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.480300533
Short name	T614
Test name
Test status
Simulation time	14589515320 ps
CPU time	4623.4 seconds
Started	Jul 19 06:50:09 PM PDT 24
Finished	Jul 19 08:07:13 PM PDT 24
Peak memory	610024 kb
Host	smart-6e13802e-bdf0-48a2-840c-564679dcf66e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480300533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.480300533
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3050395509
Short name	T732
Test name
Test status
Simulation time	14633307272 ps
CPU time	5079.51 seconds
Started	Jul 19 06:50:07 PM PDT 24
Finished	Jul 19 08:14:48 PM PDT 24
Peak memory	609500 kb
Host	smart-fb7f568c-ef99-4def-a8dc-87a2649f897f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050395509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3050395509
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1648416274
Short name	T57
Test name
Test status
Simulation time	15738204538 ps
CPU time	4426.99 seconds
Started	Jul 19 06:49:13 PM PDT 24
Finished	Jul 19 08:03:01 PM PDT 24
Peak memory	610308 kb
Host	smart-8539d3bb-a88c-42bd-9c1c-8f9912f864c8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648416274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.1648416274
Directory	/workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/0.rom_e2e_self_hash.4236160461
Short name	T740
Test name
Test status
Simulation time	26438858968 ps
CPU time	6706.78 seconds
Started	Jul 19 06:48:55 PM PDT 24
Finished	Jul 19 08:40:43 PM PDT 24
Peak memory	610184 kb
Host	smart-d000ae18-fdf9-4aa8-b304-c73f04888fc1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236160461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.4236160461
Directory	/workspace/0.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3880060129
Short name	T619
Test name
Test status
Simulation time	14260029260 ps
CPU time	3925.29 seconds
Started	Jul 19 06:45:05 PM PDT 24
Finished	Jul 19 07:50:31 PM PDT 24
Peak memory	610496 kb
Host	smart-6b1496db-1354-4355-a001-e0d28762f16b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880060129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.3880060129
Directory	/workspace/0.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/0.rom_e2e_shutdown_output.3609470935
Short name	T837
Test name
Test status
Simulation time	24757706060 ps
CPU time	3779.66 seconds
Started	Jul 19 06:44:39 PM PDT 24
Finished	Jul 19 07:47:40 PM PDT 24
Peak memory	611636 kb
Host	smart-d0d3429a-bfc2-433a-a969-7ea2a299e264
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609470935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3609470935
Directory	/workspace/0.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3539643806
Short name	T948
Test name
Test status
Simulation time	24097649376 ps
CPU time	5777.89 seconds
Started	Jul 19 06:47:32 PM PDT 24
Finished	Jul 19 08:23:51 PM PDT 24
Peak memory	611068 kb
Host	smart-a3c09bf0-e939-461c-bd73-fe5ac36c899a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3539643806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.3539643806
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2545631154
Short name	T824
Test name
Test status
Simulation time	23680858218 ps
CPU time	6298.75 seconds
Started	Jul 19 06:44:27 PM PDT 24
Finished	Jul 19 08:29:27 PM PDT 24
Peak memory	611392 kb
Host	smart-271d4501-2d77-41e4-89ea-67cc713da0c7
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2545631154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2545631154
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3838868254
Short name	T299
Test name
Test status
Simulation time	24106695704 ps
CPU time	7094.83 seconds
Started	Jul 19 06:47:29 PM PDT 24
Finished	Jul 19 08:45:45 PM PDT 24
Peak memory	609472 kb
Host	smart-ad61bf5b-e2c2-4e14-b2c5-3f48914c9758
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3838868254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.3838868254
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1818103699
Short name	T773
Test name
Test status
Simulation time	23115470952 ps
CPU time	4846.61 seconds
Started	Jul 19 06:50:19 PM PDT 24
Finished	Jul 19 08:11:07 PM PDT 24
Peak memory	611444 kb
Host	smart-5bb650f8-c15f-4531-9420-96f714f52421
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1818103699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.1818103699
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.728868885
Short name	T55
Test name
Test status
Simulation time	17855175008 ps
CPU time	5643.42 seconds
Started	Jul 19 06:45:45 PM PDT 24
Finished	Jul 19 08:19:50 PM PDT 24
Peak memory	610644 kb
Host	smart-eff41dac-98ea-48e3-9489-811a1e0d3075
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=728868885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_ bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alwa ys_a_bad_b_bad_test_unlocked0.728868885
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4274684215
Short name	T768
Test name
Test status
Simulation time	15225174224 ps
CPU time	4181.52 seconds
Started	Jul 19 06:43:30 PM PDT 24
Finished	Jul 19 07:53:12 PM PDT 24
Peak memory	610264 kb
Host	smart-da536a16-28ec-48c4-89c1-16e326907fe5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274684215 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4274684215
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1310399874
Short name	T816
Test name
Test status
Simulation time	15106825545 ps
CPU time	3873.62 seconds
Started	Jul 19 06:45:43 PM PDT 24
Finished	Jul 19 07:50:17 PM PDT 24
Peak memory	609460 kb
Host	smart-4a801805-00f7-4f72-a190-4fea5212a69d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310399874 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1310399874
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1171812822
Short name	T610
Test name
Test status
Simulation time	13944739108 ps
CPU time	3800.52 seconds
Started	Jul 19 06:46:55 PM PDT 24
Finished	Jul 19 07:50:17 PM PDT 24
Peak memory	609436 kb
Host	smart-0c3a2fb7-5f32-42b3-8aca-b7bb1c44109e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171812822 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1171812822
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1841396107
Short name	T759
Test name
Test status
Simulation time	11223415350 ps
CPU time	3508.92 seconds
Started	Jul 19 06:48:30 PM PDT 24
Finished	Jul 19 07:46:59 PM PDT 24
Peak memory	610632 kb
Host	smart-aa920ee9-6368-46ce-89ec-02b39590797b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841396107 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1841396107
Directory	/workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3607305014
Short name	T613
Test name
Test status
Simulation time	15032328948 ps
CPU time	5010.37 seconds
Started	Jul 19 06:45:20 PM PDT 24
Finished	Jul 19 08:08:52 PM PDT 24
Peak memory	609480 kb
Host	smart-9b052977-89ea-435d-a5c1-b16920f267e3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607305014 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3607305014
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3464259131
Short name	T1002
Test name
Test status
Simulation time	14449168072 ps
CPU time	4009 seconds
Started	Jul 19 06:49:56 PM PDT 24
Finished	Jul 19 07:56:46 PM PDT 24
Peak memory	609452 kb
Host	smart-ba85296a-bf89-40a9-af48-d8f0e6b6c0fe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464259131 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3464259131
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1817621183
Short name	T56
Test name
Test status
Simulation time	14820542514 ps
CPU time	3896.93 seconds
Started	Jul 19 06:45:06 PM PDT 24
Finished	Jul 19 07:50:04 PM PDT 24
Peak memory	611216 kb
Host	smart-f4ab268d-86b0-4684-ba7a-d394a64aaef5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817621183 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1817621183
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3535553256
Short name	T801
Test name
Test status
Simulation time	14304577426 ps
CPU time	3778.69 seconds
Started	Jul 19 06:46:03 PM PDT 24
Finished	Jul 19 07:49:03 PM PDT 24
Peak memory	609480 kb
Host	smart-5bdd4541-4d65-4aed-a1de-c8ea9ce0899d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535553256 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3535553256
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest

Test location	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2839384682
Short name	T702
Test name
Test status
Simulation time	10829361768 ps
CPU time	3527 seconds
Started	Jul 19 06:45:36 PM PDT 24
Finished	Jul 19 07:44:25 PM PDT 24
Peak memory	609560 kb
Host	smart-502fecd8-0b64-4792-b262-93c1dce5613f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839384682 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2839384682
Directory	/workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest

Test location	/workspace/coverage/default/0.rom_e2e_smoke.2661822056
Short name	T615
Test name
Test status
Simulation time	15567989058 ps
CPU time	4637.38 seconds
Started	Jul 19 06:47:26 PM PDT 24
Finished	Jul 19 08:04:44 PM PDT 24
Peak memory	610036 kb
Host	smart-81b51076-1584-480e-a0b3-72b67e55f1fc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2661822056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2661822056
Directory	/workspace/0.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/0.rom_e2e_static_critical.2548651221
Short name	T565
Test name
Test status
Simulation time	17180399128 ps
CPU time	4324.3 seconds
Started	Jul 19 06:44:47 PM PDT 24
Finished	Jul 19 07:56:52 PM PDT 24
Peak memory	610128 kb
Host	smart-24d4c878-d6d2-4696-a754-b6a30498c983
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548651221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2548651221
Directory	/workspace/0.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/0.rom_keymgr_functest.2918727612
Short name	T920
Test name
Test status
Simulation time	5785339444 ps
CPU time	709.59 seconds
Started	Jul 19 06:41:43 PM PDT 24
Finished	Jul 19 06:53:33 PM PDT 24
Peak memory	609496 kb
Host	smart-e1d3254b-b136-445c-9379-1c65660675ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918727612 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2918727612
Directory	/workspace/0.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/0.rom_volatile_raw_unlock.3929046924
Short name	T452
Test name
Test status
Simulation time	2272957294 ps
CPU time	128.05 seconds
Started	Jul 19 06:44:07 PM PDT 24
Finished	Jul 19 06:46:16 PM PDT 24
Peak memory	617036 kb
Host	smart-6e935a52-312e-454e-9f24-f01ba56e4f21
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929046924 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3929046924
Directory	/workspace/0.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_jtag_mem_access.1028753696
Short name	T61
Test name
Test status
Simulation time	14417251800 ps
CPU time	1447.98 seconds
Started	Jul 19 06:41:10 PM PDT 24
Finished	Jul 19 07:05:19 PM PDT 24
Peak memory	607936 kb
Host	smart-d4dccaa5-0284-4cdb-b82e-457661c5e26d
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028753696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 028753696
Directory	/workspace/1.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.264697710
Short name	T8
Test name
Test status
Simulation time	3915955108 ps
CPU time	434.76 seconds
Started	Jul 19 06:49:07 PM PDT 24
Finished	Jul 19 06:56:22 PM PDT 24
Peak memory	619880 kb
Host	smart-5872e76d-b041-4540-85b2-04adfe58f361
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 64697710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.264697710
Directory	/workspace/1.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sival_flash_info_access.685773333
Short name	T390
Test name
Test status
Simulation time	3160552548 ps
CPU time	345.53 seconds
Started	Jul 19 06:43:04 PM PDT 24
Finished	Jul 19 06:48:51 PM PDT 24
Peak memory	609720 kb
Host	smart-6a0690d3-d433-40b6-91fb-15f61108941a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=685773333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.685773333
Directory	/workspace/1.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.348261250
Short name	T354
Test name
Test status
Simulation time	18078119380 ps
CPU time	568.98 seconds
Started	Jul 19 06:47:19 PM PDT 24
Finished	Jul 19 06:56:49 PM PDT 24
Peak memory	619140 kb
Host	smart-ae591ae6-dbbf-42f4-b3c1-e0bcaf833074
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=348261250 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.348261250
Directory	/workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc.3209218132
Short name	T838
Test name
Test status
Simulation time	3184735920 ps
CPU time	262.69 seconds
Started	Jul 19 06:44:27 PM PDT 24
Finished	Jul 19 06:48:50 PM PDT 24
Peak memory	609292 kb
Host	smart-6866ef6d-f4f4-44a0-91b0-b2ef1cd71f7a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209218132 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3209218132
Directory	/workspace/1.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.4192744653
Short name	T215
Test name
Test status
Simulation time	2655754745 ps
CPU time	372.83 seconds
Started	Jul 19 06:50:03 PM PDT 24
Finished	Jul 19 06:56:16 PM PDT 24
Peak memory	609304 kb
Host	smart-0283e3ba-5ace-421e-9569-04efd5ddc678
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192 744653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.4192744653
Directory	/workspace/1.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2011308024
Short name	T575
Test name
Test status
Simulation time	2196814415 ps
CPU time	244.72 seconds
Started	Jul 19 06:52:50 PM PDT 24
Finished	Jul 19 06:56:55 PM PDT 24
Peak memory	609724 kb
Host	smart-e189e1ac-055a-4d4e-9468-6aca32bfa38f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011308024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2011308024
Directory	/workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_entropy.62878365
Short name	T595
Test name
Test status
Simulation time	2890594140 ps
CPU time	257.66 seconds
Started	Jul 19 06:45:40 PM PDT 24
Finished	Jul 19 06:49:58 PM PDT 24
Peak memory	609696 kb
Host	smart-3588a17c-6d2d-4be6-9546-9c4942af4202
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62878365 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.62878365
Directory	/workspace/1.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_idle.821726238
Short name	T916
Test name
Test status
Simulation time	3005743476 ps
CPU time	303.98 seconds
Started	Jul 19 06:43:22 PM PDT 24
Finished	Jul 19 06:48:26 PM PDT 24
Peak memory	609508 kb
Host	smart-e1d98274-578c-40eb-821d-d1d6089cef64
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821726238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.821726238
Directory	/workspace/1.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_masking_off.1644548071
Short name	T147
Test name
Test status
Simulation time	3178320646 ps
CPU time	267.59 seconds
Started	Jul 19 06:43:22 PM PDT 24
Finished	Jul 19 06:47:50 PM PDT 24
Peak memory	609368 kb
Host	smart-c5f0372f-866f-4435-9dc2-75efbbe9091b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644548071 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.1644548071
Directory	/workspace/1.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/1.chip_sw_aes_smoketest.523730294
Short name	T961
Test name
Test status
Simulation time	3352959620 ps
CPU time	243.42 seconds
Started	Jul 19 06:52:13 PM PDT 24
Finished	Jul 19 06:56:18 PM PDT 24
Peak memory	609648 kb
Host	smart-b3889537-a749-453f-8fbb-b9602bf8b589
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523730294 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.523730294
Directory	/workspace/1.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2221600353
Short name	T684
Test name
Test status
Simulation time	5371622028 ps
CPU time	555.66 seconds
Started	Jul 19 06:42:52 PM PDT 24
Finished	Jul 19 06:52:08 PM PDT 24
Peak memory	619324 kb
Host	smart-30de1e0e-9fb1-4451-a0e2-e196e8ed6cb3
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2221600353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2221600353
Directory	/workspace/1.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2358652797
Short name	T243
Test name
Test status
Simulation time	8098824020 ps
CPU time	2071.56 seconds
Started	Jul 19 06:42:56 PM PDT 24
Finished	Jul 19 07:17:28 PM PDT 24
Peak memory	609960 kb
Host	smart-7d72043e-67e9-44c4-87b4-dc4fff034b30
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2358652797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2358652797
Directory	/workspace/1.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2537776617
Short name	T891
Test name
Test status
Simulation time	7083777032 ps
CPU time	1606.39 seconds
Started	Jul 19 06:44:18 PM PDT 24
Finished	Jul 19 07:11:05 PM PDT 24
Peak memory	610200 kb
Host	smart-5f303133-9c27-4bf6-a8df-46ab4b8a3380
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537776617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.2537776617
Directory	/workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.4225848807
Short name	T632
Test name
Test status
Simulation time	7533563190 ps
CPU time	1651.3 seconds
Started	Jul 19 06:46:05 PM PDT 24
Finished	Jul 19 07:13:37 PM PDT 24
Peak memory	609892 kb
Host	smart-01be8bd6-166f-449f-a187-4b0f66a546f9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4225848807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.4225848807
Directory	/workspace/1.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.87086085
Short name	T737
Test name
Test status
Simulation time	4831891960 ps
CPU time	482.24 seconds
Started	Jul 19 06:46:56 PM PDT 24
Finished	Jul 19 06:54:59 PM PDT 24
Peak memory	610136 kb
Host	smart-97d6b9f4-4f03-4e9a-8a28-45e334d660a3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=87086085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.87086085
Directory	/workspace/1.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3492662585
Short name	T226
Test name
Test status
Simulation time	255205825048 ps
CPU time	12427.9 seconds
Started	Jul 19 06:44:54 PM PDT 24
Finished	Jul 19 10:12:03 PM PDT 24
Peak memory	610212 kb
Host	smart-66aced6f-9c4b-4e6b-b4cf-cdf0207fab10
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3492662585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3492662585
Directory	/workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_irq.1471957838
Short name	T325
Test name
Test status
Simulation time	3996363780 ps
CPU time	406.94 seconds
Started	Jul 19 06:43:12 PM PDT 24
Finished	Jul 19 06:49:59 PM PDT 24
Peak memory	609540 kb
Host	smart-f3dc7ba3-d646-444c-91b2-a218c1649b1c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471957838 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1471957838
Directory	/workspace/1.chip_sw_aon_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4273394769
Short name	T1013
Test name
Test status
Simulation time	6853912066 ps
CPU time	503.25 seconds
Started	Jul 19 06:47:39 PM PDT 24
Finished	Jul 19 06:56:03 PM PDT 24
Peak memory	610068 kb
Host	smart-cdc05f0d-7ce9-4532-8343-3c7e99b677de
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4273394769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4273394769
Directory	/workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3995093034
Short name	T571
Test name
Test status
Simulation time	2751746820 ps
CPU time	328.47 seconds
Started	Jul 19 06:53:13 PM PDT 24
Finished	Jul 19 06:58:42 PM PDT 24
Peak memory	609740 kb
Host	smart-9a7cb2ec-c43e-4c12-b2a8-b73c375eece2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995093034 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.3995093034
Directory	/workspace/1.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.3713300098
Short name	T556
Test name
Test status
Simulation time	7095223444 ps
CPU time	651.93 seconds
Started	Jul 19 06:47:26 PM PDT 24
Finished	Jul 19 06:58:18 PM PDT 24
Peak memory	610052 kb
Host	smart-f559538c-a908-4144-802b-d32e96fc9d87
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3713300098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.3713300098
Directory	/workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.467783608
Short name	T741
Test name
Test status
Simulation time	4913400266 ps
CPU time	539.99 seconds
Started	Jul 19 06:41:37 PM PDT 24
Finished	Jul 19 06:50:38 PM PDT 24
Peak memory	610444 kb
Host	smart-767cd287-3ab9-44f0-8a88-809f6a24ae1b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =467783608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.467783608
Directory	/workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2620856193
Short name	T856
Test name
Test status
Simulation time	7584409694 ps
CPU time	1050.44 seconds
Started	Jul 19 06:48:28 PM PDT 24
Finished	Jul 19 07:05:59 PM PDT 24
Peak memory	617100 kb
Host	smart-e8264070-f167-451d-8844-2a7e9670cf78
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620856193 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2620856193
Directory	/workspace/1.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.182012357
Short name	T86
Test name
Test status
Simulation time	24100207007 ps
CPU time	4200.73 seconds
Started	Jul 19 06:51:21 PM PDT 24
Finished	Jul 19 08:01:26 PM PDT 24
Peak memory	610836 kb
Host	smart-cb3d42c8-e1d4-44eb-b0cf-c5212a20eb8a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182012357 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.182012357
Directory	/workspace/1.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2735518534
Short name	T729
Test name
Test status
Simulation time	7028188272 ps
CPU time	531.91 seconds
Started	Jul 19 06:49:05 PM PDT 24
Finished	Jul 19 06:57:57 PM PDT 24
Peak memory	624772 kb
Host	smart-12ce8530-a61d-42fe-b3b8-df304ecd0bad
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2735518534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2735518534
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1342847616
Short name	T752
Test name
Test status
Simulation time	4080234728 ps
CPU time	714.23 seconds
Started	Jul 19 06:47:10 PM PDT 24
Finished	Jul 19 06:59:05 PM PDT 24
Peak memory	614032 kb
Host	smart-6113e9a0-6882-46b6-9ae9-b7592561d61c
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342847616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1342847616
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1912099164
Short name	T747
Test name
Test status
Simulation time	4524945852 ps
CPU time	782.89 seconds
Started	Jul 19 06:46:49 PM PDT 24
Finished	Jul 19 06:59:53 PM PDT 24
Peak memory	614064 kb
Host	smart-041b63a8-e7fd-4c30-a710-4fd2a6e1447c
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912099164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1912099164
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2627608791
Short name	T555
Test name
Test status
Simulation time	3921455846 ps
CPU time	542.05 seconds
Started	Jul 19 06:46:52 PM PDT 24
Finished	Jul 19 06:55:55 PM PDT 24
Peak memory	612856 kb
Host	smart-849db55b-5df8-49f5-abea-27475a7b553c
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627608791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2627608791
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1005980584
Short name	T791
Test name
Test status
Simulation time	5095038728 ps
CPU time	679.84 seconds
Started	Jul 19 06:47:09 PM PDT 24
Finished	Jul 19 06:58:29 PM PDT 24
Peak memory	611936 kb
Host	smart-1dc5a854-bc99-4015-aea3-1ec37ca2ff19
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005980584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1005980584
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2968230896
Short name	T605
Test name
Test status
Simulation time	5207476940 ps
CPU time	559.28 seconds
Started	Jul 19 06:48:18 PM PDT 24
Finished	Jul 19 06:57:38 PM PDT 24
Peak memory	614044 kb
Host	smart-97d798e6-79db-4c25-8ca2-b86eef093b75
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968230896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2968230896
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2808697127
Short name	T60
Test name
Test status
Simulation time	4439482684 ps
CPU time	603.91 seconds
Started	Jul 19 06:47:07 PM PDT 24
Finished	Jul 19 06:57:12 PM PDT 24
Peak memory	612812 kb
Host	smart-45b492d2-cf72-4be6-8cd1-99e7c53ad971
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808697127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2808697127
Directory	/workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3385992668
Short name	T770
Test name
Test status
Simulation time	3151855190 ps
CPU time	297.98 seconds
Started	Jul 19 06:47:03 PM PDT 24
Finished	Jul 19 06:52:02 PM PDT 24
Peak memory	609256 kb
Host	smart-7a3aac9a-813a-4c75-8606-67401a1c0379
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385992668 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3385992668
Directory	/workspace/1.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2639569102
Short name	T697
Test name
Test status
Simulation time	2906466564 ps
CPU time	417.67 seconds
Started	Jul 19 06:48:38 PM PDT 24
Finished	Jul 19 06:55:36 PM PDT 24
Peak memory	609376 kb
Host	smart-cf5df618-6ab5-4b6f-93cd-ecde47b4b83f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639569102 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.2639569102
Directory	/workspace/1.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.4018007098
Short name	T578
Test name
Test status
Simulation time	2210290555 ps
CPU time	205.42 seconds
Started	Jul 19 06:53:21 PM PDT 24
Finished	Jul 19 06:56:48 PM PDT 24
Peak memory	609700 kb
Host	smart-95830be3-aa3b-4047-bab7-c3f06ba3a68e
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018007098 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.4018007098
Directory	/workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3578778704
Short name	T584
Test name
Test status
Simulation time	4095450800 ps
CPU time	436.43 seconds
Started	Jul 19 06:48:07 PM PDT 24
Finished	Jul 19 06:55:24 PM PDT 24
Peak memory	609948 kb
Host	smart-a5c3a68d-64c9-4064-9f32-32f98c2f3cea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578778704 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3578778704
Directory	/workspace/1.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1017618966
Short name	T858
Test name
Test status
Simulation time	5541075144 ps
CPU time	453.51 seconds
Started	Jul 19 06:47:33 PM PDT 24
Finished	Jul 19 06:55:07 PM PDT 24
Peak memory	610396 kb
Host	smart-f576c662-039a-4881-858d-391bd112b93d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017618966 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1017618966
Directory	/workspace/1.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2332918741
Short name	T560
Test name
Test status
Simulation time	4751183750 ps
CPU time	470.71 seconds
Started	Jul 19 06:47:37 PM PDT 24
Finished	Jul 19 06:55:28 PM PDT 24
Peak memory	610380 kb
Host	smart-60f41d32-fe43-4be2-8304-417aaa26a06d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332918741 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2332918741
Directory	/workspace/1.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4115854680
Short name	T772
Test name
Test status
Simulation time	4931454750 ps
CPU time	369.02 seconds
Started	Jul 19 06:46:26 PM PDT 24
Finished	Jul 19 06:52:36 PM PDT 24
Peak memory	609364 kb
Host	smart-b17f17f4-6970-425e-83b1-c43cf281f30c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115854680 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4115854680
Directory	/workspace/1.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1267100493
Short name	T155
Test name
Test status
Simulation time	9577121826 ps
CPU time	1552.83 seconds
Started	Jul 19 06:46:53 PM PDT 24
Finished	Jul 19 07:12:47 PM PDT 24
Peak memory	610356 kb
Host	smart-078a27ef-f199-471e-9ab4-29aaf3b1d80a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267100493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1267100493
Directory	/workspace/1.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.982970120
Short name	T473
Test name
Test status
Simulation time	2852669256 ps
CPU time	421.33 seconds
Started	Jul 19 06:48:09 PM PDT 24
Finished	Jul 19 06:55:11 PM PDT 24
Peak memory	609716 kb
Host	smart-10f99547-995a-4457-b24b-3a20ea3a93fa
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982970120 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.982970120
Directory	/workspace/1.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2985779893
Short name	T543
Test name
Test status
Simulation time	4640940960 ps
CPU time	641.83 seconds
Started	Jul 19 06:49:20 PM PDT 24
Finished	Jul 19 07:00:03 PM PDT 24
Peak memory	610188 kb
Host	smart-6e2ba8d4-3427-4f14-a19f-c121adb1e589
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985779893 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2985779893
Directory	/workspace/1.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3037868694
Short name	T728
Test name
Test status
Simulation time	3285877106 ps
CPU time	273.94 seconds
Started	Jul 19 06:51:41 PM PDT 24
Finished	Jul 19 06:56:16 PM PDT 24
Peak memory	609824 kb
Host	smart-e1e3db1d-cfe8-48fb-b0e7-bb160b4f1b1f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037868694 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.3037868694
Directory	/workspace/1.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4080611101
Short name	T842
Test name
Test status
Simulation time	13611175928 ps
CPU time	3339 seconds
Started	Jul 19 06:44:33 PM PDT 24
Finished	Jul 19 07:40:13 PM PDT 24
Peak memory	610256 kb
Host	smart-af8f5ebe-26dd-4d84-a520-95f2dcab8def
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080611101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.4080611101
Directory	/workspace/1.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.339189858
Short name	T194
Test name
Test status
Simulation time	4772157072 ps
CPU time	526.35 seconds
Started	Jul 19 06:45:24 PM PDT 24
Finished	Jul 19 06:54:11 PM PDT 24
Peak memory	609684 kb
Host	smart-bc8beb86-b3e9-4cb1-a166-8fe7570f7051
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918 9858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.339189858
Directory	/workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1567349305
Short name	T662
Test name
Test status
Simulation time	2766760104 ps
CPU time	298.54 seconds
Started	Jul 19 06:47:42 PM PDT 24
Finished	Jul 19 06:52:41 PM PDT 24
Peak memory	609276 kb
Host	smart-4e478da1-3635-4db6-84ec-f5cfd536e3c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567349305 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.1567349305
Directory	/workspace/1.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1855740306
Short name	T220
Test name
Test status
Simulation time	6200344720 ps
CPU time	689.58 seconds
Started	Jul 19 06:48:39 PM PDT 24
Finished	Jul 19 07:00:09 PM PDT 24
Peak memory	610536 kb
Host	smart-5b754f03-4982-4bc1-956f-c6f4c0c4e0d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855740306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1855740306
Directory	/workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2553368872
Short name	T570
Test name
Test status
Simulation time	2497936362 ps
CPU time	180.33 seconds
Started	Jul 19 06:51:33 PM PDT 24
Finished	Jul 19 06:54:34 PM PDT 24
Peak memory	609784 kb
Host	smart-bed5026e-1831-4cda-aab4-5d05501c8170
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553368872 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2553368872
Directory	/workspace/1.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_auto_mode.878521765
Short name	T771
Test name
Test status
Simulation time	5202343860 ps
CPU time	1268.42 seconds
Started	Jul 19 06:45:13 PM PDT 24
Finished	Jul 19 07:06:22 PM PDT 24
Peak memory	610316 kb
Host	smart-b49d29df-beb3-42c6-8619-7f82100432bc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878521765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_a uto_mode.878521765
Directory	/workspace/1.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_boot_mode.928334479
Short name	T81
Test name
Test status
Simulation time	3058648840 ps
CPU time	722.52 seconds
Started	Jul 19 06:44:40 PM PDT 24
Finished	Jul 19 06:56:43 PM PDT 24
Peak memory	609888 kb
Host	smart-922fd561-27ee-4d3a-ab39-d7875346c4a3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928334479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_b oot_mode.928334479
Directory	/workspace/1.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2847200197
Short name	T88
Test name
Test status
Simulation time	7190389699 ps
CPU time	1251.14 seconds
Started	Jul 19 06:47:03 PM PDT 24
Finished	Jul 19 07:07:55 PM PDT 24
Peak memory	610524 kb
Host	smart-85b18601-c95b-45d4-8b0f-f97cc044c15d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847200197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.2847200197
Directory	/workspace/1.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_kat.3137254178
Short name	T965
Test name
Test status
Simulation time	3324400888 ps
CPU time	663.95 seconds
Started	Jul 19 06:45:53 PM PDT 24
Finished	Jul 19 06:56:58 PM PDT 24
Peak memory	616284 kb
Host	smart-8e9d0045-4591-433c-98bd-433477ec3e1e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137254178 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3137254178
Directory	/workspace/1.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1347472814
Short name	T643
Test name
Test status
Simulation time	6577911976 ps
CPU time	1547.78 seconds
Started	Jul 19 06:45:21 PM PDT 24
Finished	Jul 19 07:11:10 PM PDT 24
Peak memory	609292 kb
Host	smart-1122cf38-2f17-4fec-a51b-c25f56a837ef
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347472814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1347472814
Directory	/workspace/1.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2585584667
Short name	T307
Test name
Test status
Simulation time	2810799806 ps
CPU time	257.95 seconds
Started	Jul 19 06:46:14 PM PDT 24
Finished	Jul 19 06:50:32 PM PDT 24
Peak memory	609340 kb
Host	smart-b7d0e85c-b585-4378-bf61-eacb38a1aecf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 85584667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2585584667
Directory	/workspace/1.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3585022554
Short name	T380
Test name
Test status
Simulation time	5620397120 ps
CPU time	1449.01 seconds
Started	Jul 19 06:44:04 PM PDT 24
Finished	Jul 19 07:08:14 PM PDT 24
Peak memory	610176 kb
Host	smart-3b6a0986-67f3-4d46-8435-721bcc135aa9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3585022554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3585022554
Directory	/workspace/1.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3139474544
Short name	T574
Test name
Test status
Simulation time	3271456556 ps
CPU time	291.06 seconds
Started	Jul 19 06:45:13 PM PDT 24
Finished	Jul 19 06:50:05 PM PDT 24
Peak memory	609780 kb
Host	smart-dbde6a91-49e8-498c-aa1f-926afe19d170
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139474544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3139474544
Directory	/workspace/1.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3894864421
Short name	T547
Test name
Test status
Simulation time	3240443670 ps
CPU time	433.16 seconds
Started	Jul 19 06:51:47 PM PDT 24
Finished	Jul 19 06:59:01 PM PDT 24
Peak memory	609780 kb
Host	smart-093a8ace-0ce3-45d7-97d6-3b1fabc57b61
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3894864421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.3894864421
Directory	/workspace/1.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_example_concurrency.2897595198
Short name	T629
Test name
Test status
Simulation time	2385386344 ps
CPU time	178.04 seconds
Started	Jul 19 06:40:52 PM PDT 24
Finished	Jul 19 06:43:51 PM PDT 24
Peak memory	609716 kb
Host	smart-fe207229-3d95-4807-8196-a4f1298d67f9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897595198 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.2897595198
Directory	/workspace/1.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/1.chip_sw_example_flash.4134881436
Short name	T139
Test name
Test status
Simulation time	2945136430 ps
CPU time	169.1 seconds
Started	Jul 19 06:41:03 PM PDT 24
Finished	Jul 19 06:43:53 PM PDT 24
Peak memory	609548 kb
Host	smart-c62db15a-3728-48f7-b51f-fbffb0107925
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134881436 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.4134881436
Directory	/workspace/1.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/1.chip_sw_example_manufacturer.2379760428
Short name	T709
Test name
Test status
Simulation time	2276604028 ps
CPU time	267.21 seconds
Started	Jul 19 06:43:58 PM PDT 24
Finished	Jul 19 06:48:26 PM PDT 24
Peak memory	609232 kb
Host	smart-de3d5cb0-8397-48aa-ac34-df25f07776e7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379760428 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2379760428
Directory	/workspace/1.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/1.chip_sw_example_rom.4131123801
Short name	T622
Test name
Test status
Simulation time	2189727016 ps
CPU time	112.42 seconds
Started	Jul 19 06:46:24 PM PDT 24
Finished	Jul 19 06:48:16 PM PDT 24
Peak memory	610076 kb
Host	smart-0ce059cb-6fcf-4dc3-a84b-ea45a3efae5e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131123801 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.4131123801
Directory	/workspace/1.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2504993049
Short name	T424
Test name
Test status
Simulation time	5836944040 ps
CPU time	749.39 seconds
Started	Jul 19 06:54:09 PM PDT 24
Finished	Jul 19 07:07:34 PM PDT 24
Peak memory	611072 kb
Host	smart-39645dc0-cd55-4df4-8689-b0ba30e487ce
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2504993049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2504993049
Directory	/workspace/1.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.884611865
Short name	T579
Test name
Test status
Simulation time	5404984106 ps
CPU time	884.57 seconds
Started	Jul 19 06:44:53 PM PDT 24
Finished	Jul 19 06:59:38 PM PDT 24
Peak memory	609352 kb
Host	smart-308ef39d-4522-4bfe-a1df-25dbff57a848
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884611865 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_flash_ctrl_access.884611865
Directory	/workspace/1.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.335668190
Short name	T782
Test name
Test status
Simulation time	5691761153 ps
CPU time	1000.12 seconds
Started	Jul 19 06:43:29 PM PDT 24
Finished	Jul 19 07:00:09 PM PDT 24
Peak memory	609336 kb
Host	smart-86a8cf49-d203-4590-bcc8-2755691e1a98
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335668190 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.335668190
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1528634102
Short name	T711
Test name
Test status
Simulation time	7848611638 ps
CPU time	1256.08 seconds
Started	Jul 19 06:50:00 PM PDT 24
Finished	Jul 19 07:10:57 PM PDT 24
Peak memory	609264 kb
Host	smart-b6aaffca-c3a0-4c5b-842d-69537c5e16b7
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528634102 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1528634102
Directory	/workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1784373603
Short name	T592
Test name
Test status
Simulation time	5670737482 ps
CPU time	1074.8 seconds
Started	Jul 19 06:41:50 PM PDT 24
Finished	Jul 19 06:59:46 PM PDT 24
Peak memory	609836 kb
Host	smart-2522232a-e58c-436c-b327-88645bf5c98e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784373603 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1784373603
Directory	/workspace/1.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4086365900
Short name	T990
Test name
Test status
Simulation time	3824340568 ps
CPU time	550.46 seconds
Started	Jul 19 06:43:48 PM PDT 24
Finished	Jul 19 06:52:59 PM PDT 24
Peak memory	609580 kb
Host	smart-d64048ac-ee73-4c14-8f22-69c7fe573b53
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086365900 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.4086365900
Directory	/workspace/1.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.4108331050
Short name	T854
Test name
Test status
Simulation time	5553656128 ps
CPU time	1369.05 seconds
Started	Jul 19 06:51:27 PM PDT 24
Finished	Jul 19 07:14:18 PM PDT 24
Peak memory	609380 kb
Host	smart-0f583744-5e09-4dd3-a788-c9d99b1b0503
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108331050 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.4108331050
Directory	/workspace/1.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1287159255
Short name	T742
Test name
Test status
Simulation time	4170643630 ps
CPU time	763.85 seconds
Started	Jul 19 06:45:11 PM PDT 24
Finished	Jul 19 06:57:56 PM PDT 24
Peak memory	609924 kb
Host	smart-7606202f-547c-4578-9dc2-a90b6983a3be
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287159255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1287159255
Directory	/workspace/1.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2448519968
Short name	T744
Test name
Test status
Simulation time	4089800197 ps
CPU time	712.78 seconds
Started	Jul 19 06:42:56 PM PDT 24
Finished	Jul 19 06:54:50 PM PDT 24
Peak memory	609272 kb
Host	smart-70dc5796-7055-4aca-aff1-3d44751f4383
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2448519968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.2448519968
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.340694816
Short name	T387
Test name
Test status
Simulation time	4783606881 ps
CPU time	697.39 seconds
Started	Jul 19 06:50:34 PM PDT 24
Finished	Jul 19 07:02:12 PM PDT 24
Peak memory	610176 kb
Host	smart-cb8f2db6-95df-4d2d-b07e-48306eeeb4e6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=340694816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.340694816
Directory	/workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1431097363
Short name	T627
Test name
Test status
Simulation time	3440941092 ps
CPU time	471.82 seconds
Started	Jul 19 06:53:07 PM PDT 24
Finished	Jul 19 07:00:59 PM PDT 24
Peak memory	609424 kb
Host	smart-a5c38f4f-597b-48af-bb6d-a337d45716fa
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431097 363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1431097363
Directory	/workspace/1.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3868826360
Short name	T339
Test name
Test status
Simulation time	25555905757 ps
CPU time	1960.53 seconds
Started	Jul 19 06:50:09 PM PDT 24
Finished	Jul 19 07:22:50 PM PDT 24
Peak memory	612232 kb
Host	smart-cfd803cd-7870-4c82-b5fd-5892997bd8c8
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3868826360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.3868826360
Directory	/workspace/1.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.360407870
Short name	T749
Test name
Test status
Simulation time	2749964472 ps
CPU time	172.91 seconds
Started	Jul 19 06:57:43 PM PDT 24
Finished	Jul 19 07:00:37 PM PDT 24
Peak memory	609756 kb
Host	smart-02e81de6-5155-408c-823a-628f048c98f4
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=360407870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.360407870
Directory	/workspace/1.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3360168530
Short name	T928
Test name
Test status
Simulation time	3057324781 ps
CPU time	233.45 seconds
Started	Jul 19 06:52:21 PM PDT 24
Finished	Jul 19 06:56:15 PM PDT 24
Peak memory	609956 kb
Host	smart-dc9cec0a-7a57-460e-bda3-8d9c5cdb2231
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360168530 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.3360168530
Directory	/workspace/1.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc.2365292490
Short name	T710
Test name
Test status
Simulation time	3215253660 ps
CPU time	206.63 seconds
Started	Jul 19 06:50:01 PM PDT 24
Finished	Jul 19 06:53:28 PM PDT 24
Peak memory	609264 kb
Host	smart-f351ed21-9945-4cf7-aade-b85e0b3942f6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365292490 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2365292490
Directory	/workspace/1.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3706367907
Short name	T244
Test name
Test status
Simulation time	2330444711 ps
CPU time	225.14 seconds
Started	Jul 19 06:49:17 PM PDT 24
Finished	Jul 19 06:53:04 PM PDT 24
Peak memory	609368 kb
Host	smart-93268ed8-8a68-4d64-a762-e8aeaa73b2e3
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706367907 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.3706367907
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1765193508
Short name	T921
Test name
Test status
Simulation time	3403757135 ps
CPU time	340.51 seconds
Started	Jul 19 06:51:00 PM PDT 24
Finished	Jul 19 06:56:42 PM PDT 24
Peak memory	609720 kb
Host	smart-6fe4c79b-abec-47e2-b557-a4c251a326ef
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765193508 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.1765193508
Directory	/workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_multistream.4190528969
Short name	T755
Test name
Test status
Simulation time	7679224860 ps
CPU time	1939.92 seconds
Started	Jul 19 06:45:42 PM PDT 24
Finished	Jul 19 07:18:02 PM PDT 24
Peak memory	610012 kb
Host	smart-10afa97d-98b7-4f05-847f-fd56d0205ad4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190528969 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.4190528969
Directory	/workspace/1.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_oneshot.4176890479
Short name	T576
Test name
Test status
Simulation time	2986347688 ps
CPU time	276.97 seconds
Started	Jul 19 06:44:36 PM PDT 24
Finished	Jul 19 06:49:14 PM PDT 24
Peak memory	609832 kb
Host	smart-7063a8a2-35ab-4886-bb00-f9adda659fb6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176890479 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.4176890479
Directory	/workspace/1.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1658557677
Short name	T855
Test name
Test status
Simulation time	2672639710 ps
CPU time	306.81 seconds
Started	Jul 19 06:54:19 PM PDT 24
Finished	Jul 19 07:00:30 PM PDT 24
Peak memory	609288 kb
Host	smart-e3afc128-7274-4232-9720-70b2b8d51d0b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658557677 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1658557677
Directory	/workspace/1.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3389199857
Short name	T236
Test name
Test status
Simulation time	3968409752 ps
CPU time	518.13 seconds
Started	Jul 19 06:43:20 PM PDT 24
Finished	Jul 19 06:51:59 PM PDT 24
Peak memory	610644 kb
Host	smart-7106992e-4061-4bf2-ae3f-e1c07e750f07
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389199857 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.3389199857
Directory	/workspace/1.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.787662383
Short name	T237
Test name
Test status
Simulation time	5190203850 ps
CPU time	852.89 seconds
Started	Jul 19 06:41:37 PM PDT 24
Finished	Jul 19 06:55:51 PM PDT 24
Peak memory	609472 kb
Host	smart-35e734f7-bc30-4a4b-84d5-73a80267f3d3
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787662383 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.787662383
Directory	/workspace/1.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.917049426
Short name	T231
Test name
Test status
Simulation time	4800906624 ps
CPU time	835.71 seconds
Started	Jul 19 06:44:01 PM PDT 24
Finished	Jul 19 06:57:57 PM PDT 24
Peak memory	609336 kb
Host	smart-b1b2b85e-c7d3-475b-8f97-81309aa847a3
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917049426 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.917049426
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2139222005
Short name	T136
Test name
Test status
Simulation time	4955100116 ps
CPU time	809.65 seconds
Started	Jul 19 06:43:56 PM PDT 24
Finished	Jul 19 06:57:26 PM PDT 24
Peak memory	609528 kb
Host	smart-f35d3976-1ff5-4902-a5e6-6dcfabc2337c
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139222005 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2139222005
Directory	/workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2534713607
Short name	T797
Test name
Test status
Simulation time	64104539133 ps
CPU time	12300.4 seconds
Started	Jul 19 06:40:59 PM PDT 24
Finished	Jul 19 10:06:01 PM PDT 24
Peak memory	624748 kb
Host	smart-9c818ce8-9759-4060-ae13-6c69fb043e0b
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2534713607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.2534713607
Directory	/workspace/1.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3933646674
Short name	T730
Test name
Test status
Simulation time	11093637760 ps
CPU time	2757.9 seconds
Started	Jul 19 06:45:03 PM PDT 24
Finished	Jul 19 07:31:02 PM PDT 24
Peak memory	616636 kb
Host	smart-65739dba-8d6a-479f-87d0-c90eb663f4ba
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933 646674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3933646674
Directory	/workspace/1.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.876220114
Short name	T644
Test name
Test status
Simulation time	7263607984 ps
CPU time	940.42 seconds
Started	Jul 19 06:45:19 PM PDT 24
Finished	Jul 19 07:01:00 PM PDT 24
Peak memory	617748 kb
Host	smart-7f0dde73-040d-46f4-9959-f317817a53bd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=876220114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.876220114
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2671751737
Short name	T577
Test name
Test status
Simulation time	10725280843 ps
CPU time	1614.25 seconds
Started	Jul 19 06:50:19 PM PDT 24
Finished	Jul 19 07:17:14 PM PDT 24
Peak memory	617428 kb
Host	smart-ff308092-5fdc-4301-8592-14d4efe30802
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2671751737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2671751737
Directory	/workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.187137926
Short name	T898
Test name
Test status
Simulation time	11001416236 ps
CPU time	1787.57 seconds
Started	Jul 19 06:43:37 PM PDT 24
Finished	Jul 19 07:13:25 PM PDT 24
Peak memory	617672 kb
Host	smart-adaf6b85-ecd5-4d2a-87d1-d28fd31957fd
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=187137926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.187137926
Directory	/workspace/1.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1058659326
Short name	T332
Test name
Test status
Simulation time	11102744940 ps
CPU time	1936.23 seconds
Started	Jul 19 06:45:56 PM PDT 24
Finished	Jul 19 07:18:13 PM PDT 24
Peak memory	610764 kb
Host	smart-620610ef-feec-4228-8949-075429e78486
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105865 9326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1058659326
Directory	/workspace/1.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2973237808
Short name	T655
Test name
Test status
Simulation time	7823044060 ps
CPU time	1358.65 seconds
Started	Jul 19 06:45:38 PM PDT 24
Finished	Jul 19 07:08:17 PM PDT 24
Peak memory	609480 kb
Host	smart-045f2275-1978-42b9-8e8c-05d2f078039e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29732 37808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2973237808
Directory	/workspace/1.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.478664316
Short name	T336
Test name
Test status
Simulation time	16074124140 ps
CPU time	3322.64 seconds
Started	Jul 19 06:44:20 PM PDT 24
Finished	Jul 19 07:39:43 PM PDT 24
Peak memory	610456 kb
Host	smart-b768f7e1-8221-424e-81c0-7d41ec61ce6d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47866 4316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.478664316
Directory	/workspace/1.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_app_rom.3773969328
Short name	T974
Test name
Test status
Simulation time	3233213904 ps
CPU time	261.67 seconds
Started	Jul 19 06:46:33 PM PDT 24
Finished	Jul 19 06:50:55 PM PDT 24
Peak memory	609660 kb
Host	smart-2dd8383e-08ff-4150-91ff-247b38e85db8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773969328 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3773969328
Directory	/workspace/1.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_idle.1551894916
Short name	T687
Test name
Test status
Simulation time	2971119536 ps
CPU time	250.16 seconds
Started	Jul 19 06:47:39 PM PDT 24
Finished	Jul 19 06:51:49 PM PDT 24
Peak memory	609752 kb
Host	smart-4f17f201-6004-4d43-ad1e-dedc6d764a1f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551894916 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1551894916
Directory	/workspace/1.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.870711649
Short name	T722
Test name
Test status
Simulation time	2553323640 ps
CPU time	224.21 seconds
Started	Jul 19 06:49:14 PM PDT 24
Finished	Jul 19 06:52:59 PM PDT 24
Peak memory	609280 kb
Host	smart-b01fabd9-0e6b-4fcb-b73e-3894ccbf1a46
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870711649 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.870711649
Directory	/workspace/1.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.953125380
Short name	T956
Test name
Test status
Simulation time	2566071640 ps
CPU time	255.44 seconds
Started	Jul 19 06:46:07 PM PDT 24
Finished	Jul 19 06:50:22 PM PDT 24
Peak memory	609648 kb
Host	smart-1b35fcd5-b047-453d-b97c-e6a5c20dbdfd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953125380 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_kmac_mode_kmac.953125380
Directory	/workspace/1.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.151726048
Short name	T859
Test name
Test status
Simulation time	3465723886 ps
CPU time	417.39 seconds
Started	Jul 19 06:46:01 PM PDT 24
Finished	Jul 19 06:52:59 PM PDT 24
Peak memory	609564 kb
Host	smart-e746092e-3abf-48a2-9b94-daf1d6445da2
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151726048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.151726048
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3502584879
Short name	T551
Test name
Test status
Simulation time	3755735178 ps
CPU time	332.03 seconds
Started	Jul 19 06:50:46 PM PDT 24
Finished	Jul 19 06:56:18 PM PDT 24
Peak memory	609240 kb
Host	smart-a1fb5677-a4d3-4942-a4b1-92ff86b0fbf9
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35025848 79 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3502584879
Directory	/workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_kmac_smoketest.3494081963
Short name	T705
Test name
Test status
Simulation time	2733240554 ps
CPU time	257.2 seconds
Started	Jul 19 06:51:46 PM PDT 24
Finished	Jul 19 06:56:04 PM PDT 24
Peak memory	609808 kb
Host	smart-ee4e3c94-9542-4bdd-a9d0-2c334bb704fc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494081963 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3494081963
Directory	/workspace/1.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3002742520
Short name	T727
Test name
Test status
Simulation time	3210326000 ps
CPU time	366.65 seconds
Started	Jul 19 06:42:01 PM PDT 24
Finished	Jul 19 06:48:08 PM PDT 24
Peak memory	609596 kb
Host	smart-257e8f0a-3fb6-43d4-bcf8-6aa045769d76
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002742520 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3002742520
Directory	/workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3524725469
Short name	T179
Test name
Test status
Simulation time	5850792360 ps
CPU time	534.92 seconds
Started	Jul 19 06:48:15 PM PDT 24
Finished	Jul 19 06:57:10 PM PDT 24
Peak memory	610632 kb
Host	smart-e38175c1-97f6-40ba-8441-33ab10d7d6b2
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3524725469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.3524725469
Directory	/workspace/1.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1429417466
Short name	T186
Test name
Test status
Simulation time	2463050178 ps
CPU time	152.63 seconds
Started	Jul 19 06:41:19 PM PDT 24
Finished	Jul 19 06:43:52 PM PDT 24
Peak memory	620524 kb
Host	smart-0e2b31c9-6ab7-41b4-9539-1826ef9911e7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14294174 66 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1429417466
Directory	/workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2046693360
Short name	T950
Test name
Test status
Simulation time	6325812831 ps
CPU time	387.24 seconds
Started	Jul 19 06:41:22 PM PDT 24
Finished	Jul 19 06:47:50 PM PDT 24
Peak memory	624748 kb
Host	smart-db35ddf1-25f8-4c0a-afd2-3d67499142b4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046693360 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.2046693360
Directory	/workspace/1.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2087382251
Short name	T1008
Test name
Test status
Simulation time	2822598159 ps
CPU time	117.11 seconds
Started	Jul 19 06:42:36 PM PDT 24
Finished	Jul 19 06:44:33 PM PDT 24
Peak memory	615004 kb
Host	smart-834e69d7-6a99-4e34-a0c4-de81f62c2789
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2087382251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2087382251
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2437629740
Short name	T935
Test name
Test status
Simulation time	1980419833 ps
CPU time	100.74 seconds
Started	Jul 19 06:48:11 PM PDT 24
Finished	Jul 19 06:49:52 PM PDT 24
Peak memory	617740 kb
Host	smart-1e42c6a8-43d5-48f2-806f-d7e5e00bbffa
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437629740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2437629740
Directory	/workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3494268547
Short name	T800
Test name
Test status
Simulation time	49306175000 ps
CPU time	5781.42 seconds
Started	Jul 19 06:43:20 PM PDT 24
Finished	Jul 19 08:19:43 PM PDT 24
Peak memory	619504 kb
Host	smart-00c01b45-5e68-4917-a12b-bbb8c98d9165
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494268547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.3494268547
Directory	/workspace/1.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.779075508
Short name	T778
Test name
Test status
Simulation time	48702294881 ps
CPU time	6498.53 seconds
Started	Jul 19 06:42:48 PM PDT 24
Finished	Jul 19 08:31:08 PM PDT 24
Peak memory	620528 kb
Host	smart-5affecfc-58d4-4faf-bf03-10c9771e3310
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779075508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.779075508
Directory	/workspace/1.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3198021585
Short name	T775
Test name
Test status
Simulation time	8206751547 ps
CPU time	993.07 seconds
Started	Jul 19 06:41:15 PM PDT 24
Finished	Jul 19 06:57:48 PM PDT 24
Peak memory	619856 kb
Host	smart-a9ffc338-fbc4-4b1e-85d3-8080edad2319
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198021585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3198021585
Directory	/workspace/1.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3636605102
Short name	T917
Test name
Test status
Simulation time	45870552105 ps
CPU time	5649.57 seconds
Started	Jul 19 06:40:29 PM PDT 24
Finished	Jul 19 08:14:40 PM PDT 24
Peak memory	620208 kb
Host	smart-71e54ca2-7c26-4221-99ab-2b1d9be3c18a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636605102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.3636605102
Directory	/workspace/1.chip_sw_lc_walkthrough_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.122310309
Short name	T719
Test name
Test status
Simulation time	28387299088 ps
CPU time	2542.71 seconds
Started	Jul 19 06:41:49 PM PDT 24
Finished	Jul 19 07:24:12 PM PDT 24
Peak memory	620132 kb
Host	smart-10199c54-cf48-4e61-bd79-8308fb842cd5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=122310309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunl ocks.122310309
Directory	/workspace/1.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1781233470
Short name	T442
Test name
Test status
Simulation time	16611584876 ps
CPU time	4118.38 seconds
Started	Jul 19 06:44:24 PM PDT 24
Finished	Jul 19 07:53:03 PM PDT 24
Peak memory	610276 kb
Host	smart-53e5c60a-9cd9-4cef-beda-ebd95f89fbb3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1781233470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1781233470
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1470215537
Short name	T87
Test name
Test status
Simulation time	18091435938 ps
CPU time	4289.28 seconds
Started	Jul 19 06:43:13 PM PDT 24
Finished	Jul 19 07:54:43 PM PDT 24
Peak memory	610172 kb
Host	smart-36a2667f-a2d3-4de7-ba98-cba4d4fc9c4a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1470215537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1470215537
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2701945258
Short name	T400
Test name
Test status
Simulation time	25091460038 ps
CPU time	5165.21 seconds
Started	Jul 19 06:50:42 PM PDT 24
Finished	Jul 19 08:16:48 PM PDT 24
Peak memory	610096 kb
Host	smart-05a98592-c6b5-4769-9493-7b779493f8d2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701945258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2701945258
Directory	/workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3183971675
Short name	T311
Test name
Test status
Simulation time	3935987486 ps
CPU time	382.71 seconds
Started	Jul 19 06:44:08 PM PDT 24
Finished	Jul 19 06:50:31 PM PDT 24
Peak memory	609768 kb
Host	smart-7507f7fc-d017-4485-9008-1ac2bc75388c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183971675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3183971675
Directory	/workspace/1.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_randomness.3722468858
Short name	T695
Test name
Test status
Simulation time	5924245836 ps
CPU time	907.48 seconds
Started	Jul 19 06:46:19 PM PDT 24
Finished	Jul 19 07:01:27 PM PDT 24
Peak memory	609564 kb
Host	smart-b018f2d1-1cad-4bfd-a5b5-b51068b79649
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3722468858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3722468858
Directory	/workspace/1.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1250039553
Short name	T164
Test name
Test status
Simulation time	8154552900 ps
CPU time	2338.65 seconds
Started	Jul 19 06:52:52 PM PDT 24
Finished	Jul 19 07:31:51 PM PDT 24
Peak memory	610168 kb
Host	smart-b18d8dac-1aca-424a-abe3-35beab42fa7d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250039553 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1250039553
Directory	/workspace/1.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3866944663
Short name	T446
Test name
Test status
Simulation time	3075842331 ps
CPU time	315.17 seconds
Started	Jul 19 06:40:32 PM PDT 24
Finished	Jul 19 06:45:48 PM PDT 24
Peak memory	609988 kb
Host	smart-79cad9ce-7776-43db-97a0-4396027b73c7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866944663 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3866944663
Directory	/workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3370131840
Short name	T683
Test name
Test status
Simulation time	7357979000 ps
CPU time	1196.23 seconds
Started	Jul 19 06:40:49 PM PDT 24
Finished	Jul 19 07:00:47 PM PDT 24
Peak memory	610540 kb
Host	smart-9dbbd46b-5875-4ced-8fd5-e3494b3a2bf8
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3370131840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3370131840
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2646574234
Short name	T671
Test name
Test status
Simulation time	8106672668 ps
CPU time	1319.79 seconds
Started	Jul 19 06:43:12 PM PDT 24
Finished	Jul 19 07:05:12 PM PDT 24
Peak memory	610536 kb
Host	smart-e607eed4-6452-483a-b700-1f4683f4b804
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2646574234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2646574234
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3099435455
Short name	T940
Test name
Test status
Simulation time	6099855880 ps
CPU time	1102.28 seconds
Started	Jul 19 06:45:01 PM PDT 24
Finished	Jul 19 07:03:24 PM PDT 24
Peak memory	610528 kb
Host	smart-82e3d4b3-7437-4af4-8e81-c01de1352773
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3099435455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3099435455
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.345234173
Short name	T692
Test name
Test status
Simulation time	5098821276 ps
CPU time	757.26 seconds
Started	Jul 19 06:42:17 PM PDT 24
Finished	Jul 19 06:54:55 PM PDT 24
Peak memory	609276 kb
Host	smart-a55f3160-9f12-4abd-a160-8e3e37451898
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=345234173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.345234173
Directory	/workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4058076639
Short name	T672
Test name
Test status
Simulation time	2160109284 ps
CPU time	303.47 seconds
Started	Jul 19 06:51:46 PM PDT 24
Finished	Jul 19 06:56:50 PM PDT 24
Peak memory	609644 kb
Host	smart-81283e97-c076-4137-988c-8888d2900a5d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058076639 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.4058076639
Directory	/workspace/1.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pattgen_ios.1299291009
Short name	T391
Test name
Test status
Simulation time	3591071292 ps
CPU time	316.94 seconds
Started	Jul 19 06:40:29 PM PDT 24
Finished	Jul 19 06:45:47 PM PDT 24
Peak memory	610492 kb
Host	smart-75bfa69b-d6ca-4b57-a29b-0489ca3b4640
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299291009 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.1299291009
Directory	/workspace/1.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1124476363
Short name	T269
Test name
Test status
Simulation time	2261823316 ps
CPU time	208.11 seconds
Started	Jul 19 06:46:44 PM PDT 24
Finished	Jul 19 06:50:13 PM PDT 24
Peak memory	609680 kb
Host	smart-b780b228-fbd8-40f3-b422-c33f00d2fa66
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124476363 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1124476363
Directory	/workspace/1.chip_sw_plic_sw_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_power_idle_load.3242106766
Short name	T103
Test name
Test status
Simulation time	4203760960 ps
CPU time	584.22 seconds
Started	Jul 19 06:52:01 PM PDT 24
Finished	Jul 19 07:01:47 PM PDT 24
Peak memory	609776 kb
Host	smart-203c5114-cdbc-451b-9ae1-8097be89685b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242106766 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3242106766
Directory	/workspace/1.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2898979936
Short name	T377
Test name
Test status
Simulation time	9595750890 ps
CPU time	1298.28 seconds
Started	Jul 19 06:41:42 PM PDT 24
Finished	Jul 19 07:03:21 PM PDT 24
Peak memory	611040 kb
Host	smart-6d816b62-7d24-4880-9cbf-08756addbd16
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898 979936 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.2898979936
Directory	/workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.4255561249
Short name	T853
Test name
Test status
Simulation time	29055514467 ps
CPU time	2747.46 seconds
Started	Jul 19 06:46:38 PM PDT 24
Finished	Jul 19 07:32:26 PM PDT 24
Peak memory	610712 kb
Host	smart-2042dbe7-4c85-4cc0-99fd-bf39afd75b5b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425 5561249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.4255561249
Directory	/workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2328049669
Short name	T743
Test name
Test status
Simulation time	16832124069 ps
CPU time	1163.17 seconds
Started	Jul 19 06:43:49 PM PDT 24
Finished	Jul 19 07:03:13 PM PDT 24
Peak memory	611052 kb
Host	smart-8b3f6641-2ee2-4aea-b672-a0270755e4b1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2328049669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2328049669
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1603974090
Short name	T145
Test name
Test status
Simulation time	22342621080 ps
CPU time	1811.73 seconds
Started	Jul 19 06:49:12 PM PDT 24
Finished	Jul 19 07:19:25 PM PDT 24
Peak memory	610404 kb
Host	smart-b6ecd2fe-ff67-41a6-97f3-8b387f77392e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1603974090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1603974090
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2664336822
Short name	T364
Test name
Test status
Simulation time	8076297600 ps
CPU time	495.19 seconds
Started	Jul 19 06:43:23 PM PDT 24
Finished	Jul 19 06:51:39 PM PDT 24
Peak memory	610652 kb
Host	smart-a5c85670-1cad-442d-8f21-ea57f3062af1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664336822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2664336822
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1413730515
Short name	T680
Test name
Test status
Simulation time	7342380670 ps
CPU time	571.82 seconds
Started	Jul 19 06:43:21 PM PDT 24
Finished	Jul 19 06:52:53 PM PDT 24
Peak memory	616416 kb
Host	smart-7cf9e9b8-7f12-4d6b-9f85-387b6918d56e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1413730515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1413730515
Directory	/workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3507152012
Short name	T22
Test name
Test status
Simulation time	8686796664 ps
CPU time	493.98 seconds
Started	Jul 19 06:42:05 PM PDT 24
Finished	Jul 19 06:50:20 PM PDT 24
Peak memory	610624 kb
Host	smart-1f52ed73-2673-4801-b3f2-792afeeceb84
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507152012 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.3507152012
Directory	/workspace/1.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.655314061
Short name	T352
Test name
Test status
Simulation time	4301515615 ps
CPU time	259.44 seconds
Started	Jul 19 06:38:35 PM PDT 24
Finished	Jul 19 06:42:55 PM PDT 24
Peak memory	616152 kb
Host	smart-85ed0760-ae40-4903-b7f2-ad3b99cc7f22
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=655314061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.655314061
Directory	/workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2717565244
Short name	T795
Test name
Test status
Simulation time	11185106543 ps
CPU time	1369.71 seconds
Started	Jul 19 06:46:33 PM PDT 24
Finished	Jul 19 07:09:24 PM PDT 24
Peak memory	611288 kb
Host	smart-0aed95cc-5982-41f8-8d8e-a34f8a9d1ce7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717565244 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2717565244
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.640475782
Short name	T2
Test name
Test status
Simulation time	7848289088 ps
CPU time	444.74 seconds
Started	Jul 19 06:48:36 PM PDT 24
Finished	Jul 19 06:56:02 PM PDT 24
Peak memory	610196 kb
Host	smart-e6f59d90-c700-4685-b073-89fc2e89be0e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640475782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.640475782
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1337416783
Short name	T746
Test name
Test status
Simulation time	4983953357 ps
CPU time	555.61 seconds
Started	Jul 19 06:46:26 PM PDT 24
Finished	Jul 19 06:55:42 PM PDT 24
Peak memory	610664 kb
Host	smart-5d7899ea-cf70-4d9b-9d05-eee3c6525769
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337416783 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1337416783
Directory	/workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2933013328
Short name	T14
Test name
Test status
Simulation time	22744984266 ps
CPU time	1939.63 seconds
Started	Jul 19 06:48:57 PM PDT 24
Finished	Jul 19 07:21:17 PM PDT 24
Peak memory	610804 kb
Host	smart-e4435d5f-6a99-4562-b9ab-cf1a337e6c8e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2933013328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2933013328
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2260135385
Short name	T880
Test name
Test status
Simulation time	34030622400 ps
CPU time	2943.7 seconds
Started	Jul 19 06:46:07 PM PDT 24
Finished	Jul 19 07:35:11 PM PDT 24
Peak memory	612156 kb
Host	smart-71cc20b0-95e7-4471-8e16-d39200560f4b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260135385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2260135385
Directory	/workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3988290367
Short name	T411
Test name
Test status
Simulation time	5245867304 ps
CPU time	579.1 seconds
Started	Jul 19 06:49:14 PM PDT 24
Finished	Jul 19 06:58:54 PM PDT 24
Peak memory	610816 kb
Host	smart-8058e195-5089-4bbb-8fff-08c85355635d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3988290367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3988290367
Directory	/workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3888903076
Short name	T267
Test name
Test status
Simulation time	2941856680 ps
CPU time	259.15 seconds
Started	Jul 19 06:43:55 PM PDT 24
Finished	Jul 19 06:48:14 PM PDT 24
Peak memory	609664 kb
Host	smart-8f0297de-52ca-46c2-9c75-824e2f906b69
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888903076 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.3888903076
Directory	/workspace/1.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.35269295
Short name	T573
Test name
Test status
Simulation time	5526992492 ps
CPU time	322.25 seconds
Started	Jul 19 06:43:05 PM PDT 24
Finished	Jul 19 06:48:28 PM PDT 24
Peak memory	617224 kb
Host	smart-fdde2d1b-1c27-4497-b326-1c07a9be8085
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=35269295 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.35269295
Directory	/workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3471170706
Short name	T91
Test name
Test status
Simulation time	5303290840 ps
CPU time	403.48 seconds
Started	Jul 19 06:49:42 PM PDT 24
Finished	Jul 19 06:56:27 PM PDT 24
Peak memory	609292 kb
Host	smart-3a8862a1-f6d9-4196-97dd-43855a4d47be
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34711707 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3471170706
Directory	/workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1066232553
Short name	T986
Test name
Test status
Simulation time	5172822882 ps
CPU time	467.47 seconds
Started	Jul 19 06:48:57 PM PDT 24
Finished	Jul 19 06:56:45 PM PDT 24
Peak memory	610240 kb
Host	smart-cf0ebd76-54ce-48bc-af2c-7347aff02ba6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1066232553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.1066232553
Directory	/workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3859203623
Short name	T69
Test name
Test status
Simulation time	5826888130 ps
CPU time	529.47 seconds
Started	Jul 19 06:53:07 PM PDT 24
Finished	Jul 19 07:01:58 PM PDT 24
Peak memory	610332 kb
Host	smart-c1b78162-c13e-4150-854b-062de2cd9dc4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859203623 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.3859203623
Directory	/workspace/1.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4266453171
Short name	T316
Test name
Test status
Simulation time	6575219865 ps
CPU time	1203.86 seconds
Started	Jul 19 06:41:23 PM PDT 24
Finished	Jul 19 07:01:27 PM PDT 24
Peak memory	609524 kb
Host	smart-375e2ff1-6ffb-4198-9a9b-e69b91c59165
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266453171 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.4266453171
Directory	/workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.557758195
Short name	T882
Test name
Test status
Simulation time	5231517160 ps
CPU time	568.85 seconds
Started	Jul 19 06:42:22 PM PDT 24
Finished	Jul 19 06:51:52 PM PDT 24
Peak memory	610296 kb
Host	smart-c70ee694-fbf7-4ca8-97b6-607a81022fbc
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557758195 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.557758195
Directory	/workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.661316922
Short name	T809
Test name
Test status
Simulation time	5073566844 ps
CPU time	413.66 seconds
Started	Jul 19 06:51:54 PM PDT 24
Finished	Jul 19 06:58:48 PM PDT 24
Peak memory	610240 kb
Host	smart-fcd9d6bf-7014-4f41-97ae-61adcfdcd6c6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661316922 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.661316922
Directory	/workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1605813467
Short name	T620
Test name
Test status
Simulation time	4091598494 ps
CPU time	591.22 seconds
Started	Jul 19 06:42:04 PM PDT 24
Finished	Jul 19 06:51:56 PM PDT 24
Peak memory	609320 kb
Host	smart-12dc808c-9ad7-4b62-814c-fd85ec2e5c6e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160 5813467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1605813467
Directory	/workspace/1.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2598548865
Short name	T204
Test name
Test status
Simulation time	9055610542 ps
CPU time	529.63 seconds
Started	Jul 19 06:46:51 PM PDT 24
Finished	Jul 19 06:55:42 PM PDT 24
Peak memory	623792 kb
Host	smart-5f72bc5f-bcd9-4771-8ed6-99a231dab6a1
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598548865 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2598548865
Directory	/workspace/1.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3857451065
Short name	T161
Test name
Test status
Simulation time	14192862250 ps
CPU time	1903.43 seconds
Started	Jul 19 06:40:55 PM PDT 24
Finished	Jul 19 07:12:39 PM PDT 24
Peak memory	610744 kb
Host	smart-de60cd4b-9f38-4275-b59c-85eb91611a25
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3857451065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.3857451065
Directory	/workspace/1.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3069867509
Short name	T287
Test name
Test status
Simulation time	5886698400 ps
CPU time	702 seconds
Started	Jul 19 06:43:17 PM PDT 24
Finished	Jul 19 06:54:59 PM PDT 24
Peak memory	610072 kb
Host	smart-cee337de-0d7d-4d4b-adf6-35a18a6b1787
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069867509 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.3069867509
Directory	/workspace/1.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2165357736
Short name	T690
Test name
Test status
Simulation time	5955495566 ps
CPU time	678.22 seconds
Started	Jul 19 06:43:06 PM PDT 24
Finished	Jul 19 06:54:25 PM PDT 24
Peak memory	641244 kb
Host	smart-c4efd82e-5f8e-4fc9-ab57-804a9e1b4afa
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2165357736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2165357736
Directory	/workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2541650606
Short name	T562
Test name
Test status
Simulation time	2812776472 ps
CPU time	263.57 seconds
Started	Jul 19 06:53:11 PM PDT 24
Finished	Jul 19 06:57:35 PM PDT 24
Peak memory	609776 kb
Host	smart-b2dcdbb8-def9-4844-92bc-04d5d57bbe74
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541650606 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2541650606
Directory	/workspace/1.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2362361876
Short name	T819
Test name
Test status
Simulation time	3477508074 ps
CPU time	270.76 seconds
Started	Jul 19 06:41:26 PM PDT 24
Finished	Jul 19 06:45:58 PM PDT 24
Peak memory	609928 kb
Host	smart-261c849e-25a3-43a1-837a-38712606cb6d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362361876 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.2362361876
Directory	/workspace/1.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3684477307
Short name	T949
Test name
Test status
Simulation time	2885302520 ps
CPU time	225.98 seconds
Started	Jul 19 06:44:13 PM PDT 24
Finished	Jul 19 06:47:59 PM PDT 24
Peak memory	609656 kb
Host	smart-c04be5bd-42ac-4cad-8b18-d77b3ab6b928
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684477307 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3684477307
Directory	/workspace/1.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1518631848
Short name	T189
Test name
Test status
Simulation time	3072988194 ps
CPU time	283.91 seconds
Started	Jul 19 06:49:50 PM PDT 24
Finished	Jul 19 06:54:34 PM PDT 24
Peak memory	609296 kb
Host	smart-b9cd98d0-5e19-4b8c-ad00-9b65b11f4d5c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1518631848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1518631848
Directory	/workspace/1.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.443652110
Short name	T4
Test name
Test status
Simulation time	2827331225 ps
CPU time	273.65 seconds
Started	Jul 19 06:49:48 PM PDT 24
Finished	Jul 19 06:54:23 PM PDT 24
Peak memory	609260 kb
Host	smart-ad4b1b79-412a-43f8-8d70-902c3a7f1a92
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443652110 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.443652110
Directory	/workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.34921456
Short name	T303
Test name
Test status
Simulation time	4937078064 ps
CPU time	785.75 seconds
Started	Jul 19 06:45:55 PM PDT 24
Finished	Jul 19 06:59:01 PM PDT 24
Peak memory	609996 kb
Host	smart-9fb57916-bdb1-4d4f-b261-c3f26ff10052
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921 456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.34921456
Directory	/workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2990104482
Short name	T317
Test name
Test status
Simulation time	5445040022 ps
CPU time	1066.73 seconds
Started	Jul 19 06:43:25 PM PDT 24
Finished	Jul 19 07:01:12 PM PDT 24
Peak memory	609300 kb
Host	smart-5f8efd0c-ce9f-4d35-8e3c-bdbc8c1e8b14
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2990104482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2990104482
Directory	/workspace/1.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.398832125
Short name	T276
Test name
Test status
Simulation time	6498845980 ps
CPU time	640.57 seconds
Started	Jul 19 06:49:43 PM PDT 24
Finished	Jul 19 07:00:24 PM PDT 24
Peak memory	624088 kb
Host	smart-fe8b25fe-7243-4a77-bda3-a10bed19dde0
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398832125 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.398832125
Directory	/workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3979926160
Short name	T796
Test name
Test status
Simulation time	6919472640 ps
CPU time	489.01 seconds
Started	Jul 19 06:51:23 PM PDT 24
Finished	Jul 19 06:59:35 PM PDT 24
Peak memory	619312 kb
Host	smart-faa0a880-b3d1-48c5-924a-41030fa2a1b5
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979926160 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.3979926160
Directory	/workspace/1.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3880974196
Short name	T62
Test name
Test status
Simulation time	5033913794 ps
CPU time	584.07 seconds
Started	Jul 19 06:49:27 PM PDT 24
Finished	Jul 19 06:59:12 PM PDT 24
Peak memory	620148 kb
Host	smart-4b84ecbc-022f-4d1b-aee8-0e52743bf6b9
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388097 4196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3880974196
Directory	/workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.65428483
Short name	T130
Test name
Test status
Simulation time	2764412104 ps
CPU time	285.32 seconds
Started	Jul 19 06:52:20 PM PDT 24
Finished	Jul 19 06:57:07 PM PDT 24
Peak memory	609652 kb
Host	smart-60c21616-b686-46e5-adc7-e89ec045a3b2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65428483 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rv_plic_smoketest.65428483
Directory	/workspace/1.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_irq.4022769614
Short name	T785
Test name
Test status
Simulation time	2909752784 ps
CPU time	204.19 seconds
Started	Jul 19 06:47:23 PM PDT 24
Finished	Jul 19 06:50:48 PM PDT 24
Peak memory	609612 kb
Host	smart-c5a6caac-783f-496e-99f3-48b727c6dc1a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022769614 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.4022769614
Directory	/workspace/1.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.253759411
Short name	T284
Test name
Test status
Simulation time	3266021316 ps
CPU time	242.29 seconds
Started	Jul 19 06:52:47 PM PDT 24
Finished	Jul 19 06:56:49 PM PDT 24
Peak memory	609812 kb
Host	smart-b7fbb057-454d-4a6f-a899-c2a9b06695db
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253759411 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.253759411
Directory	/workspace/1.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2908158092
Short name	T94
Test name
Test status
Simulation time	8975009852 ps
CPU time	1236.57 seconds
Started	Jul 19 06:46:27 PM PDT 24
Finished	Jul 19 07:07:04 PM PDT 24
Peak memory	610320 kb
Host	smart-c060b649-9155-44d3-ad12-9085543547c4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29081580 92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.2908158092
Directory	/workspace/1.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3549104858
Short name	T66
Test name
Test status
Simulation time	3569405264 ps
CPU time	269.64 seconds
Started	Jul 19 06:50:23 PM PDT 24
Finished	Jul 19 06:54:53 PM PDT 24
Peak memory	610648 kb
Host	smart-e0865c37-975a-42f4-9bd2-555730c372ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549104 858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.3549104858
Directory	/workspace/1.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2177159147
Short name	T12
Test name
Test status
Simulation time	3050275452 ps
CPU time	218.43 seconds
Started	Jul 19 06:42:23 PM PDT 24
Finished	Jul 19 06:46:02 PM PDT 24
Peak memory	609752 kb
Host	smart-68111ad4-76ba-482b-bd5c-17ad46320811
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177159147 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2177159147
Directory	/workspace/1.chip_sw_sleep_pin_retention/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.826876293
Short name	T363
Test name
Test status
Simulation time	8691368556 ps
CPU time	1334.23 seconds
Started	Jul 19 06:45:06 PM PDT 24
Finished	Jul 19 07:07:21 PM PDT 24
Peak memory	610740 kb
Host	smart-8219409c-8172-4c0b-84c2-3dd87e704e89
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826876293 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.826876293
Directory	/workspace/1.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2164145497
Short name	T910
Test name
Test status
Simulation time	7190326990 ps
CPU time	791.06 seconds
Started	Jul 19 06:48:40 PM PDT 24
Finished	Jul 19 07:01:52 PM PDT 24
Peak memory	610484 kb
Host	smart-69f6ae4c-e540-4246-90e1-be4fd260456e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164145497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.2164145497
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1148143643
Short name	T666
Test name
Test status
Simulation time	7200626560 ps
CPU time	547.85 seconds
Started	Jul 19 06:47:25 PM PDT 24
Finished	Jul 19 06:56:33 PM PDT 24
Peak memory	610160 kb
Host	smart-3aad4016-2e43-4e90-9d2c-393ea749df64
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148143643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1148143643
Directory	/workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1508179040
Short name	T252
Test name
Test status
Simulation time	7201752056 ps
CPU time	822.26 seconds
Started	Jul 19 06:45:06 PM PDT 24
Finished	Jul 19 06:58:48 PM PDT 24
Peak memory	624936 kb
Host	smart-266c623f-ca12-4e22-af9a-52ee72a84fde
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508179040 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1508179040
Directory	/workspace/1.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3458436826
Short name	T113
Test name
Test status
Simulation time	4750063555 ps
CPU time	657.24 seconds
Started	Jul 19 06:40:49 PM PDT 24
Finished	Jul 19 06:51:47 PM PDT 24
Peak memory	624840 kb
Host	smart-ab0dc409-af83-4d1d-8d91-4f3f83ad3fee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458436826 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.3458436826
Directory	/workspace/1.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_device_tpm.692613251
Short name	T53
Test name
Test status
Simulation time	3638243905 ps
CPU time	402.36 seconds
Started	Jul 19 06:41:13 PM PDT 24
Finished	Jul 19 06:47:56 PM PDT 24
Peak memory	619376 kb
Host	smart-ad3e0022-ec52-47cf-9283-f4730fbb8916
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692613251 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.692613251
Directory	/workspace/1.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.556928584
Short name	T46
Test name
Test status
Simulation time	3109861894 ps
CPU time	260.5 seconds
Started	Jul 19 06:40:47 PM PDT 24
Finished	Jul 19 06:45:08 PM PDT 24
Peak memory	610136 kb
Host	smart-0f2e9e00-10b8-46fd-ac72-d028af9329d4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556928584 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.556928584
Directory	/workspace/1.chip_sw_spi_host_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4249232435
Short name	T225
Test name
Test status
Simulation time	7629268148 ps
CPU time	755.25 seconds
Started	Jul 19 06:46:14 PM PDT 24
Finished	Jul 19 06:58:50 PM PDT 24
Peak memory	610620 kb
Host	smart-933780fc-190f-4e72-b830-185b3d3e0910
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249232435 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.4249232435
Directory	/workspace/1.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3685577724
Short name	T188
Test name
Test status
Simulation time	4625627850 ps
CPU time	915.94 seconds
Started	Jul 19 06:48:43 PM PDT 24
Finished	Jul 19 07:04:00 PM PDT 24
Peak memory	609732 kb
Host	smart-9c38c784-e028-4d46-ae01-5cb2fdc2cf74
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685577724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3685577724
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3035310100
Short name	T77
Test name
Test status
Simulation time	4406402716 ps
CPU time	634.46 seconds
Started	Jul 19 06:45:55 PM PDT 24
Finished	Jul 19 06:56:30 PM PDT 24
Peak memory	610704 kb
Host	smart-679a89f8-1c2e-4801-a6f4-c7bc39178ce9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035310100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3035310100
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.680392353
Short name	T312
Test name
Test status
Simulation time	5346681446 ps
CPU time	640.96 seconds
Started	Jul 19 06:52:01 PM PDT 24
Finished	Jul 19 07:02:44 PM PDT 24
Peak memory	610648 kb
Host	smart-a37d400f-e2f0-4568-b196-977be62e4a65
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680392353 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.680392353
Directory	/workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4151628653
Short name	T353
Test name
Test status
Simulation time	2571656490 ps
CPU time	177.89 seconds
Started	Jul 19 06:51:48 PM PDT 24
Finished	Jul 19 06:54:47 PM PDT 24
Peak memory	609320 kb
Host	smart-651d5edc-bef5-4552-a9da-b5819e20a420
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151628653 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.4151628653
Directory	/workspace/1.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2733502597
Short name	T654
Test name
Test status
Simulation time	20522161811 ps
CPU time	3646.32 seconds
Started	Jul 19 06:47:46 PM PDT 24
Finished	Jul 19 07:48:33 PM PDT 24
Peak memory	609712 kb
Host	smart-a44d2c89-9a30-42f0-981f-af11440f86ba
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733502597 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2733502597
Directory	/workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.143924307
Short name	T152
Test name
Test status
Simulation time	4522532881 ps
CPU time	530.31 seconds
Started	Jul 19 06:40:27 PM PDT 24
Finished	Jul 19 06:49:19 PM PDT 24
Peak memory	613556 kb
Host	smart-42768d5c-e683-4f76-ba52-1b18191f30b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143924307 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.143924307
Directory	/workspace/1.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3683707702
Short name	T256
Test name
Test status
Simulation time	2869842739 ps
CPU time	252.43 seconds
Started	Jul 19 06:47:06 PM PDT 24
Finished	Jul 19 06:51:20 PM PDT 24
Peak memory	612908 kb
Host	smart-cf40e453-eaaf-43ea-9487-35cfa71da0a9
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683707702 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3683707702
Directory	/workspace/1.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1077635358
Short name	T35
Test name
Test status
Simulation time	2897224736 ps
CPU time	308.27 seconds
Started	Jul 19 06:41:22 PM PDT 24
Finished	Jul 19 06:46:32 PM PDT 24
Peak memory	609380 kb
Host	smart-7c6676f5-82b8-4bd6-b12f-33bbaf45d4f6
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077635358 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1077635358
Directory	/workspace/1.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.823998675
Short name	T1014
Test name
Test status
Simulation time	23078996000 ps
CPU time	1930.78 seconds
Started	Jul 19 06:43:44 PM PDT 24
Finished	Jul 19 07:15:56 PM PDT 24
Peak memory	613908 kb
Host	smart-4f587494-50bb-4cb2-b737-93e6234e5d2a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82399867 5 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.823998675
Directory	/workspace/1.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.462093681
Short name	T50
Test name
Test status
Simulation time	5773567944 ps
CPU time	307.58 seconds
Started	Jul 19 06:45:11 PM PDT 24
Finished	Jul 19 06:50:19 PM PDT 24
Peak memory	610360 kb
Host	smart-cc96db5c-a279-4fa8-8983-8196571890f7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462093681 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.462093681
Directory	/workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1671877835
Short name	T756
Test name
Test status
Simulation time	8448241304 ps
CPU time	1399.75 seconds
Started	Jul 19 06:45:13 PM PDT 24
Finished	Jul 19 07:08:33 PM PDT 24
Peak memory	619048 kb
Host	smart-fff89000-9b3d-4543-8fd0-4e7925001398
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1671877835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1671877835
Directory	/workspace/1.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_smoketest.3545043458
Short name	T611
Test name
Test status
Simulation time	2903991916 ps
CPU time	293.01 seconds
Started	Jul 19 06:52:45 PM PDT 24
Finished	Jul 19 06:57:39 PM PDT 24
Peak memory	616108 kb
Host	smart-7865f1ab-5678-43d0-952a-a43e8a5079ef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545043458 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.3545043458
Directory	/workspace/1.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx.242360458
Short name	T725
Test name
Test status
Simulation time	3803657442 ps
CPU time	578.94 seconds
Started	Jul 19 06:41:29 PM PDT 24
Finished	Jul 19 06:51:09 PM PDT 24
Peak memory	622516 kb
Host	smart-83be9497-98a0-4e03-9eb8-48fc84aa2ae4
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242360458 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.242360458
Directory	/workspace/1.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.609349874
Short name	T815
Test name
Test status
Simulation time	8131034145 ps
CPU time	1278.45 seconds
Started	Jul 19 06:45:24 PM PDT 24
Finished	Jul 19 07:06:43 PM PDT 24
Peak memory	623140 kb
Host	smart-fb06509e-0408-4f5f-b1fd-0b129b8c0d0c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609349874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.609349874
Directory	/workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1315344897
Short name	T112
Test name
Test status
Simulation time	78805872172 ps
CPU time	14310.3 seconds
Started	Jul 19 06:42:07 PM PDT 24
Finished	Jul 19 10:40:39 PM PDT 24
Peak memory	636056 kb
Host	smart-777924e0-cb8c-42c0-a4de-878c66a4972d
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1315344897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1315344897
Directory	/workspace/1.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1519709905
Short name	T640
Test name
Test status
Simulation time	4134672152 ps
CPU time	619.09 seconds
Started	Jul 19 06:43:39 PM PDT 24
Finished	Jul 19 06:53:59 PM PDT 24
Peak memory	622464 kb
Host	smart-1f7fab47-a22e-470d-af99-f84ffe3cc5a6
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519709905 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1519709905
Directory	/workspace/1.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.635626009
Short name	T102
Test name
Test status
Simulation time	4373012834 ps
CPU time	600.65 seconds
Started	Jul 19 06:48:05 PM PDT 24
Finished	Jul 19 06:58:06 PM PDT 24
Peak memory	623824 kb
Host	smart-ce0f91a8-f96c-4de8-b057-eac2bcb06afe
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635626009 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.635626009
Directory	/workspace/1.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.239509215
Short name	T31
Test name
Test status
Simulation time	5149218520 ps
CPU time	672.6 seconds
Started	Jul 19 06:41:20 PM PDT 24
Finished	Jul 19 06:52:33 PM PDT 24
Peak memory	624084 kb
Host	smart-c37a2cd4-1478-473e-b1c4-63ab520d11d1
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239509215 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.239509215
Directory	/workspace/1.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_prod.634418574
Short name	T125
Test name
Test status
Simulation time	10675211281 ps
CPU time	1103.04 seconds
Started	Jul 19 06:51:14 PM PDT 24
Finished	Jul 19 07:09:40 PM PDT 24
Peak memory	620904 kb
Host	smart-49e73bec-5794-45d6-9304-c6d30f2cf6f5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634418574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.634418574
Directory	/workspace/1.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_rma.1054873356
Short name	T583
Test name
Test status
Simulation time	3474802272 ps
CPU time	189.37 seconds
Started	Jul 19 06:48:51 PM PDT 24
Finished	Jul 19 06:52:01 PM PDT 24
Peak memory	620936 kb
Host	smart-d389edde-4518-4a37-aeb0-f519b4d7ddc2
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054873356 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.1054873356
Directory	/workspace/1.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/1.chip_tap_straps_testunlock0.2219092341
Short name	T101
Test name
Test status
Simulation time	5486882533 ps
CPU time	548.91 seconds
Started	Jul 19 06:50:41 PM PDT 24
Finished	Jul 19 06:59:52 PM PDT 24
Peak memory	620928 kb
Host	smart-0bd577a6-de80-4699-b33a-bf6252ad3c9f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219092341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2219092341
Directory	/workspace/1.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3259116574
Short name	T895
Test name
Test status
Simulation time	15949864109 ps
CPU time	4651.86 seconds
Started	Jul 19 07:03:33 PM PDT 24
Finished	Jul 19 08:21:06 PM PDT 24
Peak memory	610432 kb
Host	smart-b95f7e24-7d3a-48bc-b36c-0e4e44a81274
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259116574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.3259116574
Directory	/workspace/1.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod.2264817075
Short name	T638
Test name
Test status
Simulation time	15549383240 ps
CPU time	4454.3 seconds
Started	Jul 19 06:56:53 PM PDT 24
Finished	Jul 19 08:11:09 PM PDT 24
Peak memory	610328 kb
Host	smart-37f32181-ed88-44f2-a9b4-2d8a0f18f8e5
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264817075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2264817075
Directory	/workspace/1.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1338288186
Short name	T875
Test name
Test status
Simulation time	15220935789 ps
CPU time	4242.39 seconds
Started	Jul 19 06:57:45 PM PDT 24
Finished	Jul 19 08:08:28 PM PDT 24
Peak memory	610272 kb
Host	smart-a9760075-108b-453b-86ff-24c4c2e9e87f
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338288186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1338288186
Directory	/workspace/1.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_rma.1753776762
Short name	T739
Test name
Test status
Simulation time	14424913004 ps
CPU time	4195.08 seconds
Started	Jul 19 07:03:35 PM PDT 24
Finished	Jul 19 08:13:32 PM PDT 24
Peak memory	611676 kb
Host	smart-5f21ea50-18f0-47d6-8d2b-e248dfad8201
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753776762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1753776762
Directory	/workspace/1.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.638022901
Short name	T989
Test name
Test status
Simulation time	11572429030 ps
CPU time	2840.62 seconds
Started	Jul 19 06:58:07 PM PDT 24
Finished	Jul 19 07:45:29 PM PDT 24
Peak memory	610676 kb
Host	smart-7f6b23f6-cfbf-4649-baec-dcf05ff26114
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638022901 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.638022901
Directory	/workspace/1.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.757794204
Short name	T569
Test name
Test status
Simulation time	14693919036 ps
CPU time	4072.8 seconds
Started	Jul 19 06:56:42 PM PDT 24
Finished	Jul 19 08:04:35 PM PDT 24
Peak memory	610244 kb
Host	smart-457d8ad4-6c8b-4b94-8ecd-d3f0d99ad10f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757794204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.757794204
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1347589753
Short name	T790
Test name
Test status
Simulation time	14775096416 ps
CPU time	4331.28 seconds
Started	Jul 19 06:57:10 PM PDT 24
Finished	Jul 19 08:09:22 PM PDT 24
Peak memory	610172 kb
Host	smart-136f7186-cb31-40ea-93cd-e965dfcba113
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347589753 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1347589753
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1141621823
Short name	T945
Test name
Test status
Simulation time	15369071546 ps
CPU time	4064.16 seconds
Started	Jul 19 06:56:38 PM PDT 24
Finished	Jul 19 08:04:23 PM PDT 24
Peak memory	610028 kb
Host	smart-3dc98cf2-e43b-4788-94c9-332cdc833375
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141621823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.1141621823
Directory	/workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/1.rom_e2e_self_hash.1735332116
Short name	T913
Test name
Test status
Simulation time	25759472648 ps
CPU time	6299.44 seconds
Started	Jul 19 06:57:19 PM PDT 24
Finished	Jul 19 08:42:20 PM PDT 24
Peak memory	610108 kb
Host	smart-2293fdad-f678-4d15-ad7c-2091d2744626
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735332116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.1735332116
Directory	/workspace/1.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1547068100
Short name	T733
Test name
Test status
Simulation time	14348620888 ps
CPU time	4344.96 seconds
Started	Jul 19 06:57:16 PM PDT 24
Finished	Jul 19 08:09:41 PM PDT 24
Peak memory	610204 kb
Host	smart-5071fb1e-ceb9-42cb-a93e-0fd177238f83
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547068100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.1547068100
Directory	/workspace/1.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/1.rom_e2e_shutdown_output.3345586182
Short name	T757
Test name
Test status
Simulation time	22326835375 ps
CPU time	3818.18 seconds
Started	Jul 19 06:56:29 PM PDT 24
Finished	Jul 19 08:00:08 PM PDT 24
Peak memory	611332 kb
Host	smart-cb9b7fe0-4ab5-447a-8b4a-0e203b6e29c6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345586182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3345586182
Directory	/workspace/1.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/1.rom_e2e_smoke.6577281
Short name	T641
Test name
Test status
Simulation time	15235263736 ps
CPU time	4172.95 seconds
Started	Jul 19 06:57:23 PM PDT 24
Finished	Jul 19 08:06:57 PM PDT 24
Peak memory	609492 kb
Host	smart-7eb91efa-c730-401b-9468-4397a76a99e2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=6577281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.6577281
Directory	/workspace/1.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/1.rom_e2e_static_critical.383035431
Short name	T602
Test name
Test status
Simulation time	17291036456 ps
CPU time	4236.75 seconds
Started	Jul 19 07:03:22 PM PDT 24
Finished	Jul 19 08:14:00 PM PDT 24
Peak memory	610016 kb
Host	smart-09c4f4f9-dd80-4b9c-a553-5e3df6712242
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383035431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.383035431
Directory	/workspace/1.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/1.rom_keymgr_functest.1962668283
Short name	T1015
Test name
Test status
Simulation time	3959952790 ps
CPU time	384.81 seconds
Started	Jul 19 06:52:14 PM PDT 24
Finished	Jul 19 06:58:39 PM PDT 24
Peak memory	609256 kb
Host	smart-2d762822-8eb6-402e-bbe0-a443d0db7934
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962668283 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1962668283
Directory	/workspace/1.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/1.rom_raw_unlock.2159377866
Short name	T365
Test name
Test status
Simulation time	4556510935 ps
CPU time	291.9 seconds
Started	Jul 19 06:57:33 PM PDT 24
Finished	Jul 19 07:02:27 PM PDT 24
Peak memory	623884 kb
Host	smart-3a7cc2a6-1606-42eb-bb48-11657c6b6ba4
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2159377866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.2159377866
Directory	/workspace/1.rom_raw_unlock/latest

Test location	/workspace/coverage/default/1.rom_volatile_raw_unlock.984494545
Short name	T696
Test name
Test status
Simulation time	2226677872 ps
CPU time	114.44 seconds
Started	Jul 19 06:53:20 PM PDT 24
Finished	Jul 19 06:55:15 PM PDT 24
Peak memory	617712 kb
Host	smart-b24798d4-f33e-4386-9833-8c90f0374ecf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984494545 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.984494545
Directory	/workspace/1.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/10.chip_sw_all_escalation_resets.3407182240
Short name	T766
Test name
Test status
Simulation time	4338273720 ps
CPU time	559.3 seconds
Started	Jul 19 07:05:34 PM PDT 24
Finished	Jul 19 07:14:56 PM PDT 24
Peak memory	616800 kb
Host	smart-514f2a58-6458-4a5b-acac-f3fb4c06cc03
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3407182240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3407182240
Directory	/workspace/10.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3073831436
Short name	T105
Test name
Test status
Simulation time	7231751382 ps
CPU time	498.23 seconds
Started	Jul 19 07:05:01 PM PDT 24
Finished	Jul 19 07:13:21 PM PDT 24
Peak memory	621104 kb
Host	smart-69d510ed-4c0c-4222-8080-d697719e960f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073831436 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.3073831436
Directory	/workspace/10.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3767127106
Short name	T903
Test name
Test status
Simulation time	8544835250 ps
CPU time	1894.26 seconds
Started	Jul 19 07:05:06 PM PDT 24
Finished	Jul 19 07:36:42 PM PDT 24
Peak memory	618832 kb
Host	smart-5a507295-996f-4213-8d29-ffb39ca8e5dc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3767127106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3767127106
Directory	/workspace/10.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396679495
Short name	T416
Test name
Test status
Simulation time	3209630120 ps
CPU time	399.89 seconds
Started	Jul 19 07:06:53 PM PDT 24
Finished	Jul 19 07:13:34 PM PDT 24
Peak memory	648804 kb
Host	smart-ca31bc77-16d1-4a04-bf93-2fa91c2ca5c0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396679495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3396679495
Directory	/workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1966226289
Short name	T371
Test name
Test status
Simulation time	6469846151 ps
CPU time	421.88 seconds
Started	Jul 19 07:04:02 PM PDT 24
Finished	Jul 19 07:11:05 PM PDT 24
Peak memory	622368 kb
Host	smart-d56ca318-97da-4d84-a27b-a688f9f6d87e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966226289 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1966226289
Directory	/workspace/11.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.4119968429
Short name	T132
Test name
Test status
Simulation time	7906013014 ps
CPU time	1450.49 seconds
Started	Jul 19 07:06:42 PM PDT 24
Finished	Jul 19 07:30:54 PM PDT 24
Peak memory	618808 kb
Host	smart-23632c02-2d6e-4acb-b501-ac1767fafd38
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4119968429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.4119968429
Directory	/workspace/11.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1717240168
Short name	T812
Test name
Test status
Simulation time	7545988374 ps
CPU time	493.69 seconds
Started	Jul 19 07:06:55 PM PDT 24
Finished	Jul 19 07:15:10 PM PDT 24
Peak memory	624736 kb
Host	smart-8a198b89-36d2-4267-bd54-eeab08aafc25
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717240168 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.1717240168
Directory	/workspace/12.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.823798660
Short name	T808
Test name
Test status
Simulation time	8610965340 ps
CPU time	2039.05 seconds
Started	Jul 19 07:05:33 PM PDT 24
Finished	Jul 19 07:39:35 PM PDT 24
Peak memory	618836 kb
Host	smart-167a4b4d-145a-48e1-920b-65685cc93b93
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=823798660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.823798660
Directory	/workspace/12.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3830127858
Short name	T297
Test name
Test status
Simulation time	6714662106 ps
CPU time	406.12 seconds
Started	Jul 19 07:05:54 PM PDT 24
Finished	Jul 19 07:12:41 PM PDT 24
Peak memory	622328 kb
Host	smart-6ace276d-e2ac-4a5b-b3f3-3789538a2f31
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830127858 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3830127858
Directory	/workspace/13.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1103313948
Short name	T750
Test name
Test status
Simulation time	7629130400 ps
CPU time	1466.6 seconds
Started	Jul 19 07:07:01 PM PDT 24
Finished	Jul 19 07:31:29 PM PDT 24
Peak memory	618824 kb
Host	smart-fc7ebc3c-0e68-4e8d-ab29-aef74f64962f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1103313948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1103313948
Directory	/workspace/13.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3530398983
Short name	T645
Test name
Test status
Simulation time	8637999241 ps
CPU time	1052.19 seconds
Started	Jul 19 07:04:26 PM PDT 24
Finished	Jul 19 07:22:08 PM PDT 24
Peak memory	623016 kb
Host	smart-ba9ee0b1-d684-4fce-8b6b-458fa45593d0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530398983 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.3530398983
Directory	/workspace/14.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.1510092930
Short name	T805
Test name
Test status
Simulation time	12856240432 ps
CPU time	2673.96 seconds
Started	Jul 19 07:06:42 PM PDT 24
Finished	Jul 19 07:51:17 PM PDT 24
Peak memory	618448 kb
Host	smart-0759954a-775e-4812-bf5e-3dca7532312a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1510092930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.1510092930
Directory	/workspace/14.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.553228416
Short name	T980
Test name
Test status
Simulation time	4050569600 ps
CPU time	411.44 seconds
Started	Jul 19 07:07:21 PM PDT 24
Finished	Jul 19 07:14:18 PM PDT 24
Peak memory	648816 kb
Host	smart-e459139e-031b-4a3f-aa84-3b33d27b5bcd
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553228416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_s w_alert_handler_lpg_sleep_mode_alerts.553228416
Directory	/workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.997904542
Short name	T918
Test name
Test status
Simulation time	13173709640 ps
CPU time	2054.83 seconds
Started	Jul 19 07:04:48 PM PDT 24
Finished	Jul 19 07:39:06 PM PDT 24
Peak memory	618852 kb
Host	smart-48343800-cb43-4753-a142-9dba80888199
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=997904542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.997904542
Directory	/workspace/15.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1830578575
Short name	T901
Test name
Test status
Simulation time	8281886892 ps
CPU time	1463.36 seconds
Started	Jul 19 07:05:10 PM PDT 24
Finished	Jul 19 07:29:35 PM PDT 24
Peak memory	618836 kb
Host	smart-08ee554a-f195-4440-83bb-3330f570ecbb
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1830578575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1830578575
Directory	/workspace/16.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/17.chip_sw_all_escalation_resets.298336833
Short name	T418
Test name
Test status
Simulation time	5852278734 ps
CPU time	639 seconds
Started	Jul 19 07:08:12 PM PDT 24
Finished	Jul 19 07:18:54 PM PDT 24
Peak memory	649960 kb
Host	smart-0df18dea-67d5-4ba7-a4d7-f39050b5b1e2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 298336833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.298336833
Directory	/workspace/17.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2070632877
Short name	T694
Test name
Test status
Simulation time	4142852236 ps
CPU time	426.09 seconds
Started	Jul 19 07:05:45 PM PDT 24
Finished	Jul 19 07:12:52 PM PDT 24
Peak memory	617772 kb
Host	smart-f351221c-ee71-4184-b357-31862ee66c5f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2070632877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.2070632877
Directory	/workspace/17.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3535122787
Short name	T250
Test name
Test status
Simulation time	8844523914 ps
CPU time	1467.91 seconds
Started	Jul 19 07:04:59 PM PDT 24
Finished	Jul 19 07:29:29 PM PDT 24
Peak memory	618780 kb
Host	smart-6cc77b20-fa24-453f-aa9b-536cb50b58c1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3535122787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3535122787
Directory	/workspace/18.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1353810179
Short name	T635
Test name
Test status
Simulation time	4348952560 ps
CPU time	703.59 seconds
Started	Jul 19 07:05:33 PM PDT 24
Finished	Jul 19 07:17:19 PM PDT 24
Peak memory	618392 kb
Host	smart-f3532b7d-e732-4cc9-8194-e5bf6779d576
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1353810179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1353810179
Directory	/workspace/19.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_jtag_mem_access.559673313
Short name	T367
Test name
Test status
Simulation time	13855262600 ps
CPU time	1417.34 seconds
Started	Jul 19 06:51:24 PM PDT 24
Finished	Jul 19 07:15:04 PM PDT 24
Peak memory	607956 kb
Host	smart-6050c58c-553c-4f90-98b3-1034f6cde7ff
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559673313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.559673313
Directory	/workspace/2.chip_jtag_mem_access/latest

Test location	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.122660678
Short name	T355
Test name
Test status
Simulation time	4728655700 ps
CPU time	538.65 seconds
Started	Jul 19 07:01:24 PM PDT 24
Finished	Jul 19 07:10:25 PM PDT 24
Peak memory	618476 kb
Host	smart-fba48455-0b67-412f-a957-f63686da612f
User	root
Command	/workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 22660678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.122660678
Directory	/workspace/2.chip_rv_dm_ndm_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sival_flash_info_access.2707637861
Short name	T886
Test name
Test status
Simulation time	3009565362 ps
CPU time	260.87 seconds
Started	Jul 19 06:52:57 PM PDT 24
Finished	Jul 19 06:57:19 PM PDT 24
Peak memory	609220 kb
Host	smart-7bb34290-1484-4102-af2c-f4cf24373aac
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2707637861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2707637861
Directory	/workspace/2.chip_sival_flash_info_access/latest

Test location	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.384683167
Short name	T953
Test name
Test status
Simulation time	18917945388 ps
CPU time	676.18 seconds
Started	Jul 19 06:56:35 PM PDT 24
Finished	Jul 19 07:07:52 PM PDT 24
Peak memory	619188 kb
Host	smart-cc77091c-66f9-47ce-b06c-286300b8a223
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=384683167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.384683167
Directory	/workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc.1753787785
Short name	T966
Test name
Test status
Simulation time	3198632760 ps
CPU time	270.4 seconds
Started	Jul 19 06:55:35 PM PDT 24
Finished	Jul 19 07:00:36 PM PDT 24
Peak memory	609680 kb
Host	smart-b34a6380-70ab-415e-9702-6dbaf0bb552e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753787785 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1753787785
Directory	/workspace/2.chip_sw_aes_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2049335216
Short name	T879
Test name
Test status
Simulation time	2955734320 ps
CPU time	289.86 seconds
Started	Jul 19 06:57:13 PM PDT 24
Finished	Jul 19 07:02:04 PM PDT 24
Peak memory	609588 kb
Host	smart-7290acf9-986e-4f56-9932-a9498f2af37b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049 335216 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2049335216
Directory	/workspace/2.chip_sw_aes_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3636642330
Short name	T955
Test name
Test status
Simulation time	3049795226 ps
CPU time	294.9 seconds
Started	Jul 19 06:59:12 PM PDT 24
Finished	Jul 19 07:04:08 PM PDT 24
Peak memory	609716 kb
Host	smart-773c838b-3d3d-4a4b-8e0a-b2848d80b731
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636642330 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3636642330
Directory	/workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_entropy.1987901161
Short name	T131
Test name
Test status
Simulation time	2897905246 ps
CPU time	371.25 seconds
Started	Jul 19 06:56:11 PM PDT 24
Finished	Jul 19 07:02:24 PM PDT 24
Peak memory	609224 kb
Host	smart-7e979f1c-be7b-4b48-8412-b1224ea2a51f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987901161 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.1987901161
Directory	/workspace/2.chip_sw_aes_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_idle.3826403330
Short name	T976
Test name
Test status
Simulation time	2650900336 ps
CPU time	292.79 seconds
Started	Jul 19 06:57:56 PM PDT 24
Finished	Jul 19 07:02:50 PM PDT 24
Peak memory	609316 kb
Host	smart-637660fd-0d3f-48c0-aad4-a0443b4b9315
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826403330 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3826403330
Directory	/workspace/2.chip_sw_aes_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_masking_off.2191667145
Short name	T434
Test name
Test status
Simulation time	3033842780 ps
CPU time	252.58 seconds
Started	Jul 19 06:57:16 PM PDT 24
Finished	Jul 19 07:01:29 PM PDT 24
Peak memory	610280 kb
Host	smart-4f71012d-b5ba-443b-935e-094fce7ef899
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191667145 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.2191667145
Directory	/workspace/2.chip_sw_aes_masking_off/latest

Test location	/workspace/coverage/default/2.chip_sw_aes_smoketest.500040470
Short name	T321
Test name
Test status
Simulation time	3256947752 ps
CPU time	313.24 seconds
Started	Jul 19 07:01:59 PM PDT 24
Finished	Jul 19 07:07:13 PM PDT 24
Peak memory	609752 kb
Host	smart-6055eaf6-bb59-47a4-bf41-b8a2503bcc16
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500040470 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.500040470
Directory	/workspace/2.chip_sw_aes_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1757651100
Short name	T888
Test name
Test status
Simulation time	3738849362 ps
CPU time	372.22 seconds
Started	Jul 19 06:56:55 PM PDT 24
Finished	Jul 19 07:03:09 PM PDT 24
Peak memory	609472 kb
Host	smart-24e79675-ff10-4fe4-9b59-a8cc75c88510
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1757651100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.1757651100
Directory	/workspace/2.chip_sw_alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1078913571
Short name	T715
Test name
Test status
Simulation time	4604546608 ps
CPU time	579.21 seconds
Started	Jul 19 06:56:36 PM PDT 24
Finished	Jul 19 07:06:15 PM PDT 24
Peak memory	619404 kb
Host	smart-cd492ddc-c5d7-47c4-b28f-82df79fe90be
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1078913571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1078913571
Directory	/workspace/2.chip_sw_alert_handler_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1146570818
Short name	T870
Test name
Test status
Simulation time	7244978024 ps
CPU time	1884.17 seconds
Started	Jul 19 06:56:52 PM PDT 24
Finished	Jul 19 07:28:18 PM PDT 24
Peak memory	610240 kb
Host	smart-0cf4b58b-3aa8-414e-9485-6b2879997df9
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1146570818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1146570818
Directory	/workspace/2.chip_sw_alert_handler_lpg_clkoff/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2404250943
Short name	T1011
Test name
Test status
Simulation time	8347001256 ps
CPU time	1839.34 seconds
Started	Jul 19 06:58:07 PM PDT 24
Finished	Jul 19 07:28:48 PM PDT 24
Peak memory	609684 kb
Host	smart-c42d544e-08c6-4cb2-a01b-36722d249d6e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404250943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2404250943
Directory	/workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4177430575
Short name	T476
Test name
Test status
Simulation time	10975786832 ps
CPU time	1253.2 seconds
Started	Jul 19 07:00:09 PM PDT 24
Finished	Jul 19 07:21:03 PM PDT 24
Peak memory	610588 kb
Host	smart-b8a43b8a-3f6e-4863-98e3-53fffecf28be
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177430575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.4177430575
Directory	/workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2925808513
Short name	T894
Test name
Test status
Simulation time	7371242448 ps
CPU time	1245.14 seconds
Started	Jul 19 06:57:06 PM PDT 24
Finished	Jul 19 07:17:52 PM PDT 24
Peak memory	609348 kb
Host	smart-a9972b5e-b8eb-4b9b-9c94-eb3e8e505b5f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2925808513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2925808513
Directory	/workspace/2.chip_sw_alert_handler_ping_ok/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2419420246
Short name	T780
Test name
Test status
Simulation time	5234212784 ps
CPU time	613.73 seconds
Started	Jul 19 06:57:19 PM PDT 24
Finished	Jul 19 07:07:34 PM PDT 24
Peak memory	609916 kb
Host	smart-081dcce2-c038-4ff8-bbd4-5afd0de57385
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2419420246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.2419420246
Directory	/workspace/2.chip_sw_alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/2.chip_sw_alert_test.2147152339
Short name	T120
Test name
Test status
Simulation time	3338744752 ps
CPU time	349.1 seconds
Started	Jul 19 06:56:08 PM PDT 24
Finished	Jul 19 07:01:59 PM PDT 24
Peak memory	609572 kb
Host	smart-8b1519a3-3f71-46c8-bce2-835a1499be74
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147152339 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2147152339
Directory	/workspace/2.chip_sw_alert_test/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1536491107
Short name	T979
Test name
Test status
Simulation time	6291823220 ps
CPU time	515.71 seconds
Started	Jul 19 06:59:42 PM PDT 24
Finished	Jul 19 07:08:18 PM PDT 24
Peak memory	609348 kb
Host	smart-de08644f-0d19-466d-8daf-db36baf13be0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1536491107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1536491107
Directory	/workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1598690751
Short name	T754
Test name
Test status
Simulation time	3045415960 ps
CPU time	396.85 seconds
Started	Jul 19 07:02:06 PM PDT 24
Finished	Jul 19 07:08:43 PM PDT 24
Peak memory	609556 kb
Host	smart-28273740-f1ac-4e36-9727-6e4f4114f0ea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598690751 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.1598690751
Directory	/workspace/2.chip_sw_aon_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.502952637
Short name	T826
Test name
Test status
Simulation time	7779270614 ps
CPU time	789.97 seconds
Started	Jul 19 06:56:40 PM PDT 24
Finished	Jul 19 07:09:50 PM PDT 24
Peak memory	610284 kb
Host	smart-563d34c1-8ab4-4257-b9c8-bc294c828c6a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 502952637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.502952637
Directory	/workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1989836086
Short name	T698
Test name
Test status
Simulation time	5099421096 ps
CPU time	593.67 seconds
Started	Jul 19 06:55:42 PM PDT 24
Finished	Jul 19 07:06:00 PM PDT 24
Peak memory	609280 kb
Host	smart-7dd5d71d-7e16-4851-bdde-223e703730d0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =1989836086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.1989836086
Directory	/workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3813560427
Short name	T68
Test name
Test status
Simulation time	7197904200 ps
CPU time	1063.2 seconds
Started	Jul 19 07:01:58 PM PDT 24
Finished	Jul 19 07:19:42 PM PDT 24
Peak memory	617116 kb
Host	smart-a6210212-582a-4849-ba95-525e07753425
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813560427 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.3813560427
Directory	/workspace/2.chip_sw_ast_clk_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2599857358
Short name	T98
Test name
Test status
Simulation time	22248986769 ps
CPU time	3460.52 seconds
Started	Jul 19 07:01:20 PM PDT 24
Finished	Jul 19 07:59:04 PM PDT 24
Peak memory	610512 kb
Host	smart-e5dc40ab-4e3d-4a0b-99b3-8581aa4c8b03
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599857358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.2599857358
Directory	/workspace/2.chip_sw_ast_clk_rst_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.603496039
Short name	T631
Test name
Test status
Simulation time	5901334617 ps
CPU time	752.66 seconds
Started	Jul 19 06:59:50 PM PDT 24
Finished	Jul 19 07:12:25 PM PDT 24
Peak memory	623388 kb
Host	smart-8f6b0535-f1c6-4b7b-a9cd-e55c6bd72162
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=603496039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.603496039
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.935685258
Short name	T150
Test name
Test status
Simulation time	4186329336 ps
CPU time	503.87 seconds
Started	Jul 19 06:59:17 PM PDT 24
Finished	Jul 19 07:07:42 PM PDT 24
Peak memory	614028 kb
Host	smart-58e47dde-abb7-46d4-b1f8-d26a010c24de
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935685258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.935685258
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3826113661
Short name	T294
Test name
Test status
Simulation time	3473378232 ps
CPU time	642.9 seconds
Started	Jul 19 07:00:27 PM PDT 24
Finished	Jul 19 07:11:11 PM PDT 24
Peak memory	614032 kb
Host	smart-eee89744-617c-4f36-9a2f-47bb602ae563
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826113661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3826113661
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.910673499
Short name	T693
Test name
Test status
Simulation time	4069529504 ps
CPU time	508.7 seconds
Started	Jul 19 06:59:16 PM PDT 24
Finished	Jul 19 07:07:46 PM PDT 24
Peak memory	612716 kb
Host	smart-b6de5439-f1fc-43f8-8661-d425fc6b565f
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910673499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.910673499
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1921051942
Short name	T721
Test name
Test status
Simulation time	4991884032 ps
CPU time	687.98 seconds
Started	Jul 19 07:00:07 PM PDT 24
Finished	Jul 19 07:11:36 PM PDT 24
Peak memory	614096 kb
Host	smart-47bb0ce9-eefa-4d71-84f9-6d7edc0e9b3f
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921051942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1921051942
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.888227904
Short name	T59
Test name
Test status
Simulation time	4396509430 ps
CPU time	754.85 seconds
Started	Jul 19 07:02:55 PM PDT 24
Finished	Jul 19 07:15:31 PM PDT 24
Peak memory	614032 kb
Host	smart-bf1d6399-2c76-4990-9d48-4e155f339577
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888227904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.888227904
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1345536886
Short name	T836
Test name
Test status
Simulation time	4511202122 ps
CPU time	494.84 seconds
Started	Jul 19 06:59:15 PM PDT 24
Finished	Jul 19 07:07:31 PM PDT 24
Peak memory	612904 kb
Host	smart-97026295-8782-475d-a9c7-c9821cdf9783
User	root
Command	/workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345536886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1345536886
Directory	/workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.4091299429
Short name	T549
Test name
Test status
Simulation time	3246080595 ps
CPU time	302.56 seconds
Started	Jul 19 07:02:54 PM PDT 24
Finished	Jul 19 07:07:58 PM PDT 24
Peak memory	609260 kb
Host	smart-d6482c45-e526-44cd-9c88-dc86a849b302
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091299429 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.4091299429
Directory	/workspace/2.chip_sw_clkmgr_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.224385236
Short name	T585
Test name
Test status
Simulation time	3111425160 ps
CPU time	403.56 seconds
Started	Jul 19 07:02:48 PM PDT 24
Finished	Jul 19 07:09:33 PM PDT 24
Peak memory	609376 kb
Host	smart-99cbd1c5-6113-4b69-b760-43d3654bc111
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224385236 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.224385236
Directory	/workspace/2.chip_sw_clkmgr_jitter_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4070426666
Short name	T777
Test name
Test status
Simulation time	3215453464 ps
CPU time	278.72 seconds
Started	Jul 19 06:59:17 PM PDT 24
Finished	Jul 19 07:03:56 PM PDT 24
Peak memory	609716 kb
Host	smart-a4e4add2-bf47-4fc6-96bd-ca0da99c1982
User	root
Command	/workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070426666 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.4070426666
Directory	/workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3756283691
Short name	T1016
Test name
Test status
Simulation time	5402107816 ps
CPU time	536.24 seconds
Started	Jul 19 07:00:54 PM PDT 24
Finished	Jul 19 07:09:57 PM PDT 24
Peak memory	610404 kb
Host	smart-8d627d68-359a-4945-8622-7323e01d8ce0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756283691 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3756283691
Directory	/workspace/2.chip_sw_clkmgr_off_aes_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2531393603
Short name	T582
Test name
Test status
Simulation time	4454682750 ps
CPU time	546.61 seconds
Started	Jul 19 06:59:51 PM PDT 24
Finished	Jul 19 07:09:04 PM PDT 24
Peak memory	610060 kb
Host	smart-0e063ccd-00ca-4490-bbbb-227391c353de
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531393603 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2531393603
Directory	/workspace/2.chip_sw_clkmgr_off_hmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2231914868
Short name	T216
Test name
Test status
Simulation time	5196784720 ps
CPU time	499.09 seconds
Started	Jul 19 06:59:52 PM PDT 24
Finished	Jul 19 07:08:18 PM PDT 24
Peak memory	610264 kb
Host	smart-c4e0c425-7b0c-4733-8cab-5bf73a0da3f5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231914868 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2231914868
Directory	/workspace/2.chip_sw_clkmgr_off_kmac_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3620665229
Short name	T866
Test name
Test status
Simulation time	4850094020 ps
CPU time	489.12 seconds
Started	Jul 19 07:00:16 PM PDT 24
Finished	Jul 19 07:08:25 PM PDT 24
Peak memory	610252 kb
Host	smart-da3e309e-0a5d-4f71-8b3d-1f7130e379b4
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620665229 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3620665229
Directory	/workspace/2.chip_sw_clkmgr_off_otbn_trans/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.17635516
Short name	T162
Test name
Test status
Simulation time	13410408912 ps
CPU time	1434.84 seconds
Started	Jul 19 06:59:55 PM PDT 24
Finished	Jul 19 07:23:56 PM PDT 24
Peak memory	610472 kb
Host	smart-796225e8-fdd4-42be-9112-fa3296f8f99f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17635516 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.17635516
Directory	/workspace/2.chip_sw_clkmgr_off_peri/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1372448239
Short name	T138
Test name
Test status
Simulation time	3103828200 ps
CPU time	513.63 seconds
Started	Jul 19 07:01:47 PM PDT 24
Finished	Jul 19 07:10:22 PM PDT 24
Peak memory	609384 kb
Host	smart-bebf1a06-2e9c-496b-b8f1-36aa0565b1ee
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372448239 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1372448239
Directory	/workspace/2.chip_sw_clkmgr_reset_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2079634595
Short name	T857
Test name
Test status
Simulation time	4754621964 ps
CPU time	642.11 seconds
Started	Jul 19 06:58:05 PM PDT 24
Finished	Jul 19 07:08:47 PM PDT 24
Peak memory	610148 kb
Host	smart-113dd314-5ffb-4a8d-bfa4-29c603a4b4ac
User	root
Command	/workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079634595 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2079634595
Directory	/workspace/2.chip_sw_clkmgr_sleep_frequency/latest

Test location	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3472081122
Short name	T862
Test name
Test status
Simulation time	3116805320 ps
CPU time	249.04 seconds
Started	Jul 19 07:00:55 PM PDT 24
Finished	Jul 19 07:05:11 PM PDT 24
Peak memory	609764 kb
Host	smart-693ee3be-2d3d-4a8b-ac45-3cde43d9aaef
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472081122 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3472081122
Directory	/workspace/2.chip_sw_clkmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2650002812
Short name	T286
Test name
Test status
Simulation time	10867606212 ps
CPU time	2922.97 seconds
Started	Jul 19 06:57:02 PM PDT 24
Finished	Jul 19 07:45:46 PM PDT 24
Peak memory	610232 kb
Host	smart-8630049b-a707-4f6e-b4c9-17dd15216dfa
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650002812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.2650002812
Directory	/workspace/2.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.533018120
Short name	T84
Test name
Test status
Simulation time	16737973607 ps
CPU time	3314.13 seconds
Started	Jul 19 07:00:29 PM PDT 24
Finished	Jul 19 07:55:45 PM PDT 24
Peak memory	610096 kb
Host	smart-a682e66c-f110-49aa-b8ee-2d8390cbc30d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=533018120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.533018120
Directory	/workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1340813246
Short name	T196
Test name
Test status
Simulation time	4402028496 ps
CPU time	498.11 seconds
Started	Jul 19 06:57:08 PM PDT 24
Finished	Jul 19 07:05:27 PM PDT 24
Peak memory	610692 kb
Host	smart-fefdb7d3-08eb-4375-8f74-6cd3771b64ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13408 13246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1340813246
Directory	/workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_kat_test.3672233017
Short name	T649
Test name
Test status
Simulation time	2781414488 ps
CPU time	228.45 seconds
Started	Jul 19 06:58:14 PM PDT 24
Finished	Jul 19 07:02:03 PM PDT 24
Peak memory	609324 kb
Host	smart-9e90c000-cbd4-4f7b-bd91-0f359eef58a6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672233017 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.3672233017
Directory	/workspace/2.chip_sw_csrng_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.877778305
Short name	T912
Test name
Test status
Simulation time	6334629436 ps
CPU time	785.34 seconds
Started	Jul 19 06:57:30 PM PDT 24
Finished	Jul 19 07:10:36 PM PDT 24
Peak memory	610740 kb
Host	smart-9c1bf7ca-2cdc-4fb3-9fcd-78fef2d7b9fe
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877778305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrn g_lc_hw_debug_en_test.877778305
Directory	/workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest

Test location	/workspace/coverage/default/2.chip_sw_csrng_smoketest.3930880916
Short name	T893
Test name
Test status
Simulation time	2108761060 ps
CPU time	257.21 seconds
Started	Jul 19 07:00:24 PM PDT 24
Finished	Jul 19 07:04:43 PM PDT 24
Peak memory	609708 kb
Host	smart-2a4cbb4f-09a6-452d-bba3-6ab846ef07bb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930880916 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3930880916
Directory	/workspace/2.chip_sw_csrng_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_auto_mode.2370668948
Short name	T686
Test name
Test status
Simulation time	4661332286 ps
CPU time	1050.51 seconds
Started	Jul 19 06:56:53 PM PDT 24
Finished	Jul 19 07:14:25 PM PDT 24
Peak memory	610312 kb
Host	smart-9ae37bdc-42ba-43ea-a6f7-f567ebc23326
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370668948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2370668948
Directory	/workspace/2.chip_sw_edn_auto_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_boot_mode.3487692278
Short name	T436
Test name
Test status
Simulation time	2676757636 ps
CPU time	588.35 seconds
Started	Jul 19 06:56:47 PM PDT 24
Finished	Jul 19 07:06:37 PM PDT 24
Peak memory	609936 kb
Host	smart-61a71033-85f8-44d7-9248-8219607ffe7d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487692278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.3487692278
Directory	/workspace/2.chip_sw_edn_boot_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.871956431
Short name	T669
Test name
Test status
Simulation time	5272188468 ps
CPU time	802.13 seconds
Started	Jul 19 06:57:10 PM PDT 24
Finished	Jul 19 07:10:33 PM PDT 24
Peak memory	610496 kb
Host	smart-0c35daf2-c3f9-4bcb-a52d-46c20ee32bf6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=871956431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.871956431
Directory	/workspace/2.chip_sw_edn_entropy_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.921575548
Short name	T431
Test name
Test status
Simulation time	4993307281 ps
CPU time	902.75 seconds
Started	Jul 19 06:58:21 PM PDT 24
Finished	Jul 19 07:13:24 PM PDT 24
Peak memory	610772 kb
Host	smart-365cc218-8667-4c72-9167-2d1184be5c24
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921575548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.921575548
Directory	/workspace/2.chip_sw_edn_entropy_reqs_jitter/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_kat.589156530
Short name	T603
Test name
Test status
Simulation time	3399382740 ps
CPU time	820.81 seconds
Started	Jul 19 06:58:03 PM PDT 24
Finished	Jul 19 07:11:44 PM PDT 24
Peak memory	616332 kb
Host	smart-9ac16fb9-49ca-4c1e-9dc7-6c59e199d55d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589156530 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.589156530
Directory	/workspace/2.chip_sw_edn_kat/latest

Test location	/workspace/coverage/default/2.chip_sw_edn_sw_mode.1901387993
Short name	T552
Test name
Test status
Simulation time	11350881170 ps
CPU time	2741.18 seconds
Started	Jul 19 07:00:18 PM PDT 24
Finished	Jul 19 07:46:01 PM PDT 24
Peak memory	609304 kb
Host	smart-d45b31ef-a148-4a61-b9f7-837cda1d889d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901387993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1901387993
Directory	/workspace/2.chip_sw_edn_sw_mode/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1505650238
Short name	T589
Test name
Test status
Simulation time	2733850122 ps
CPU time	200.11 seconds
Started	Jul 19 06:56:45 PM PDT 24
Finished	Jul 19 07:00:07 PM PDT 24
Peak memory	609244 kb
Host	smart-0acdf081-18fa-4324-b0a7-5c3623f8143b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15 05650238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1505650238
Directory	/workspace/2.chip_sw_entropy_src_ast_rng_req/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3056151656
Short name	T82
Test name
Test status
Simulation time	5708683832 ps
CPU time	1215.47 seconds
Started	Jul 19 06:56:56 PM PDT 24
Finished	Jul 19 07:17:13 PM PDT 24
Peak memory	610204 kb
Host	smart-f97ebcfe-fc34-4f7c-b5c0-592663fcb406
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3056151656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.3056151656
Directory	/workspace/2.chip_sw_entropy_src_csrng/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1911796517
Short name	T846
Test name
Test status
Simulation time	3199570400 ps
CPU time	276.23 seconds
Started	Jul 19 06:56:37 PM PDT 24
Finished	Jul 19 07:01:14 PM PDT 24
Peak memory	609772 kb
Host	smart-da78dcc4-185f-48c9-9324-533a5ff084a1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911796517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.1911796517
Directory	/workspace/2.chip_sw_entropy_src_kat_test/latest

Test location	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.357631435
Short name	T977
Test name
Test status
Simulation time	3268042828 ps
CPU time	507.44 seconds
Started	Jul 19 07:00:47 PM PDT 24
Finished	Jul 19 07:09:20 PM PDT 24
Peak memory	609728 kb
Host	smart-de39eb7e-aa39-46a0-86ba-795d0474bead
User	root
Command	/workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=357631435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.357631435
Directory	/workspace/2.chip_sw_entropy_src_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_example_concurrency.1996030733
Short name	T444
Test name
Test status
Simulation time	2434671544 ps
CPU time	230.91 seconds
Started	Jul 19 06:52:19 PM PDT 24
Finished	Jul 19 06:56:10 PM PDT 24
Peak memory	609384 kb
Host	smart-9692bca1-92fe-4f51-89d3-7052792cb2a7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996030733 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1996030733
Directory	/workspace/2.chip_sw_example_concurrency/latest

Test location	/workspace/coverage/default/2.chip_sw_example_flash.1044641139
Short name	T1012
Test name
Test status
Simulation time	2772986152 ps
CPU time	208.23 seconds
Started	Jul 19 06:53:28 PM PDT 24
Finished	Jul 19 06:56:57 PM PDT 24
Peak memory	609728 kb
Host	smart-406b1ee1-b2e2-447b-9345-522df0f44a73
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044641139 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.1044641139
Directory	/workspace/2.chip_sw_example_flash/latest

Test location	/workspace/coverage/default/2.chip_sw_example_manufacturer.143152891
Short name	T991
Test name
Test status
Simulation time	2841919872 ps
CPU time	259.45 seconds
Started	Jul 19 06:52:42 PM PDT 24
Finished	Jul 19 06:57:03 PM PDT 24
Peak memory	609172 kb
Host	smart-5eb8eeb5-e38a-4647-8695-72fed4229f32
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143152891 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_example_manufacturer.143152891
Directory	/workspace/2.chip_sw_example_manufacturer/latest

Test location	/workspace/coverage/default/2.chip_sw_example_rom.2883625755
Short name	T911
Test name
Test status
Simulation time	3004581518 ps
CPU time	119.92 seconds
Started	Jul 19 06:53:55 PM PDT 24
Finished	Jul 19 06:56:16 PM PDT 24
Peak memory	609380 kb
Host	smart-7729903d-cf14-4acd-bac6-488779f4fb5a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883625755 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2883625755
Directory	/workspace/2.chip_sw_example_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2844147527
Short name	T860
Test name
Test status
Simulation time	59792840984 ps
CPU time	11627.6 seconds
Started	Jul 19 06:52:42 PM PDT 24
Finished	Jul 19 10:06:32 PM PDT 24
Peak memory	623840 kb
Host	smart-378044dc-2d2c-4fbc-bfb9-e69a93e916ba
User	root
Command	/workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2844147527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2844147527
Directory	/workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_crash_alert.2254333570
Short name	T877
Test name
Test status
Simulation time	6213801800 ps
CPU time	767.14 seconds
Started	Jul 19 06:59:08 PM PDT 24
Finished	Jul 19 07:11:56 PM PDT 24
Peak memory	611036 kb
Host	smart-1f2f20c0-331a-433d-89c7-7fda3931c4a9
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2254333570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2254333570
Directory	/workspace/2.chip_sw_flash_crash_alert/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2689295884
Short name	T606
Test name
Test status
Simulation time	5312714608 ps
CPU time	1278.34 seconds
Started	Jul 19 06:54:51 PM PDT 24
Finished	Jul 19 07:17:12 PM PDT 24
Peak memory	610028 kb
Host	smart-1bf162aa-f10a-44c0-91f8-d8fed8b76afb
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689295884 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.2689295884
Directory	/workspace/2.chip_sw_flash_ctrl_access/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2533572986
Short name	T580
Test name
Test status
Simulation time	6001359578 ps
CPU time	1073.4 seconds
Started	Jul 19 06:55:19 PM PDT 24
Finished	Jul 19 07:13:56 PM PDT 24
Peak memory	609320 kb
Host	smart-fe6582ee-331d-4d2c-b9d2-9091df84b99d
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533572986 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2533572986
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4221333305
Short name	T1001
Test name
Test status
Simulation time	7068223588 ps
CPU time	1371.15 seconds
Started	Jul 19 06:58:57 PM PDT 24
Finished	Jul 19 07:21:48 PM PDT 24
Peak memory	609264 kb
Host	smart-0987e7f3-cd62-407a-8e58-6cb197c6131d
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221333305 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4221333305
Directory	/workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1576576487
Short name	T304
Test name
Test status
Simulation time	5494981552 ps
CPU time	1153.71 seconds
Started	Jul 19 06:55:57 PM PDT 24
Finished	Jul 19 07:15:22 PM PDT 24
Peak memory	610032 kb
Host	smart-07fc3f28-43e8-4f67-8988-9042ce7ebdf3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576576487 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1576576487
Directory	/workspace/2.chip_sw_flash_ctrl_clock_freqs/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.434535696
Short name	T678
Test name
Test status
Simulation time	3429374024 ps
CPU time	425.22 seconds
Started	Jul 19 06:53:55 PM PDT 24
Finished	Jul 19 07:01:20 PM PDT 24
Peak memory	609560 kb
Host	smart-90e0f64c-fddf-492d-a7a7-8114d90f1cff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434535696 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.434535696
Directory	/workspace/2.chip_sw_flash_ctrl_idle_low_power/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1253251733
Short name	T342
Test name
Test status
Simulation time	4849975368 ps
CPU time	702.78 seconds
Started	Jul 19 06:55:08 PM PDT 24
Finished	Jul 19 07:07:43 PM PDT 24
Peak memory	609676 kb
Host	smart-6f66189e-32a9-4e4f-bcf7-5ccdf2e77e8c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 53251733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1253251733
Directory	/workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3691490199
Short name	T420
Test name
Test status
Simulation time	5127842916 ps
CPU time	1331.39 seconds
Started	Jul 19 07:00:03 PM PDT 24
Finished	Jul 19 07:22:18 PM PDT 24
Peak memory	609256 kb
Host	smart-6f256e26-0bf8-4eb9-a724-08a2653a503c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691490199 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3691490199
Directory	/workspace/2.chip_sw_flash_ctrl_mem_protection/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4240280741
Short name	T396
Test name
Test status
Simulation time	4211137892 ps
CPU time	714.53 seconds
Started	Jul 19 06:54:41 PM PDT 24
Finished	Jul 19 07:07:42 PM PDT 24
Peak memory	609604 kb
Host	smart-e4dc379c-de63-44e3-82ec-6959d3662ce6
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240280741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.4240280741
Directory	/workspace/2.chip_sw_flash_ctrl_ops/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2380698835
Short name	T388
Test name
Test status
Simulation time	4687281703 ps
CPU time	728.05 seconds
Started	Jul 19 06:54:47 PM PDT 24
Finished	Jul 19 07:07:59 PM PDT 24
Peak memory	610180 kb
Host	smart-6f0f0ec7-3ce1-4c9b-8ff9-ed5f31204677
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2380698835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2380698835
Directory	/workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.971237353
Short name	T706
Test name
Test status
Simulation time	2821676514 ps
CPU time	353.38 seconds
Started	Jul 19 07:01:43 PM PDT 24
Finished	Jul 19 07:07:37 PM PDT 24
Peak memory	609268 kb
Host	smart-408c0929-1bc2-414b-ae5f-87e724c80bfa
User	root
Command	/workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9712373 53 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.971237353
Directory	/workspace/2.chip_sw_flash_ctrl_write_clear/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init.3321179754
Short name	T337
Test name
Test status
Simulation time	19229000750 ps
CPU time	2224.93 seconds
Started	Jul 19 06:53:33 PM PDT 24
Finished	Jul 19 07:30:39 PM PDT 24
Peak memory	613424 kb
Host	smart-308b5a67-4aff-41c5-87ed-84b39b0c0cd1
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321179754 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3321179754
Directory	/workspace/2.chip_sw_flash_init/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3723058612
Short name	T869
Test name
Test status
Simulation time	25703711123 ps
CPU time	1980.29 seconds
Started	Jul 19 06:59:29 PM PDT 24
Finished	Jul 19 07:32:30 PM PDT 24
Peak memory	616040 kb
Host	smart-a4acd0ac-d7b8-46ad-8fa8-9a89abaaf034
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3723058612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3723058612
Directory	/workspace/2.chip_sw_flash_init_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3350377087
Short name	T544
Test name
Test status
Simulation time	3245255284 ps
CPU time	298.75 seconds
Started	Jul 19 07:06:31 PM PDT 24
Finished	Jul 19 07:11:31 PM PDT 24
Peak memory	609696 kb
Host	smart-e0e2f213-5b32-44de-b5e3-8f0f56d75d21
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3350377087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.3350377087
Directory	/workspace/2.chip_sw_flash_scrambling_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3092820509
Short name	T738
Test name
Test status
Simulation time	3202175839 ps
CPU time	243.87 seconds
Started	Jul 19 07:01:31 PM PDT 24
Finished	Jul 19 07:05:38 PM PDT 24
Peak memory	610032 kb
Host	smart-8603095c-2bde-4ca7-85eb-06a8c8a9902b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092820509 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3092820509
Directory	/workspace/2.chip_sw_gpio_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc.3366637450
Short name	T1005
Test name
Test status
Simulation time	3143223332 ps
CPU time	345.07 seconds
Started	Jul 19 06:57:46 PM PDT 24
Finished	Jul 19 07:03:32 PM PDT 24
Peak memory	609716 kb
Host	smart-94a36342-c86d-490f-a7ea-358544b259a0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366637450 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.3366637450
Directory	/workspace/2.chip_sw_hmac_enc/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.4002516320
Short name	T938
Test name
Test status
Simulation time	2742852160 ps
CPU time	285.76 seconds
Started	Jul 19 06:58:14 PM PDT 24
Finished	Jul 19 07:03:01 PM PDT 24
Peak memory	609764 kb
Host	smart-f2f4ef4d-fe8f-4ff8-b7fc-4325281891c5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002516320 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.4002516320
Directory	/workspace/2.chip_sw_hmac_enc_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.4187787297
Short name	T398
Test name
Test status
Simulation time	3262847903 ps
CPU time	282.59 seconds
Started	Jul 19 06:58:17 PM PDT 24
Finished	Jul 19 07:03:00 PM PDT 24
Peak memory	609368 kb
Host	smart-dc4ca9a6-7d00-4305-8598-267c4ebacded
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187787297 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.4187787297
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3397197373
Short name	T651
Test name
Test status
Simulation time	3470059159 ps
CPU time	300.76 seconds
Started	Jul 19 07:02:46 PM PDT 24
Finished	Jul 19 07:07:47 PM PDT 24
Peak memory	609728 kb
Host	smart-8f2077db-fa15-4845-b6ef-f86c876e4e78
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397197373 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.3397197373
Directory	/workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_multistream.341199644
Short name	T844
Test name
Test status
Simulation time	8209546000 ps
CPU time	1629.43 seconds
Started	Jul 19 06:56:57 PM PDT 24
Finished	Jul 19 07:24:08 PM PDT 24
Peak memory	609296 kb
Host	smart-c6157d31-8ba5-48ca-b1ff-9aeb7ce34e98
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341199644 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.341199644
Directory	/workspace/2.chip_sw_hmac_multistream/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_oneshot.294082405
Short name	T923
Test name
Test status
Simulation time	3327544040 ps
CPU time	315.49 seconds
Started	Jul 19 06:58:13 PM PDT 24
Finished	Jul 19 07:03:29 PM PDT 24
Peak memory	609272 kb
Host	smart-96f245a0-30ef-458b-874b-593af0a834b7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294082405 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.294082405
Directory	/workspace/2.chip_sw_hmac_oneshot/latest

Test location	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1332563519
Short name	T210
Test name
Test status
Simulation time	2758561634 ps
CPU time	394.41 seconds
Started	Jul 19 07:01:03 PM PDT 24
Finished	Jul 19 07:07:42 PM PDT 24
Peak memory	609736 kb
Host	smart-9c5ecc08-4c6c-4b9d-8db9-93f4a2981f36
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332563519 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1332563519
Directory	/workspace/2.chip_sw_hmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1742618078
Short name	T382
Test name
Test status
Simulation time	4840132488 ps
CPU time	671.93 seconds
Started	Jul 19 06:54:21 PM PDT 24
Finished	Jul 19 07:06:39 PM PDT 24
Peak memory	609480 kb
Host	smart-8188de5a-c407-4e56-9801-ce6de70b9a38
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742618078 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1742618078
Directory	/workspace/2.chip_sw_i2c_device_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3673782469
Short name	T238
Test name
Test status
Simulation time	4516570530 ps
CPU time	681.8 seconds
Started	Jul 19 06:53:48 PM PDT 24
Finished	Jul 19 07:05:18 PM PDT 24
Peak memory	609304 kb
Host	smart-9ab33912-9361-4664-a267-53b74248da62
User	root
Command	/workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673782469 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3673782469
Directory	/workspace/2.chip_sw_i2c_host_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.652693529
Short name	T648
Test name
Test status
Simulation time	5342878290 ps
CPU time	909.32 seconds
Started	Jul 19 06:55:46 PM PDT 24
Finished	Jul 19 07:11:16 PM PDT 24
Peak memory	609452 kb
Host	smart-1671ff37-7586-4abd-b5b3-e488c46e721f
User	root
Command	/workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652693529 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.652693529
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2839223969
Short name	T240
Test name
Test status
Simulation time	5185845544 ps
CPU time	810.24 seconds
Started	Jul 19 06:54:37 PM PDT 24
Finished	Jul 19 07:09:15 PM PDT 24
Peak memory	609564 kb
Host	smart-09d4c389-c96f-4a1e-8b27-888f8054fd8b
User	root
Command	/workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839223969 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2839223969
Directory	/workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2931187884
Short name	T253
Test name
Test status
Simulation time	63284697473 ps
CPU time	11685.2 seconds
Started	Jul 19 06:53:08 PM PDT 24
Finished	Jul 19 10:07:55 PM PDT 24
Peak memory	624756 kb
Host	smart-160cef8c-6bd6-4e55-a06d-89fdefa71695
User	root
Command	/workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2931187884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.2931187884
Directory	/workspace/2.chip_sw_inject_scramble_seed/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1281580364
Short name	T637
Test name
Test status
Simulation time	9331530428 ps
CPU time	1818.82 seconds
Started	Jul 19 06:58:20 PM PDT 24
Finished	Jul 19 07:28:39 PM PDT 24
Peak memory	617612 kb
Host	smart-683b5f25-0fdf-40dd-ae3e-c434f9bf2816
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281 580364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.1281580364
Directory	/workspace/2.chip_sw_keymgr_key_derivation/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4266025441
Short name	T151
Test name
Test status
Simulation time	8842597324 ps
CPU time	2113.6 seconds
Started	Jul 19 06:58:32 PM PDT 24
Finished	Jul 19 07:33:46 PM PDT 24
Peak memory	617688 kb
Host	smart-085a6de6-faa3-4545-802a-44232fbd6a13
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4266025441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.4266025441
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2222230948
Short name	T699
Test name
Test status
Simulation time	11406195914 ps
CPU time	1843.77 seconds
Started	Jul 19 06:59:46 PM PDT 24
Finished	Jul 19 07:30:31 PM PDT 24
Peak memory	617676 kb
Host	smart-559d3fa2-f0c6-4a8a-be93-06bf8f4b4a39
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2222230948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2222230948
Directory	/workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.158510760
Short name	T44
Test name
Test status
Simulation time	8748721298 ps
CPU time	1503.1 seconds
Started	Jul 19 06:58:48 PM PDT 24
Finished	Jul 19 07:23:52 PM PDT 24
Peak memory	617672 kb
Host	smart-c499e3d0-6442-41a1-a69a-0242557514da
User	root
Command	/workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=158510760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.158510760
Directory	/workspace/2.chip_sw_keymgr_key_derivation_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1207586544
Short name	T333
Test name
Test status
Simulation time	6695940444 ps
CPU time	1314.35 seconds
Started	Jul 19 06:57:21 PM PDT 24
Finished	Jul 19 07:19:17 PM PDT 24
Peak memory	611220 kb
Host	smart-a6343adf-49d9-43a8-ad73-3c719140db42
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120758 6544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1207586544
Directory	/workspace/2.chip_sw_keymgr_sideload_aes/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3115901202
Short name	T868
Test name
Test status
Simulation time	6017755168 ps
CPU time	1037.47 seconds
Started	Jul 19 06:57:02 PM PDT 24
Finished	Jul 19 07:14:20 PM PDT 24
Peak memory	610956 kb
Host	smart-bd315362-4336-4dea-9d79-4806106b06bf
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31159 01202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3115901202
Directory	/workspace/2.chip_sw_keymgr_sideload_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3704511509
Short name	T335
Test name
Test status
Simulation time	12521337638 ps
CPU time	4312.63 seconds
Started	Jul 19 06:57:31 PM PDT 24
Finished	Jul 19 08:09:25 PM PDT 24
Peak memory	610684 kb
Host	smart-1183516d-883b-4375-a468-1a75563cbc0e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37045 11509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3704511509
Directory	/workspace/2.chip_sw_keymgr_sideload_otbn/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2364930201
Short name	T205
Test name
Test status
Simulation time	2366376880 ps
CPU time	338.3 seconds
Started	Jul 19 06:59:27 PM PDT 24
Finished	Jul 19 07:05:06 PM PDT 24
Peak memory	609672 kb
Host	smart-2f9152e9-906e-478a-8481-9d91b4a1ca21
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364930201 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.2364930201
Directory	/workspace/2.chip_sw_kmac_app_rom/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_entropy.338485750
Short name	T212
Test name
Test status
Simulation time	2714098468 ps
CPU time	206.35 seconds
Started	Jul 19 06:55:12 PM PDT 24
Finished	Jul 19 06:59:28 PM PDT 24
Peak memory	609684 kb
Host	smart-eadc5c4d-f071-419b-ac68-ffade382d8d7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338485750 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.338485750
Directory	/workspace/2.chip_sw_kmac_entropy/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_idle.1573802507
Short name	T558
Test name
Test status
Simulation time	2747363800 ps
CPU time	209.72 seconds
Started	Jul 19 06:57:21 PM PDT 24
Finished	Jul 19 07:00:52 PM PDT 24
Peak memory	609688 kb
Host	smart-5aa1e007-e0a5-49e2-8add-c632a98b4fc0
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573802507 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1573802507
Directory	/workspace/2.chip_sw_kmac_idle/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.713498727
Short name	T667
Test name
Test status
Simulation time	2837347760 ps
CPU time	379.87 seconds
Started	Jul 19 06:59:32 PM PDT 24
Finished	Jul 19 07:05:53 PM PDT 24
Peak memory	609720 kb
Host	smart-87f33b23-5fa3-48d7-9b95-85922a6c4954
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713498727 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_kmac_mode_cshake.713498727
Directory	/workspace/2.chip_sw_kmac_mode_cshake/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2429403871
Short name	T581
Test name
Test status
Simulation time	2486513160 ps
CPU time	248.45 seconds
Started	Jul 19 06:58:00 PM PDT 24
Finished	Jul 19 07:02:09 PM PDT 24
Peak memory	609256 kb
Host	smart-9652c915-5856-4149-be3d-7ae87b7e3888
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429403871 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2429403871
Directory	/workspace/2.chip_sw_kmac_mode_kmac/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2332974930
Short name	T792
Test name
Test status
Simulation time	2926531733 ps
CPU time	353.61 seconds
Started	Jul 19 06:56:56 PM PDT 24
Finished	Jul 19 07:02:51 PM PDT 24
Peak memory	609352 kb
Host	smart-8e2d4ef8-53ee-4d16-8c20-eeda92f61976
User	root
Command	/workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332974930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2332974930
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3979102016
Short name	T964
Test name
Test status
Simulation time	3978280391 ps
CPU time	363.92 seconds
Started	Jul 19 07:00:17 PM PDT 24
Finished	Jul 19 07:06:22 PM PDT 24
Peak memory	609584 kb
Host	smart-e0f7d32c-30aa-49b7-a74f-c32ded955bef
User	root
Command	/workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791020 16 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3979102016
Directory	/workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_kmac_smoketest.3865657711
Short name	T994
Test name
Test status
Simulation time	3409996588 ps
CPU time	371.74 seconds
Started	Jul 19 07:01:41 PM PDT 24
Finished	Jul 19 07:07:55 PM PDT 24
Peak memory	609848 kb
Host	smart-3d712005-c7ac-4e35-bf26-be967964150e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865657711 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.3865657711
Directory	/workspace/2.chip_sw_kmac_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4088196588
Short name	T563
Test name
Test status
Simulation time	2805200510 ps
CPU time	271.92 seconds
Started	Jul 19 06:55:15 PM PDT 24
Finished	Jul 19 07:00:34 PM PDT 24
Peak memory	609664 kb
Host	smart-e71d636b-8e19-43eb-a49c-daccb8d5b4f5
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088196588 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.4088196588
Directory	/workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2383393572
Short name	T178
Test name
Test status
Simulation time	5175841100 ps
CPU time	476.65 seconds
Started	Jul 19 07:01:18 PM PDT 24
Finished	Jul 19 07:09:16 PM PDT 24
Peak memory	610856 kb
Host	smart-e50d8440-c1e2-4ca4-ba44-3eb2cfd00d61
User	root
Command	/workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2383393572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2383393572
Directory	/workspace/2.chip_sw_lc_ctrl_program_error/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3759982099
Short name	T449
Test name
Test status
Simulation time	2490854651 ps
CPU time	118.58 seconds
Started	Jul 19 06:54:39 PM PDT 24
Finished	Jul 19 06:57:44 PM PDT 24
Peak memory	616808 kb
Host	smart-c8bfa38d-fcca-4a4c-8790-91d52c38b344
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3759982099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3759982099
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1449644392
Short name	T450
Test name
Test status
Simulation time	1945249467 ps
CPU time	115.75 seconds
Started	Jul 19 06:57:25 PM PDT 24
Finished	Jul 19 06:59:22 PM PDT 24
Peak memory	617716 kb
Host	smart-dfd9d6ba-bc4f-4049-abf7-491a4c7b5173
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449644392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1449644392
Directory	/workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3744757526
Short name	T340
Test name
Test status
Simulation time	50856711678 ps
CPU time	6068.62 seconds
Started	Jul 19 06:57:27 PM PDT 24
Finished	Jul 19 08:38:38 PM PDT 24
Peak memory	623840 kb
Host	smart-b934ee3d-e101-4c67-86e5-af0577e1b85b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744757526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.3744757526
Directory	/workspace/2.chip_sw_lc_walkthrough_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.853687337
Short name	T338
Test name
Test status
Simulation time	49976004717 ps
CPU time	5748.96 seconds
Started	Jul 19 06:54:47 PM PDT 24
Finished	Jul 19 08:31:40 PM PDT 24
Peak memory	620520 kb
Host	smart-abfc6640-97f3-489b-8af7-ba64e162b398
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853687337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.853687337
Directory	/workspace/2.chip_sw_lc_walkthrough_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3187883141
Short name	T852
Test name
Test status
Simulation time	9021902760 ps
CPU time	1038.22 seconds
Started	Jul 19 06:55:19 PM PDT 24
Finished	Jul 19 07:13:22 PM PDT 24
Peak memory	618760 kb
Host	smart-34638a9c-4daf-4b77-827d-c4ee3c10a86e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187883141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.3187883141
Directory	/workspace/2.chip_sw_lc_walkthrough_prodend/latest

Test location	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2303319130
Short name	T608
Test name
Test status
Simulation time	35633297424 ps
CPU time	2319.46 seconds
Started	Jul 19 06:55:20 PM PDT 24
Finished	Jul 19 07:34:44 PM PDT 24
Peak memory	620372 kb
Host	smart-9bf02da0-fe6f-4e19-be89-c92d1a165fa1
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2303319130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2303319130
Directory	/workspace/2.chip_sw_lc_walkthrough_testunlocks/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.554240847
Short name	T828
Test name
Test status
Simulation time	16703154888 ps
CPU time	3597.46 seconds
Started	Jul 19 06:55:24 PM PDT 24
Finished	Jul 19 07:56:01 PM PDT 24
Peak memory	609436 kb
Host	smart-b17bf9ef-248f-4837-9a48-f47988ea15d2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=554240847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.554240847
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.879460536
Short name	T612
Test name
Test status
Simulation time	19047253446 ps
CPU time	4322.91 seconds
Started	Jul 19 06:56:55 PM PDT 24
Finished	Jul 19 08:08:59 PM PDT 24
Peak memory	610200 kb
Host	smart-5d83c273-47fd-4e1b-b7ee-a17f590bf4fd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=879460536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.879460536
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3209453912
Short name	T73
Test name
Test status
Simulation time	25530598976 ps
CPU time	4543.93 seconds
Started	Jul 19 07:00:29 PM PDT 24
Finished	Jul 19 08:16:14 PM PDT 24
Peak memory	610292 kb
Host	smart-7159fe23-e350-4966-9958-068a03fc62a5
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209453912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3209453912
Directory	/workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.577351049
Short name	T954
Test name
Test status
Simulation time	3598923600 ps
CPU time	566.71 seconds
Started	Jul 19 06:55:17 PM PDT 24
Finished	Jul 19 07:05:29 PM PDT 24
Peak memory	609744 kb
Host	smart-2bc70030-63e9-4dd2-87bf-e649c8f442bd
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577351049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.577351049
Directory	/workspace/2.chip_sw_otbn_mem_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_randomness.876979100
Short name	T379
Test name
Test status
Simulation time	5881412420 ps
CPU time	775.58 seconds
Started	Jul 19 06:57:34 PM PDT 24
Finished	Jul 19 07:10:31 PM PDT 24
Peak memory	609508 kb
Host	smart-e897e6de-24c7-4290-8c59-645f7fce9b14
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=876979100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.876979100
Directory	/workspace/2.chip_sw_otbn_randomness/latest

Test location	/workspace/coverage/default/2.chip_sw_otbn_smoketest.2188432975
Short name	T652
Test name
Test status
Simulation time	8741337464 ps
CPU time	2057.4 seconds
Started	Jul 19 07:04:06 PM PDT 24
Finished	Jul 19 07:38:25 PM PDT 24
Peak memory	609388 kb
Host	smart-239038dd-8c40-4ec7-b233-58692cb9ecea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188432975 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2188432975
Directory	/workspace/2.chip_sw_otbn_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.408288092
Short name	T642
Test name
Test status
Simulation time	3167307541 ps
CPU time	248.36 seconds
Started	Jul 19 06:55:18 PM PDT 24
Finished	Jul 19 07:00:11 PM PDT 24
Peak memory	609964 kb
Host	smart-4217a3da-ec92-4447-80bf-87e0742ea029
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408288092 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.408288092
Directory	/workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2572287016
Short name	T823
Test name
Test status
Simulation time	8235124814 ps
CPU time	1349.9 seconds
Started	Jul 19 06:55:44 PM PDT 24
Finished	Jul 19 07:18:37 PM PDT 24
Peak memory	610536 kb
Host	smart-1a7ca53a-0ed1-4133-8bc4-9deec81e17ef
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2572287016 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2572287016
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1619327067
Short name	T572
Test name
Test status
Simulation time	8125605312 ps
CPU time	1035.63 seconds
Started	Jul 19 06:54:59 PM PDT 24
Finished	Jul 19 07:13:14 PM PDT 24
Peak memory	610308 kb
Host	smart-7dca5da8-a36c-4c0b-8028-65261043be87
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1619327067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1619327067
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.538931718
Short name	T845
Test name
Test status
Simulation time	5957578752 ps
CPU time	1109.66 seconds
Started	Jul 19 06:55:15 PM PDT 24
Finished	Jul 19 07:14:32 PM PDT 24
Peak memory	610600 kb
Host	smart-827cfcd2-0b97-4c57-8c34-013da298ae44
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=538931718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.538931718
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.829401923
Short name	T985
Test name
Test status
Simulation time	4423433940 ps
CPU time	720.81 seconds
Started	Jul 19 06:55:32 PM PDT 24
Finished	Jul 19 07:08:06 PM PDT 24
Peak memory	610140 kb
Host	smart-1fa99b86-24b1-4045-9357-81a8c9baf91b
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=829401923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.829401923
Directory	/workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest

Test location	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1906500556
Short name	T765
Test name
Test status
Simulation time	3181186600 ps
CPU time	376.37 seconds
Started	Jul 19 07:01:49 PM PDT 24
Finished	Jul 19 07:08:08 PM PDT 24
Peak memory	609676 kb
Host	smart-86164a5a-12ea-441a-b40a-ac2861314786
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906500556 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1906500556
Directory	/workspace/2.chip_sw_otp_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pattgen_ios.2104251452
Short name	T264
Test name
Test status
Simulation time	3219237540 ps
CPU time	237.53 seconds
Started	Jul 19 06:53:20 PM PDT 24
Finished	Jul 19 06:57:18 PM PDT 24
Peak memory	610488 kb
Host	smart-54a40386-da21-41ef-a7dc-b13361fe41ff
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104251452 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2104251452
Directory	/workspace/2.chip_sw_pattgen_ios/latest

Test location	/workspace/coverage/default/2.chip_sw_power_idle_load.900112359
Short name	T983
Test name
Test status
Simulation time	4271998302 ps
CPU time	795.8 seconds
Started	Jul 19 07:01:59 PM PDT 24
Finished	Jul 19 07:15:17 PM PDT 24
Peak memory	609016 kb
Host	smart-39a1f2c3-3c2b-4664-8ae6-5993771691ba
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900112359 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.900112359
Directory	/workspace/2.chip_sw_power_idle_load/latest

Test location	/workspace/coverage/default/2.chip_sw_power_sleep_load.1978669158
Short name	T327
Test name
Test status
Simulation time	10448078188 ps
CPU time	579.79 seconds
Started	Jul 19 07:00:36 PM PDT 24
Finished	Jul 19 07:10:18 PM PDT 24
Peak memory	610784 kb
Host	smart-9f5ce165-6401-44e2-aab4-7187f2bbfa7c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978669158 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1978669158
Directory	/workspace/2.chip_sw_power_sleep_load/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.87768532
Short name	T403
Test name
Test status
Simulation time	11234585275 ps
CPU time	1557.49 seconds
Started	Jul 19 06:55:26 PM PDT 24
Finished	Jul 19 07:22:01 PM PDT 24
Peak memory	611276 kb
Host	smart-65f14d7a-3c16-4adb-86bb-9334e2ac47ac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8776 8532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.87768532
Directory	/workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3029865815
Short name	T908
Test name
Test status
Simulation time	27230194035 ps
CPU time	2284.48 seconds
Started	Jul 19 07:00:33 PM PDT 24
Finished	Jul 19 07:38:40 PM PDT 24
Peak memory	610716 kb
Host	smart-cac7aaea-6505-4ec1-95e5-01a5be808210
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302 9865815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3029865815
Directory	/workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1449073506
Short name	T378
Test name
Test status
Simulation time	12519581736 ps
CPU time	1377.84 seconds
Started	Jul 19 06:56:02 PM PDT 24
Finished	Jul 19 07:19:07 PM PDT 24
Peak memory	611272 kb
Host	smart-771cf8a9-708d-4226-8b56-ddd773c7ec85
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1449073506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1449073506
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4072271864
Short name	T681
Test name
Test status
Simulation time	9763252080 ps
CPU time	582.62 seconds
Started	Jul 19 06:55:47 PM PDT 24
Finished	Jul 19 07:05:49 PM PDT 24
Peak memory	610436 kb
Host	smart-edbb6cb3-74a6-464a-a808-d1d5b37ee021
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072271864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.4072271864
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1466700612
Short name	T943
Test name
Test status
Simulation time	6625171400 ps
CPU time	435.73 seconds
Started	Jul 19 06:55:42 PM PDT 24
Finished	Jul 19 07:03:22 PM PDT 24
Peak memory	616116 kb
Host	smart-d5c40ce0-a030-48cd-bbff-c46fcb2225c7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1466700612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1466700612
Directory	/workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1110917954
Short name	T399
Test name
Test status
Simulation time	7924046579 ps
CPU time	626.93 seconds
Started	Jul 19 06:55:24 PM PDT 24
Finished	Jul 19 07:06:31 PM PDT 24
Peak memory	610464 kb
Host	smart-1219ada6-cffa-4858-b213-636d39810cea
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110917954 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1110917954
Directory	/workspace/2.chip_sw_pwrmgr_full_aon_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3498545566
Short name	T384
Test name
Test status
Simulation time	4002649960 ps
CPU time	536.99 seconds
Started	Jul 19 07:00:31 PM PDT 24
Finished	Jul 19 07:09:29 PM PDT 24
Peak memory	609516 kb
Host	smart-bad356bf-0786-4e0c-a22c-5dd3091ee778
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498545566 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.3498545566
Directory	/workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1256277315
Short name	T799
Test name
Test status
Simulation time	4214427578 ps
CPU time	400.19 seconds
Started	Jul 19 06:54:47 PM PDT 24
Finished	Jul 19 07:02:30 PM PDT 24
Peak memory	615840 kb
Host	smart-670d1bf5-a4cb-472d-8c7f-f71b67d28fa1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1256277315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1256277315
Directory	/workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2177882666
Short name	T443
Test name
Test status
Simulation time	7594373240 ps
CPU time	550.66 seconds
Started	Jul 19 06:58:45 PM PDT 24
Finished	Jul 19 07:07:57 PM PDT 24
Peak memory	610340 kb
Host	smart-67c87c1c-1f32-4544-af74-7e2c485450c8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177882666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2177882666
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.804612684
Short name	T831
Test name
Test status
Simulation time	6277808808 ps
CPU time	628.18 seconds
Started	Jul 19 06:57:07 PM PDT 24
Finished	Jul 19 07:07:36 PM PDT 24
Peak memory	610664 kb
Host	smart-786b0a14-287a-4d0f-80f6-b88a68408345
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804612684 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.804612684
Directory	/workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3594918147
Short name	T369
Test name
Test status
Simulation time	24647671166 ps
CPU time	2646.83 seconds
Started	Jul 19 06:54:21 PM PDT 24
Finished	Jul 19 07:39:32 PM PDT 24
Peak memory	611320 kb
Host	smart-1812721b-ea0e-4f55-97f1-34605f50fb2c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3594918147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3594918147
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.46690552
Short name	T763
Test name
Test status
Simulation time	34707953370 ps
CPU time	3731.03 seconds
Started	Jul 19 06:56:41 PM PDT 24
Finished	Jul 19 07:58:53 PM PDT 24
Peak memory	611440 kb
Host	smart-03f4534f-646d-48f4-a58d-607844f50355
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46690552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitch _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sle ep_power_glitch_reset.46690552
Directory	/workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3468797537
Short name	T409
Test name
Test status
Simulation time	6245005700 ps
CPU time	715.94 seconds
Started	Jul 19 06:59:59 PM PDT 24
Finished	Jul 19 07:12:00 PM PDT 24
Peak memory	610724 kb
Host	smart-2bfc6e0a-8f86-48c1-8184-eb6d026f9f64
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3468797537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3468797537
Directory	/workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2413861692
Short name	T268
Test name
Test status
Simulation time	3482955798 ps
CPU time	238.24 seconds
Started	Jul 19 06:55:35 PM PDT 24
Finished	Jul 19 07:00:04 PM PDT 24
Peak memory	609728 kb
Host	smart-18f00724-3802-4336-a6fb-47ed31e246ee
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413861692 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.2413861692
Directory	/workspace/2.chip_sw_pwrmgr_sleep_disabled/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.198771168
Short name	T67
Test name
Test status
Simulation time	4574986398 ps
CPU time	339.31 seconds
Started	Jul 19 06:54:43 PM PDT 24
Finished	Jul 19 07:01:27 PM PDT 24
Peak memory	616260 kb
Host	smart-2b79d8a8-bb77-4394-b001-1dc7ee383e88
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=198771168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.198771168
Directory	/workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1893775481
Short name	T93
Test name
Test status
Simulation time	5651476266 ps
CPU time	509.44 seconds
Started	Jul 19 06:58:35 PM PDT 24
Finished	Jul 19 07:07:05 PM PDT 24
Peak memory	609248 kb
Host	smart-350f448d-cb2e-47ea-b812-bfe43554def4
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18937754 81 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1893775481
Directory	/workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3296030385
Short name	T717
Test name
Test status
Simulation time	6748922392 ps
CPU time	565 seconds
Started	Jul 19 06:58:33 PM PDT 24
Finished	Jul 19 07:07:58 PM PDT 24
Peak memory	610204 kb
Host	smart-c5175970-6c7b-4895-92d6-12e324e4a27c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3296030385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.3296030385
Directory	/workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.665008934
Short name	T996
Test name
Test status
Simulation time	4851600588 ps
CPU time	403.93 seconds
Started	Jul 19 07:03:13 PM PDT 24
Finished	Jul 19 07:09:58 PM PDT 24
Peak memory	610340 kb
Host	smart-a4a441a1-7dda-4409-a4ef-7242d4c43f03
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665008934 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.665008934
Directory	/workspace/2.chip_sw_pwrmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3088050953
Short name	T546
Test name
Test status
Simulation time	6429574220 ps
CPU time	829.19 seconds
Started	Jul 19 06:56:52 PM PDT 24
Finished	Jul 19 07:10:42 PM PDT 24
Peak memory	610536 kb
Host	smart-97b8ea13-ebec-469c-99da-bf4405bd849e
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088050953 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3088050953
Directory	/workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3428035545
Short name	T154
Test name
Test status
Simulation time	4027787764 ps
CPU time	412.03 seconds
Started	Jul 19 06:55:07 PM PDT 24
Finished	Jul 19 07:02:52 PM PDT 24
Peak memory	610016 kb
Host	smart-37c5588e-ffed-49e4-91eb-7b61bdfab145
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428035545 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3428035545
Directory	/workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1846285550
Short name	T439
Test name
Test status
Simulation time	5967322656 ps
CPU time	313.72 seconds
Started	Jul 19 07:00:40 PM PDT 24
Finished	Jul 19 07:05:55 PM PDT 24
Peak memory	610312 kb
Host	smart-4211c7ef-107f-4e0e-b690-bce55c57fc0c
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846285550 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1846285550
Directory	/workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3073304762
Short name	T673
Test name
Test status
Simulation time	4387083028 ps
CPU time	601.92 seconds
Started	Jul 19 06:56:00 PM PDT 24
Finished	Jul 19 07:06:10 PM PDT 24
Peak memory	609308 kb
Host	smart-12b69077-65c2-4e3b-adb5-8097fb496fe9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307 3304762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.3073304762
Directory	/workspace/2.chip_sw_pwrmgr_wdog_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1246525182
Short name	T206
Test name
Test status
Simulation time	9600101182 ps
CPU time	648.83 seconds
Started	Jul 19 06:56:53 PM PDT 24
Finished	Jul 19 07:07:44 PM PDT 24
Peak memory	623764 kb
Host	smart-b531daad-b71d-4935-b201-357643bba856
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246525182 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1246525182
Directory	/workspace/2.chip_sw_rom_ctrl_integrity_check/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.153820282
Short name	T359
Test name
Test status
Simulation time	10451490422 ps
CPU time	1651.01 seconds
Started	Jul 19 06:54:34 PM PDT 24
Finished	Jul 19 07:23:14 PM PDT 24
Peak memory	610696 kb
Host	smart-b269bbed-14bf-4f89-bc2b-f3f1e5fa5130
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=153820282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.153820282
Directory	/workspace/2.chip_sw_rstmgr_alert_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2173551397
Short name	T275
Test name
Test status
Simulation time	4936528400 ps
CPU time	629.78 seconds
Started	Jul 19 06:55:33 PM PDT 24
Finished	Jul 19 07:06:35 PM PDT 24
Peak memory	610360 kb
Host	smart-e8373f49-6af5-484d-9a2f-bb69c8f51dff
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173551397 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2173551397
Directory	/workspace/2.chip_sw_rstmgr_cpu_info/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2638878343
Short name	T906
Test name
Test status
Simulation time	5826371624 ps
CPU time	434.08 seconds
Started	Jul 19 06:53:05 PM PDT 24
Finished	Jul 19 07:00:20 PM PDT 24
Peak memory	641592 kb
Host	smart-54ab4c48-9d58-4ae0-8d22-c2258a65e41c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2638878343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2638878343
Directory	/workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2347407324
Short name	T670
Test name
Test status
Simulation time	2344430676 ps
CPU time	163.14 seconds
Started	Jul 19 07:08:24 PM PDT 24
Finished	Jul 19 07:11:09 PM PDT 24
Peak memory	609768 kb
Host	smart-170033c1-b530-4012-acbc-a9cbad6c0a41
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347407324 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2347407324
Directory	/workspace/2.chip_sw_rstmgr_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3888563907
Short name	T758
Test name
Test status
Simulation time	5200179320 ps
CPU time	620.73 seconds
Started	Jul 19 06:57:34 PM PDT 24
Finished	Jul 19 07:07:56 PM PDT 24
Peak memory	610316 kb
Host	smart-438ab400-34e2-43ca-9785-e1d44c13dcf8
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888563907 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.3888563907
Directory	/workspace/2.chip_sw_rstmgr_sw_req/latest

Test location	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.4003269126
Short name	T163
Test name
Test status
Simulation time	3149636140 ps
CPU time	257.95 seconds
Started	Jul 19 06:54:40 PM PDT 24
Finished	Jul 19 07:00:04 PM PDT 24
Peak memory	609656 kb
Host	smart-c613ab07-3741-4a6a-bb62-d99296dfccdf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003269126 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.4003269126
Directory	/workspace/2.chip_sw_rstmgr_sw_rst/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1050302421
Short name	T322
Test name
Test status
Simulation time	3102327368 ps
CPU time	271.01 seconds
Started	Jul 19 06:59:34 PM PDT 24
Finished	Jul 19 07:04:06 PM PDT 24
Peak memory	609292 kb
Host	smart-c420d0f1-7969-49cb-a5cc-c43ed070b4f9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1050302421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1050302421
Directory	/workspace/2.chip_sw_rv_core_ibex_address_translation/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3761100646
Short name	T191
Test name
Test status
Simulation time	2618149904 ps
CPU time	338.46 seconds
Started	Jul 19 07:01:00 PM PDT 24
Finished	Jul 19 07:06:44 PM PDT 24
Peak memory	609664 kb
Host	smart-8052cb21-6a87-48ed-8a5a-a9b50b6bbc1f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761100646 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3761100646
Directory	/workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4216975908
Short name	T402
Test name
Test status
Simulation time	4654510760 ps
CPU time	931.22 seconds
Started	Jul 19 06:56:33 PM PDT 24
Finished	Jul 19 07:12:05 PM PDT 24
Peak memory	610016 kb
Host	smart-98d78212-59b4-43f3-be00-f92f3e0adc62
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42169 75908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.4216975908
Directory	/workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1365321056
Short name	T779
Test name
Test status
Simulation time	5089113950 ps
CPU time	985.8 seconds
Started	Jul 19 06:57:19 PM PDT 24
Finished	Jul 19 07:13:46 PM PDT 24
Peak memory	609304 kb
Host	smart-edca0d79-9e58-4c77-a51c-4a93022976ce
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1365321056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1365321056
Directory	/workspace/2.chip_sw_rv_core_ibex_rnd/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.619138810
Short name	T448
Test name
Test status
Simulation time	6024802511 ps
CPU time	868.54 seconds
Started	Jul 19 06:59:25 PM PDT 24
Finished	Jul 19 07:13:55 PM PDT 24
Peak memory	623736 kb
Host	smart-4ffd92ae-025c-4894-bfe0-1dc06e701780
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619138810 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.619138810
Directory	/workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2358503144
Short name	T1010
Test name
Test status
Simulation time	5055462090 ps
CPU time	503.44 seconds
Started	Jul 19 07:01:48 PM PDT 24
Finished	Jul 19 07:10:13 PM PDT 24
Peak memory	624044 kb
Host	smart-fcea14f0-ea3a-4604-b67f-13261c047ac3
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358503144 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2358503144
Directory	/workspace/2.chip_sw_rv_dm_access_after_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.910643892
Short name	T203
Test name
Test status
Simulation time	4561459188 ps
CPU time	436.18 seconds
Started	Jul 19 07:01:12 PM PDT 24
Finished	Jul 19 07:08:31 PM PDT 24
Peak memory	619216 kb
Host	smart-579e5449-2bf2-4ec4-a1ca-4723af08fa32
User	root
Command	/workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910643 892 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.910643892
Directory	/workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.749748733
Short name	T934
Test name
Test status
Simulation time	2871155400 ps
CPU time	189.97 seconds
Started	Jul 19 07:09:38 PM PDT 24
Finished	Jul 19 07:12:58 PM PDT 24
Peak memory	609656 kb
Host	smart-504548f3-a5d0-474f-904e-3240b71f2fe3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749748733 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.749748733
Directory	/workspace/2.chip_sw_rv_plic_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_irq.1573695
Short name	T942
Test name
Test status
Simulation time	2908408080 ps
CPU time	303.74 seconds
Started	Jul 19 06:54:57 PM PDT 24
Finished	Jul 19 07:01:01 PM PDT 24
Peak memory	609224 kb
Host	smart-d43efda4-a4eb-4974-b1bb-e67581de3603
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573695 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_rv_timer_irq.1573695
Directory	/workspace/2.chip_sw_rv_timer_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.472016528
Short name	T283
Test name
Test status
Simulation time	2903354792 ps
CPU time	273.61 seconds
Started	Jul 19 07:09:41 PM PDT 24
Finished	Jul 19 07:14:23 PM PDT 24
Peak memory	609644 kb
Host	smart-8a81c33d-0971-47a8-8b9b-31cee7c07698
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472016528 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_smoketest.472016528
Directory	/workspace/2.chip_sw_rv_timer_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2490313478
Short name	T392
Test name
Test status
Simulation time	2227070451 ps
CPU time	306.9 seconds
Started	Jul 19 07:00:35 PM PDT 24
Finished	Jul 19 07:05:44 PM PDT 24
Peak memory	610356 kb
Host	smart-563fd157-c98f-4d00-a0d4-83518298493b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490313 478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.2490313478
Directory	/workspace/2.chip_sw_sensor_ctrl_status/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1656574601
Short name	T625
Test name
Test status
Simulation time	9343666450 ps
CPU time	1622.22 seconds
Started	Jul 19 06:52:41 PM PDT 24
Finished	Jul 19 07:19:44 PM PDT 24
Peak memory	610436 kb
Host	smart-fc1826e6-0de8-49f0-88bf-a83324da78cd
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656574601 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.1656574601
Directory	/workspace/2.chip_sw_sleep_pwm_pulses/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.793768004
Short name	T587
Test name
Test status
Simulation time	6550765130 ps
CPU time	643.92 seconds
Started	Jul 19 06:58:01 PM PDT 24
Finished	Jul 19 07:08:46 PM PDT 24
Peak memory	610224 kb
Host	smart-007f2554-471b-41cd-8a40-adeb88503b96
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793768004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.793768004
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.698266109
Short name	T899
Test name
Test status
Simulation time	8952803524 ps
CPU time	771.61 seconds
Started	Jul 19 06:58:39 PM PDT 24
Finished	Jul 19 07:11:32 PM PDT 24
Peak memory	610208 kb
Host	smart-6d5f298b-164b-4afd-8be0-3ffe050895b0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698266109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.698266109
Directory	/workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2758275366
Short name	T251
Test name
Test status
Simulation time	5766746693 ps
CPU time	683.81 seconds
Started	Jul 19 06:53:45 PM PDT 24
Finished	Jul 19 07:05:14 PM PDT 24
Peak memory	624868 kb
Host	smart-8fcd2152-1a1e-495c-a7dd-91e23c05db27
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758275366 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.2758275366
Directory	/workspace/2.chip_sw_spi_device_pass_through/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.104464428
Short name	T28
Test name
Test status
Simulation time	4015366437 ps
CPU time	555.34 seconds
Started	Jul 19 06:56:01 PM PDT 24
Finished	Jul 19 07:05:24 PM PDT 24
Peak memory	624852 kb
Host	smart-82b2a6aa-c751-4776-adf6-c7ccd30aa8e2
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104464428 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.104464428
Directory	/workspace/2.chip_sw_spi_device_pass_through_collision/latest

Test location	/workspace/coverage/default/2.chip_sw_spi_device_tpm.564495690
Short name	T51
Test name
Test status
Simulation time	3454729243 ps
CPU time	333.26 seconds
Started	Jul 19 06:56:29 PM PDT 24
Finished	Jul 19 07:02:03 PM PDT 24
Peak memory	618352 kb
Host	smart-9cf5bff1-f286-47ec-9658-551c70d0c68b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564495690 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.564495690
Directory	/workspace/2.chip_sw_spi_device_tpm/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1684801332
Short name	T224
Test name
Test status
Simulation time	7915127606 ps
CPU time	1041.74 seconds
Started	Jul 19 06:58:45 PM PDT 24
Finished	Jul 19 07:16:07 PM PDT 24
Peak memory	610336 kb
Host	smart-60bed2b3-ad52-4381-80b1-11a0f947b923
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684801332 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1684801332
Directory	/workspace/2.chip_sw_sram_ctrl_execution_main/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2813513032
Short name	T827
Test name
Test status
Simulation time	3745083092 ps
CPU time	545.12 seconds
Started	Jul 19 06:57:21 PM PDT 24
Finished	Jul 19 07:06:27 PM PDT 24
Peak memory	609608 kb
Host	smart-b40cc665-e9c1-4f2e-a6ed-2b8ef361d87e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813513032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2813513032
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2662591785
Short name	T76
Test name
Test status
Simulation time	3642254404 ps
CPU time	535.3 seconds
Started	Jul 19 06:58:30 PM PDT 24
Finished	Jul 19 07:07:26 PM PDT 24
Peak memory	610432 kb
Host	smart-f143a1a6-1762-4480-9f65-9e2e89382b48
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662591785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2662591785
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.918510136
Short name	T313
Test name
Test status
Simulation time	4830766961 ps
CPU time	684.98 seconds
Started	Jul 19 07:00:58 PM PDT 24
Finished	Jul 19 07:12:30 PM PDT 24
Peak memory	610472 kb
Host	smart-1adf7a3a-fb78-4428-9e4d-deb05f5c7583
User	root
Command	/workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918510136 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.918510136
Directory	/workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.350527338
Short name	T995
Test name
Test status
Simulation time	2897054632 ps
CPU time	210.77 seconds
Started	Jul 19 07:02:09 PM PDT 24
Finished	Jul 19 07:05:40 PM PDT 24
Peak memory	609648 kb
Host	smart-b2f0d7e3-ece1-4cc7-9bb1-2a9cd452d9de
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350527338 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_sram_ctrl_smoketest.350527338
Directory	/workspace/2.chip_sw_sram_ctrl_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1734080523
Short name	T959
Test name
Test status
Simulation time	20161806100 ps
CPU time	3090.63 seconds
Started	Jul 19 06:57:32 PM PDT 24
Finished	Jul 19 07:49:03 PM PDT 24
Peak memory	609512 kb
Host	smart-3eca8222-5123-45b9-9f74-04da93b26abf
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734080523 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1734080523
Directory	/workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2316268276
Short name	T255
Test name
Test status
Simulation time	5434417571 ps
CPU time	711.53 seconds
Started	Jul 19 06:55:29 PM PDT 24
Finished	Jul 19 07:07:58 PM PDT 24
Peak memory	613672 kb
Host	smart-5d3d83df-6ebd-4c17-9df8-a56d92b8cc42
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316268276 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2316268276
Directory	/workspace/2.chip_sw_sysrst_ctrl_in_irq/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2662069371
Short name	T258
Test name
Test status
Simulation time	3727612970 ps
CPU time	391.86 seconds
Started	Jul 19 06:56:29 PM PDT 24
Finished	Jul 19 07:03:04 PM PDT 24
Peak memory	613260 kb
Host	smart-ef2e2044-262e-420e-a056-bb711a37c52a
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662069371 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2662069371
Directory	/workspace/2.chip_sw_sysrst_ctrl_inputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.622553416
Short name	T36
Test name
Test status
Simulation time	3385821250 ps
CPU time	383.57 seconds
Started	Jul 19 06:55:31 PM PDT 24
Finished	Jul 19 07:02:28 PM PDT 24
Peak memory	609284 kb
Host	smart-9b584612-9a0e-45aa-a742-d5655829d407
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622553416 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.622553416
Directory	/workspace/2.chip_sw_sysrst_ctrl_outputs/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1734797105
Short name	T902
Test name
Test status
Simulation time	22079178410 ps
CPU time	1471.61 seconds
Started	Jul 19 06:57:38 PM PDT 24
Finished	Jul 19 07:22:11 PM PDT 24
Peak memory	613584 kb
Host	smart-a375140d-ac82-4736-a775-b2f9add411b3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17347971 05 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1734797105
Directory	/workspace/2.chip_sw_sysrst_ctrl_reset/latest

Test location	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2661050837
Short name	T49
Test name
Test status
Simulation time	5980189920 ps
CPU time	684.58 seconds
Started	Jul 19 06:56:44 PM PDT 24
Finished	Jul 19 07:08:09 PM PDT 24
Peak memory	610376 kb
Host	smart-c8525c8d-70c9-4e25-b74f-a88a1c63aca7
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661050837 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2661050837
Directory	/workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.844483876
Short name	T981
Test name
Test status
Simulation time	4286170596 ps
CPU time	692.84 seconds
Started	Jul 19 06:54:39 PM PDT 24
Finished	Jul 19 07:07:19 PM PDT 24
Peak memory	618820 kb
Host	smart-b1f76747-7274-48aa-b88c-55d0e1412c96
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=844483876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.844483876
Directory	/workspace/2.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_smoketest.3508620123
Short name	T557
Test name
Test status
Simulation time	3332279174 ps
CPU time	303.45 seconds
Started	Jul 19 07:01:00 PM PDT 24
Finished	Jul 19 07:06:09 PM PDT 24
Peak memory	616104 kb
Host	smart-be4ab05c-4705-4cfb-adf5-f0813282370b
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508620123 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.3508620123
Directory	/workspace/2.chip_sw_uart_smoketest/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx.3748877925
Short name	T720
Test name
Test status
Simulation time	3798424688 ps
CPU time	700.77 seconds
Started	Jul 19 06:53:15 PM PDT 24
Finished	Jul 19 07:04:56 PM PDT 24
Peak memory	623776 kb
Host	smart-3e6c5c33-b92b-4210-aa11-d021b49255d2
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748877925 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3748877925
Directory	/workspace/2.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3453193347
Short name	T811
Test name
Test status
Simulation time	8432339586 ps
CPU time	1868.92 seconds
Started	Jul 19 06:55:08 PM PDT 24
Finished	Jul 19 07:27:10 PM PDT 24
Peak memory	623092 kb
Host	smart-2dfa2fb6-3907-4715-b3a8-a7662cc000dc
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453193347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3453193347
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.436363926
Short name	T665
Test name
Test status
Simulation time	8854444550 ps
CPU time	1219.45 seconds
Started	Jul 19 06:53:47 PM PDT 24
Finished	Jul 19 07:14:15 PM PDT 24
Peak memory	624700 kb
Host	smart-090d3c00-f6b7-437b-86fa-c1f22012e5c2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436363926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.436363926
Directory	/workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2792199303
Short name	T760
Test name
Test status
Simulation time	78054940446 ps
CPU time	14242.9 seconds
Started	Jul 19 06:55:06 PM PDT 24
Finished	Jul 19 10:53:24 PM PDT 24
Peak memory	634108 kb
Host	smart-db3c6f25-a68d-4dfe-a003-6d1d82739de7
User	root
Command	/workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2792199303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.2792199303
Directory	/workspace/2.chip_sw_uart_tx_rx_bootstrap/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2009559060
Short name	T659
Test name
Test status
Simulation time	4935571628 ps
CPU time	765.71 seconds
Started	Jul 19 06:53:26 PM PDT 24
Finished	Jul 19 07:06:12 PM PDT 24
Peak memory	624100 kb
Host	smart-f5c96474-9293-4af2-810a-db9ebad8b092
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009559060 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.2009559060
Directory	/workspace/2.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.848020492
Short name	T599
Test name
Test status
Simulation time	4477487110 ps
CPU time	628.96 seconds
Started	Jul 19 06:53:24 PM PDT 24
Finished	Jul 19 07:03:54 PM PDT 24
Peak memory	624052 kb
Host	smart-04496b0d-a734-4f53-ac7a-7bb1e4f36475
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848020492 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.848020492
Directory	/workspace/2.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2544475169
Short name	T975
Test name
Test status
Simulation time	4620858000 ps
CPU time	672.4 seconds
Started	Jul 19 06:53:24 PM PDT 24
Finished	Jul 19 07:04:37 PM PDT 24
Peak memory	622792 kb
Host	smart-b08a0546-67e1-492c-b25a-f88cac444052
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544475169 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.2544475169
Directory	/workspace/2.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_dev.3666943144
Short name	T767
Test name
Test status
Simulation time	3855012550 ps
CPU time	244.08 seconds
Started	Jul 19 06:58:25 PM PDT 24
Finished	Jul 19 07:02:29 PM PDT 24
Peak memory	622048 kb
Host	smart-e5807c83-1048-4025-8e65-653e6c13a5ea
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3666943144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3666943144
Directory	/workspace/2.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_prod.1362974746
Short name	T663
Test name
Test status
Simulation time	17431370924 ps
CPU time	1789.51 seconds
Started	Jul 19 06:59:50 PM PDT 24
Finished	Jul 19 07:29:42 PM PDT 24
Peak memory	620928 kb
Host	smart-3699a5f5-84cc-44f4-ba57-84f71dd9d688
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362974746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1362974746
Directory	/workspace/2.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3930485729
Short name	T818
Test name
Test status
Simulation time	5356389560 ps
CPU time	490.72 seconds
Started	Jul 19 06:58:04 PM PDT 24
Finished	Jul 19 07:06:15 PM PDT 24
Peak memory	620892 kb
Host	smart-e00fb4e9-46dc-48dd-95e7-2cc35762d2f2
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3930485729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3930485729
Directory	/workspace/2.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_dev.2494387294
Short name	T806
Test name
Test status
Simulation time	14936261718 ps
CPU time	3827.05 seconds
Started	Jul 19 07:04:13 PM PDT 24
Finished	Jul 19 08:08:02 PM PDT 24
Peak memory	610304 kb
Host	smart-f293683d-8b1b-4f99-a341-f571ab40009c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494387294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2494387294
Directory	/workspace/2.rom_e2e_asm_init_dev/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1898044795
Short name	T967
Test name
Test status
Simulation time	15721376206 ps
CPU time	3849.14 seconds
Started	Jul 19 07:06:33 PM PDT 24
Finished	Jul 19 08:10:44 PM PDT 24
Peak memory	610404 kb
Host	smart-b2c6c180-e02b-4544-a3e4-6ad80faa1c3a
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898044795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1898044795
Directory	/workspace/2.rom_e2e_asm_init_prod/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3220897076
Short name	T351
Test name
Test status
Simulation time	15628759127 ps
CPU time	4552.14 seconds
Started	Jul 19 07:04:26 PM PDT 24
Finished	Jul 19 08:20:28 PM PDT 24
Peak memory	611200 kb
Host	smart-530bc7f9-444a-4af7-baa9-e73115c12dde
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220897076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3220897076
Directory	/workspace/2.rom_e2e_asm_init_prod_end/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_rma.4266784986
Short name	T566
Test name
Test status
Simulation time	14688885723 ps
CPU time	3631.78 seconds
Started	Jul 19 07:06:59 PM PDT 24
Finished	Jul 19 08:07:33 PM PDT 24
Peak memory	610296 kb
Host	smart-52de7259-5cf9-40a5-a761-c3b6726e82ac
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266784986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.4266784986
Directory	/workspace/2.rom_e2e_asm_init_rma/latest

Test location	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.672142819
Short name	T922
Test name
Test status
Simulation time	11299377898 ps
CPU time	2567.62 seconds
Started	Jul 19 07:02:44 PM PDT 24
Finished	Jul 19 07:45:32 PM PDT 24
Peak memory	610616 kb
Host	smart-8b8c6d25-01a1-45c1-acaf-e436c5996259
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672142819 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.672142819
Directory	/workspace/2.rom_e2e_asm_init_test_unlocked0/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1447532776
Short name	T731
Test name
Test status
Simulation time	14946900474 ps
CPU time	3972.73 seconds
Started	Jul 19 07:06:01 PM PDT 24
Finished	Jul 19 08:12:15 PM PDT 24
Peak memory	610300 kb
Host	smart-49c1f2cd-ca59-4196-8b46-dbb482d8c840
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447532776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1447532776
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.1195200008
Short name	T867
Test name
Test status
Simulation time	14687657304 ps
CPU time	3511.97 seconds
Started	Jul 19 07:04:16 PM PDT 24
Finished	Jul 19 08:02:51 PM PDT 24
Peak memory	610312 kb
Host	smart-e2b27303-3158-40aa-a2a7-b53dab66c53f
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195200008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.1195200008
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2457681530
Short name	T609
Test name
Test status
Simulation time	15648499420 ps
CPU time	4051.97 seconds
Started	Jul 19 07:06:59 PM PDT 24
Finished	Jul 19 08:14:33 PM PDT 24
Peak memory	610128 kb
Host	smart-8bda2ae4-4271-402b-97c9-7ddf747c8cd2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457681530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.2457681530
Directory	/workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest

Test location	/workspace/coverage/default/2.rom_e2e_self_hash.1842774592
Short name	T1009
Test name
Test status
Simulation time	26453338680 ps
CPU time	6952.72 seconds
Started	Jul 19 07:05:49 PM PDT 24
Finished	Jul 19 09:01:42 PM PDT 24
Peak memory	610188 kb
Host	smart-b7e80043-1b2b-4c43-9d74-de267280b5b3
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842774592 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1842774592
Directory	/workspace/2.rom_e2e_self_hash/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1545362856
Short name	T851
Test name
Test status
Simulation time	14912759193 ps
CPU time	4133.47 seconds
Started	Jul 19 07:03:47 PM PDT 24
Finished	Jul 19 08:12:42 PM PDT 24
Peak memory	611176 kb
Host	smart-9ba72050-5224-4bcb-8ae5-4f22a5658b12
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545362856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.1545362856
Directory	/workspace/2.rom_e2e_shutdown_exception_c/latest

Test location	/workspace/coverage/default/2.rom_e2e_shutdown_output.3767813398
Short name	T843
Test name
Test status
Simulation time	28654493659 ps
CPU time	3814.52 seconds
Started	Jul 19 07:06:35 PM PDT 24
Finished	Jul 19 08:10:12 PM PDT 24
Peak memory	611352 kb
Host	smart-6f06e47d-afa2-4636-afdb-6b7cec556e84
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767813398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3767813398
Directory	/workspace/2.rom_e2e_shutdown_output/latest

Test location	/workspace/coverage/default/2.rom_e2e_smoke.2631773179
Short name	T633
Test name
Test status
Simulation time	14706426220 ps
CPU time	3412.88 seconds
Started	Jul 19 07:08:02 PM PDT 24
Finished	Jul 19 08:04:56 PM PDT 24
Peak memory	609480 kb
Host	smart-f7d0ccb7-c786-4174-b293-e0ba78afc889
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2631773179 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.2631773179
Directory	/workspace/2.rom_e2e_smoke/latest

Test location	/workspace/coverage/default/2.rom_e2e_static_critical.150378993
Short name	T832
Test name
Test status
Simulation time	17408611402 ps
CPU time	4847.92 seconds
Started	Jul 19 07:08:09 PM PDT 24
Finished	Jul 19 08:28:59 PM PDT 24
Peak memory	609992 kb
Host	smart-d84faa46-4601-4dce-b2fb-3bf00e870d19
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150378993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.150378993
Directory	/workspace/2.rom_e2e_static_critical/latest

Test location	/workspace/coverage/default/2.rom_keymgr_functest.2235100873
Short name	T334
Test name
Test status
Simulation time	4070103928 ps
CPU time	523.01 seconds
Started	Jul 19 07:01:49 PM PDT 24
Finished	Jul 19 07:10:34 PM PDT 24
Peak memory	609928 kb
Host	smart-ec51b4d9-6e5d-43bc-9756-9ab906648e78
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235100873 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2235100873
Directory	/workspace/2.rom_keymgr_functest/latest

Test location	/workspace/coverage/default/2.rom_raw_unlock.2241896264
Short name	T166
Test name
Test status
Simulation time	6463041051 ps
CPU time	271.34 seconds
Started	Jul 19 07:00:26 PM PDT 24
Finished	Jul 19 07:04:59 PM PDT 24
Peak memory	623836 kb
Host	smart-be6e3f90-dd5d-489f-bd73-a83cf3c9f9d6
User	root
Command	/workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2241896264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2241896264
Directory	/workspace/2.rom_raw_unlock/latest

Test location	/workspace/coverage/default/2.rom_volatile_raw_unlock.1806298903
Short name	T298
Test name
Test status
Simulation time	2650512268 ps
CPU time	102.07 seconds
Started	Jul 19 07:00:11 PM PDT 24
Finished	Jul 19 07:01:54 PM PDT 24
Peak memory	617120 kb
Host	smart-233128aa-599e-4810-92ab-c385826f613c
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806298903 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.1806298903
Directory	/workspace/2.rom_volatile_raw_unlock/latest

Test location	/workspace/coverage/default/20.chip_sw_all_escalation_resets.2727742502
Short name	T498
Test name
Test status
Simulation time	5312328928 ps
CPU time	872.21 seconds
Started	Jul 19 07:08:21 PM PDT 24
Finished	Jul 19 07:22:55 PM PDT 24
Peak memory	650060 kb
Host	smart-9b860e81-3736-4e74-83a4-0829916d31c1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2727742502 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2727742502
Directory	/workspace/20.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422948120
Short name	T489
Test name
Test status
Simulation time	3644668660 ps
CPU time	505.38 seconds
Started	Jul 19 07:04:51 PM PDT 24
Finished	Jul 19 07:13:18 PM PDT 24
Peak memory	648648 kb
Host	smart-16bfc2d1-d437-4339-ac3d-01f87f546fab
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422948120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3422948120
Directory	/workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/21.chip_sw_all_escalation_resets.361036854
Short name	T467
Test name
Test status
Simulation time	4844999292 ps
CPU time	472.81 seconds
Started	Jul 19 07:05:21 PM PDT 24
Finished	Jul 19 07:13:17 PM PDT 24
Peak memory	619776 kb
Host	smart-67c79d27-3ef2-4b1f-b04c-07774e246a1a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 361036854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.361036854
Directory	/workspace/21.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2625488100
Short name	T515
Test name
Test status
Simulation time	5029374480 ps
CPU time	821.43 seconds
Started	Jul 19 07:06:15 PM PDT 24
Finished	Jul 19 07:19:58 PM PDT 24
Peak memory	650076 kb
Host	smart-b5f21c16-dc80-4d5c-b06a-27d0dc99bd7c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2625488100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2625488100
Directory	/workspace/22.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1031565725
Short name	T141
Test name
Test status
Simulation time	4229274120 ps
CPU time	473.81 seconds
Started	Jul 19 07:06:13 PM PDT 24
Finished	Jul 19 07:14:08 PM PDT 24
Peak memory	648952 kb
Host	smart-fcb05d7d-06ed-4e26-b41b-5b4b0ddf7ce3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031565725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1031565725
Directory	/workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/24.chip_sw_all_escalation_resets.908791605
Short name	T511
Test name
Test status
Simulation time	5175279760 ps
CPU time	636.15 seconds
Started	Jul 19 07:07:18 PM PDT 24
Finished	Jul 19 07:17:58 PM PDT 24
Peak memory	650120 kb
Host	smart-1b05df40-eded-4dfb-b465-13827130d8fc
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 908791605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.908791605
Directory	/workspace/24.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.229734399
Short name	T835
Test name
Test status
Simulation time	3219228500 ps
CPU time	405.37 seconds
Started	Jul 19 07:06:30 PM PDT 24
Finished	Jul 19 07:13:17 PM PDT 24
Peak memory	618520 kb
Host	smart-e05a6da7-623b-4966-94fd-9f72a8fc8ee6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229734399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.229734399
Directory	/workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2140271542
Short name	T291
Test name
Test status
Simulation time	6049949256 ps
CPU time	550.17 seconds
Started	Jul 19 07:05:20 PM PDT 24
Finished	Jul 19 07:14:32 PM PDT 24
Peak memory	650480 kb
Host	smart-faa8859b-e070-4768-b9d3-3b0f235268b2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2140271542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.2140271542
Directory	/workspace/25.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638917909
Short name	T788
Test name
Test status
Simulation time	3274914284 ps
CPU time	340.7 seconds
Started	Jul 19 07:07:48 PM PDT 24
Finished	Jul 19 07:13:30 PM PDT 24
Peak memory	648824 kb
Host	smart-dc931fa6-8026-42f3-bf33-de5ef6c19509
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638917909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1638917909
Directory	/workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/26.chip_sw_all_escalation_resets.1278121236
Short name	T328
Test name
Test status
Simulation time	4415549988 ps
CPU time	656.91 seconds
Started	Jul 19 07:05:36 PM PDT 24
Finished	Jul 19 07:16:37 PM PDT 24
Peak memory	649864 kb
Host	smart-62083053-6704-4f12-8cd5-47ec26e5fce6
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1278121236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.1278121236
Directory	/workspace/26.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2072215758
Short name	T495
Test name
Test status
Simulation time	3335326558 ps
CPU time	461.58 seconds
Started	Jul 19 07:06:34 PM PDT 24
Finished	Jul 19 07:14:17 PM PDT 24
Peak memory	648824 kb
Host	smart-e873abbf-f60e-4e6b-8ead-20b741848b22
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072215758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2072215758
Directory	/workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/29.chip_sw_all_escalation_resets.201732982
Short name	T488
Test name
Test status
Simulation time	4893100168 ps
CPU time	509.93 seconds
Started	Jul 19 07:06:28 PM PDT 24
Finished	Jul 19 07:14:59 PM PDT 24
Peak memory	649956 kb
Host	smart-09b3bf0a-f0d4-4df2-a10b-9387dd20d0fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 201732982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.201732982
Directory	/workspace/29.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.979850943
Short name	T487
Test name
Test status
Simulation time	3554149720 ps
CPU time	446.9 seconds
Started	Jul 19 07:09:37 PM PDT 24
Finished	Jul 19 07:17:13 PM PDT 24
Peak memory	648684 kb
Host	smart-16e9a7e2-e939-44f1-aa03-7f3b8432a2ba
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979850943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw _alert_handler_lpg_sleep_mode_alerts.979850943
Directory	/workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/3.chip_sw_all_escalation_resets.1413275335
Short name	T484
Test name
Test status
Simulation time	6387913032 ps
CPU time	604.7 seconds
Started	Jul 19 07:09:22 PM PDT 24
Finished	Jul 19 07:19:42 PM PDT 24
Peak memory	650036 kb
Host	smart-c232fb8a-f219-41ec-a333-de59727d8edf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1413275335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.1413275335
Directory	/workspace/3.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.65919364
Short name	T301
Test name
Test status
Simulation time	5546736928 ps
CPU time	738.12 seconds
Started	Jul 19 07:00:57 PM PDT 24
Finished	Jul 19 07:13:22 PM PDT 24
Peak memory	610596 kb
Host	smart-97264c2c-cab7-474d-a353-3f6c5f678971
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=65919364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.65919364
Directory	/workspace/3.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1425924842
Short name	T704
Test name
Test status
Simulation time	12418938979 ps
CPU time	676.2 seconds
Started	Jul 19 07:01:54 PM PDT 24
Finished	Jul 19 07:13:11 PM PDT 24
Peak memory	624768 kb
Host	smart-d12dca76-f9e5-4159-94ca-e8c90e02f85f
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425924842 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.1425924842
Directory	/workspace/3.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2110547800
Short name	T97
Test name
Test status
Simulation time	6039149552 ps
CPU time	800.7 seconds
Started	Jul 19 07:08:42 PM PDT 24
Finished	Jul 19 07:22:07 PM PDT 24
Peak memory	609376 kb
Host	smart-c4778950-34c9-44d8-bcc7-5a5870ee9c25
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21105478 00 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.2110547800
Directory	/workspace/3.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.566260055
Short name	T987
Test name
Test status
Simulation time	12651701910 ps
CPU time	2261.94 seconds
Started	Jul 19 07:02:31 PM PDT 24
Finished	Jul 19 07:40:14 PM PDT 24
Peak memory	618828 kb
Host	smart-c2a97bda-4b59-4388-8bb5-b910c9299d34
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=566260055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.566260055
Directory	/workspace/3.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2623535340
Short name	T306
Test name
Test status
Simulation time	4122034488 ps
CPU time	593.56 seconds
Started	Jul 19 07:01:20 PM PDT 24
Finished	Jul 19 07:11:15 PM PDT 24
Peak memory	622484 kb
Host	smart-9b4d56c9-3cfe-4475-9192-d716454cfdbf
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623535340 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2623535340
Directory	/workspace/3.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4216658615
Short name	T993
Test name
Test status
Simulation time	4387492843 ps
CPU time	756.78 seconds
Started	Jul 19 07:02:12 PM PDT 24
Finished	Jul 19 07:14:50 PM PDT 24
Peak memory	624680 kb
Host	smart-0f453e7f-d498-451c-bdbb-d85d8f2c4dec
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216658615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.4216658615
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1019829308
Short name	T445
Test name
Test status
Simulation time	8401999725 ps
CPU time	928.96 seconds
Started	Jul 19 07:01:40 PM PDT 24
Finished	Jul 19 07:17:10 PM PDT 24
Peak memory	624668 kb
Host	smart-7f946a41-3f38-46b7-aa39-31a5efbfa340
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019829308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1019829308
Directory	/workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1379837333
Short name	T794
Test name
Test status
Simulation time	3714990460 ps
CPU time	707.73 seconds
Started	Jul 19 07:01:22 PM PDT 24
Finished	Jul 19 07:13:12 PM PDT 24
Peak memory	623672 kb
Host	smart-f7c350a6-0158-4d4d-b652-c95291ec5818
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379837333 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1379837333
Directory	/workspace/3.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3762785602
Short name	T140
Test name
Test status
Simulation time	5000068542 ps
CPU time	666.72 seconds
Started	Jul 19 07:04:30 PM PDT 24
Finished	Jul 19 07:15:44 PM PDT 24
Peak memory	624040 kb
Host	smart-e3265144-b70c-4fc2-a184-aaccad094c2b
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762785602 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.3762785602
Directory	/workspace/3.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3346136455
Short name	T753
Test name
Test status
Simulation time	4033546784 ps
CPU time	605.66 seconds
Started	Jul 19 07:03:27 PM PDT 24
Finished	Jul 19 07:13:34 PM PDT 24
Peak memory	623780 kb
Host	smart-f04f6473-1157-4120-b179-ece3e1bcd532
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346136455 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3346136455
Directory	/workspace/3.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_dev.186648795
Short name	T564
Test name
Test status
Simulation time	2373753890 ps
CPU time	136.57 seconds
Started	Jul 19 07:02:24 PM PDT 24
Finished	Jul 19 07:04:41 PM PDT 24
Peak memory	620080 kb
Host	smart-9c1e07a3-944a-4764-9b57-3374bac612c7
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=186648795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.186648795
Directory	/workspace/3.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_prod.3317761973
Short name	T978
Test name
Test status
Simulation time	5210951060 ps
CPU time	471.54 seconds
Started	Jul 19 07:01:00 PM PDT 24
Finished	Jul 19 07:08:57 PM PDT 24
Peak memory	620908 kb
Host	smart-9943289b-5eb9-475c-8070-118baf608599
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317761973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3317761973
Directory	/workspace/3.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_rma.1422927248
Short name	T718
Test name
Test status
Simulation time	5823613634 ps
CPU time	615.81 seconds
Started	Jul 19 07:01:24 PM PDT 24
Finished	Jul 19 07:11:42 PM PDT 24
Peak memory	620908 kb
Host	smart-9ba3ef65-0bed-49f3-a42b-e06b040a91b5
User	root
Command	/workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422927248 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1422927248
Directory	/workspace/3.chip_tap_straps_rma/latest

Test location	/workspace/coverage/default/3.chip_tap_straps_testunlock0.3768096802
Short name	T621
Test name
Test status
Simulation time	6138767265 ps
CPU time	608.15 seconds
Started	Jul 19 07:01:34 PM PDT 24
Finished	Jul 19 07:11:44 PM PDT 24
Peak memory	630864 kb
Host	smart-f03a82bb-0cf3-49b1-bd61-b76a64afe245
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768096802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3768096802
Directory	/workspace/3.chip_tap_straps_testunlock0/latest

Test location	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2582218792
Short name	T516
Test name
Test status
Simulation time	3872191640 ps
CPU time	414.84 seconds
Started	Jul 19 07:07:34 PM PDT 24
Finished	Jul 19 07:14:33 PM PDT 24
Peak memory	648656 kb
Host	smart-304ffe48-7ea9-401f-9298-a9bcb50f6ea4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582218792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2582218792
Directory	/workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/30.chip_sw_all_escalation_resets.3582008737
Short name	T510
Test name
Test status
Simulation time	4695705876 ps
CPU time	776.54 seconds
Started	Jul 19 07:07:22 PM PDT 24
Finished	Jul 19 07:20:23 PM PDT 24
Peak memory	650012 kb
Host	smart-a5dad6b5-5ef1-4275-8589-8cdf50157920
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3582008737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3582008737
Directory	/workspace/30.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/32.chip_sw_all_escalation_resets.248505246
Short name	T538
Test name
Test status
Simulation time	5703258232 ps
CPU time	621.92 seconds
Started	Jul 19 07:06:29 PM PDT 24
Finished	Jul 19 07:16:52 PM PDT 24
Peak memory	650080 kb
Host	smart-ea7c5cb0-34fd-4e57-a019-8be99b385985
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 248505246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.248505246
Directory	/workspace/32.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/34.chip_sw_all_escalation_resets.4241449323
Short name	T503
Test name
Test status
Simulation time	6004791434 ps
CPU time	605.99 seconds
Started	Jul 19 07:07:30 PM PDT 24
Finished	Jul 19 07:17:41 PM PDT 24
Peak memory	650116 kb
Host	smart-27494592-e8b7-4dd5-8397-aae7e4c82ce7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4241449323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.4241449323
Directory	/workspace/34.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.4084854581
Short name	T485
Test name
Test status
Simulation time	3797530630 ps
CPU time	366.81 seconds
Started	Jul 19 07:06:50 PM PDT 24
Finished	Jul 19 07:12:58 PM PDT 24
Peak memory	648772 kb
Host	smart-504b736a-a414-472e-80c5-d7493321e10b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084854581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4084854581
Directory	/workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1780948827
Short name	T235
Test name
Test status
Simulation time	3916290960 ps
CPU time	555.52 seconds
Started	Jul 19 07:07:02 PM PDT 24
Finished	Jul 19 07:16:18 PM PDT 24
Peak memory	648644 kb
Host	smart-4805867d-1e47-4424-a1da-ad4ca96dcae3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780948827 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1780948827
Directory	/workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/37.chip_sw_all_escalation_resets.200437499
Short name	T493
Test name
Test status
Simulation time	4824875250 ps
CPU time	538.5 seconds
Started	Jul 19 07:08:34 PM PDT 24
Finished	Jul 19 07:17:34 PM PDT 24
Peak memory	650048 kb
Host	smart-50666c53-8e77-4d4a-bb7c-f33d99d164d3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 200437499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.200437499
Directory	/workspace/37.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2626482032
Short name	T272
Test name
Test status
Simulation time	3938587598 ps
CPU time	430.83 seconds
Started	Jul 19 07:09:13 PM PDT 24
Finished	Jul 19 07:16:36 PM PDT 24
Peak memory	648792 kb
Host	smart-d10120d6-728e-4796-a9c2-e521046ebb8e
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626482032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2626482032
Directory	/workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1728821826
Short name	T925
Test name
Test status
Simulation time	5423158020 ps
CPU time	658.77 seconds
Started	Jul 19 07:09:28 PM PDT 24
Finished	Jul 19 07:20:40 PM PDT 24
Peak memory	650080 kb
Host	smart-db5ad8d7-ec61-4499-b570-56f7a99c3323
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1728821826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1728821826
Directory	/workspace/38.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277518861
Short name	T513
Test name
Test status
Simulation time	3430136920 ps
CPU time	432.63 seconds
Started	Jul 19 07:07:47 PM PDT 24
Finished	Jul 19 07:15:02 PM PDT 24
Peak memory	649080 kb
Host	smart-def74a77-b847-468c-a13b-2e9a2934ea38
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277518861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1277518861
Directory	/workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1312078519
Short name	T345
Test name
Test status
Simulation time	3946067800 ps
CPU time	360.51 seconds
Started	Jul 19 07:03:13 PM PDT 24
Finished	Jul 19 07:09:15 PM PDT 24
Peak memory	648572 kb
Host	smart-3af9f9cb-1cfc-4c88-87e0-29d6aa18a5f0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312078519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1312078519
Directory	/workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2967296666
Short name	T127
Test name
Test status
Simulation time	5481524592 ps
CPU time	573.83 seconds
Started	Jul 19 07:04:08 PM PDT 24
Finished	Jul 19 07:13:43 PM PDT 24
Peak memory	650584 kb
Host	smart-8e50c7fc-1570-4bfc-8f86-e9404bc20fd2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2967296666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2967296666
Directory	/workspace/4.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2067997602
Short name	T848
Test name
Test status
Simulation time	8007823360 ps
CPU time	409.81 seconds
Started	Jul 19 07:02:39 PM PDT 24
Finished	Jul 19 07:09:29 PM PDT 24
Peak memory	609892 kb
Host	smart-45a7cea1-8437-4f26-ae1d-0f621593ec09
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2067997602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2067997602
Directory	/workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest

Test location	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3383714376
Short name	T588
Test name
Test status
Simulation time	8998384620 ps
CPU time	2128.59 seconds
Started	Jul 19 07:04:17 PM PDT 24
Finished	Jul 19 07:39:51 PM PDT 24
Peak memory	610128 kb
Host	smart-0af28b26-8de6-4b7c-ab0c-eaff040b8c89
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383714376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3383714376
Directory	/workspace/4.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3063872867
Short name	T1017
Test name
Test status
Simulation time	5865529688 ps
CPU time	527.69 seconds
Started	Jul 19 07:02:11 PM PDT 24
Finished	Jul 19 07:11:00 PM PDT 24
Peak memory	610600 kb
Host	smart-8a631000-ddf4-4101-8e43-b40f8c29ff71
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3063872867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.3063872867
Directory	/workspace/4.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3926014203
Short name	T701
Test name
Test status
Simulation time	5098412035 ps
CPU time	366.2 seconds
Started	Jul 19 07:02:57 PM PDT 24
Finished	Jul 19 07:09:04 PM PDT 24
Peak memory	621004 kb
Host	smart-3f085d7a-0d32-4abf-862f-71842932b476
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926014203 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.3926014203
Directory	/workspace/4.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3971507346
Short name	T96
Test name
Test status
Simulation time	5860174242 ps
CPU time	606.53 seconds
Started	Jul 19 07:02:45 PM PDT 24
Finished	Jul 19 07:12:52 PM PDT 24
Peak memory	609392 kb
Host	smart-ecc11432-9626-4d08-a2a9-f6725ef42d9e
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715073 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.3971507346
Directory	/workspace/4.chip_sw_sensor_ctrl_alert/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.334591204
Short name	T829
Test name
Test status
Simulation time	3665091512 ps
CPU time	614.49 seconds
Started	Jul 19 07:03:57 PM PDT 24
Finished	Jul 19 07:14:13 PM PDT 24
Peak memory	618556 kb
Host	smart-283e6f77-42e5-4742-a923-e3e2813c3f8b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=334591204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.334591204
Directory	/workspace/4.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1972590350
Short name	T376
Test name
Test status
Simulation time	3497780420 ps
CPU time	705.52 seconds
Started	Jul 19 07:04:38 PM PDT 24
Finished	Jul 19 07:16:30 PM PDT 24
Peak memory	623744 kb
Host	smart-38f09a8a-74f8-4a72-92fc-655ff23b9a00
User	root
Command	/workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972590350 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.1972590350
Directory	/workspace/4.chip_sw_uart_tx_rx/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4100048087
Short name	T617
Test name
Test status
Simulation time	9432159639 ps
CPU time	1645.12 seconds
Started	Jul 19 07:03:17 PM PDT 24
Finished	Jul 19 07:30:43 PM PDT 24
Peak memory	624708 kb
Host	smart-e44fb347-0160-481f-b7eb-e313d23373a2
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100048087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.4100048087
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2694562694
Short name	T876
Test name
Test status
Simulation time	4182260438 ps
CPU time	394.45 seconds
Started	Jul 19 07:02:23 PM PDT 24
Finished	Jul 19 07:08:58 PM PDT 24
Peak memory	624668 kb
Host	smart-1c928a45-7716-425d-af08-95970604a372
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694562694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2694562694
Directory	/workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3196678242
Short name	T703
Test name
Test status
Simulation time	4610525906 ps
CPU time	680.28 seconds
Started	Jul 19 07:02:02 PM PDT 24
Finished	Jul 19 07:13:23 PM PDT 24
Peak memory	622776 kb
Host	smart-aba2915d-eefa-493b-89c5-05cf3c5a7257
User	root
Command	/workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196678242 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3196678242
Directory	/workspace/4.chip_sw_uart_tx_rx_idx1/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4104573107
Short name	T425
Test name
Test status
Simulation time	3753918344 ps
CPU time	668.72 seconds
Started	Jul 19 07:03:16 PM PDT 24
Finished	Jul 19 07:14:26 PM PDT 24
Peak memory	623760 kb
Host	smart-357c6ce3-35a2-41f6-a893-45819eb11313
User	root
Command	/workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104573107 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.4104573107
Directory	/workspace/4.chip_sw_uart_tx_rx_idx2/latest

Test location	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3357195262
Short name	T30
Test name
Test status
Simulation time	4447942450 ps
CPU time	554.38 seconds
Started	Jul 19 07:04:50 PM PDT 24
Finished	Jul 19 07:14:06 PM PDT 24
Peak memory	622776 kb
Host	smart-44b5f6db-629f-4060-b8d8-aaf9bc2b8ec7
User	root
Command	/workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357195262 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3357195262
Directory	/workspace/4.chip_sw_uart_tx_rx_idx3/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_dev.578032507
Short name	T124
Test name
Test status
Simulation time	3577854311 ps
CPU time	331.67 seconds
Started	Jul 19 07:02:42 PM PDT 24
Finished	Jul 19 07:08:14 PM PDT 24
Peak memory	622012 kb
Host	smart-ae26f641-449b-4567-9647-0eaf180bcb2c
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=578032507 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.578032507
Directory	/workspace/4.chip_tap_straps_dev/latest

Test location	/workspace/coverage/default/4.chip_tap_straps_prod.1668375806
Short name	T939
Test name
Test status
Simulation time	12649655102 ps
CPU time	1363.41 seconds
Started	Jul 19 07:02:15 PM PDT 24
Finished	Jul 19 07:25:00 PM PDT 24
Peak memory	620912 kb
Host	smart-fb13c68a-c083-4d74-934a-3e535bcf9fec
User	root
Command	/workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668375806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.1668375806
Directory	/workspace/4.chip_tap_straps_prod/latest

Test location	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1356999312
Short name	T456
Test name
Test status
Simulation time	3590976630 ps
CPU time	421.66 seconds
Started	Jul 19 07:08:14 PM PDT 24
Finished	Jul 19 07:15:16 PM PDT 24
Peak memory	648900 kb
Host	smart-11a77030-cd21-4eb5-bfbb-bbf62a65abe6
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356999312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1356999312
Directory	/workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3278356701
Short name	T374
Test name
Test status
Simulation time	3538973500 ps
CPU time	384.12 seconds
Started	Jul 19 07:09:39 PM PDT 24
Finished	Jul 19 07:16:12 PM PDT 24
Peak memory	648848 kb
Host	smart-99478387-d18e-4c23-bd15-73e17ef2ef34
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278356701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3278356701
Directory	/workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/41.chip_sw_all_escalation_resets.250292028
Short name	T478
Test name
Test status
Simulation time	6059354936 ps
CPU time	777.46 seconds
Started	Jul 19 07:08:18 PM PDT 24
Finished	Jul 19 07:21:16 PM PDT 24
Peak memory	650324 kb
Host	smart-fe402c31-5f3b-4219-8432-8bf17e17ce7c
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 250292028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.250292028
Directory	/workspace/41.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1164898388
Short name	T628
Test name
Test status
Simulation time	3385287692 ps
CPU time	478.77 seconds
Started	Jul 19 07:08:57 PM PDT 24
Finished	Jul 19 07:17:00 PM PDT 24
Peak memory	648676 kb
Host	smart-e5e98c57-f521-4165-b7ed-76bd10a0fd1b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164898388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1164898388
Directory	/workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/42.chip_sw_all_escalation_resets.460270837
Short name	T472
Test name
Test status
Simulation time	4363430222 ps
CPU time	681.61 seconds
Started	Jul 19 07:07:52 PM PDT 24
Finished	Jul 19 07:19:14 PM PDT 24
Peak memory	649976 kb
Host	smart-817f1257-df90-4b23-92c5-1c9aa66daf8d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 460270837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.460270837
Directory	/workspace/42.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827692293
Short name	T735
Test name
Test status
Simulation time	4120052920 ps
CPU time	373.48 seconds
Started	Jul 19 07:07:28 PM PDT 24
Finished	Jul 19 07:13:47 PM PDT 24
Peak memory	648816 kb
Host	smart-b87b0e9a-ebdf-4f3c-a1e5-127dd5a8181b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827692293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3827692293
Directory	/workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/44.chip_sw_all_escalation_resets.1239278733
Short name	T454
Test name
Test status
Simulation time	5044691602 ps
CPU time	546.39 seconds
Started	Jul 19 07:07:58 PM PDT 24
Finished	Jul 19 07:17:06 PM PDT 24
Peak memory	650092 kb
Host	smart-a6f56000-1538-46a9-bb6c-a1b69f39a8f1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1239278733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1239278733
Directory	/workspace/44.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.749058365
Short name	T535
Test name
Test status
Simulation time	3673333424 ps
CPU time	523.4 seconds
Started	Jul 19 07:08:58 PM PDT 24
Finished	Jul 19 07:17:47 PM PDT 24
Peak memory	648780 kb
Host	smart-d9035d91-09a7-42d1-935f-a8c5523f598f
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749058365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_s w_alert_handler_lpg_sleep_mode_alerts.749058365
Directory	/workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3301175846
Short name	T524
Test name
Test status
Simulation time	5809627190 ps
CPU time	585.59 seconds
Started	Jul 19 07:08:50 PM PDT 24
Finished	Jul 19 07:18:39 PM PDT 24
Peak memory	649808 kb
Host	smart-d5ed396e-4bcb-41ac-94d2-f27c2bb22f04
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3301175846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3301175846
Directory	/workspace/46.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1417591871
Short name	T109
Test name
Test status
Simulation time	3170161800 ps
CPU time	344.78 seconds
Started	Jul 19 07:08:04 PM PDT 24
Finished	Jul 19 07:13:51 PM PDT 24
Peak memory	648616 kb
Host	smart-97a7742a-1257-4104-95c6-9b36f566fc79
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417591871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1417591871
Directory	/workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115889355
Short name	T169
Test name
Test status
Simulation time	3496319888 ps
CPU time	364.56 seconds
Started	Jul 19 07:08:54 PM PDT 24
Finished	Jul 19 07:15:01 PM PDT 24
Peak memory	649040 kb
Host	smart-d84e95c9-2315-42e3-9adc-2834df7f1004
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115889355 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1115889355
Directory	/workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581394307
Short name	T915
Test name
Test status
Simulation time	4159847442 ps
CPU time	435.62 seconds
Started	Jul 19 07:05:21 PM PDT 24
Finished	Jul 19 07:12:39 PM PDT 24
Peak memory	618804 kb
Host	smart-a78aa041-8d8e-4042-bf4a-897d6700df3d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581394307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.2581394307
Directory	/workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.614204882
Short name	T433
Test name
Test status
Simulation time	27052319230 ps
CPU time	7745.04 seconds
Started	Jul 19 07:03:22 PM PDT 24
Finished	Jul 19 09:12:28 PM PDT 24
Peak memory	610108 kb
Host	smart-4b0a2e62-307c-4588-8e7e-7e948d70368a
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614204882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.614204882
Directory	/workspace/5.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2891574492
Short name	T933
Test name
Test status
Simulation time	4465229048 ps
CPU time	527.27 seconds
Started	Jul 19 07:02:34 PM PDT 24
Finished	Jul 19 07:11:22 PM PDT 24
Peak memory	610848 kb
Host	smart-6ad90d1a-de70-4183-8ae9-b33f41a9b65a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2891574492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2891574492
Directory	/workspace/5.chip_sw_data_integrity_escalation/latest

Test location	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2768922723
Short name	T781
Test name
Test status
Simulation time	10207167643 ps
CPU time	922.31 seconds
Started	Jul 19 07:03:36 PM PDT 24
Finished	Jul 19 07:19:00 PM PDT 24
Peak memory	624680 kb
Host	smart-45a4485e-4cb6-468b-baec-d331cd7fc40d
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768922723 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2768922723
Directory	/workspace/5.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.15508149
Short name	T999
Test name
Test status
Simulation time	8273482738 ps
CPU time	1675.44 seconds
Started	Jul 19 07:04:05 PM PDT 24
Finished	Jul 19 07:32:01 PM PDT 24
Peak memory	618428 kb
Host	smart-6df6edc8-aa4e-44dc-9633-9d882811860d
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=15508149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.15508149
Directory	/workspace/5.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/50.chip_sw_all_escalation_resets.2406956326
Short name	T542
Test name
Test status
Simulation time	4642690896 ps
CPU time	629.64 seconds
Started	Jul 19 07:09:45 PM PDT 24
Finished	Jul 19 07:20:20 PM PDT 24
Peak memory	649900 kb
Host	smart-309fc418-3294-4499-9dba-5959cb86769a
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2406956326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.2406956326
Directory	/workspace/50.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2295495555
Short name	T470
Test name
Test status
Simulation time	5877628312 ps
CPU time	539.58 seconds
Started	Jul 19 07:08:10 PM PDT 24
Finished	Jul 19 07:17:11 PM PDT 24
Peak memory	650080 kb
Host	smart-a13c7dd4-668e-473b-aeda-3e8e8000f94e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2295495555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.2295495555
Directory	/workspace/51.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4275835883
Short name	T520
Test name
Test status
Simulation time	4198857960 ps
CPU time	395.17 seconds
Started	Jul 19 07:09:24 PM PDT 24
Finished	Jul 19 07:16:14 PM PDT 24
Peak memory	648540 kb
Host	smart-2910a174-6565-48b1-98c1-014ba7438c26
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275835883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4275835883
Directory	/workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1352301218
Short name	T167
Test name
Test status
Simulation time	4188174078 ps
CPU time	397.34 seconds
Started	Jul 19 07:08:07 PM PDT 24
Finished	Jul 19 07:14:46 PM PDT 24
Peak memory	649020 kb
Host	smart-535a74ec-7ff4-4f34-b42d-e9b449d0c700
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352301218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1352301218
Directory	/workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2077842796
Short name	T1006
Test name
Test status
Simulation time	3814244760 ps
CPU time	433.76 seconds
Started	Jul 19 07:10:04 PM PDT 24
Finished	Jul 19 07:17:19 PM PDT 24
Peak memory	648832 kb
Host	smart-af456ef6-db02-4dc8-86d7-1292b981544c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077842796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2077842796
Directory	/workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/55.chip_sw_all_escalation_resets.188332086
Short name	T181
Test name
Test status
Simulation time	5152365672 ps
CPU time	664.02 seconds
Started	Jul 19 07:09:37 PM PDT 24
Finished	Jul 19 07:20:52 PM PDT 24
Peak memory	619672 kb
Host	smart-82227cbb-9eeb-4a70-ac19-082d09527a55
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 188332086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.188332086
Directory	/workspace/55.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.700897323
Short name	T414
Test name
Test status
Simulation time	3316278928 ps
CPU time	334.33 seconds
Started	Jul 19 07:08:32 PM PDT 24
Finished	Jul 19 07:14:07 PM PDT 24
Peak memory	648492 kb
Host	smart-1f780a7a-0e7d-47c0-a072-5869924becb1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700897323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.700897323
Directory	/workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2287838322
Short name	T497
Test name
Test status
Simulation time	4868230568 ps
CPU time	520.33 seconds
Started	Jul 19 07:13:58 PM PDT 24
Finished	Jul 19 07:22:43 PM PDT 24
Peak memory	650056 kb
Host	smart-89725afd-a0f6-4f28-8fe6-b8d85fbc80bf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2287838322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.2287838322
Directory	/workspace/56.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3590274255
Short name	T466
Test name
Test status
Simulation time	4089867880 ps
CPU time	389.34 seconds
Started	Jul 19 07:09:12 PM PDT 24
Finished	Jul 19 07:15:55 PM PDT 24
Peak memory	618544 kb
Host	smart-9f925d55-3f34-4b62-b1bb-10c966fdccef
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590274255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3590274255
Directory	/workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.535250727
Short name	T481
Test name
Test status
Simulation time	3180109640 ps
CPU time	386.86 seconds
Started	Jul 19 07:09:15 PM PDT 24
Finished	Jul 19 07:15:57 PM PDT 24
Peak memory	648536 kb
Host	smart-8afc9983-b1d5-4990-a657-d1e11ca8e7c0
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535250727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.535250727
Directory	/workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/58.chip_sw_all_escalation_resets.3601812787
Short name	T308
Test name
Test status
Simulation time	4712604350 ps
CPU time	657.25 seconds
Started	Jul 19 07:08:31 PM PDT 24
Finished	Jul 19 07:19:29 PM PDT 24
Peak memory	650204 kb
Host	smart-f7fa5cbc-8911-483b-b2d0-f030646628e1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3601812787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3601812787
Directory	/workspace/58.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1466808052
Short name	T370
Test name
Test status
Simulation time	6005338986 ps
CPU time	660.97 seconds
Started	Jul 19 07:04:07 PM PDT 24
Finished	Jul 19 07:15:09 PM PDT 24
Peak memory	616772 kb
Host	smart-50475168-0010-4f1a-b10b-05146ab4a124
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1466808052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1466808052
Directory	/workspace/6.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1919639419
Short name	T969
Test name
Test status
Simulation time	16090870626 ps
CPU time	4078.52 seconds
Started	Jul 19 07:03:39 PM PDT 24
Finished	Jul 19 08:11:39 PM PDT 24
Peak memory	610236 kb
Host	smart-b4edf7f3-25b4-4be8-ab1c-6a62a7b1b1b9
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919639419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1919639419
Directory	/workspace/6.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.163261238
Short name	T639
Test name
Test status
Simulation time	5831930377 ps
CPU time	662.86 seconds
Started	Jul 19 07:05:56 PM PDT 24
Finished	Jul 19 07:17:00 PM PDT 24
Peak memory	624736 kb
Host	smart-bcbacd01-dd66-4986-badf-084601a9a700
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163261238 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.163261238
Directory	/workspace/6.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1610220049
Short name	T149
Test name
Test status
Simulation time	3979557488 ps
CPU time	597.06 seconds
Started	Jul 19 07:02:57 PM PDT 24
Finished	Jul 19 07:12:55 PM PDT 24
Peak memory	618716 kb
Host	smart-9bfe92d8-c017-4bec-b2a2-2af8dfe0ae7b
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1610220049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1610220049
Directory	/workspace/6.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.783067399
Short name	T128
Test name
Test status
Simulation time	3329819172 ps
CPU time	373.06 seconds
Started	Jul 19 07:08:57 PM PDT 24
Finished	Jul 19 07:15:16 PM PDT 24
Peak memory	648828 kb
Host	smart-947eec9a-3b69-414e-9cf6-8fa551b428ed
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783067399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_s w_alert_handler_lpg_sleep_mode_alerts.783067399
Directory	/workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455527806
Short name	T534
Test name
Test status
Simulation time	4061023896 ps
CPU time	336.32 seconds
Started	Jul 19 07:09:28 PM PDT 24
Finished	Jul 19 07:15:17 PM PDT 24
Peak memory	648468 kb
Host	smart-b5945dec-1e59-4d07-ac12-19c63b1d0dae
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455527806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2455527806
Directory	/workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2486603406
Short name	T459
Test name
Test status
Simulation time	5979558318 ps
CPU time	659.54 seconds
Started	Jul 19 07:09:30 PM PDT 24
Finished	Jul 19 07:20:42 PM PDT 24
Peak memory	650004 kb
Host	smart-a981a5eb-4691-48ba-b17b-a060c162bb88
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2486603406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.2486603406
Directory	/workspace/62.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.902018092
Short name	T984
Test name
Test status
Simulation time	4004074352 ps
CPU time	292.36 seconds
Started	Jul 19 07:10:55 PM PDT 24
Finished	Jul 19 07:15:50 PM PDT 24
Peak memory	648592 kb
Host	smart-cdce4e97-46a9-4be7-b956-398b7ecdd1c2
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902018092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.902018092
Directory	/workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/63.chip_sw_all_escalation_resets.181652141
Short name	T825
Test name
Test status
Simulation time	5530115028 ps
CPU time	614.72 seconds
Started	Jul 19 07:09:40 PM PDT 24
Finished	Jul 19 07:20:03 PM PDT 24
Peak memory	616844 kb
Host	smart-ad700195-627b-4839-8e08-11a720162372
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 181652141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.181652141
Directory	/workspace/63.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/64.chip_sw_all_escalation_resets.1918462543
Short name	T947
Test name
Test status
Simulation time	5337507848 ps
CPU time	564.64 seconds
Started	Jul 19 07:11:34 PM PDT 24
Finished	Jul 19 07:21:08 PM PDT 24
Peak memory	650044 kb
Host	smart-77ed7557-d127-4b54-9a18-1d43a78ed0cf
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1918462543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.1918462543
Directory	/workspace/64.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3826436229
Short name	T468
Test name
Test status
Simulation time	3779194352 ps
CPU time	413.93 seconds
Started	Jul 19 07:11:04 PM PDT 24
Finished	Jul 19 07:18:14 PM PDT 24
Peak memory	648776 kb
Host	smart-4f1b14c5-ddbf-4080-91c1-59917f405102
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826436229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3826436229
Directory	/workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3803540433
Short name	T541
Test name
Test status
Simulation time	4589846280 ps
CPU time	644.73 seconds
Started	Jul 19 07:09:05 PM PDT 24
Finished	Jul 19 07:19:59 PM PDT 24
Peak memory	650128 kb
Host	smart-eb6ac755-77a8-413f-a254-4a54563e71f5
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3803540433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3803540433
Directory	/workspace/65.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3108955999
Short name	T532
Test name
Test status
Simulation time	4174864850 ps
CPU time	322.23 seconds
Started	Jul 19 07:08:44 PM PDT 24
Finished	Jul 19 07:14:11 PM PDT 24
Peak memory	648776 kb
Host	smart-2e2634b2-0794-4dea-8275-09eba7606b1d
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108955999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3108955999
Directory	/workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/67.chip_sw_all_escalation_resets.472496839
Short name	T529
Test name
Test status
Simulation time	5164961152 ps
CPU time	629.09 seconds
Started	Jul 19 07:11:12 PM PDT 24
Finished	Jul 19 07:21:58 PM PDT 24
Peak memory	649840 kb
Host	smart-bf7e32dd-6104-492b-b0ee-cfcce27e9cab
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 472496839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.472496839
Directory	/workspace/67.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055058194
Short name	T517
Test name
Test status
Simulation time	3919483150 ps
CPU time	393.67 seconds
Started	Jul 19 07:10:10 PM PDT 24
Finished	Jul 19 07:16:50 PM PDT 24
Peak memory	648744 kb
Host	smart-1594aaf4-74c2-49d5-8af9-80a47609f005
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055058194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4055058194
Directory	/workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3093913181
Short name	T764
Test name
Test status
Simulation time	6208453608 ps
CPU time	757.07 seconds
Started	Jul 19 07:09:53 PM PDT 24
Finished	Jul 19 07:22:33 PM PDT 24
Peak memory	649904 kb
Host	smart-e221fd8a-d4ff-4e78-89b5-c50bcb058555
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3093913181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3093913181
Directory	/workspace/69.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_all_escalation_resets.946892940
Short name	T407
Test name
Test status
Simulation time	6226375672 ps
CPU time	503.71 seconds
Started	Jul 19 07:04:05 PM PDT 24
Finished	Jul 19 07:12:30 PM PDT 24
Peak memory	651036 kb
Host	smart-b19b6226-a555-4480-8eb3-fa1d1ff9fac7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 946892940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.946892940
Directory	/workspace/7.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1373410928
Short name	T679
Test name
Test status
Simulation time	18199203380 ps
CPU time	5042.78 seconds
Started	Jul 19 07:04:01 PM PDT 24
Finished	Jul 19 08:28:04 PM PDT 24
Peak memory	610308 kb
Host	smart-3e9f08b2-571b-420c-b882-ed3f16402642
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373410928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.1373410928
Directory	/workspace/7.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2019130377
Short name	T58
Test name
Test status
Simulation time	8858083659 ps
CPU time	691.59 seconds
Started	Jul 19 07:05:00 PM PDT 24
Finished	Jul 19 07:16:33 PM PDT 24
Peak memory	624740 kb
Host	smart-2ca8c964-bcf6-4a11-9531-46187afa9d01
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019130377 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2019130377
Directory	/workspace/7.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2649339021
Short name	T597
Test name
Test status
Simulation time	7982243040 ps
CPU time	1680.46 seconds
Started	Jul 19 07:03:29 PM PDT 24
Finished	Jul 19 07:31:31 PM PDT 24
Peak memory	618848 kb
Host	smart-7ac8ecaa-c079-4f1e-a7d4-b670466348ac
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2649339021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2649339021
Directory	/workspace/7.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.975856442
Short name	T523
Test name
Test status
Simulation time	4264284400 ps
CPU time	337.14 seconds
Started	Jul 19 07:12:13 PM PDT 24
Finished	Jul 19 07:17:52 PM PDT 24
Peak memory	648756 kb
Host	smart-b0296f04-e372-4298-942a-01bd5efbfa04
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975856442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_s w_alert_handler_lpg_sleep_mode_alerts.975856442
Directory	/workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/70.chip_sw_all_escalation_resets.236193874
Short name	T461
Test name
Test status
Simulation time	4866136488 ps
CPU time	631.45 seconds
Started	Jul 19 07:11:05 PM PDT 24
Finished	Jul 19 07:21:54 PM PDT 24
Peak memory	649968 kb
Host	smart-c1c72705-9bad-4cbb-ad3c-a287b053362d
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 236193874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.236193874
Directory	/workspace/70.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2396085709
Short name	T305
Test name
Test status
Simulation time	5075248614 ps
CPU time	547.04 seconds
Started	Jul 19 07:11:35 PM PDT 24
Finished	Jul 19 07:20:51 PM PDT 24
Peak memory	619716 kb
Host	smart-f4410514-8647-4e78-b034-c88b04391fc9
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2396085709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2396085709
Directory	/workspace/71.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.590951
Short name	T540
Test name
Test status
Simulation time	3955460324 ps
CPU time	361.7 seconds
Started	Jul 19 07:11:04 PM PDT 24
Finished	Jul 19 07:17:22 PM PDT 24
Peak memory	648748 kb
Host	smart-684f4810-3f15-4f2e-b395-8a21922beccc
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_es calation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_a lert_handler_lpg_sleep_mode_alerts.590951
Directory	/workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3076723001
Short name	T348
Test name
Test status
Simulation time	4254823280 ps
CPU time	432.04 seconds
Started	Jul 19 07:11:51 PM PDT 24
Finished	Jul 19 07:19:08 PM PDT 24
Peak memory	648696 kb
Host	smart-83ae5177-668d-438d-98f7-0a53af25c706
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076723001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3076723001
Directory	/workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3106975567
Short name	T329
Test name
Test status
Simulation time	5520384090 ps
CPU time	565 seconds
Started	Jul 19 07:10:48 PM PDT 24
Finished	Jul 19 07:20:15 PM PDT 24
Peak memory	649912 kb
Host	smart-a26fb307-3ae1-4132-9a19-a46a5f489618
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3106975567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3106975567
Directory	/workspace/73.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2341754071
Short name	T234
Test name
Test status
Simulation time	3852533432 ps
CPU time	407.77 seconds
Started	Jul 19 07:10:14 PM PDT 24
Finished	Jul 19 07:17:11 PM PDT 24
Peak memory	648800 kb
Host	smart-26690267-df34-4cf9-9a40-2f2d6fc47e3c
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341754071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2341754071
Directory	/workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1360674717
Short name	T723
Test name
Test status
Simulation time	5265831404 ps
CPU time	678.51 seconds
Started	Jul 19 07:09:57 PM PDT 24
Finished	Jul 19 07:21:18 PM PDT 24
Peak memory	650200 kb
Host	smart-c2c80494-55e7-41d4-a73d-8f33e0d89ba4
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1360674717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1360674717
Directory	/workspace/74.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1874764156
Short name	T507
Test name
Test status
Simulation time	4089793624 ps
CPU time	408.5 seconds
Started	Jul 19 07:10:44 PM PDT 24
Finished	Jul 19 07:17:36 PM PDT 24
Peak memory	648504 kb
Host	smart-46fa3ad7-7f63-4ffd-9879-d9a968611706
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874764156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1874764156
Directory	/workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2046060242
Short name	T745
Test name
Test status
Simulation time	4126283244 ps
CPU time	381.65 seconds
Started	Jul 19 07:11:27 PM PDT 24
Finished	Jul 19 07:18:00 PM PDT 24
Peak memory	648780 kb
Host	smart-ffde99db-f4fc-4171-96bb-633b3fb7a7fa
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046060242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2046060242
Directory	/workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3550915716
Short name	T318
Test name
Test status
Simulation time	5425135360 ps
CPU time	621.02 seconds
Started	Jul 19 07:09:52 PM PDT 24
Finished	Jul 19 07:20:14 PM PDT 24
Peak memory	650200 kb
Host	smart-16391ab2-e520-48eb-b4c5-580074e5b2b3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3550915716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.3550915716
Directory	/workspace/77.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124170358
Short name	T346
Test name
Test status
Simulation time	4616806878 ps
CPU time	461.18 seconds
Started	Jul 19 07:10:08 PM PDT 24
Finished	Jul 19 07:17:54 PM PDT 24
Peak memory	649284 kb
Host	smart-e1b47975-9b4c-49be-87d7-960ec47662e5
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124170358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2124170358
Directory	/workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/78.chip_sw_all_escalation_resets.424181287
Short name	T349
Test name
Test status
Simulation time	5303639612 ps
CPU time	697.75 seconds
Started	Jul 19 07:11:13 PM PDT 24
Finished	Jul 19 07:23:08 PM PDT 24
Peak memory	649968 kb
Host	smart-833c66f6-aee4-4fb3-b939-02fb53eefba3
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 424181287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.424181287
Directory	/workspace/78.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131044809
Short name	T438
Test name
Test status
Simulation time	3860826144 ps
CPU time	362.24 seconds
Started	Jul 19 07:11:29 PM PDT 24
Finished	Jul 19 07:17:43 PM PDT 24
Peak memory	648756 kb
Host	smart-e535d210-a3ce-4e9d-9c05-8dbe726de9f3
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131044809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4131044809
Directory	/workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/79.chip_sw_all_escalation_resets.2450581348
Short name	T292
Test name
Test status
Simulation time	5329470580 ps
CPU time	583.77 seconds
Started	Jul 19 07:11:25 PM PDT 24
Finished	Jul 19 07:21:22 PM PDT 24
Peak memory	650276 kb
Host	smart-ea87cab3-8f64-4b94-8ad0-0da09ea7df5b
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2450581348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2450581348
Directory	/workspace/79.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3909132720
Short name	T508
Test name
Test status
Simulation time	5088977844 ps
CPU time	540.2 seconds
Started	Jul 19 07:05:39 PM PDT 24
Finished	Jul 19 07:14:40 PM PDT 24
Peak memory	650096 kb
Host	smart-bcfe622c-b8d9-464d-ade4-e5343b39db77
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3909132720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.3909132720
Directory	/workspace/8.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2041155968
Short name	T219
Test name
Test status
Simulation time	12286227398 ps
CPU time	3067.74 seconds
Started	Jul 19 07:04:54 PM PDT 24
Finished	Jul 19 07:56:03 PM PDT 24
Peak memory	610204 kb
Host	smart-a104b9fd-c835-404d-a472-7537a900f826
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041155968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.2041155968
Directory	/workspace/8.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1949754521
Short name	T873
Test name
Test status
Simulation time	12178139352 ps
CPU time	884.87 seconds
Started	Jul 19 07:03:43 PM PDT 24
Finished	Jul 19 07:18:28 PM PDT 24
Peak memory	623804 kb
Host	smart-6889c3b8-ed23-42d7-b270-c23404657c52
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949754521 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1949754521
Directory	/workspace/8.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4179470587
Short name	T841
Test name
Test status
Simulation time	3493103668 ps
CPU time	547.9 seconds
Started	Jul 19 07:05:29 PM PDT 24
Finished	Jul 19 07:14:38 PM PDT 24
Peak memory	618596 kb
Host	smart-7153def8-37e0-44b2-a01b-42b80330e4e0
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4179470587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.4179470587
Directory	/workspace/8.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118179033
Short name	T530
Test name
Test status
Simulation time	3497361210 ps
CPU time	401.94 seconds
Started	Jul 19 07:13:15 PM PDT 24
Finished	Jul 19 07:20:01 PM PDT 24
Peak memory	648772 kb
Host	smart-4d1d6bc4-08a6-4041-99e0-e121d2aa3e83
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118179033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2118179033
Directory	/workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/80.chip_sw_all_escalation_resets.4187020626
Short name	T347
Test name
Test status
Simulation time	5675702528 ps
CPU time	569.53 seconds
Started	Jul 19 07:10:48 PM PDT 24
Finished	Jul 19 07:20:21 PM PDT 24
Peak memory	650196 kb
Host	smart-1b522788-23ba-4a60-98a7-f547d5cc14fd
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4187020626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.4187020626
Directory	/workspace/80.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.4034411239
Short name	T494
Test name
Test status
Simulation time	4412708362 ps
CPU time	395.35 seconds
Started	Jul 19 07:10:23 PM PDT 24
Finished	Jul 19 07:17:04 PM PDT 24
Peak memory	648904 kb
Host	smart-5b954461-bb85-4dff-957b-650132cce55b
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034411239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4034411239
Directory	/workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3228176915
Short name	T512
Test name
Test status
Simulation time	4348337256 ps
CPU time	557.07 seconds
Started	Jul 19 07:11:02 PM PDT 24
Finished	Jul 19 07:20:32 PM PDT 24
Peak memory	650236 kb
Host	smart-c9d4b3b1-7e15-4572-b75d-815e49665771
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3228176915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3228176915
Directory	/workspace/81.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3130544359
Short name	T500
Test name
Test status
Simulation time	3785164520 ps
CPU time	379.62 seconds
Started	Jul 19 07:12:09 PM PDT 24
Finished	Jul 19 07:18:32 PM PDT 24
Peak memory	648820 kb
Host	smart-be858d19-f309-4d24-ac31-8daf6a46c3cb
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130544359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3130544359
Directory	/workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/82.chip_sw_all_escalation_resets.142836284
Short name	T175
Test name
Test status
Simulation time	6356610898 ps
CPU time	623.15 seconds
Started	Jul 19 07:11:14 PM PDT 24
Finished	Jul 19 07:21:54 PM PDT 24
Peak memory	620664 kb
Host	smart-b5dc94e5-d269-4fba-8ed9-5cab25e9b4b7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 142836284 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.142836284
Directory	/workspace/82.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3188277407
Short name	T457
Test name
Test status
Simulation time	3604921154 ps
CPU time	382.39 seconds
Started	Jul 19 07:10:52 PM PDT 24
Finished	Jul 19 07:17:18 PM PDT 24
Peak memory	648608 kb
Host	smart-a9498972-b69c-4155-9bfa-f69e6f0839ad
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188277407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3188277407
Directory	/workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/83.chip_sw_all_escalation_resets.181964381
Short name	T350
Test name
Test status
Simulation time	5737809356 ps
CPU time	595.84 seconds
Started	Jul 19 07:11:34 PM PDT 24
Finished	Jul 19 07:21:39 PM PDT 24
Peak memory	650072 kb
Host	smart-36bbeefc-0dc5-4b2a-bd77-0d01a17d4ca8
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 181964381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.181964381
Directory	/workspace/83.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1456842833
Short name	T618
Test name
Test status
Simulation time	3475377600 ps
CPU time	381.28 seconds
Started	Jul 19 07:10:56 PM PDT 24
Finished	Jul 19 07:17:20 PM PDT 24
Peak memory	648904 kb
Host	smart-4fe72964-b69e-4904-8d42-2baceabbe9f1
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456842833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1456842833
Directory	/workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/84.chip_sw_all_escalation_resets.137932889
Short name	T492
Test name
Test status
Simulation time	6042109020 ps
CPU time	658.57 seconds
Started	Jul 19 07:12:50 PM PDT 24
Finished	Jul 19 07:23:52 PM PDT 24
Peak memory	649968 kb
Host	smart-6431885a-a6ae-4225-b7c6-ab9b0ba10fed
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 137932889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.137932889
Directory	/workspace/84.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/85.chip_sw_all_escalation_resets.4102421087
Short name	T751
Test name
Test status
Simulation time	5387876744 ps
CPU time	475.56 seconds
Started	Jul 19 07:10:38 PM PDT 24
Finished	Jul 19 07:18:35 PM PDT 24
Peak memory	650012 kb
Host	smart-d65d90f6-6d7e-4e04-b490-3f132e732db2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4102421087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.4102421087
Directory	/workspace/85.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1895256925
Short name	T521
Test name
Test status
Simulation time	3241138374 ps
CPU time	351.77 seconds
Started	Jul 19 07:14:28 PM PDT 24
Finished	Jul 19 07:20:24 PM PDT 24
Peak memory	648792 kb
Host	smart-218a1ac5-46ae-49ce-bac6-b2afb1bb19ff
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895256925 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1895256925
Directory	/workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3818373254
Short name	T413
Test name
Test status
Simulation time	4523790040 ps
CPU time	567.61 seconds
Started	Jul 19 07:14:06 PM PDT 24
Finished	Jul 19 07:23:36 PM PDT 24
Peak memory	649788 kb
Host	smart-899afac0-5253-4a56-9395-24a6d06226b0
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3818373254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.3818373254
Directory	/workspace/86.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1764599091
Short name	T421
Test name
Test status
Simulation time	3073729646 ps
CPU time	411.62 seconds
Started	Jul 19 07:11:39 PM PDT 24
Finished	Jul 19 07:18:37 PM PDT 24
Peak memory	649100 kb
Host	smart-37881dec-cac1-4742-8be7-d2f6af68f6e4
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764599091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1764599091
Directory	/workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/87.chip_sw_all_escalation_resets.199533931
Short name	T482
Test name
Test status
Simulation time	4949673162 ps
CPU time	660.25 seconds
Started	Jul 19 07:14:13 PM PDT 24
Finished	Jul 19 07:25:16 PM PDT 24
Peak memory	649776 kb
Host	smart-435b579a-64bb-4616-8ad2-773203c5e330
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 199533931 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.199533931
Directory	/workspace/87.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3689940213
Short name	T261
Test name
Test status
Simulation time	3894686244 ps
CPU time	350.1 seconds
Started	Jul 19 07:12:47 PM PDT 24
Finished	Jul 19 07:18:39 PM PDT 24
Peak memory	648960 kb
Host	smart-32df29c8-9e65-431c-9c1d-cc17123f53db
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689940213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3689940213
Directory	/workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/88.chip_sw_all_escalation_resets.4009513218
Short name	T505
Test name
Test status
Simulation time	4704580402 ps
CPU time	462.3 seconds
Started	Jul 19 07:10:11 PM PDT 24
Finished	Jul 19 07:18:02 PM PDT 24
Peak memory	649808 kb
Host	smart-06c45aa1-4f5f-425d-8f1a-7537d6eb01d1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4009513218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.4009513218
Directory	/workspace/88.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2734178287
Short name	T170
Test name
Test status
Simulation time	3416414062 ps
CPU time	326.76 seconds
Started	Jul 19 07:12:04 PM PDT 24
Finished	Jul 19 07:17:34 PM PDT 24
Peak memory	618536 kb
Host	smart-576c1702-6886-4028-98f2-b994dd2f0106
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734178287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2734178287
Directory	/workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/89.chip_sw_all_escalation_resets.3167484492
Short name	T274
Test name
Test status
Simulation time	4960404920 ps
CPU time	469.09 seconds
Started	Jul 19 07:11:28 PM PDT 24
Finished	Jul 19 07:19:29 PM PDT 24
Peak memory	650188 kb
Host	smart-c5db7b3b-02ee-428a-856a-c4b738fe18f7
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3167484492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.3167484492
Directory	/workspace/89.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1787792486
Short name	T315
Test name
Test status
Simulation time	3915827196 ps
CPU time	320.08 seconds
Started	Jul 19 07:05:30 PM PDT 24
Finished	Jul 19 07:10:52 PM PDT 24
Peak memory	648828 kb
Host	smart-29461e73-6769-4a24-b38a-6c690abfe611
User	root
Command	/workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrlstate_regs +avoid_ferr_ips_append=otp_ctrlu_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787792486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1787792486
Directory	/workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest

Test location	/workspace/coverage/default/9.chip_sw_all_escalation_resets.915234991
Short name	T295
Test name
Test status
Simulation time	6164078136 ps
CPU time	676.4 seconds
Started	Jul 19 07:04:24 PM PDT 24
Finished	Jul 19 07:15:51 PM PDT 24
Peak memory	649812 kb
Host	smart-4abee03f-027b-440b-a398-ddf173ee2e57
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 915234991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.915234991
Directory	/workspace/9.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2569686388
Short name	T726
Test name
Test status
Simulation time	20178680680 ps
CPU time	5857.6 seconds
Started	Jul 19 07:04:27 PM PDT 24
Finished	Jul 19 08:42:14 PM PDT 24
Peak memory	610300 kb
Host	smart-519f48ff-ef37-4321-8984-efd35604f929
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569686388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.2569686388
Directory	/workspace/9.chip_sw_csrng_edn_concurrency/latest

Test location	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1035796712
Short name	T783
Test name
Test status
Simulation time	6600649219 ps
CPU time	483.88 seconds
Started	Jul 19 07:06:28 PM PDT 24
Finished	Jul 19 07:14:33 PM PDT 24
Peak memory	624488 kb
Host	smart-7879fbcf-18ca-4948-819d-981c20794ef3
User	root
Command	/workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035796712 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1035796712
Directory	/workspace/9.chip_sw_lc_ctrl_transition/latest

Test location	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4007493717
Short name	T360
Test name
Test status
Simulation time	13275497776 ps
CPU time	2710.76 seconds
Started	Jul 19 07:04:39 PM PDT 24
Finished	Jul 19 07:49:55 PM PDT 24
Peak memory	618764 kb
Host	smart-6a6a6a12-2494-45bc-8627-7f80afeb2380
User	root
Command	/workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4007493717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.4007493717
Directory	/workspace/9.chip_sw_uart_rand_baudrate/latest

Test location	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4252728227
Short name	T168
Test name
Test status
Simulation time	4736624360 ps
CPU time	592.15 seconds
Started	Jul 19 07:11:49 PM PDT 24
Finished	Jul 19 07:21:45 PM PDT 24
Peak memory	650112 kb
Host	smart-82110f9b-eaa0-4b1d-9144-f198842a011e
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4252728227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.4252728227
Directory	/workspace/91.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/92.chip_sw_all_escalation_resets.461485061
Short name	T528
Test name
Test status
Simulation time	5629614288 ps
CPU time	709.93 seconds
Started	Jul 19 07:11:48 PM PDT 24
Finished	Jul 19 07:23:42 PM PDT 24
Peak memory	650004 kb
Host	smart-7157adec-e13c-469b-a592-c46976686d10
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 461485061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.461485061
Directory	/workspace/92.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/93.chip_sw_all_escalation_resets.641711386
Short name	T474
Test name
Test status
Simulation time	5203655248 ps
CPU time	583.94 seconds
Started	Jul 19 07:11:29 PM PDT 24
Finished	Jul 19 07:21:25 PM PDT 24
Peak memory	649996 kb
Host	smart-1cad1738-6f56-4cc6-b49d-e50a76dc066f
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 641711386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.641711386
Directory	/workspace/93.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/94.chip_sw_all_escalation_resets.267385976
Short name	T356
Test name
Test status
Simulation time	4954696324 ps
CPU time	499.92 seconds
Started	Jul 19 07:11:46 PM PDT 24
Finished	Jul 19 07:20:10 PM PDT 24
Peak memory	650076 kb
Host	smart-0f34506d-0904-4720-8df1-b73227e0fae1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 267385976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.267385976
Directory	/workspace/94.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/95.chip_sw_all_escalation_resets.1331941619
Short name	T417
Test name
Test status
Simulation time	6114277070 ps
CPU time	599.24 seconds
Started	Jul 19 07:11:43 PM PDT 24
Finished	Jul 19 07:21:47 PM PDT 24
Peak memory	649852 kb
Host	smart-9bdd9e63-e866-4551-bd3c-4d92193aee92
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1331941619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1331941619
Directory	/workspace/95.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2820777608
Short name	T525
Test name
Test status
Simulation time	5137577150 ps
CPU time	662.19 seconds
Started	Jul 19 07:11:14 PM PDT 24
Finished	Jul 19 07:22:33 PM PDT 24
Peak memory	649996 kb
Host	smart-220d6f1c-fa8d-4e32-a67f-cd9b90e4b7ca
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2820777608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2820777608
Directory	/workspace/96.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/97.chip_sw_all_escalation_resets.1717369429
Short name	T227
Test name
Test status
Simulation time	4590630524 ps
CPU time	596.22 seconds
Started	Jul 19 07:14:20 PM PDT 24
Finished	Jul 19 07:24:17 PM PDT 24
Peak memory	650500 kb
Host	smart-33ad70ca-69a2-4e05-91db-bad410f2cad2
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1717369429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1717369429
Directory	/workspace/97.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/default/99.chip_sw_all_escalation_resets.4049159143
Short name	T344
Test name
Test status
Simulation time	5642164310 ps
CPU time	565.03 seconds
Started	Jul 19 07:11:27 PM PDT 24
Finished	Jul 19 07:21:04 PM PDT 24
Peak memory	650036 kb
Host	smart-743bedfd-803c-42e0-a4d7-3e4d0852ffb1
User	root
Command	/workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4049159143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.4049159143
Directory	/workspace/99.chip_sw_all_escalation_resets/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3728004525
Short name	T246
Test name
Test status
Simulation time	5400777908 ps
CPU time	374.02 seconds
Started	Jul 19 04:48:40 PM PDT 24
Finished	Jul 19 04:55:12 PM PDT 24
Peak memory	649068 kb
Host	smart-6ddd56c6-a446-4d49-ac0f-0384ceb1ca6e
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728004525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.3728004525
Directory	/workspace/0.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.772270036
Short name	T248
Test name
Test status
Simulation time	5235191500 ps
CPU time	274.64 seconds
Started	Jul 19 04:48:46 PM PDT 24
Finished	Jul 19 04:53:36 PM PDT 24
Peak memory	654708 kb
Host	smart-f94c72a7-cf31-4941-b992-6e85e6222433
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772270036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.772270036
Directory	/workspace/1.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.451408801
Short name	T247
Test name
Test status
Simulation time	4886873120 ps
CPU time	289.37 seconds
Started	Jul 19 04:48:51 PM PDT 24
Finished	Jul 19 04:53:55 PM PDT 24
Peak memory	656968 kb
Host	smart-dbd17982-f5b3-4ade-aa67-5a6f4927f2bc
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451408801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.451408801
Directory	/workspace/2.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1363544344
Short name	T200
Test name
Test status
Simulation time	3895258445 ps
CPU time	207.16 seconds
Started	Jul 19 04:48:40 PM PDT 24
Finished	Jul 19 04:52:25 PM PDT 24
Peak memory	640884 kb
Host	smart-88d49a57-1eb1-4458-8fa7-a4eeb407223f
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363544344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1363544344
Directory	/workspace/4.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.568917921
Short name	T245
Test name
Test status
Simulation time	5589113635 ps
CPU time	264.88 seconds
Started	Jul 19 04:48:49 PM PDT 24
Finished	Jul 19 04:53:28 PM PDT 24
Peak memory	657244 kb
Host	smart-92135583-869c-46b1-9861-5c8311d3cdef
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568917921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.568917921
Directory	/workspace/5.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3150757964
Short name	T249
Test name
Test status
Simulation time	5498134860 ps
CPU time	203.67 seconds
Started	Jul 19 04:48:44 PM PDT 24
Finished	Jul 19 04:52:24 PM PDT 24
Peak memory	640816 kb
Host	smart-7867528d-5d5f-4f6d-a402-3a5a7ccb24ab
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150757964 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3150757964
Directory	/workspace/7.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3547711923
Short name	T41
Test name
Test status
Simulation time	5241144085 ps
CPU time	228.95 seconds
Started	Jul 19 04:48:50 PM PDT 24
Finished	Jul 19 04:52:53 PM PDT 24
Peak memory	640940 kb
Host	smart-5b191a7e-cb37-4c62-96f7-82711befa651
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547711923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.3547711923
Directory	/workspace/8.chip_padctrl_attributes/latest

Test location	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.250181597
Short name	T42
Test name
Test status
Simulation time	5551571340 ps
CPU time	294.14 seconds
Started	Jul 19 04:48:43 PM PDT 24
Finished	Jul 19 04:53:54 PM PDT 24
Peak memory	642648 kb
Host	smart-b6256440-d8bc-41a2-9a67-7d6d9234b82a
User	root
Command	/workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250181597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 9.chip_padctrl_attributes.250181597
Directory	/workspace/9.chip_padctrl_attributes/latest

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