| T109 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2030097315 |
|
|
Jul 20 08:05:50 PM PDT 24 |
Jul 20 09:08:31 PM PDT 24 |
25487841278 ps |
| T121 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.260989402 |
|
|
Jul 20 08:13:26 PM PDT 24 |
Jul 20 08:27:47 PM PDT 24 |
5056697080 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_alert_test.3387762688 |
|
|
Jul 20 07:50:23 PM PDT 24 |
Jul 20 07:55:28 PM PDT 24 |
3056994956 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1148899410 |
|
|
Jul 20 07:57:19 PM PDT 24 |
Jul 20 08:21:18 PM PDT 24 |
12906457434 ps |
| T966 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1519323042 |
|
|
Jul 20 08:17:23 PM PDT 24 |
Jul 20 08:28:44 PM PDT 24 |
12313422292 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3088253819 |
|
|
Jul 20 07:56:45 PM PDT 24 |
Jul 20 08:27:57 PM PDT 24 |
13592124803 ps |
| T166 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.845595941 |
|
|
Jul 20 07:50:02 PM PDT 24 |
Jul 20 11:11:08 PM PDT 24 |
254755162394 ps |
| T840 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.127213739 |
|
|
Jul 20 08:21:21 PM PDT 24 |
Jul 20 08:36:03 PM PDT 24 |
5583093230 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2881339889 |
|
|
Jul 20 07:49:57 PM PDT 24 |
Jul 20 09:30:42 PM PDT 24 |
47486589700 ps |
| T967 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1674988661 |
|
|
Jul 20 07:56:45 PM PDT 24 |
Jul 20 08:02:28 PM PDT 24 |
3361524096 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2227191733 |
|
|
Jul 20 08:13:19 PM PDT 24 |
Jul 20 08:16:47 PM PDT 24 |
3083896838 ps |
| T969 |
/workspace/coverage/default/2.rom_e2e_static_critical.2988895294 |
|
|
Jul 20 08:18:40 PM PDT 24 |
Jul 20 09:23:21 PM PDT 24 |
17709905324 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2292319705 |
|
|
Jul 20 07:48:43 PM PDT 24 |
Jul 20 09:27:41 PM PDT 24 |
51701558010 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3285824195 |
|
|
Jul 20 07:50:26 PM PDT 24 |
Jul 20 07:53:58 PM PDT 24 |
2946566842 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.359426558 |
|
|
Jul 20 08:00:30 PM PDT 24 |
Jul 20 08:09:54 PM PDT 24 |
8280647024 ps |
| T972 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.278134538 |
|
|
Jul 20 08:15:43 PM PDT 24 |
Jul 20 08:18:59 PM PDT 24 |
2946527352 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3732282384 |
|
|
Jul 20 08:07:11 PM PDT 24 |
Jul 20 08:11:46 PM PDT 24 |
2655417450 ps |
| T784 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3295066957 |
|
|
Jul 20 08:23:12 PM PDT 24 |
Jul 20 08:35:26 PM PDT 24 |
5696507020 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3010064845 |
|
|
Jul 20 08:12:15 PM PDT 24 |
Jul 20 08:18:24 PM PDT 24 |
4476602264 ps |
| T975 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2788200845 |
|
|
Jul 20 07:53:40 PM PDT 24 |
Jul 20 08:02:06 PM PDT 24 |
5190873864 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3052728134 |
|
|
Jul 20 07:56:06 PM PDT 24 |
Jul 20 08:03:55 PM PDT 24 |
5147488789 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2996528773 |
|
|
Jul 20 07:51:17 PM PDT 24 |
Jul 20 07:57:45 PM PDT 24 |
3652092186 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1324152361 |
|
|
Jul 20 08:11:45 PM PDT 24 |
Jul 20 08:23:21 PM PDT 24 |
4219214052 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3445340793 |
|
|
Jul 20 08:08:46 PM PDT 24 |
Jul 20 09:12:33 PM PDT 24 |
18984225031 ps |
| T980 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2832566048 |
|
|
Jul 20 08:18:44 PM PDT 24 |
Jul 20 08:28:47 PM PDT 24 |
9095410091 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.301906689 |
|
|
Jul 20 08:06:30 PM PDT 24 |
Jul 20 08:09:53 PM PDT 24 |
2584915350 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3155330104 |
|
|
Jul 20 07:50:16 PM PDT 24 |
Jul 20 08:08:06 PM PDT 24 |
5528089404 ps |
| T696 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4212410561 |
|
|
Jul 20 07:51:07 PM PDT 24 |
Jul 20 08:03:06 PM PDT 24 |
6003089816 ps |
| T697 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.360056383 |
|
|
Jul 20 08:21:50 PM PDT 24 |
Jul 20 08:28:24 PM PDT 24 |
3508061528 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.842701629 |
|
|
Jul 20 07:59:57 PM PDT 24 |
Jul 20 08:58:08 PM PDT 24 |
15488768870 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2049691570 |
|
|
Jul 20 07:56:46 PM PDT 24 |
Jul 20 08:16:44 PM PDT 24 |
6804269912 ps |
| T985 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1888996304 |
|
|
Jul 20 07:55:48 PM PDT 24 |
Jul 20 08:59:25 PM PDT 24 |
15377074610 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3589123672 |
|
|
Jul 20 07:52:16 PM PDT 24 |
Jul 20 08:04:45 PM PDT 24 |
8721675889 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3601381160 |
|
|
Jul 20 07:49:25 PM PDT 24 |
Jul 20 08:07:15 PM PDT 24 |
8703221634 ps |
| T281 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2335914011 |
|
|
Jul 20 08:11:59 PM PDT 24 |
Jul 20 08:19:55 PM PDT 24 |
3021602780 ps |
| T986 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1418389309 |
|
|
Jul 20 08:10:02 PM PDT 24 |
Jul 20 09:07:41 PM PDT 24 |
15878738212 ps |
| T363 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2314477294 |
|
|
Jul 20 08:19:22 PM PDT 24 |
Jul 20 09:02:15 PM PDT 24 |
13630222528 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1108893703 |
|
|
Jul 20 08:16:30 PM PDT 24 |
Jul 20 08:21:45 PM PDT 24 |
2320553256 ps |
| T143 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1822128768 |
|
|
Jul 20 08:03:11 PM PDT 24 |
Jul 20 08:07:19 PM PDT 24 |
2933170291 ps |
| T185 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.172885376 |
|
|
Jul 20 08:06:43 PM PDT 24 |
Jul 20 08:41:20 PM PDT 24 |
24587143786 ps |
| T167 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3215043656 |
|
|
Jul 20 07:57:09 PM PDT 24 |
Jul 20 07:58:34 PM PDT 24 |
1906686948 ps |
| T988 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.930323361 |
|
|
Jul 20 08:18:39 PM PDT 24 |
Jul 20 09:20:30 PM PDT 24 |
16432863070 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3683808578 |
|
|
Jul 20 08:07:01 PM PDT 24 |
Jul 20 08:11:55 PM PDT 24 |
2768134560 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.207265941 |
|
|
Jul 20 07:51:20 PM PDT 24 |
Jul 20 07:57:56 PM PDT 24 |
3720253401 ps |
| T27 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1488659031 |
|
|
Jul 20 07:49:06 PM PDT 24 |
Jul 20 07:59:06 PM PDT 24 |
3916125031 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3131811784 |
|
|
Jul 20 08:08:29 PM PDT 24 |
Jul 20 08:35:05 PM PDT 24 |
11973386971 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1034771736 |
|
|
Jul 20 08:08:12 PM PDT 24 |
Jul 20 08:25:26 PM PDT 24 |
5756102700 ps |
| T282 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.532258804 |
|
|
Jul 20 07:59:54 PM PDT 24 |
Jul 20 08:55:30 PM PDT 24 |
15413958330 ps |
| T186 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.428767593 |
|
|
Jul 20 07:49:27 PM PDT 24 |
Jul 20 07:51:45 PM PDT 24 |
2796827632 ps |
| T315 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931960891 |
|
|
Jul 20 08:26:20 PM PDT 24 |
Jul 20 08:31:54 PM PDT 24 |
3791600930 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2359970913 |
|
|
Jul 20 08:00:05 PM PDT 24 |
Jul 20 08:09:28 PM PDT 24 |
3873341210 ps |
| T351 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2071115881 |
|
|
Jul 20 08:06:44 PM PDT 24 |
Jul 20 08:17:09 PM PDT 24 |
3795820718 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.381491171 |
|
|
Jul 20 08:09:15 PM PDT 24 |
Jul 20 08:16:10 PM PDT 24 |
7804401152 ps |
| T7 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2217618582 |
|
|
Jul 20 08:12:21 PM PDT 24 |
Jul 20 08:20:29 PM PDT 24 |
3880016064 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3410627458 |
|
|
Jul 20 07:53:19 PM PDT 24 |
Jul 20 07:58:22 PM PDT 24 |
2804905262 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.1932320561 |
|
|
Jul 20 08:15:44 PM PDT 24 |
Jul 20 08:19:52 PM PDT 24 |
3579356148 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1319398932 |
|
|
Jul 20 08:01:13 PM PDT 24 |
Jul 20 08:13:06 PM PDT 24 |
4968476708 ps |
| T996 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1836098142 |
|
|
Jul 20 08:00:48 PM PDT 24 |
Jul 20 09:38:39 PM PDT 24 |
23665772412 ps |
| T417 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3472660023 |
|
|
Jul 20 08:23:29 PM PDT 24 |
Jul 20 08:34:32 PM PDT 24 |
5692100674 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.615313907 |
|
|
Jul 20 07:57:56 PM PDT 24 |
Jul 20 08:09:32 PM PDT 24 |
4830352520 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2464319937 |
|
|
Jul 20 08:11:26 PM PDT 24 |
Jul 20 08:16:01 PM PDT 24 |
3554310750 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3028807772 |
|
|
Jul 20 08:07:07 PM PDT 24 |
Jul 20 08:12:32 PM PDT 24 |
3919703368 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2380431787 |
|
|
Jul 20 08:11:53 PM PDT 24 |
Jul 20 08:22:40 PM PDT 24 |
4398189792 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.891787063 |
|
|
Jul 20 07:58:46 PM PDT 24 |
Jul 20 08:02:31 PM PDT 24 |
2602768980 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2806952375 |
|
|
Jul 20 08:02:02 PM PDT 24 |
Jul 20 08:08:53 PM PDT 24 |
4805437068 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.699666037 |
|
|
Jul 20 08:02:23 PM PDT 24 |
Jul 20 08:12:45 PM PDT 24 |
3761858316 ps |
| T255 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3941060518 |
|
|
Jul 20 08:08:43 PM PDT 24 |
Jul 20 08:17:58 PM PDT 24 |
6489774874 ps |
| T778 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131894569 |
|
|
Jul 20 08:10:47 PM PDT 24 |
Jul 20 08:16:21 PM PDT 24 |
3698018860 ps |
| T329 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2252187332 |
|
|
Jul 20 08:19:41 PM PDT 24 |
Jul 20 08:28:05 PM PDT 24 |
4568860496 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3342597441 |
|
|
Jul 20 07:50:51 PM PDT 24 |
Jul 20 08:01:39 PM PDT 24 |
3688455032 ps |
| T1003 |
/workspace/coverage/default/0.rom_keymgr_functest.455413607 |
|
|
Jul 20 07:54:06 PM PDT 24 |
Jul 20 08:06:35 PM PDT 24 |
3775790312 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2769337107 |
|
|
Jul 20 08:08:22 PM PDT 24 |
Jul 20 08:13:48 PM PDT 24 |
2874402890 ps |
| T1005 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3481093882 |
|
|
Jul 20 08:19:10 PM PDT 24 |
Jul 20 08:29:50 PM PDT 24 |
4506791966 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3996852230 |
|
|
Jul 20 07:59:39 PM PDT 24 |
Jul 20 08:10:13 PM PDT 24 |
5101279554 ps |
| T1006 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.729254237 |
|
|
Jul 20 08:17:31 PM PDT 24 |
Jul 20 08:36:05 PM PDT 24 |
8603992458 ps |
| T1007 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.605185064 |
|
|
Jul 20 08:05:59 PM PDT 24 |
Jul 20 08:14:05 PM PDT 24 |
10712686178 ps |
| T785 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1434991824 |
|
|
Jul 20 08:08:47 PM PDT 24 |
Jul 20 08:14:27 PM PDT 24 |
3479309857 ps |
| T330 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2929795601 |
|
|
Jul 20 08:13:30 PM PDT 24 |
Jul 20 08:28:46 PM PDT 24 |
5582069090 ps |
| T793 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.704769192 |
|
|
Jul 20 08:23:16 PM PDT 24 |
Jul 20 08:28:55 PM PDT 24 |
3392371590 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_example_rom.3271950323 |
|
|
Jul 20 08:05:54 PM PDT 24 |
Jul 20 08:08:16 PM PDT 24 |
2513889776 ps |
| T794 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1785248491 |
|
|
Jul 20 08:24:35 PM PDT 24 |
Jul 20 08:36:23 PM PDT 24 |
5595811774 ps |
| T256 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.785331536 |
|
|
Jul 20 07:57:31 PM PDT 24 |
Jul 20 08:07:58 PM PDT 24 |
5159488068 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3804063197 |
|
|
Jul 20 08:09:40 PM PDT 24 |
Jul 20 08:14:59 PM PDT 24 |
2920129658 ps |
| T158 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3428443354 |
|
|
Jul 20 07:52:08 PM PDT 24 |
Jul 20 08:00:35 PM PDT 24 |
3865578800 ps |
| T1010 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2858391040 |
|
|
Jul 20 08:01:06 PM PDT 24 |
Jul 20 08:10:37 PM PDT 24 |
4811820438 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_aes_idle.981339318 |
|
|
Jul 20 07:50:26 PM PDT 24 |
Jul 20 07:54:49 PM PDT 24 |
2638730280 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1107549720 |
|
|
Jul 20 07:52:54 PM PDT 24 |
Jul 20 08:33:31 PM PDT 24 |
10416456672 ps |
| T799 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.2621478043 |
|
|
Jul 20 08:20:24 PM PDT 24 |
Jul 20 08:32:51 PM PDT 24 |
5142946050 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.122197375 |
|
|
Jul 20 07:59:59 PM PDT 24 |
Jul 20 08:05:04 PM PDT 24 |
2652747340 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1253395118 |
|
|
Jul 20 07:57:53 PM PDT 24 |
Jul 20 08:02:20 PM PDT 24 |
2815728824 ps |
| T786 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2335276712 |
|
|
Jul 20 08:18:57 PM PDT 24 |
Jul 20 08:31:12 PM PDT 24 |
5205178120 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.605300911 |
|
|
Jul 20 07:52:09 PM PDT 24 |
Jul 20 08:00:07 PM PDT 24 |
3783480616 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3757164752 |
|
|
Jul 20 07:51:10 PM PDT 24 |
Jul 20 08:03:56 PM PDT 24 |
3813565492 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2168769618 |
|
|
Jul 20 08:01:04 PM PDT 24 |
Jul 20 09:05:02 PM PDT 24 |
16894513544 ps |
| T824 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182906132 |
|
|
Jul 20 08:21:56 PM PDT 24 |
Jul 20 08:28:25 PM PDT 24 |
3166204660 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.476099974 |
|
|
Jul 20 08:18:08 PM PDT 24 |
Jul 20 08:22:47 PM PDT 24 |
2191802248 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2090100429 |
|
|
Jul 20 07:50:53 PM PDT 24 |
Jul 20 09:01:29 PM PDT 24 |
40460192007 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.420060460 |
|
|
Jul 20 08:06:51 PM PDT 24 |
Jul 20 09:35:45 PM PDT 24 |
44015377234 ps |
| T1018 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1388887914 |
|
|
Jul 20 08:18:05 PM PDT 24 |
Jul 20 08:27:28 PM PDT 24 |
4225078734 ps |
| T358 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2490268594 |
|
|
Jul 20 08:24:02 PM PDT 24 |
Jul 20 08:33:12 PM PDT 24 |
4301497150 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1352020672 |
|
|
Jul 20 08:08:48 PM PDT 24 |
Jul 20 08:24:14 PM PDT 24 |
8333031528 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.205056940 |
|
|
Jul 20 07:57:14 PM PDT 24 |
Jul 20 08:05:59 PM PDT 24 |
5568332746 ps |
| T1021 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2448987906 |
|
|
Jul 20 07:55:49 PM PDT 24 |
Jul 20 07:59:10 PM PDT 24 |
2967055800 ps |
| T275 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3746427153 |
|
|
Jul 20 07:50:55 PM PDT 24 |
Jul 20 08:03:58 PM PDT 24 |
6720873850 ps |
| T850 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.4059219627 |
|
|
Jul 20 08:21:14 PM PDT 24 |
Jul 20 08:33:44 PM PDT 24 |
6262877064 ps |
| T407 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2354112506 |
|
|
Jul 20 08:01:12 PM PDT 24 |
Jul 20 09:38:11 PM PDT 24 |
24183679840 ps |
| T722 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1431736250 |
|
|
Jul 20 07:56:55 PM PDT 24 |
Jul 20 08:01:52 PM PDT 24 |
2754263142 ps |
| T1022 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4100288021 |
|
|
Jul 20 08:13:55 PM PDT 24 |
Jul 20 08:20:23 PM PDT 24 |
4768381246 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3731785320 |
|
|
Jul 20 07:58:37 PM PDT 24 |
Jul 20 08:07:06 PM PDT 24 |
4246235960 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1172931461 |
|
|
Jul 20 07:55:59 PM PDT 24 |
Jul 20 11:56:43 PM PDT 24 |
77806176703 ps |
| T80 |
/workspace/coverage/default/0.rom_raw_unlock.1171812669 |
|
|
Jul 20 07:54:37 PM PDT 24 |
Jul 20 07:58:35 PM PDT 24 |
4514608097 ps |
| T542 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3213331579 |
|
|
Jul 20 08:09:12 PM PDT 24 |
Jul 20 08:23:11 PM PDT 24 |
4885530320 ps |
| T10 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3900793420 |
|
|
Jul 20 07:50:58 PM PDT 24 |
Jul 20 07:59:32 PM PDT 24 |
6163326648 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2786999687 |
|
|
Jul 20 07:49:54 PM PDT 24 |
Jul 20 08:36:40 PM PDT 24 |
31107764396 ps |
| T1024 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2970851425 |
|
|
Jul 20 08:16:11 PM PDT 24 |
Jul 20 08:24:48 PM PDT 24 |
7205856784 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.837131127 |
|
|
Jul 20 08:06:50 PM PDT 24 |
Jul 20 08:16:10 PM PDT 24 |
4478857950 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1117678642 |
|
|
Jul 20 07:52:34 PM PDT 24 |
Jul 20 07:57:36 PM PDT 24 |
3158344564 ps |
| T803 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2142437256 |
|
|
Jul 20 08:24:35 PM PDT 24 |
Jul 20 08:35:09 PM PDT 24 |
5558297392 ps |
| T1027 |
/workspace/coverage/default/0.rom_e2e_smoke.2851287605 |
|
|
Jul 20 07:58:59 PM PDT 24 |
Jul 20 08:53:08 PM PDT 24 |
14664146568 ps |
| T360 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2526179386 |
|
|
Jul 20 08:07:05 PM PDT 24 |
Jul 20 08:18:03 PM PDT 24 |
4031806414 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4214093276 |
|
|
Jul 20 07:52:43 PM PDT 24 |
Jul 20 08:04:54 PM PDT 24 |
5197465479 ps |
| T1028 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1752609236 |
|
|
Jul 20 07:54:22 PM PDT 24 |
Jul 20 07:58:27 PM PDT 24 |
3008476150 ps |
| T1029 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.4270667654 |
|
|
Jul 20 07:55:34 PM PDT 24 |
Jul 20 08:00:36 PM PDT 24 |
2161236720 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1387836247 |
|
|
Jul 20 08:09:02 PM PDT 24 |
Jul 20 09:44:35 PM PDT 24 |
46619489272 ps |
| T791 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.1342083542 |
|
|
Jul 20 08:17:43 PM PDT 24 |
Jul 20 08:28:20 PM PDT 24 |
5352929898 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3499258380 |
|
|
Jul 20 08:02:15 PM PDT 24 |
Jul 20 08:15:05 PM PDT 24 |
3924699280 ps |
| T765 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2361190092 |
|
|
Jul 20 08:23:00 PM PDT 24 |
Jul 20 08:31:50 PM PDT 24 |
5882674616 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1175688038 |
|
|
Jul 20 08:08:17 PM PDT 24 |
Jul 20 08:14:23 PM PDT 24 |
2997676510 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1880862450 |
|
|
Jul 20 07:58:15 PM PDT 24 |
Jul 20 08:01:14 PM PDT 24 |
2617362161 ps |
| T1032 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2528716268 |
|
|
Jul 20 07:58:27 PM PDT 24 |
Jul 20 08:55:47 PM PDT 24 |
14962520918 ps |
| T369 |
/workspace/coverage/default/0.chip_sival_flash_info_access.764561516 |
|
|
Jul 20 07:49:05 PM PDT 24 |
Jul 20 07:53:25 PM PDT 24 |
2791780568 ps |
| T1033 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.418677336 |
|
|
Jul 20 08:14:40 PM PDT 24 |
Jul 20 08:18:07 PM PDT 24 |
2479379552 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2578231506 |
|
|
Jul 20 08:11:51 PM PDT 24 |
Jul 20 08:21:08 PM PDT 24 |
4818011784 ps |
| T800 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.323661837 |
|
|
Jul 20 08:24:53 PM PDT 24 |
Jul 20 08:32:49 PM PDT 24 |
5353043096 ps |
| T1034 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3650324282 |
|
|
Jul 20 07:49:48 PM PDT 24 |
Jul 20 08:07:03 PM PDT 24 |
6627176770 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1781265970 |
|
|
Jul 20 07:55:04 PM PDT 24 |
Jul 20 08:04:53 PM PDT 24 |
3451946301 ps |
| T211 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1841854520 |
|
|
Jul 20 08:07:19 PM PDT 24 |
Jul 20 08:20:47 PM PDT 24 |
6614242925 ps |
| T788 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3859362968 |
|
|
Jul 20 08:23:35 PM PDT 24 |
Jul 20 08:39:22 PM PDT 24 |
5994863826 ps |
| T189 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1530425230 |
|
|
Jul 20 07:52:59 PM PDT 24 |
Jul 20 08:05:26 PM PDT 24 |
7212887864 ps |
| T809 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552206452 |
|
|
Jul 20 08:31:02 PM PDT 24 |
Jul 20 08:36:52 PM PDT 24 |
3036673900 ps |
| T777 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.790363953 |
|
|
Jul 20 08:20:03 PM PDT 24 |
Jul 20 08:27:23 PM PDT 24 |
3548603072 ps |
| T160 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.996807704 |
|
|
Jul 20 07:49:47 PM PDT 24 |
Jul 20 07:58:36 PM PDT 24 |
4948633046 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3625107723 |
|
|
Jul 20 08:10:55 PM PDT 24 |
Jul 20 08:47:33 PM PDT 24 |
30607590733 ps |
| T1036 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3270693332 |
|
|
Jul 20 08:14:43 PM PDT 24 |
Jul 20 08:17:53 PM PDT 24 |
2938460364 ps |
| T14 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.554691758 |
|
|
Jul 20 07:55:02 PM PDT 24 |
Jul 20 08:00:36 PM PDT 24 |
4934137808 ps |
| T1037 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1991436557 |
|
|
Jul 20 08:07:26 PM PDT 24 |
Jul 20 08:30:12 PM PDT 24 |
8813502874 ps |
| T123 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1643887523 |
|
|
Jul 20 08:10:55 PM PDT 24 |
Jul 20 08:37:04 PM PDT 24 |
7875083184 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.3183115708 |
|
|
Jul 20 07:48:39 PM PDT 24 |
Jul 20 08:18:41 PM PDT 24 |
7933574932 ps |
| T334 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1645086008 |
|
|
Jul 20 07:49:51 PM PDT 24 |
Jul 20 08:03:05 PM PDT 24 |
4643561922 ps |
| T782 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.832831145 |
|
|
Jul 20 08:22:05 PM PDT 24 |
Jul 20 08:30:21 PM PDT 24 |
5864443304 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.215614006 |
|
|
Jul 20 08:10:33 PM PDT 24 |
Jul 20 11:20:07 PM PDT 24 |
255149989440 ps |
| T1038 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2952351791 |
|
|
Jul 20 07:51:59 PM PDT 24 |
Jul 20 09:25:17 PM PDT 24 |
23565187048 ps |
| T1039 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3607904794 |
|
|
Jul 20 08:11:32 PM PDT 24 |
Jul 20 08:19:06 PM PDT 24 |
4512785040 ps |
| T159 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3502875820 |
|
|
Jul 20 08:13:10 PM PDT 24 |
Jul 20 08:22:43 PM PDT 24 |
3575267480 ps |
| T1040 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2418977337 |
|
|
Jul 20 07:58:37 PM PDT 24 |
Jul 20 08:03:50 PM PDT 24 |
5111732950 ps |
| T142 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3015539012 |
|
|
Jul 20 07:53:49 PM PDT 24 |
Jul 20 08:00:40 PM PDT 24 |
5187559776 ps |
| T1041 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2688613958 |
|
|
Jul 20 08:08:29 PM PDT 24 |
Jul 20 09:02:23 PM PDT 24 |
15949289444 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2600832884 |
|
|
Jul 20 07:52:28 PM PDT 24 |
Jul 20 08:05:20 PM PDT 24 |
2999030280 ps |
| T1042 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.772822373 |
|
|
Jul 20 07:59:36 PM PDT 24 |
Jul 20 09:01:56 PM PDT 24 |
15346174904 ps |
| T1043 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.570084676 |
|
|
Jul 20 08:18:35 PM PDT 24 |
Jul 20 08:26:05 PM PDT 24 |
4088086960 ps |
| T366 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.145449058 |
|
|
Jul 20 08:28:18 PM PDT 24 |
Jul 20 08:38:49 PM PDT 24 |
5535420876 ps |
| T402 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180510691 |
|
|
Jul 20 08:22:20 PM PDT 24 |
Jul 20 08:28:00 PM PDT 24 |
3848638212 ps |
| T1044 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4284015093 |
|
|
Jul 20 07:51:10 PM PDT 24 |
Jul 20 07:57:12 PM PDT 24 |
3617096465 ps |
| T1045 |
/workspace/coverage/default/3.chip_tap_straps_prod.3824927476 |
|
|
Jul 20 08:15:48 PM PDT 24 |
Jul 20 08:18:43 PM PDT 24 |
2877354403 ps |
| T70 |
/workspace/coverage/default/2.chip_tap_straps_rma.1072024039 |
|
|
Jul 20 08:12:48 PM PDT 24 |
Jul 20 08:16:42 PM PDT 24 |
3504404214 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2999280725 |
|
|
Jul 20 08:01:12 PM PDT 24 |
Jul 20 08:32:25 PM PDT 24 |
9847592178 ps |
| T1046 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1804637548 |
|
|
Jul 20 07:50:52 PM PDT 24 |
Jul 20 07:56:36 PM PDT 24 |
3187631486 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3377120345 |
|
|
Jul 20 08:06:24 PM PDT 24 |
Jul 20 08:11:54 PM PDT 24 |
3064892114 ps |
| T129 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1650850154 |
|
|
Jul 20 07:50:56 PM PDT 24 |
Jul 20 07:59:43 PM PDT 24 |
6789566620 ps |
| T1047 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1140791341 |
|
|
Jul 20 08:21:21 PM PDT 24 |
Jul 20 08:33:36 PM PDT 24 |
4432252968 ps |
| T265 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2295642795 |
|
|
Jul 20 07:52:43 PM PDT 24 |
Jul 20 08:24:37 PM PDT 24 |
11358213626 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2541569957 |
|
|
Jul 20 07:51:35 PM PDT 24 |
Jul 20 08:43:08 PM PDT 24 |
12915455297 ps |
| T131 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2277142280 |
|
|
Jul 20 08:12:37 PM PDT 24 |
Jul 20 08:20:42 PM PDT 24 |
4862293060 ps |
| T841 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.459822646 |
|
|
Jul 20 08:23:12 PM PDT 24 |
Jul 20 08:30:23 PM PDT 24 |
3640190536 ps |
| T1048 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1562848825 |
|
|
Jul 20 08:20:50 PM PDT 24 |
Jul 20 09:23:54 PM PDT 24 |
18798110248 ps |
| T153 |
/workspace/coverage/default/2.rom_raw_unlock.2045112911 |
|
|
Jul 20 08:17:42 PM PDT 24 |
Jul 20 08:21:43 PM PDT 24 |
6027933907 ps |
| T1049 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3348837130 |
|
|
Jul 20 07:50:00 PM PDT 24 |
Jul 20 08:01:14 PM PDT 24 |
3872895596 ps |
| T316 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.409809739 |
|
|
Jul 20 08:24:05 PM PDT 24 |
Jul 20 08:33:16 PM PDT 24 |
4889428968 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4153997802 |
|
|
Jul 20 07:51:46 PM PDT 24 |
Jul 20 08:16:03 PM PDT 24 |
8212679592 ps |
| T110 |
/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2801577784 |
|
|
Jul 20 07:54:06 PM PDT 24 |
Jul 20 08:27:07 PM PDT 24 |
16020285025 ps |
| T783 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2773361360 |
|
|
Jul 20 08:18:56 PM PDT 24 |
Jul 20 08:28:05 PM PDT 24 |
4362741880 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2414022813 |
|
|
Jul 20 07:50:20 PM PDT 24 |
Jul 20 07:58:35 PM PDT 24 |
4768539000 ps |
| T1052 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1801127666 |
|
|
Jul 20 07:55:39 PM PDT 24 |
Jul 20 08:06:20 PM PDT 24 |
4277542708 ps |
| T1053 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3713087015 |
|
|
Jul 20 07:53:27 PM PDT 24 |
Jul 20 08:03:18 PM PDT 24 |
4569477368 ps |
| T1054 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2072062622 |
|
|
Jul 20 08:20:26 PM PDT 24 |
Jul 20 08:41:15 PM PDT 24 |
8424542856 ps |
| T1055 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3198358729 |
|
|
Jul 20 07:53:25 PM PDT 24 |
Jul 20 08:05:16 PM PDT 24 |
3972660268 ps |
| T317 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2385321235 |
|
|
Jul 20 08:21:48 PM PDT 24 |
Jul 20 08:31:20 PM PDT 24 |
4775081456 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2974171577 |
|
|
Jul 20 08:10:34 PM PDT 24 |
Jul 20 08:45:35 PM PDT 24 |
8844328928 ps |
| T1057 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2051010759 |
|
|
Jul 20 07:50:13 PM PDT 24 |
Jul 20 07:56:48 PM PDT 24 |
7093116840 ps |
| T370 |
/workspace/coverage/default/2.chip_sw_hmac_enc.4050533442 |
|
|
Jul 20 08:10:23 PM PDT 24 |
Jul 20 08:15:44 PM PDT 24 |
2731850928 ps |
| T703 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2038471760 |
|
|
Jul 20 07:49:35 PM PDT 24 |
Jul 20 07:51:44 PM PDT 24 |
1971804514 ps |
| T83 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2875615446 |
|
|
Jul 20 08:01:04 PM PDT 24 |
Jul 20 08:07:30 PM PDT 24 |
4023378493 ps |
| T1058 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3341752187 |
|
|
Jul 20 08:20:30 PM PDT 24 |
Jul 20 09:24:23 PM PDT 24 |
15298055050 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.862950319 |
|
|
Jul 20 07:54:31 PM PDT 24 |
Jul 20 08:42:29 PM PDT 24 |
27625945935 ps |
| T1060 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2536594636 |
|
|
Jul 20 08:24:09 PM PDT 24 |
Jul 20 08:33:06 PM PDT 24 |
5205302312 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3224420587 |
|
|
Jul 20 08:02:35 PM PDT 24 |
Jul 20 08:22:32 PM PDT 24 |
7571544260 ps |
| T252 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1800025082 |
|
|
Jul 20 08:06:36 PM PDT 24 |
Jul 20 08:16:08 PM PDT 24 |
4723930282 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3504680439 |
|
|
Jul 20 08:06:40 PM PDT 24 |
Jul 20 08:10:03 PM PDT 24 |
2994846482 ps |
| T802 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001543232 |
|
|
Jul 20 08:22:19 PM PDT 24 |
Jul 20 08:28:06 PM PDT 24 |
3505855850 ps |
| T111 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3233636731 |
|
|
Jul 20 08:13:56 PM PDT 24 |
Jul 20 08:49:01 PM PDT 24 |
18362380196 ps |
| T291 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3126242805 |
|
|
Jul 20 08:01:25 PM PDT 24 |
Jul 20 08:10:29 PM PDT 24 |
4020609208 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2140531771 |
|
|
Jul 20 07:59:18 PM PDT 24 |
Jul 20 08:03:42 PM PDT 24 |
2629671004 ps |
| T45 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.693517791 |
|
|
Jul 20 07:50:01 PM PDT 24 |
Jul 20 07:56:52 PM PDT 24 |
4808411256 ps |
| T1064 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1348985075 |
|
|
Jul 20 08:02:08 PM PDT 24 |
Jul 20 08:06:56 PM PDT 24 |
2568814856 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3411081669 |
|
|
Jul 20 07:56:09 PM PDT 24 |
Jul 20 09:38:48 PM PDT 24 |
50399551121 ps |
| T1065 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3911450928 |
|
|
Jul 20 07:49:40 PM PDT 24 |
Jul 20 07:54:05 PM PDT 24 |
3031141600 ps |
| T1066 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2378593628 |
|
|
Jul 20 08:05:44 PM PDT 24 |
Jul 20 08:30:38 PM PDT 24 |
11411587192 ps |
| T58 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1355586697 |
|
|
Jul 20 07:49:18 PM PDT 24 |
Jul 20 07:58:09 PM PDT 24 |
4149559080 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3908515033 |
|
|
Jul 20 07:59:06 PM PDT 24 |
Jul 20 08:08:43 PM PDT 24 |
4953699018 ps |
| T1068 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2952750771 |
|
|
Jul 20 08:10:25 PM PDT 24 |
Jul 20 09:09:28 PM PDT 24 |
15040590152 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3975353624 |
|
|
Jul 20 08:08:05 PM PDT 24 |
Jul 20 08:13:47 PM PDT 24 |
3116242369 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2657095738 |
|
|
Jul 20 07:54:21 PM PDT 24 |
Jul 20 07:57:42 PM PDT 24 |
3207425296 ps |
| T1070 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3287092285 |
|
|
Jul 20 08:08:14 PM PDT 24 |
Jul 20 08:14:57 PM PDT 24 |
4811888810 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3198584320 |
|
|
Jul 20 07:49:59 PM PDT 24 |
Jul 20 08:09:17 PM PDT 24 |
11384524692 ps |
| T779 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1019306677 |
|
|
Jul 20 08:25:31 PM PDT 24 |
Jul 20 08:36:16 PM PDT 24 |
6464383552 ps |
| T81 |
/workspace/coverage/default/1.chip_jtag_mem_access.754474044 |
|
|
Jul 20 07:55:09 PM PDT 24 |
Jul 20 08:19:58 PM PDT 24 |
13492077343 ps |
| T781 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.427623400 |
|
|
Jul 20 08:05:43 PM PDT 24 |
Jul 20 08:15:52 PM PDT 24 |
5661824312 ps |
| T832 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562002077 |
|
|
Jul 20 08:24:43 PM PDT 24 |
Jul 20 08:30:23 PM PDT 24 |
3541721422 ps |
| T193 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1155010384 |
|
|
Jul 20 08:03:11 PM PDT 24 |
Jul 20 08:07:43 PM PDT 24 |
3059980556 ps |
| T1072 |
/workspace/coverage/default/0.rom_e2e_static_critical.1466287310 |
|
|
Jul 20 08:00:44 PM PDT 24 |
Jul 20 09:01:51 PM PDT 24 |
16906646600 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3320520063 |
|
|
Jul 20 08:11:43 PM PDT 24 |
Jul 20 09:23:11 PM PDT 24 |
16117437960 ps |
| T257 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.811384292 |
|
|
Jul 20 08:26:52 PM PDT 24 |
Jul 20 08:37:04 PM PDT 24 |
5834362456 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2306036585 |
|
|
Jul 20 08:07:29 PM PDT 24 |
Jul 20 08:21:41 PM PDT 24 |
5284902870 ps |
| T1073 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.329733177 |
|
|
Jul 20 07:48:47 PM PDT 24 |
Jul 20 07:53:56 PM PDT 24 |
3339916932 ps |
| T780 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2435459882 |
|
|
Jul 20 08:26:03 PM PDT 24 |
Jul 20 08:35:30 PM PDT 24 |
4880010452 ps |
| T1074 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4033408038 |
|
|
Jul 20 08:08:37 PM PDT 24 |
Jul 20 08:54:01 PM PDT 24 |
10766294149 ps |
| T1075 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3936375050 |
|
|
Jul 20 07:57:18 PM PDT 24 |
Jul 20 08:21:31 PM PDT 24 |
8258442232 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2278240477 |
|
|
Jul 20 07:57:46 PM PDT 24 |
Jul 20 08:33:45 PM PDT 24 |
9227686524 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.454060386 |
|
|
Jul 20 07:50:03 PM PDT 24 |
Jul 20 07:59:08 PM PDT 24 |
5632274892 ps |
| T403 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1494324945 |
|
|
Jul 20 07:55:34 PM PDT 24 |
Jul 20 08:09:22 PM PDT 24 |
4893351328 ps |
| T1077 |
/workspace/coverage/default/0.rom_e2e_self_hash.2144518379 |
|
|
Jul 20 07:57:02 PM PDT 24 |
Jul 20 10:03:46 PM PDT 24 |
26255296024 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.702500729 |
|
|
Jul 20 07:51:12 PM PDT 24 |
Jul 20 08:31:36 PM PDT 24 |
10897951486 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1246647075 |
|
|
Jul 20 08:07:15 PM PDT 24 |
Jul 20 08:18:57 PM PDT 24 |
4173881678 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.389963613 |
|
|
Jul 20 07:51:15 PM PDT 24 |
Jul 20 08:26:16 PM PDT 24 |
7865942552 ps |
| T851 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483759658 |
|
|
Jul 20 08:28:56 PM PDT 24 |
Jul 20 08:33:38 PM PDT 24 |
3648073156 ps |
| T15 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.362278759 |
|
|
Jul 20 08:13:15 PM PDT 24 |
Jul 20 08:35:18 PM PDT 24 |
21714273480 ps |
| T87 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134106517 |
|
|
Jul 20 08:19:12 PM PDT 24 |
Jul 20 08:26:06 PM PDT 24 |
3749969904 ps |
| T35 |
/workspace/coverage/default/2.chip_sw_gpio.3818547904 |
|
|
Jul 20 08:07:52 PM PDT 24 |
Jul 20 08:15:35 PM PDT 24 |
3713500958 ps |
| T92 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.42773922 |
|
|
Jul 20 08:03:17 PM PDT 24 |
Jul 20 08:14:56 PM PDT 24 |
3626309616 ps |
| T93 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.90451407 |
|
|
Jul 20 07:51:33 PM PDT 24 |
Jul 20 08:01:57 PM PDT 24 |
5018392424 ps |
| T94 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1614056632 |
|
|
Jul 20 08:03:30 PM PDT 24 |
Jul 20 10:10:35 PM PDT 24 |
52198700951 ps |
| T95 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2962417308 |
|
|
Jul 20 08:18:32 PM PDT 24 |
Jul 20 08:26:54 PM PDT 24 |
4896799400 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3029865984 |
|
|
Jul 20 07:57:08 PM PDT 24 |
Jul 20 09:30:51 PM PDT 24 |
48779507060 ps |
| T97 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2297611989 |
|
|
Jul 20 08:08:52 PM PDT 24 |
Jul 20 09:07:47 PM PDT 24 |
15449301302 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.169537956 |
|
|
Jul 20 07:52:35 PM PDT 24 |
Jul 20 08:04:01 PM PDT 24 |
8824800651 ps |
| T99 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679379477 |
|
|
Jul 20 08:23:48 PM PDT 24 |
Jul 20 08:31:17 PM PDT 24 |
3781268264 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2586227417 |
|
|
Jul 20 07:51:19 PM PDT 24 |
Jul 20 08:41:17 PM PDT 24 |
10659827076 ps |
| T1080 |
/workspace/coverage/default/0.chip_tap_straps_dev.2786491371 |
|
|
Jul 20 07:51:27 PM PDT 24 |
Jul 20 08:21:52 PM PDT 24 |
15278653852 ps |
| T13 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3558905006 |
|
|
Jul 20 07:55:40 PM PDT 24 |
Jul 20 08:01:13 PM PDT 24 |
5055173444 ps |
| T1081 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1980472569 |
|
|
Jul 20 07:49:50 PM PDT 24 |
Jul 20 08:03:05 PM PDT 24 |
4753841912 ps |