| T1082 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1842890481 |
|
|
Jul 20 07:59:12 PM PDT 24 |
Jul 20 08:13:47 PM PDT 24 |
6608097534 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4087225192 |
|
|
Jul 20 08:12:49 PM PDT 24 |
Jul 20 08:17:24 PM PDT 24 |
2896984280 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3331157500 |
|
|
Jul 20 07:48:55 PM PDT 24 |
Jul 20 08:03:55 PM PDT 24 |
6344277122 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_alert_test.2238657943 |
|
|
Jul 20 07:58:14 PM PDT 24 |
Jul 20 08:04:47 PM PDT 24 |
3325079780 ps |
| T1084 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.923895315 |
|
|
Jul 20 07:55:49 PM PDT 24 |
Jul 20 09:43:30 PM PDT 24 |
23844882040 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3839036098 |
|
|
Jul 20 07:49:26 PM PDT 24 |
Jul 20 07:54:21 PM PDT 24 |
2917963032 ps |
| T346 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1239079245 |
|
|
Jul 20 07:48:58 PM PDT 24 |
Jul 20 07:54:58 PM PDT 24 |
4286257620 ps |
| T1086 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3636002176 |
|
|
Jul 20 07:48:58 PM PDT 24 |
Jul 20 09:17:43 PM PDT 24 |
47497555448 ps |
| T1087 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.258748805 |
|
|
Jul 20 08:07:21 PM PDT 24 |
Jul 20 08:26:40 PM PDT 24 |
8599292280 ps |
| T820 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.275197828 |
|
|
Jul 20 07:54:30 PM PDT 24 |
Jul 20 08:07:56 PM PDT 24 |
4695824176 ps |
| T416 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4240526080 |
|
|
Jul 20 08:02:43 PM PDT 24 |
Jul 20 08:13:40 PM PDT 24 |
9819043832 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2960098698 |
|
|
Jul 20 07:50:51 PM PDT 24 |
Jul 20 07:59:06 PM PDT 24 |
3136556016 ps |
| T761 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2418515949 |
|
|
Jul 20 08:25:05 PM PDT 24 |
Jul 20 08:36:37 PM PDT 24 |
5899397240 ps |
| T797 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233765363 |
|
|
Jul 20 08:20:51 PM PDT 24 |
Jul 20 08:28:38 PM PDT 24 |
3668176696 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1433198924 |
|
|
Jul 20 07:54:35 PM PDT 24 |
Jul 20 09:26:10 PM PDT 24 |
42587487160 ps |
| T1089 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.866680381 |
|
|
Jul 20 07:53:52 PM PDT 24 |
Jul 20 07:57:00 PM PDT 24 |
2732284142 ps |
| T266 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1583809761 |
|
|
Jul 20 07:53:42 PM PDT 24 |
Jul 20 08:41:06 PM PDT 24 |
24963793195 ps |
| T1090 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.707983841 |
|
|
Jul 20 07:50:31 PM PDT 24 |
Jul 20 08:01:28 PM PDT 24 |
5570629726 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4132371863 |
|
|
Jul 20 07:52:25 PM PDT 24 |
Jul 20 08:10:33 PM PDT 24 |
9277521160 ps |
| T1092 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1338974844 |
|
|
Jul 20 08:09:38 PM PDT 24 |
Jul 20 09:07:51 PM PDT 24 |
14895277112 ps |
| T763 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194959650 |
|
|
Jul 20 08:23:51 PM PDT 24 |
Jul 20 08:31:24 PM PDT 24 |
4579004088 ps |
| T1093 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1408579053 |
|
|
Jul 20 08:25:31 PM PDT 24 |
Jul 20 08:33:35 PM PDT 24 |
5097707440 ps |
| T704 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4057346358 |
|
|
Jul 20 07:49:11 PM PDT 24 |
Jul 20 07:51:58 PM PDT 24 |
3280704445 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1697569717 |
|
|
Jul 20 07:56:34 PM PDT 24 |
Jul 20 08:21:33 PM PDT 24 |
21711665220 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.909434181 |
|
|
Jul 20 07:51:37 PM PDT 24 |
Jul 20 08:23:28 PM PDT 24 |
25402298410 ps |
| T1094 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.104442773 |
|
|
Jul 20 08:13:29 PM PDT 24 |
Jul 20 09:04:54 PM PDT 24 |
14816870794 ps |
| T700 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000439622 |
|
|
Jul 20 08:19:21 PM PDT 24 |
Jul 20 08:25:46 PM PDT 24 |
3681912184 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2898084113 |
|
|
Jul 20 08:11:45 PM PDT 24 |
Jul 20 08:25:34 PM PDT 24 |
4901534024 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3669691319 |
|
|
Jul 20 08:07:32 PM PDT 24 |
Jul 20 08:34:22 PM PDT 24 |
8900694187 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1828480355 |
|
|
Jul 20 08:05:38 PM PDT 24 |
Jul 20 08:11:00 PM PDT 24 |
2933345608 ps |
| T1098 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3014218341 |
|
|
Jul 20 07:55:18 PM PDT 24 |
Jul 20 08:05:57 PM PDT 24 |
4535753840 ps |
| T694 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.4002529835 |
|
|
Jul 20 07:59:41 PM PDT 24 |
Jul 20 08:08:25 PM PDT 24 |
2905846376 ps |
| T436 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.463361000 |
|
|
Jul 20 08:12:31 PM PDT 24 |
Jul 20 08:37:27 PM PDT 24 |
6526809200 ps |
| T1099 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3177141057 |
|
|
Jul 20 08:21:47 PM PDT 24 |
Jul 20 09:10:00 PM PDT 24 |
11674918077 ps |
| T1100 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1567046902 |
|
|
Jul 20 07:51:19 PM PDT 24 |
Jul 20 07:56:25 PM PDT 24 |
3648295626 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2085629128 |
|
|
Jul 20 07:59:27 PM PDT 24 |
Jul 20 08:24:56 PM PDT 24 |
7407731140 ps |
| T1101 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4255532656 |
|
|
Jul 20 07:57:37 PM PDT 24 |
Jul 20 09:13:51 PM PDT 24 |
14383563838 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3556604587 |
|
|
Jul 20 07:54:51 PM PDT 24 |
Jul 20 07:58:52 PM PDT 24 |
3131292472 ps |
| T378 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.1636251863 |
|
|
Jul 20 08:20:52 PM PDT 24 |
Jul 20 09:15:48 PM PDT 24 |
25965103394 ps |
| T1103 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3407715363 |
|
|
Jul 20 07:59:15 PM PDT 24 |
Jul 20 08:35:25 PM PDT 24 |
29994448046 ps |
| T705 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2430435490 |
|
|
Jul 20 07:57:44 PM PDT 24 |
Jul 20 07:59:34 PM PDT 24 |
2722599116 ps |
| T706 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3753031455 |
|
|
Jul 20 07:49:26 PM PDT 24 |
Jul 20 07:51:16 PM PDT 24 |
2351202409 ps |
| T1104 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.3956539371 |
|
|
Jul 20 07:59:13 PM PDT 24 |
Jul 20 09:06:11 PM PDT 24 |
14839448192 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3297878077 |
|
|
Jul 20 08:14:38 PM PDT 24 |
Jul 20 08:19:12 PM PDT 24 |
2522229480 ps |
| T1106 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2954514951 |
|
|
Jul 20 07:55:12 PM PDT 24 |
Jul 20 08:03:29 PM PDT 24 |
3907400488 ps |
| T746 |
/workspace/coverage/default/1.chip_sw_power_idle_load.4041322686 |
|
|
Jul 20 08:03:23 PM PDT 24 |
Jul 20 08:14:39 PM PDT 24 |
4234391272 ps |
| T1107 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3224368014 |
|
|
Jul 20 08:08:38 PM PDT 24 |
Jul 20 09:06:41 PM PDT 24 |
26329353208 ps |
| T1108 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1753991149 |
|
|
Jul 20 08:09:21 PM PDT 24 |
Jul 20 08:30:32 PM PDT 24 |
8102035492 ps |
| T1109 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.279483344 |
|
|
Jul 20 07:58:18 PM PDT 24 |
Jul 20 08:24:18 PM PDT 24 |
6841823786 ps |
| T1110 |
/workspace/coverage/default/4.chip_tap_straps_prod.4070008828 |
|
|
Jul 20 08:17:48 PM PDT 24 |
Jul 20 08:25:38 PM PDT 24 |
4817102492 ps |
| T1111 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1961286187 |
|
|
Jul 20 08:14:58 PM PDT 24 |
Jul 20 08:21:44 PM PDT 24 |
3079412248 ps |
| T318 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2006765138 |
|
|
Jul 20 08:22:13 PM PDT 24 |
Jul 20 08:32:21 PM PDT 24 |
4775743424 ps |
| T57 |
/workspace/coverage/default/2.chip_sw_alert_test.4190204856 |
|
|
Jul 20 08:10:52 PM PDT 24 |
Jul 20 08:16:57 PM PDT 24 |
2842559400 ps |
| T1112 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2157031607 |
|
|
Jul 20 08:02:13 PM PDT 24 |
Jul 20 08:09:59 PM PDT 24 |
3670436700 ps |
| T88 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2716662120 |
|
|
Jul 20 08:23:08 PM PDT 24 |
Jul 20 08:34:48 PM PDT 24 |
5169557498 ps |
| T1113 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1658144439 |
|
|
Jul 20 07:58:46 PM PDT 24 |
Jul 20 09:25:21 PM PDT 24 |
22638949642 ps |
| T1114 |
/workspace/coverage/default/0.chip_sw_coremark.2334467062 |
|
|
Jul 20 07:50:36 PM PDT 24 |
Jul 21 12:04:18 AM PDT 24 |
72092185400 ps |
| T1115 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.328212202 |
|
|
Jul 20 08:09:40 PM PDT 24 |
Jul 20 08:17:34 PM PDT 24 |
3663063680 ps |
| T1116 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2068912927 |
|
|
Jul 20 08:23:05 PM PDT 24 |
Jul 20 08:36:34 PM PDT 24 |
6071509978 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4158956530 |
|
|
Jul 20 08:10:12 PM PDT 24 |
Jul 20 08:20:05 PM PDT 24 |
5349770663 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.766535331 |
|
|
Jul 20 07:56:27 PM PDT 24 |
Jul 20 09:22:41 PM PDT 24 |
42774982140 ps |
| T1117 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2004420555 |
|
|
Jul 20 07:51:09 PM PDT 24 |
Jul 20 08:02:02 PM PDT 24 |
4982598616 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.605509523 |
|
|
Jul 20 07:58:07 PM PDT 24 |
Jul 20 08:03:28 PM PDT 24 |
3129957802 ps |
| T144 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1881611012 |
|
|
Jul 20 08:13:38 PM PDT 24 |
Jul 20 08:18:34 PM PDT 24 |
2811442539 ps |
| T293 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2696966120 |
|
|
Jul 20 08:07:13 PM PDT 24 |
Jul 20 08:16:04 PM PDT 24 |
4729678042 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1609876587 |
|
|
Jul 20 07:52:42 PM PDT 24 |
Jul 20 08:00:42 PM PDT 24 |
4507159712 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2737422334 |
|
|
Jul 20 07:52:54 PM PDT 24 |
Jul 20 08:25:16 PM PDT 24 |
19381888277 ps |
| T1119 |
/workspace/coverage/default/1.chip_sw_example_rom.2392884856 |
|
|
Jul 20 07:55:41 PM PDT 24 |
Jul 20 07:57:39 PM PDT 24 |
2414506376 ps |
| T319 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.906525639 |
|
|
Jul 20 08:06:24 PM PDT 24 |
Jul 20 08:16:31 PM PDT 24 |
5311479860 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.855859992 |
|
|
Jul 20 07:49:38 PM PDT 24 |
Jul 20 08:04:54 PM PDT 24 |
5143386328 ps |
| T695 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.101820600 |
|
|
Jul 20 08:13:42 PM PDT 24 |
Jul 20 08:24:33 PM PDT 24 |
3393190720 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3384167287 |
|
|
Jul 20 08:02:38 PM PDT 24 |
Jul 20 08:10:33 PM PDT 24 |
4199469780 ps |
| T1120 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.71278299 |
|
|
Jul 20 07:49:49 PM PDT 24 |
Jul 20 08:48:12 PM PDT 24 |
20420117556 ps |
| T736 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489069616 |
|
|
Jul 20 08:27:38 PM PDT 24 |
Jul 20 08:35:55 PM PDT 24 |
3443414778 ps |
| T1121 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3454734077 |
|
|
Jul 20 07:58:09 PM PDT 24 |
Jul 20 09:07:38 PM PDT 24 |
14757576733 ps |
| T1122 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1696825780 |
|
|
Jul 20 07:59:13 PM PDT 24 |
Jul 20 08:02:26 PM PDT 24 |
2734187104 ps |
| T821 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455163096 |
|
|
Jul 20 08:24:44 PM PDT 24 |
Jul 20 08:31:13 PM PDT 24 |
4481953480 ps |
| T702 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.656579110 |
|
|
Jul 20 08:13:36 PM PDT 24 |
Jul 20 08:26:05 PM PDT 24 |
4918785786 ps |
| T1123 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.7534360 |
|
|
Jul 20 07:57:42 PM PDT 24 |
Jul 20 08:01:54 PM PDT 24 |
2691113480 ps |
| T1124 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.652849014 |
|
|
Jul 20 08:15:27 PM PDT 24 |
Jul 20 08:25:51 PM PDT 24 |
8033900716 ps |
| T1125 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3921846231 |
|
|
Jul 20 07:56:03 PM PDT 24 |
Jul 20 08:09:48 PM PDT 24 |
10871295318 ps |
| T1126 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.213553100 |
|
|
Jul 20 07:50:23 PM PDT 24 |
Jul 20 08:29:06 PM PDT 24 |
9763499340 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.836781640 |
|
|
Jul 20 08:15:21 PM PDT 24 |
Jul 20 08:22:31 PM PDT 24 |
3144694232 ps |
| T214 |
/workspace/coverage/default/0.chip_jtag_mem_access.368247519 |
|
|
Jul 20 07:43:34 PM PDT 24 |
Jul 20 08:13:29 PM PDT 24 |
14594200844 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2440269343 |
|
|
Jul 20 08:05:51 PM PDT 24 |
Jul 20 08:13:49 PM PDT 24 |
5169972692 ps |
| T320 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3865842241 |
|
|
Jul 20 08:23:55 PM PDT 24 |
Jul 20 08:34:17 PM PDT 24 |
6095351000 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2764596705 |
|
|
Jul 20 07:57:52 PM PDT 24 |
Jul 20 09:25:54 PM PDT 24 |
28362082208 ps |
| T75 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2056176979 |
|
|
Jul 20 07:55:51 PM PDT 24 |
Jul 20 08:00:20 PM PDT 24 |
2176769218 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.998611755 |
|
|
Jul 20 08:07:55 PM PDT 24 |
Jul 20 08:12:53 PM PDT 24 |
2615308022 ps |
| T764 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1094410711 |
|
|
Jul 20 08:20:10 PM PDT 24 |
Jul 20 08:26:10 PM PDT 24 |
3573614896 ps |
| T215 |
/workspace/coverage/default/2.chip_jtag_mem_access.566815654 |
|
|
Jul 20 08:04:59 PM PDT 24 |
Jul 20 08:28:20 PM PDT 24 |
13706062664 ps |
| T194 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3856862548 |
|
|
Jul 20 08:15:39 PM PDT 24 |
Jul 20 08:21:16 PM PDT 24 |
3076591400 ps |
| T798 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1418249879 |
|
|
Jul 20 08:20:52 PM PDT 24 |
Jul 20 08:31:39 PM PDT 24 |
4560793300 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.710479809 |
|
|
Jul 20 08:11:06 PM PDT 24 |
Jul 20 08:40:56 PM PDT 24 |
7545105348 ps |
| T852 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3606090643 |
|
|
Jul 20 08:23:50 PM PDT 24 |
Jul 20 08:32:22 PM PDT 24 |
6154578164 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3761272317 |
|
|
Jul 20 08:01:18 PM PDT 24 |
Jul 20 08:23:04 PM PDT 24 |
6127562808 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.808579966 |
|
|
Jul 20 08:01:22 PM PDT 24 |
Jul 20 08:13:04 PM PDT 24 |
6669478373 ps |
| T812 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3686377173 |
|
|
Jul 20 08:23:19 PM PDT 24 |
Jul 20 08:34:12 PM PDT 24 |
5934534248 ps |
| T356 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4095886821 |
|
|
Jul 20 07:54:10 PM PDT 24 |
Jul 20 08:09:17 PM PDT 24 |
5185282818 ps |
| T1133 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3949719639 |
|
|
Jul 20 07:57:54 PM PDT 24 |
Jul 20 08:07:18 PM PDT 24 |
3868402740 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3646777562 |
|
|
Jul 20 07:51:34 PM PDT 24 |
Jul 20 08:01:22 PM PDT 24 |
4767671785 ps |
| T1134 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1619245810 |
|
|
Jul 20 08:16:51 PM PDT 24 |
Jul 20 08:22:36 PM PDT 24 |
5030793088 ps |
| T1135 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2534862748 |
|
|
Jul 20 08:15:04 PM PDT 24 |
Jul 20 08:21:14 PM PDT 24 |
2681076062 ps |
| T1136 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1735612173 |
|
|
Jul 20 07:55:48 PM PDT 24 |
Jul 20 08:41:37 PM PDT 24 |
13411241960 ps |
| T1137 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3815309041 |
|
|
Jul 20 07:49:33 PM PDT 24 |
Jul 20 07:57:51 PM PDT 24 |
6806572945 ps |
| T1138 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2684318563 |
|
|
Jul 20 08:15:05 PM PDT 24 |
Jul 20 08:22:40 PM PDT 24 |
5002283492 ps |
| T750 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.749233280 |
|
|
Jul 20 08:22:17 PM PDT 24 |
Jul 20 08:30:30 PM PDT 24 |
4558082206 ps |
| T844 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658134656 |
|
|
Jul 20 08:18:34 PM PDT 24 |
Jul 20 08:27:39 PM PDT 24 |
4067106432 ps |
| T46 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1593106901 |
|
|
Jul 20 08:08:49 PM PDT 24 |
Jul 20 08:16:49 PM PDT 24 |
4705011436 ps |
| T295 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2591837382 |
|
|
Jul 20 08:17:15 PM PDT 24 |
Jul 20 08:27:25 PM PDT 24 |
5353403668 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4231495584 |
|
|
Jul 20 08:11:58 PM PDT 24 |
Jul 20 08:25:02 PM PDT 24 |
3754688264 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4061095179 |
|
|
Jul 20 08:10:38 PM PDT 24 |
Jul 20 08:19:09 PM PDT 24 |
4532505624 ps |
| T426 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1523806693 |
|
|
Jul 20 07:57:15 PM PDT 24 |
Jul 20 08:45:12 PM PDT 24 |
39194705243 ps |
| T1141 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4024872911 |
|
|
Jul 20 08:07:04 PM PDT 24 |
Jul 20 08:16:48 PM PDT 24 |
4256185132 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2077752046 |
|
|
Jul 20 07:58:08 PM PDT 24 |
Jul 20 08:11:29 PM PDT 24 |
19156714368 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4214004647 |
|
|
Jul 20 08:09:11 PM PDT 24 |
Jul 20 08:29:05 PM PDT 24 |
9456395490 ps |
| T1144 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1310247217 |
|
|
Jul 20 08:14:47 PM PDT 24 |
Jul 20 08:45:53 PM PDT 24 |
9144926992 ps |
| T1145 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2693251560 |
|
|
Jul 20 07:52:25 PM PDT 24 |
Jul 20 08:02:11 PM PDT 24 |
5702723540 ps |
| T1146 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1749035998 |
|
|
Jul 20 08:17:37 PM PDT 24 |
Jul 20 08:25:57 PM PDT 24 |
7172441427 ps |
| T1147 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3402822097 |
|
|
Jul 20 08:12:24 PM PDT 24 |
Jul 20 08:32:03 PM PDT 24 |
10285922030 ps |
| T89 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809745559 |
|
|
Jul 20 08:23:56 PM PDT 24 |
Jul 20 08:31:00 PM PDT 24 |
4182598398 ps |
| T829 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2161887463 |
|
|
Jul 20 08:24:54 PM PDT 24 |
Jul 20 08:36:25 PM PDT 24 |
5821028178 ps |
| T154 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3836916175 |
|
|
Jul 20 07:54:00 PM PDT 24 |
Jul 20 11:06:09 PM PDT 24 |
59422575175 ps |
| T1148 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3439726227 |
|
|
Jul 20 07:57:43 PM PDT 24 |
Jul 20 08:45:55 PM PDT 24 |
11305997450 ps |
| T100 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.213745634 |
|
|
Jul 20 08:01:51 PM PDT 24 |
Jul 20 08:09:10 PM PDT 24 |
6822755634 ps |
| T707 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.373858613 |
|
|
Jul 20 08:09:38 PM PDT 24 |
Jul 20 08:11:29 PM PDT 24 |
2485021672 ps |
| T1149 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2377340291 |
|
|
Jul 20 07:59:32 PM PDT 24 |
Jul 20 09:02:31 PM PDT 24 |
15561527256 ps |
| T1150 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.67706858 |
|
|
Jul 20 07:56:13 PM PDT 24 |
Jul 20 08:05:56 PM PDT 24 |
4254442756 ps |
| T84 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2095740268 |
|
|
Jul 20 08:01:06 PM PDT 24 |
Jul 20 08:21:28 PM PDT 24 |
10901415476 ps |
| T1151 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3858384600 |
|
|
Jul 20 08:18:45 PM PDT 24 |
Jul 20 09:27:14 PM PDT 24 |
21739833740 ps |
| T1152 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3423687850 |
|
|
Jul 20 08:01:44 PM PDT 24 |
Jul 20 08:06:37 PM PDT 24 |
2985775384 ps |
| T1153 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4010733003 |
|
|
Jul 20 08:18:37 PM PDT 24 |
Jul 20 08:28:11 PM PDT 24 |
5207430252 ps |
| T1154 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3071539798 |
|
|
Jul 20 07:57:10 PM PDT 24 |
Jul 20 08:59:03 PM PDT 24 |
15197836005 ps |
| T1155 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3500060602 |
|
|
Jul 20 08:16:49 PM PDT 24 |
Jul 20 08:28:03 PM PDT 24 |
4419818904 ps |
| T1156 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.146572441 |
|
|
Jul 20 08:11:06 PM PDT 24 |
Jul 20 08:23:04 PM PDT 24 |
5114689686 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3958385787 |
|
|
Jul 20 07:52:37 PM PDT 24 |
Jul 20 08:04:59 PM PDT 24 |
4950917392 ps |
| T1158 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1788864372 |
|
|
Jul 20 07:53:55 PM PDT 24 |
Jul 20 07:57:08 PM PDT 24 |
3253232886 ps |
| T419 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3931417168 |
|
|
Jul 20 08:12:48 PM PDT 24 |
Jul 20 08:20:58 PM PDT 24 |
6880782732 ps |
| T1159 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3446589468 |
|
|
Jul 20 08:00:50 PM PDT 24 |
Jul 20 08:29:36 PM PDT 24 |
14918837591 ps |
| T1160 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.300048752 |
|
|
Jul 20 08:20:59 PM PDT 24 |
Jul 20 09:11:46 PM PDT 24 |
14233013694 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.397698479 |
|
|
Jul 20 08:13:15 PM PDT 24 |
Jul 20 08:31:11 PM PDT 24 |
7992985884 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.512690655 |
|
|
Jul 20 08:12:48 PM PDT 24 |
Jul 20 09:14:19 PM PDT 24 |
25434267933 ps |
| T1163 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3705148442 |
|
|
Jul 20 08:15:27 PM PDT 24 |
Jul 20 08:26:53 PM PDT 24 |
5392852526 ps |
| T1164 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1890763880 |
|
|
Jul 20 08:09:31 PM PDT 24 |
Jul 20 09:11:44 PM PDT 24 |
15843421432 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1789052359 |
|
|
Jul 20 08:06:57 PM PDT 24 |
Jul 20 08:15:12 PM PDT 24 |
3893821512 ps |
| T1166 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2422093807 |
|
|
Jul 20 07:49:29 PM PDT 24 |
Jul 20 07:56:12 PM PDT 24 |
4324732524 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.178021482 |
|
|
Jul 20 07:57:44 PM PDT 24 |
Jul 20 08:06:04 PM PDT 24 |
8361278792 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1600623047 |
|
|
Jul 20 07:57:05 PM PDT 24 |
Jul 20 09:32:36 PM PDT 24 |
45771075752 ps |
| T1169 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.525878755 |
|
|
Jul 20 07:58:14 PM PDT 24 |
Jul 20 08:02:39 PM PDT 24 |
2821124928 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3683109788 |
|
|
Jul 20 08:08:47 PM PDT 24 |
Jul 20 08:14:15 PM PDT 24 |
3667627531 ps |
| T1170 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3864034458 |
|
|
Jul 20 07:57:08 PM PDT 24 |
Jul 20 08:59:14 PM PDT 24 |
14190528087 ps |
| T1171 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1716763247 |
|
|
Jul 20 08:25:17 PM PDT 24 |
Jul 20 08:34:49 PM PDT 24 |
6269569832 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2456509388 |
|
|
Jul 20 08:11:01 PM PDT 24 |
Jul 20 09:10:38 PM PDT 24 |
17367958306 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.80500802 |
|
|
Jul 20 07:49:18 PM PDT 24 |
Jul 20 08:07:04 PM PDT 24 |
6094104086 ps |
| T1174 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3099517219 |
|
|
Jul 20 08:16:17 PM PDT 24 |
Jul 20 08:40:33 PM PDT 24 |
8462334430 ps |
| T382 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009195868 |
|
|
Jul 20 08:22:00 PM PDT 24 |
Jul 20 08:29:04 PM PDT 24 |
3767520000 ps |
| T384 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767300552 |
|
|
Jul 20 08:27:22 PM PDT 24 |
Jul 20 08:33:30 PM PDT 24 |
3224788396 ps |
| T8 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4209015577 |
|
|
Jul 20 07:53:27 PM PDT 24 |
Jul 20 08:01:41 PM PDT 24 |
5025189662 ps |
| T385 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.3837919309 |
|
|
Jul 20 07:53:11 PM PDT 24 |
Jul 20 07:54:58 PM PDT 24 |
2322059482 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2935793313 |
|
|
Jul 20 08:11:58 PM PDT 24 |
Jul 20 08:28:17 PM PDT 24 |
7157418400 ps |
| T387 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.772901232 |
|
|
Jul 20 08:10:46 PM PDT 24 |
Jul 20 08:21:13 PM PDT 24 |
4457795756 ps |
| T388 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3456656397 |
|
|
Jul 20 08:09:27 PM PDT 24 |
Jul 20 08:11:19 PM PDT 24 |
2302969990 ps |
| T389 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.582543375 |
|
|
Jul 20 08:11:46 PM PDT 24 |
Jul 20 08:32:13 PM PDT 24 |
8449221800 ps |
| T390 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2528116930 |
|
|
Jul 20 07:49:53 PM PDT 24 |
Jul 20 09:36:28 PM PDT 24 |
28177598248 ps |
| T391 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3068031982 |
|
|
Jul 20 08:25:21 PM PDT 24 |
Jul 20 08:32:27 PM PDT 24 |
3899644830 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3939890833 |
|
|
Jul 20 08:13:50 PM PDT 24 |
Jul 20 08:17:48 PM PDT 24 |
2894243318 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2503507203 |
|
|
Jul 20 08:08:19 PM PDT 24 |
Jul 20 09:04:43 PM PDT 24 |
40813583040 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1686845159 |
|
|
Jul 20 08:02:09 PM PDT 24 |
Jul 20 08:13:37 PM PDT 24 |
6909552804 ps |
| T813 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.192146883 |
|
|
Jul 20 08:18:32 PM PDT 24 |
Jul 20 08:30:10 PM PDT 24 |
5942848712 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3490736614 |
|
|
Jul 20 07:50:43 PM PDT 24 |
Jul 20 08:00:28 PM PDT 24 |
5199639420 ps |
| T549 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2983864060 |
|
|
Jul 20 07:52:36 PM PDT 24 |
Jul 20 08:00:55 PM PDT 24 |
4272659716 ps |
| T1179 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.659041880 |
|
|
Jul 20 08:22:31 PM PDT 24 |
Jul 20 08:29:36 PM PDT 24 |
3906834380 ps |
| T1180 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1288807117 |
|
|
Jul 20 07:51:38 PM PDT 24 |
Jul 20 07:56:40 PM PDT 24 |
3331519377 ps |
| T1181 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.278696973 |
|
|
Jul 20 08:10:43 PM PDT 24 |
Jul 20 08:16:15 PM PDT 24 |
3621829020 ps |
| T1182 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2718549393 |
|
|
Jul 20 08:11:54 PM PDT 24 |
Jul 20 08:21:35 PM PDT 24 |
5547519330 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3681167301 |
|
|
Jul 20 08:04:14 PM PDT 24 |
Jul 20 08:09:43 PM PDT 24 |
3757124303 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.258505851 |
|
|
Jul 20 08:00:31 PM PDT 24 |
Jul 20 08:08:08 PM PDT 24 |
4871412722 ps |
| T244 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2298627377 |
|
|
Jul 20 08:00:25 PM PDT 24 |
Jul 20 09:03:29 PM PDT 24 |
12896008306 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.4106823886 |
|
|
Jul 20 08:14:28 PM PDT 24 |
Jul 20 08:23:41 PM PDT 24 |
10158987904 ps |
| T1185 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1416449461 |
|
|
Jul 20 08:19:06 PM PDT 24 |
Jul 20 08:34:18 PM PDT 24 |
10535763310 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.805047048 |
|
|
Jul 20 08:03:13 PM PDT 24 |
Jul 20 08:17:31 PM PDT 24 |
4590527028 ps |
| T769 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.412348111 |
|
|
Jul 20 08:20:33 PM PDT 24 |
Jul 20 08:31:31 PM PDT 24 |
4255780522 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2376648248 |
|
|
Jul 20 07:49:48 PM PDT 24 |
Jul 20 07:58:15 PM PDT 24 |
5144748250 ps |
| T1188 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2354414311 |
|
|
Jul 20 07:52:07 PM PDT 24 |
Jul 20 08:30:37 PM PDT 24 |
7692587540 ps |
| T819 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2517464914 |
|
|
Jul 20 08:31:08 PM PDT 24 |
Jul 20 08:37:00 PM PDT 24 |
3244839650 ps |
| T1189 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1948990544 |
|
|
Jul 20 08:22:56 PM PDT 24 |
Jul 20 08:34:19 PM PDT 24 |
5835448432 ps |
| T847 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826540530 |
|
|
Jul 20 08:20:31 PM PDT 24 |
Jul 20 08:25:53 PM PDT 24 |
3546463220 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.922710859 |
|
|
Jul 20 08:01:45 PM PDT 24 |
Jul 20 08:12:06 PM PDT 24 |
4460031640 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3475326081 |
|
|
Jul 20 08:11:26 PM PDT 24 |
Jul 20 08:21:49 PM PDT 24 |
5828494958 ps |
| T268 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3706317684 |
|
|
Jul 20 07:56:59 PM PDT 24 |
Jul 20 08:30:28 PM PDT 24 |
10946629742 ps |
| T1191 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1585559453 |
|
|
Jul 20 08:13:44 PM PDT 24 |
Jul 20 08:44:26 PM PDT 24 |
13002076164 ps |
| T1192 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3264082634 |
|
|
Jul 20 07:57:03 PM PDT 24 |
Jul 20 09:01:14 PM PDT 24 |
14084915244 ps |
| T1193 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1560062648 |
|
|
Jul 20 08:19:51 PM PDT 24 |
Jul 20 08:28:37 PM PDT 24 |
7831198293 ps |
| T1194 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.490627876 |
|
|
Jul 20 08:20:48 PM PDT 24 |
Jul 20 08:30:22 PM PDT 24 |
4684462144 ps |
| T379 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3077980108 |
|
|
Jul 20 07:48:53 PM PDT 24 |
Jul 20 11:06:08 PM PDT 24 |
64052652492 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.1327960898 |
|
|
Jul 20 07:58:26 PM PDT 24 |
Jul 20 08:02:21 PM PDT 24 |
2895190702 ps |
| T845 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3060219978 |
|
|
Jul 20 08:24:29 PM PDT 24 |
Jul 20 08:36:43 PM PDT 24 |
5974390616 ps |
| T1196 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3499213792 |
|
|
Jul 20 08:19:21 PM PDT 24 |
Jul 20 09:07:04 PM PDT 24 |
14603408840 ps |
| T830 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2155952043 |
|
|
Jul 20 08:24:02 PM PDT 24 |
Jul 20 08:32:37 PM PDT 24 |
5319766284 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.477595784 |
|
|
Jul 20 07:50:28 PM PDT 24 |
Jul 20 08:00:27 PM PDT 24 |
4956401717 ps |
| T1197 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242544580 |
|
|
Jul 20 08:25:09 PM PDT 24 |
Jul 20 08:31:34 PM PDT 24 |
3687202890 ps |
| T1198 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1308492754 |
|
|
Jul 20 08:17:36 PM PDT 24 |
Jul 20 08:32:56 PM PDT 24 |
12649172321 ps |
| T839 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030448234 |
|
|
Jul 20 08:20:35 PM PDT 24 |
Jul 20 08:27:29 PM PDT 24 |
3117397640 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.965161067 |
|
|
Jul 20 07:58:16 PM PDT 24 |
Jul 20 08:14:03 PM PDT 24 |
4306885912 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1773578134 |
|
|
Jul 20 07:55:54 PM PDT 24 |
Jul 20 08:06:22 PM PDT 24 |
4714062652 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3193454141 |
|
|
Jul 20 08:09:18 PM PDT 24 |
Jul 20 09:03:18 PM PDT 24 |
19929824486 ps |
| T1202 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.836559491 |
|
|
Jul 20 08:19:19 PM PDT 24 |
Jul 20 09:11:14 PM PDT 24 |
15904530600 ps |
| T44 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1115640888 |
|
|
Jul 20 07:55:27 PM PDT 24 |
Jul 20 07:59:23 PM PDT 24 |
2684382536 ps |
| T36 |
/workspace/coverage/default/0.chip_sw_gpio.3985556177 |
|
|
Jul 20 07:51:07 PM PDT 24 |
Jul 20 07:59:35 PM PDT 24 |
4390169432 ps |
| T807 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171723156 |
|
|
Jul 20 08:23:24 PM PDT 24 |
Jul 20 08:29:54 PM PDT 24 |
3745004472 ps |
| T383 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3371867994 |
|
|
Jul 20 08:25:10 PM PDT 24 |
Jul 20 08:31:33 PM PDT 24 |
3251876468 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1282610223 |
|
|
Jul 20 08:05:47 PM PDT 24 |
Jul 20 08:17:25 PM PDT 24 |
4842026100 ps |
| T827 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219828690 |
|
|
Jul 20 08:24:26 PM PDT 24 |
Jul 20 08:30:12 PM PDT 24 |
4377388408 ps |
| T1204 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3892099076 |
|
|
Jul 20 07:58:13 PM PDT 24 |
Jul 20 09:06:30 PM PDT 24 |
15076003008 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1326799853 |
|
|
Jul 20 08:06:13 PM PDT 24 |
Jul 20 08:16:26 PM PDT 24 |
6244298904 ps |
| T1206 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.839275321 |
|
|
Jul 20 08:18:20 PM PDT 24 |
Jul 20 08:27:30 PM PDT 24 |
5482146344 ps |
| T748 |
/workspace/coverage/default/1.rom_raw_unlock.3375827792 |
|
|
Jul 20 08:06:35 PM PDT 24 |
Jul 20 08:10:57 PM PDT 24 |
6440277227 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2625767481 |
|
|
Jul 20 08:04:13 PM PDT 24 |
Jul 20 08:25:21 PM PDT 24 |
5833369850 ps |
| T1208 |
/workspace/coverage/default/1.rom_e2e_static_critical.2769807935 |
|
|
Jul 20 08:08:43 PM PDT 24 |
Jul 20 09:11:13 PM PDT 24 |
16419784820 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1672657818 |
|
|
Jul 20 07:53:31 PM PDT 24 |
Jul 20 08:04:28 PM PDT 24 |
3928647058 ps |
| T1210 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2575134642 |
|
|
Jul 20 08:15:49 PM PDT 24 |
Jul 20 08:25:55 PM PDT 24 |
5164443760 ps |
| T221 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1845035193 |
|
|
Jul 20 07:59:08 PM PDT 24 |
Jul 20 08:10:15 PM PDT 24 |
5126484083 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1526006517 |
|
|
Jul 20 07:57:46 PM PDT 24 |
Jul 20 08:08:57 PM PDT 24 |
5889773808 ps |
| T853 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1277025411 |
|
|
Jul 20 08:26:38 PM PDT 24 |
Jul 20 08:34:23 PM PDT 24 |
5079936184 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2044395676 |
|
|
Jul 20 08:14:31 PM PDT 24 |
Jul 20 08:22:52 PM PDT 24 |
5235079320 ps |
| T408 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2282602986 |
|
|
Jul 20 08:02:55 PM PDT 24 |
Jul 20 08:06:58 PM PDT 24 |
3083569350 ps |
| T1212 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2345389419 |
|
|
Jul 20 07:58:59 PM PDT 24 |
Jul 20 08:08:17 PM PDT 24 |
5121232618 ps |
| T1213 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.80412122 |
|
|
Jul 20 08:12:11 PM PDT 24 |
Jul 20 08:18:30 PM PDT 24 |
3077593800 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.297278128 |
|
|
Jul 20 07:53:08 PM PDT 24 |
Jul 20 08:00:26 PM PDT 24 |
10944611326 ps |
| T1215 |
/workspace/coverage/default/1.rom_e2e_self_hash.512047747 |
|
|
Jul 20 08:13:44 PM PDT 24 |
Jul 20 09:43:54 PM PDT 24 |
26553656198 ps |
| T258 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2523709184 |
|
|
Jul 20 08:24:51 PM PDT 24 |
Jul 20 08:32:53 PM PDT 24 |
4764506946 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3115371078 |
|
|
Jul 20 07:49:25 PM PDT 24 |
Jul 20 07:59:35 PM PDT 24 |
4205249940 ps |
| T415 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.510456321 |
|
|
Jul 20 08:05:44 PM PDT 24 |
Jul 20 08:13:11 PM PDT 24 |
5201581512 ps |
| T1217 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4090150458 |
|
|
Jul 20 08:08:42 PM PDT 24 |
Jul 20 08:19:06 PM PDT 24 |
3914881472 ps |
| T1218 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1279984460 |
|
|
Jul 20 07:55:40 PM PDT 24 |
Jul 20 08:01:55 PM PDT 24 |
6060537400 ps |
| T770 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3043701126 |
|
|
Jul 20 08:22:58 PM PDT 24 |
Jul 20 08:33:18 PM PDT 24 |
4401325970 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3918547204 |
|
|
Jul 20 08:10:37 PM PDT 24 |
Jul 20 08:45:19 PM PDT 24 |
11483091292 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2028673921 |
|
|
Jul 20 08:06:50 PM PDT 24 |
Jul 20 08:45:54 PM PDT 24 |
10898631156 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.967482523 |
|
|
Jul 20 08:02:33 PM PDT 24 |
Jul 20 08:32:33 PM PDT 24 |
7656832760 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1990433754 |
|
|
Jul 20 08:08:56 PM PDT 24 |
Jul 20 08:15:17 PM PDT 24 |
3437051658 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2666600594 |
|
|
Jul 20 08:15:35 PM PDT 24 |
Jul 20 08:18:32 PM PDT 24 |
1933848476 ps |
| T1224 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.908836271 |
|
|
Jul 20 07:52:02 PM PDT 24 |
Jul 20 07:56:35 PM PDT 24 |
3500289464 ps |
| T420 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3674041192 |
|
|
Jul 20 08:12:36 PM PDT 24 |
Jul 20 08:30:10 PM PDT 24 |
22557643976 ps |
| T335 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.227114180 |
|
|
Jul 20 08:07:56 PM PDT 24 |
Jul 20 08:43:14 PM PDT 24 |
13376836780 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1845520619 |
|
|
Jul 20 07:56:26 PM PDT 24 |
Jul 20 08:12:04 PM PDT 24 |
7695177289 ps |
| T816 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.130003813 |
|
|
Jul 20 08:22:39 PM PDT 24 |
Jul 20 08:33:55 PM PDT 24 |
6343601752 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.4134193277 |
|
|
Jul 20 08:01:02 PM PDT 24 |
Jul 20 08:32:45 PM PDT 24 |
6241804624 ps |
| T1226 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.794135393 |
|
|
Jul 20 08:15:54 PM PDT 24 |
Jul 20 08:30:36 PM PDT 24 |
6927631260 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3252610595 |
|
|
Jul 20 08:13:42 PM PDT 24 |
Jul 20 08:33:29 PM PDT 24 |
14020176940 ps |
| T1228 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.949962063 |
|
|
Jul 20 08:24:52 PM PDT 24 |
Jul 20 08:35:57 PM PDT 24 |
4075707400 ps |