| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.25 | 95.48 | 94.26 | 95.49 | 95.20 | 97.53 | 99.52 |
| T2762 | /workspace/coverage/cover_reg_top/51.xbar_error_random.4241751388 | Jul 20 07:33:32 PM PDT 24 | Jul 20 07:33:58 PM PDT 24 | 558230288 ps | ||
| T2763 | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1598103626 | Jul 20 07:37:36 PM PDT 24 | Jul 20 07:39:07 PM PDT 24 | 5631447592 ps | ||
| T2764 | /workspace/coverage/cover_reg_top/73.xbar_stress_all.734114585 | Jul 20 07:37:10 PM PDT 24 | Jul 20 07:37:23 PM PDT 24 | 278357614 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1066098381 | Jul 20 07:32:04 PM PDT 24 | Jul 20 07:36:53 PM PDT 24 | 24327502124 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.4171841499 | Jul 20 07:28:21 PM PDT 24 | Jul 20 07:33:29 PM PDT 24 | 8632955101 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.847534824 | Jul 20 07:27:22 PM PDT 24 | Jul 20 07:28:54 PM PDT 24 | 8701611677 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2616933423 | Jul 20 07:22:20 PM PDT 24 | Jul 20 07:52:20 PM PDT 24 | 14300511336 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/96.xbar_random.1564837624 | Jul 20 07:40:49 PM PDT 24 | Jul 20 07:42:33 PM PDT 24 | 2267334535 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1487959430 | Jul 20 07:24:13 PM PDT 24 | Jul 20 07:28:59 PM PDT 24 | 784096639 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4247907918 | Jul 20 07:28:36 PM PDT 24 | Jul 20 07:32:54 PM PDT 24 | 562824248 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/21.xbar_same_source.3829690056 | Jul 20 07:27:01 PM PDT 24 | Jul 20 07:28:33 PM PDT 24 | 2709427832 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2748438509 | Jul 20 07:41:06 PM PDT 24 | Jul 20 07:41:38 PM PDT 24 | 47607742 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.539747612 | Jul 20 07:30:25 PM PDT 24 | Jul 20 07:34:37 PM PDT 24 | 22553829864 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/17.xbar_smoke.2399273366 | Jul 20 07:25:41 PM PDT 24 | Jul 20 07:25:53 PM PDT 24 | 216176627 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2151107083 | Jul 20 07:40:12 PM PDT 24 | Jul 20 07:40:20 PM PDT 24 | 47161447 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2316954531 | Jul 20 07:38:36 PM PDT 24 | Jul 20 07:40:40 PM PDT 24 | 3190641128 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3287441129 | Jul 20 07:24:25 PM PDT 24 | Jul 20 07:24:58 PM PDT 24 | 386881887 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/19.xbar_same_source.2350471192 | Jul 20 07:26:20 PM PDT 24 | Jul 20 07:26:29 PM PDT 24 | 144697970 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1382228468 | Jul 20 07:41:24 PM PDT 24 | Jul 20 07:42:25 PM PDT 24 | 417575108 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1379924173 | Jul 20 07:27:41 PM PDT 24 | Jul 20 07:30:28 PM PDT 24 | 2354626919 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1566082771 | Jul 20 07:33:24 PM PDT 24 | Jul 20 07:50:06 PM PDT 24 | 56149179321 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2763398402 | Jul 20 07:24:35 PM PDT 24 | Jul 20 07:32:44 PM PDT 24 | 7295755132 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/3.xbar_same_source.713902586 | Jul 20 07:22:31 PM PDT 24 | Jul 20 07:22:55 PM PDT 24 | 707104943 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1878738632 | Jul 20 07:26:51 PM PDT 24 | Jul 20 07:26:57 PM PDT 24 | 40931432 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2261495293 | Jul 20 07:36:47 PM PDT 24 | Jul 20 07:38:00 PM PDT 24 | 6737835375 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1399427686 | Jul 20 07:39:11 PM PDT 24 | Jul 20 08:19:55 PM PDT 24 | 129693693388 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.112136526 | Jul 20 07:40:13 PM PDT 24 | Jul 20 07:40:33 PM PDT 24 | 193108324 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.521306070 | Jul 20 07:29:50 PM PDT 24 | Jul 20 07:31:11 PM PDT 24 | 1921653018 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1500236948 | Jul 20 07:41:14 PM PDT 24 | Jul 20 08:02:29 PM PDT 24 | 71702920992 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/35.xbar_smoke.2211584968 | Jul 20 07:30:28 PM PDT 24 | Jul 20 07:30:34 PM PDT 24 | 40005086 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/86.xbar_smoke.3736262313 | Jul 20 07:39:11 PM PDT 24 | Jul 20 07:39:18 PM PDT 24 | 41205401 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3032590553 | Jul 20 07:38:35 PM PDT 24 | Jul 20 07:39:06 PM PDT 24 | 346443408 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.4084775872 | Jul 20 07:35:00 PM PDT 24 | Jul 20 07:35:37 PM PDT 24 | 907972157 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4033530598 | Jul 20 07:41:42 PM PDT 24 | Jul 20 07:45:10 PM PDT 24 | 561195556 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/79.xbar_random.3339911088 | Jul 20 07:38:12 PM PDT 24 | Jul 20 07:39:19 PM PDT 24 | 1950526376 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2207633826 | Jul 20 07:29:56 PM PDT 24 | Jul 20 07:30:42 PM PDT 24 | 481700144 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1849008836 | Jul 20 07:22:23 PM PDT 24 | Jul 20 07:24:36 PM PDT 24 | 11964435806 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2054397396 | Jul 20 07:22:39 PM PDT 24 | Jul 20 07:23:06 PM PDT 24 | 269070068 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1504320310 | Jul 20 07:32:41 PM PDT 24 | Jul 20 07:33:19 PM PDT 24 | 109468929 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2929318836 | Jul 20 07:25:26 PM PDT 24 | Jul 20 07:26:11 PM PDT 24 | 932635184 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1188683578 | Jul 20 07:29:42 PM PDT 24 | Jul 20 07:31:13 PM PDT 24 | 8269996744 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2774046009 | Jul 20 07:26:55 PM PDT 24 | Jul 20 07:32:14 PM PDT 24 | 2072972070 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.303866549 | Jul 20 07:36:40 PM PDT 24 | Jul 20 07:37:42 PM PDT 24 | 5110411889 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/77.xbar_error_random.994395877 | Jul 20 07:37:48 PM PDT 24 | Jul 20 07:39:07 PM PDT 24 | 2338494779 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3365005252 | Jul 20 07:25:15 PM PDT 24 | Jul 20 07:27:05 PM PDT 24 | 9158120785 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1982635449 | Jul 20 07:36:31 PM PDT 24 | Jul 20 07:37:54 PM PDT 24 | 1836706515 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2306632830 | Jul 20 07:35:08 PM PDT 24 | Jul 20 07:35:15 PM PDT 24 | 35731433 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2469204372 | Jul 20 07:35:48 PM PDT 24 | Jul 20 07:47:37 PM PDT 24 | 41784207682 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2874086014 | Jul 20 07:23:48 PM PDT 24 | Jul 20 07:30:13 PM PDT 24 | 7012382372 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2860076787 | Jul 20 07:31:38 PM PDT 24 | Jul 20 07:32:32 PM PDT 24 | 1247083457 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2774941441 | Jul 20 07:34:14 PM PDT 24 | Jul 20 07:34:57 PM PDT 24 | 990491321 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3341431299 | Jul 20 07:22:33 PM PDT 24 | Jul 20 07:29:47 PM PDT 24 | 5423047268 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1335791661 | Jul 20 07:31:54 PM PDT 24 | Jul 20 07:34:38 PM PDT 24 | 1924668120 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2530808352 | Jul 20 07:40:11 PM PDT 24 | Jul 20 07:44:14 PM PDT 24 | 22872610428 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.4039622571 | Jul 20 07:29:32 PM PDT 24 | Jul 20 07:30:00 PM PDT 24 | 610587220 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.281867696 | Jul 20 07:34:16 PM PDT 24 | Jul 20 07:35:55 PM PDT 24 | 8708542514 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/41.xbar_smoke.1676830415 | Jul 20 07:31:32 PM PDT 24 | Jul 20 07:31:39 PM PDT 24 | 150307402 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2029378493 | Jul 20 07:25:09 PM PDT 24 | Jul 20 07:36:42 PM PDT 24 | 5711794086 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2420201688 | Jul 20 07:31:15 PM PDT 24 | Jul 20 07:40:34 PM PDT 24 | 9269460647 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1299425980 | Jul 20 07:38:47 PM PDT 24 | Jul 20 07:39:34 PM PDT 24 | 575698103 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.2127187637 | Jul 20 07:36:29 PM PDT 24 | Jul 20 07:38:10 PM PDT 24 | 1489886702 ps | ||
| T409 | /workspace/coverage/cover_reg_top/13.chip_csr_rw.423470569 | Jul 20 07:24:59 PM PDT 24 | Jul 20 07:35:33 PM PDT 24 | 5302435302 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1876549443 | Jul 20 07:38:13 PM PDT 24 | Jul 20 07:42:03 PM PDT 24 | 3355680595 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/38.xbar_error_random.2764383781 | Jul 20 07:30:59 PM PDT 24 | Jul 20 07:32:21 PM PDT 24 | 2236479929 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2325924199 | Jul 20 07:29:09 PM PDT 24 | Jul 20 07:29:30 PM PDT 24 | 167907149 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.767680459 | Jul 20 07:39:13 PM PDT 24 | Jul 20 07:41:06 PM PDT 24 | 428414450 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1083197017 | Jul 20 07:30:17 PM PDT 24 | Jul 20 07:36:35 PM PDT 24 | 9970288007 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1057738007 | Jul 20 07:37:35 PM PDT 24 | Jul 20 08:01:58 PM PDT 24 | 74541078441 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.4083297733 | Jul 20 07:39:39 PM PDT 24 | Jul 20 07:41:19 PM PDT 24 | 8606787829 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.875387017 | Jul 20 07:25:03 PM PDT 24 | Jul 20 07:28:18 PM PDT 24 | 12043900007 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.355107773 | Jul 20 07:22:21 PM PDT 24 | Jul 20 07:47:57 PM PDT 24 | 10744277338 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2644283008 | Jul 20 07:35:38 PM PDT 24 | Jul 20 07:38:01 PM PDT 24 | 3356962470 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2172343710 | Jul 20 07:23:32 PM PDT 24 | Jul 20 07:24:57 PM PDT 24 | 1592056279 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.4275218870 | Jul 20 07:22:23 PM PDT 24 | Jul 20 07:24:07 PM PDT 24 | 9179617722 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/6.xbar_smoke.1046142935 | Jul 20 07:22:38 PM PDT 24 | Jul 20 07:22:45 PM PDT 24 | 41227223 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3995004443 | Jul 20 07:24:22 PM PDT 24 | Jul 20 07:35:09 PM PDT 24 | 57382304638 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/66.xbar_smoke.1659149430 | Jul 20 07:35:55 PM PDT 24 | Jul 20 07:36:02 PM PDT 24 | 38630125 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1019183078 | Jul 20 07:26:13 PM PDT 24 | Jul 20 07:33:17 PM PDT 24 | 7005445350 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.152701661 | Jul 20 07:34:13 PM PDT 24 | Jul 20 07:38:11 PM PDT 24 | 737697422 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2505409818 | Jul 20 07:38:11 PM PDT 24 | Jul 20 07:52:51 PM PDT 24 | 46826625958 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/70.xbar_same_source.3758993132 | Jul 20 07:36:42 PM PDT 24 | Jul 20 07:37:07 PM PDT 24 | 296605323 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3373706698 | Jul 20 07:36:44 PM PDT 24 | Jul 20 07:37:18 PM PDT 24 | 311947762 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.838718300 | Jul 20 07:22:59 PM PDT 24 | Jul 20 07:23:27 PM PDT 24 | 533772707 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1198819719 | Jul 20 07:36:05 PM PDT 24 | Jul 20 07:36:12 PM PDT 24 | 45141538 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1498594497 | Jul 20 07:41:08 PM PDT 24 | Jul 20 07:43:16 PM PDT 24 | 9781132932 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/17.xbar_random.2571483699 | Jul 20 07:25:41 PM PDT 24 | Jul 20 07:25:59 PM PDT 24 | 160111092 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3340737279 | Jul 20 07:31:38 PM PDT 24 | Jul 20 07:33:34 PM PDT 24 | 484471939 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.767982669 | Jul 20 07:30:53 PM PDT 24 | Jul 20 07:34:30 PM PDT 24 | 3013396674 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.733337760 | Jul 20 07:30:19 PM PDT 24 | Jul 20 08:11:41 PM PDT 24 | 132414383553 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/35.xbar_error_random.981359511 | Jul 20 07:30:38 PM PDT 24 | Jul 20 07:31:12 PM PDT 24 | 1060886468 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1642619314 | Jul 20 07:33:55 PM PDT 24 | Jul 20 07:34:58 PM PDT 24 | 1666054634 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/52.xbar_random.1221457152 | Jul 20 07:33:39 PM PDT 24 | Jul 20 07:34:54 PM PDT 24 | 2384283589 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2173863023 | Jul 20 07:22:34 PM PDT 24 | Jul 20 07:23:44 PM PDT 24 | 6311776855 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/53.xbar_stress_all.921606862 | Jul 20 07:33:57 PM PDT 24 | Jul 20 07:37:43 PM PDT 24 | 6263773934 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/10.xbar_random.423685474 | Jul 20 07:23:49 PM PDT 24 | Jul 20 07:24:19 PM PDT 24 | 283376023 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2211227678 | Jul 20 07:39:44 PM PDT 24 | Jul 20 07:45:00 PM PDT 24 | 7858476960 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/72.xbar_error_random.3619092835 | Jul 20 07:36:56 PM PDT 24 | Jul 20 07:37:04 PM PDT 24 | 145333688 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3178932703 | Jul 20 07:23:14 PM PDT 24 | Jul 20 07:54:37 PM PDT 24 | 15382488723 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/24.xbar_random.1209580423 | Jul 20 07:27:33 PM PDT 24 | Jul 20 07:28:14 PM PDT 24 | 1145882477 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3839685596 | Jul 20 07:22:34 PM PDT 24 | Jul 20 07:28:15 PM PDT 24 | 8924226104 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.620999142 | Jul 20 07:29:27 PM PDT 24 | Jul 20 07:30:07 PM PDT 24 | 514305847 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4169217346 | Jul 20 07:30:55 PM PDT 24 | Jul 20 07:33:36 PM PDT 24 | 14301777808 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2965192626 | Jul 20 07:28:06 PM PDT 24 | Jul 20 07:32:22 PM PDT 24 | 3019751857 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2494769694 | Jul 20 07:38:46 PM PDT 24 | Jul 20 07:38:53 PM PDT 24 | 44810717 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/91.xbar_smoke.1895878040 | Jul 20 07:39:59 PM PDT 24 | Jul 20 07:40:09 PM PDT 24 | 208813637 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.4182559363 | Jul 20 07:31:29 PM PDT 24 | Jul 20 07:33:40 PM PDT 24 | 543462141 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/33.xbar_random.2357698511 | Jul 20 07:29:56 PM PDT 24 | Jul 20 07:30:58 PM PDT 24 | 1902079901 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.598625800 | Jul 20 07:35:25 PM PDT 24 | Jul 20 07:35:39 PM PDT 24 | 113576758 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/47.xbar_random.4136670443 | Jul 20 07:32:48 PM PDT 24 | Jul 20 07:33:34 PM PDT 24 | 501920546 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.133823461 | Jul 20 07:32:45 PM PDT 24 | Jul 20 07:53:12 PM PDT 24 | 107664993934 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2406693287 | Jul 20 07:32:55 PM PDT 24 | Jul 20 07:33:04 PM PDT 24 | 39070873 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2185517304 | Jul 20 07:22:34 PM PDT 24 | Jul 20 07:23:56 PM PDT 24 | 4974702366 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/69.xbar_stress_all.3128663989 | Jul 20 07:36:33 PM PDT 24 | Jul 20 07:44:22 PM PDT 24 | 5712520411 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2182532257 | Jul 20 07:22:55 PM PDT 24 | Jul 20 07:23:07 PM PDT 24 | 91489171 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2202839633 | Jul 20 07:23:55 PM PDT 24 | Jul 20 07:25:26 PM PDT 24 | 5172269771 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/75.xbar_error_random.2715379629 | Jul 20 07:37:33 PM PDT 24 | Jul 20 07:38:09 PM PDT 24 | 1063036303 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/9.xbar_smoke.2547607086 | Jul 20 07:23:16 PM PDT 24 | Jul 20 07:23:26 PM PDT 24 | 166651297 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/84.xbar_same_source.594755938 | Jul 20 07:39:02 PM PDT 24 | Jul 20 07:39:59 PM PDT 24 | 2114000331 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/53.xbar_same_source.3876147273 | Jul 20 07:33:48 PM PDT 24 | Jul 20 07:34:39 PM PDT 24 | 1417503180 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.4273060593 | Jul 20 07:32:09 PM PDT 24 | Jul 20 07:32:17 PM PDT 24 | 54258382 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/44.xbar_stress_all.510716000 | Jul 20 07:32:12 PM PDT 24 | Jul 20 07:36:28 PM PDT 24 | 3203945737 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1203374755 | Jul 20 07:27:39 PM PDT 24 | Jul 20 07:36:10 PM PDT 24 | 7779636274 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/44.xbar_same_source.2843812722 | Jul 20 07:32:11 PM PDT 24 | Jul 20 07:33:00 PM PDT 24 | 1644095730 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2568586194 | Jul 20 07:22:24 PM PDT 24 | Jul 20 07:34:41 PM PDT 24 | 13763584923 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3476875231 | Jul 20 07:41:25 PM PDT 24 | Jul 20 07:54:14 PM PDT 24 | 45009531420 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3755999659 | Jul 20 07:32:22 PM PDT 24 | Jul 20 07:33:19 PM PDT 24 | 1162768856 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.973404087 | Jul 20 07:36:50 PM PDT 24 | Jul 20 07:37:31 PM PDT 24 | 1118467665 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3987949778 | Jul 20 07:22:36 PM PDT 24 | Jul 20 07:22:55 PM PDT 24 | 152957121 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2837076269 | Jul 20 07:22:24 PM PDT 24 | Jul 20 07:29:07 PM PDT 24 | 8179952729 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3254436640 | Jul 20 07:36:31 PM PDT 24 | Jul 20 07:38:11 PM PDT 24 | 5727723595 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1054555801 | Jul 20 07:35:36 PM PDT 24 | Jul 20 07:36:15 PM PDT 24 | 406996616 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/12.xbar_smoke.3497414616 | Jul 20 07:24:24 PM PDT 24 | Jul 20 07:24:35 PM PDT 24 | 228709584 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3179522841 | Jul 20 07:22:32 PM PDT 24 | Jul 20 07:24:18 PM PDT 24 | 6064955365 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1647569730 | Jul 20 07:39:11 PM PDT 24 | Jul 20 07:39:44 PM PDT 24 | 296575861 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/26.xbar_error_random.1518968418 | Jul 20 07:28:11 PM PDT 24 | Jul 20 07:29:15 PM PDT 24 | 1784299572 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.314976634 | Jul 20 07:28:38 PM PDT 24 | Jul 20 07:29:01 PM PDT 24 | 517212804 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2808480741 | Jul 20 07:24:29 PM PDT 24 | Jul 20 07:24:39 PM PDT 24 | 143887630 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2186024820 | Jul 20 07:38:44 PM PDT 24 | Jul 20 07:39:54 PM PDT 24 | 206549691 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/1.xbar_same_source.32082394 | Jul 20 07:22:21 PM PDT 24 | Jul 20 07:23:46 PM PDT 24 | 2679714462 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1784642279 | Jul 20 07:34:14 PM PDT 24 | Jul 20 07:47:25 PM PDT 24 | 46050102413 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2713724409 | Jul 20 07:33:17 PM PDT 24 | Jul 20 07:33:45 PM PDT 24 | 544660084 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2537741270 | Jul 20 07:37:00 PM PDT 24 | Jul 20 07:38:21 PM PDT 24 | 1047649395 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1585585538 | Jul 20 07:36:33 PM PDT 24 | Jul 20 07:38:31 PM PDT 24 | 1177171528 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.800476989 | Jul 20 07:36:41 PM PDT 24 | Jul 20 07:37:02 PM PDT 24 | 205226361 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.74478385 | Jul 20 07:32:37 PM PDT 24 | Jul 20 07:51:39 PM PDT 24 | 89837845824 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.233103792 | Jul 20 07:25:45 PM PDT 24 | Jul 20 07:27:38 PM PDT 24 | 10219275129 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3285184269 | Jul 20 07:34:49 PM PDT 24 | Jul 20 07:35:33 PM PDT 24 | 962569824 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3635756412 | Jul 20 07:26:59 PM PDT 24 | Jul 20 07:27:53 PM PDT 24 | 1383927947 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2185769535 | Jul 20 07:36:13 PM PDT 24 | Jul 20 07:37:22 PM PDT 24 | 3889093889 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1055065600 | Jul 20 07:38:12 PM PDT 24 | Jul 20 07:38:17 PM PDT 24 | 7151272 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3012674623 | Jul 20 07:38:15 PM PDT 24 | Jul 20 07:39:48 PM PDT 24 | 8333221886 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2545018711 | Jul 20 07:31:31 PM PDT 24 | Jul 20 07:41:46 PM PDT 24 | 35658357421 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1344342029 | Jul 20 07:30:19 PM PDT 24 | Jul 20 07:31:27 PM PDT 24 | 1043318020 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.280278380 | Jul 20 07:25:01 PM PDT 24 | Jul 20 07:26:04 PM PDT 24 | 5731229300 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1350127544 | Jul 20 07:33:33 PM PDT 24 | Jul 20 07:35:10 PM PDT 24 | 5286898823 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.838349857 | Jul 20 07:39:25 PM PDT 24 | Jul 20 07:41:08 PM PDT 24 | 5879092019 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1370579532 | Jul 20 07:30:35 PM PDT 24 | Jul 20 07:33:38 PM PDT 24 | 2360076056 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.904408003 | Jul 20 07:31:40 PM PDT 24 | Jul 20 07:33:20 PM PDT 24 | 5371742256 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/4.xbar_random.802696879 | Jul 20 07:22:35 PM PDT 24 | Jul 20 07:22:43 PM PDT 24 | 26891868 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2075173942 | Jul 20 07:32:21 PM PDT 24 | Jul 20 07:37:49 PM PDT 24 | 31270925612 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3098451975 | Jul 20 07:25:57 PM PDT 24 | Jul 20 07:28:33 PM PDT 24 | 3626971327 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.1901713110 | Jul 20 07:37:12 PM PDT 24 | Jul 20 07:38:20 PM PDT 24 | 5995432376 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3291609705 | Jul 20 07:22:43 PM PDT 24 | Jul 20 08:05:13 PM PDT 24 | 144667362701 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2167192096 | Jul 20 07:25:30 PM PDT 24 | Jul 20 07:26:36 PM PDT 24 | 3716218038 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.826553894 | Jul 20 07:36:28 PM PDT 24 | Jul 20 07:36:34 PM PDT 24 | 25489408 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1429080702 | Jul 20 07:39:20 PM PDT 24 | Jul 20 08:13:39 PM PDT 24 | 110446919395 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.998987491 | Jul 20 07:30:34 PM PDT 24 | Jul 20 07:43:10 PM PDT 24 | 66877174515 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3164297876 | Jul 20 07:22:23 PM PDT 24 | Jul 20 07:38:20 PM PDT 24 | 10902849294 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4195724210 | Jul 20 07:38:07 PM PDT 24 | Jul 20 07:39:41 PM PDT 24 | 5692224551 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1245699810 | Jul 20 07:30:42 PM PDT 24 | Jul 20 07:31:56 PM PDT 24 | 6832574289 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.778060650 | Jul 20 07:38:26 PM PDT 24 | Jul 20 07:53:00 PM PDT 24 | 75427563389 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3634620191 | Jul 20 07:32:51 PM PDT 24 | Jul 20 07:33:02 PM PDT 24 | 153679474 ps | ||
| T38 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.207814563 | Jul 20 07:41:42 PM PDT 24 | Jul 20 07:45:37 PM PDT 24 | 4449117443 ps | ||
| T39 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.103035996 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:45:52 PM PDT 24 | 4034064696 ps | ||
| T40 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1140481835 | Jul 20 07:41:37 PM PDT 24 | Jul 20 07:46:03 PM PDT 24 | 4997750715 ps | ||
| T201 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4039200814 | Jul 20 07:41:32 PM PDT 24 | Jul 20 07:45:58 PM PDT 24 | 5284559002 ps | ||
| T202 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1452800166 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:44:45 PM PDT 24 | 3762038000 ps | ||
| T203 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2860518876 | Jul 20 07:41:37 PM PDT 24 | Jul 20 07:45:40 PM PDT 24 | 5130929542 ps | ||
| T204 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4027032859 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:44:48 PM PDT 24 | 4667073856 ps | ||
| T205 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.268207362 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:47:24 PM PDT 24 | 5815907938 ps | ||
| T206 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.264792659 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:46:58 PM PDT 24 | 5771284512 ps | ||
| T207 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.747808695 | Jul 20 07:41:31 PM PDT 24 | Jul 20 07:45:36 PM PDT 24 | 5121140141 ps |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2595161287 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 5181778044 ps |
| CPU time | 595.06 seconds |
| Started | Jul 20 08:21:47 PM PDT 24 |
| Finished | Jul 20 08:31:43 PM PDT 24 |
| Peak memory | 650040 kb |
| Host | smart-ca0034a7-4cf6-4876-b96a-719e680435a8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2595161287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2595161287 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4190348363 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 6323025246 ps |
| CPU time | 494.11 seconds |
| Started | Jul 20 07:24:06 PM PDT 24 |
| Finished | Jul 20 07:32:21 PM PDT 24 |
| Peak memory | 637628 kb |
| Host | smart-e1ce9258-ae53-4de1-8abb-0e51ea3d0708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190348363 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.4190348363 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.129135832 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 5879058154 ps |
| CPU time | 1439.96 seconds |
| Started | Jul 20 08:02:11 PM PDT 24 |
| Finished | Jul 20 08:26:13 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-aed8a86f-b146-4760-823a-99b56795f2bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129135832 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.129135832 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.550671107 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4117656139 ps |
| CPU time | 156.77 seconds |
| Started | Jul 20 07:37:27 PM PDT 24 |
| Finished | Jul 20 07:40:04 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c3ec57ad-58d9-43e5-8556-24c6a0228873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550671107 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.550671107 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.12699406 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 122522881988 ps |
| CPU time | 2207.42 seconds |
| Started | Jul 20 07:29:08 PM PDT 24 |
| Finished | Jul 20 08:05:57 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-84672725-affe-45f9-ac23-e0381d2078e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12699406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_de vice_slow_rsp.12699406 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.207814563 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4449117443 ps |
| CPU time | 220.15 seconds |
| Started | Jul 20 07:41:42 PM PDT 24 |
| Finished | Jul 20 07:45:37 PM PDT 24 |
| Peak memory | 640944 kb |
| Host | smart-8c7a62dd-c396-4090-a06d-fe0c231e68ad |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207814563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.207814563 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.3362936665 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 14529222165 ps |
| CPU time | 1501.15 seconds |
| Started | Jul 20 07:43:34 PM PDT 24 |
| Finished | Jul 20 08:08:36 PM PDT 24 |
| Peak memory | 608004 kb |
| Host | smart-3e1bbf32-ad01-43dc-b88f-3e937060787b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362936665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.3362936665 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1077240967 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 23969747456 ps |
| CPU time | 6389.47 seconds |
| Started | Jul 20 08:01:03 PM PDT 24 |
| Finished | Jul 20 09:47:34 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-819e5812-99e8-408d-a366-ae6ab1c84140 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1077240967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1077240967 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2220542716 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 108916363651 ps |
| CPU time | 2082.15 seconds |
| Started | Jul 20 07:29:32 PM PDT 24 |
| Finished | Jul 20 08:04:15 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-31e2540d-f18c-45fe-8718-315296bcea3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220542716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2220542716 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2439317437 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 6965301592 ps |
| CPU time | 1254.18 seconds |
| Started | Jul 20 08:02:15 PM PDT 24 |
| Finished | Jul 20 08:23:10 PM PDT 24 |
| Peak memory | 617960 kb |
| Host | smart-72924505-7f02-49ef-9f06-6b873838f3f3 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2439317437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.2439317437 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1729249884 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 119109405527 ps |
| CPU time | 2217.63 seconds |
| Started | Jul 20 07:30:29 PM PDT 24 |
| Finished | Jul 20 08:07:28 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-511cc623-7044-4eb4-b372-29e235e6b2b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729249884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.1729249884 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1999101419 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 18587629517 ps |
| CPU time | 691.17 seconds |
| Started | Jul 20 07:25:10 PM PDT 24 |
| Finished | Jul 20 07:36:42 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f407641b-9983-4423-b613-e4655ebea25e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999101419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1999101419 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.495268168 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 48702135766 ps |
| CPU time | 5087.67 seconds |
| Started | Jul 20 08:08:10 PM PDT 24 |
| Finished | Jul 20 09:32:58 PM PDT 24 |
| Peak memory | 620260 kb |
| Host | smart-f461d9a6-1b34-495f-bce2-30cac3678787 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495268168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_dev.495268168 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1549074997 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 91801781637 ps |
| CPU time | 1735.52 seconds |
| Started | Jul 20 07:29:24 PM PDT 24 |
| Finished | Jul 20 07:58:21 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-acdf7432-1a43-4791-9315-5ab1e8daaa67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549074997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.1549074997 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.407977462 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2875156621 ps |
| CPU time | 297.94 seconds |
| Started | Jul 20 07:59:05 PM PDT 24 |
| Finished | Jul 20 08:04:04 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-5eaea71e-d68f-4fd7-8602-40cc86dce5dd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079 77462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.407977462 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1987194543 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3025866840 ps |
| CPU time | 213.17 seconds |
| Started | Jul 20 07:53:06 PM PDT 24 |
| Finished | Jul 20 07:56:39 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-bcd00e77-f4a9-43c1-8c50-53f5d6c6d3a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1987194543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.1987194543 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.93724595 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 11036241100 ps |
| CPU time | 1158.15 seconds |
| Started | Jul 20 08:05:05 PM PDT 24 |
| Finished | Jul 20 08:24:24 PM PDT 24 |
| Peak memory | 608012 kb |
| Host | smart-a4ae49be-c7cf-4276-9a36-7c2fd608018d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93724595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_jtag_csr_rw.93724595 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.4129258152 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 123592313612 ps |
| CPU time | 2298.06 seconds |
| Started | Jul 20 07:38:03 PM PDT 24 |
| Finished | Jul 20 08:16:22 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-78095b8e-ced6-4794-ac4b-93ee3b28d210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129258152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.4129258152 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4070110845 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 78050669079 ps |
| CPU time | 13216.1 seconds |
| Started | Jul 20 08:00:54 PM PDT 24 |
| Finished | Jul 20 11:41:12 PM PDT 24 |
| Peak memory | 634076 kb |
| Host | smart-85c681b3-4e3f-4333-9b0d-a41710cee230 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4070110845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.4070110845 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229977943 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3466257954 ps |
| CPU time | 431.26 seconds |
| Started | Jul 20 08:17:41 PM PDT 24 |
| Finished | Jul 20 08:24:52 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-fe95238c-3f76-4ef5-8e2a-ecb93bc0567f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229977943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2229977943 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3999355436 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2877615768 ps |
| CPU time | 125.6 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:24:39 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-d3726bad-f9f9-4210-bb6d-44f3731307df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999355436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3999355436 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.986350269 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3698294736 ps |
| CPU time | 666.04 seconds |
| Started | Jul 20 08:02:15 PM PDT 24 |
| Finished | Jul 20 08:13:21 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-8e8c4238-674d-4dbb-a270-7dad9ec51bb4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986350269 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.986350269 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.3818547904 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3713500958 ps |
| CPU time | 461.85 seconds |
| Started | Jul 20 08:07:52 PM PDT 24 |
| Finished | Jul 20 08:15:35 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-9c20eb33-c095-41ba-a8e1-91faf407934f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818547904 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.3818547904 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3048308534 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 6556088584 ps |
| CPU time | 607.3 seconds |
| Started | Jul 20 08:09:00 PM PDT 24 |
| Finished | Jul 20 08:19:09 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-b44152dc-552c-45ef-be8f-82dbdca5fb51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048308534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.3048308534 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1800061348 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 27245281000 ps |
| CPU time | 2239.02 seconds |
| Started | Jul 20 07:53:26 PM PDT 24 |
| Finished | Jul 20 08:30:46 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-2c107d0a-121d-4590-a245-39332e8c0c66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1800061348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1800061348 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.747181361 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 31399602201 ps |
| CPU time | 4670.19 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 08:40:32 PM PDT 24 |
| Peak memory | 593448 kb |
| Host | smart-58ba5627-4a73-45f3-b9be-e82df9a1fdec |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747181361 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.chip_same_csr_outstanding.747181361 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3762392358 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 6180302012 ps |
| CPU time | 723.74 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:34:57 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-3ce9c421-961e-41b2-b2c9-a113bb8f6156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762392358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3762392358 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.530689283 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4771458226 ps |
| CPU time | 845.12 seconds |
| Started | Jul 20 07:51:52 PM PDT 24 |
| Finished | Jul 20 08:05:57 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-72e676fc-4bf7-414a-ab07-495c56f767a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530689283 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_20.530689283 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.817736165 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 64693484341 ps |
| CPU time | 742.9 seconds |
| Started | Jul 20 07:40:59 PM PDT 24 |
| Finished | Jul 20 07:53:46 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-bacbe903-d1b3-41d5-b16f-32040e7b7791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817736165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.817736165 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.1027844267 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5040001228 ps |
| CPU time | 485.06 seconds |
| Started | Jul 20 07:22:09 PM PDT 24 |
| Finished | Jul 20 07:30:15 PM PDT 24 |
| Peak memory | 598616 kb |
| Host | smart-93a3f1b1-27a3-4e74-af34-019201fe5f96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027844267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.1027844267 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.207265941 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 3720253401 ps |
| CPU time | 395.68 seconds |
| Started | Jul 20 07:51:20 PM PDT 24 |
| Finished | Jul 20 07:57:56 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-5903603f-6e73-47ef-be82-cfc7c40c8bb7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=207265941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.207265941 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1569489487 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 3545024825 ps |
| CPU time | 304.5 seconds |
| Started | Jul 20 07:24:13 PM PDT 24 |
| Finished | Jul 20 07:29:19 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-add1c156-e1b1-44b5-a172-bc9fa842730c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569489487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.1569489487 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1835772670 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 13120234602 ps |
| CPU time | 1302.44 seconds |
| Started | Jul 20 07:55:05 PM PDT 24 |
| Finished | Jul 20 08:16:48 PM PDT 24 |
| Peak memory | 604816 kb |
| Host | smart-c6f1770f-be95-4b3f-9619-8ba88ac81d60 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835772670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1835772670 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3958901292 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7443114752 ps |
| CPU time | 517.97 seconds |
| Started | Jul 20 08:18:24 PM PDT 24 |
| Finished | Jul 20 08:27:03 PM PDT 24 |
| Peak memory | 622468 kb |
| Host | smart-d3cce42d-a0f2-4e1e-a90f-59f3a023bf35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958901292 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3958901292 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.454060386 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5632274892 ps |
| CPU time | 544.22 seconds |
| Started | Jul 20 07:50:03 PM PDT 24 |
| Finished | Jul 20 07:59:08 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-50acece3-0da0-4f7d-ac60-ad324812bc63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45406038 6 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.454060386 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.273220633 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 12338106586 ps |
| CPU time | 2134.96 seconds |
| Started | Jul 20 07:57:01 PM PDT 24 |
| Finished | Jul 20 08:32:36 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-087935e2-652d-402c-bb8a-3fa9f5714d7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732 20633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.273220633 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1697569717 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 21711665220 ps |
| CPU time | 1498.32 seconds |
| Started | Jul 20 07:56:34 PM PDT 24 |
| Finished | Jul 20 08:21:33 PM PDT 24 |
| Peak memory | 614392 kb |
| Host | smart-a1b57867-6a91-4ce3-98d3-a1170706d982 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16975697 17 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.1697569717 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2716934150 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 712768090 ps |
| CPU time | 61.11 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:23:23 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ba3943b9-df5e-426e-84ed-dc5d5315322a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716934150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 2716934150 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.377565272 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4598178222 ps |
| CPU time | 586.12 seconds |
| Started | Jul 20 08:21:39 PM PDT 24 |
| Finished | Jul 20 08:31:26 PM PDT 24 |
| Peak memory | 619632 kb |
| Host | smart-d1e968c7-58de-4b65-b4df-ac4a6288e55c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 377565272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.377565272 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2730631347 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4414983156 ps |
| CPU time | 586.68 seconds |
| Started | Jul 20 08:00:23 PM PDT 24 |
| Finished | Jul 20 08:10:11 PM PDT 24 |
| Peak memory | 623756 kb |
| Host | smart-07c7ffd4-9bf2-4e94-ac6e-5d08c1c365a3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730631347 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.2730631347 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.2166056586 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 19994899016 ps |
| CPU time | 2545.64 seconds |
| Started | Jul 20 07:48:28 PM PDT 24 |
| Finished | Jul 20 08:30:55 PM PDT 24 |
| Peak memory | 614432 kb |
| Host | smart-71c3d6f2-c085-479a-b58d-b8cb81fa129c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166056586 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.2166056586 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.3529868296 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 3582602881 ps |
| CPU time | 210.45 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:26:01 PM PDT 24 |
| Peak memory | 603664 kb |
| Host | smart-70e8bedc-6acf-41ff-a2db-d70ac891449b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529868296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.3529868296 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3088253819 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 13592124803 ps |
| CPU time | 1870.16 seconds |
| Started | Jul 20 07:56:45 PM PDT 24 |
| Finished | Jul 20 08:27:57 PM PDT 24 |
| Peak memory | 624716 kb |
| Host | smart-052eceb6-5ac6-493f-8c63-cc36c3926f96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088253819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3088253819 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3249765418 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3400011106 ps |
| CPU time | 348.74 seconds |
| Started | Jul 20 08:06:06 PM PDT 24 |
| Finished | Jul 20 08:11:55 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-c65a60bf-e5c6-424b-95cc-1bd0c2de2290 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249 765418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.3249765418 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1324562086 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 4124936214 ps |
| CPU time | 644.97 seconds |
| Started | Jul 20 08:01:34 PM PDT 24 |
| Finished | Jul 20 08:12:20 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-951afec1-b1d7-4eb7-9655-daf515cf698d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324562086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1324562086 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.3387762688 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3056994956 ps |
| CPU time | 304.87 seconds |
| Started | Jul 20 07:50:23 PM PDT 24 |
| Finished | Jul 20 07:55:28 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-c2e80ebc-26e7-44c6-b796-9c608f82c9fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387762688 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3387762688 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.676592701 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 7834168498 ps |
| CPU time | 1535.23 seconds |
| Started | Jul 20 08:15:23 PM PDT 24 |
| Finished | Jul 20 08:40:59 PM PDT 24 |
| Peak memory | 624604 kb |
| Host | smart-c6288bcd-f97d-4545-a9ad-3b9209599c94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676592701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq.676592701 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.4015845236 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 6945293664 ps |
| CPU time | 2501.17 seconds |
| Started | Jul 20 08:09:41 PM PDT 24 |
| Finished | Jul 20 08:51:23 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-8dc48883-63fa-4009-b1b2-73447af2f019 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015845236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.4015845236 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.2561208912 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 5299728196 ps |
| CPU time | 486.79 seconds |
| Started | Jul 20 08:25:14 PM PDT 24 |
| Finished | Jul 20 08:33:21 PM PDT 24 |
| Peak memory | 650188 kb |
| Host | smart-1e912526-e895-4961-b888-56c0067ebe02 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2561208912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.2561208912 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.756473655 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 64754975598 ps |
| CPU time | 1225.25 seconds |
| Started | Jul 20 07:34:41 PM PDT 24 |
| Finished | Jul 20 07:55:09 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-4359100b-95f1-41c7-9f21-0ab4f432312d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756473655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_d evice_slow_rsp.756473655 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1488659031 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3916125031 ps |
| CPU time | 598.24 seconds |
| Started | Jul 20 07:49:06 PM PDT 24 |
| Finished | Jul 20 07:59:06 PM PDT 24 |
| Peak memory | 624860 kb |
| Host | smart-3b30f4e9-a0d0-44ac-ae02-11641610eb48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488659031 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1488659031 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3589123672 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8721675889 ps |
| CPU time | 748.52 seconds |
| Started | Jul 20 07:52:16 PM PDT 24 |
| Finished | Jul 20 08:04:45 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-e3ffd45d-06b5-4468-838f-3b03a0cbcb07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589123672 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3589123672 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1733221097 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3234563870 ps |
| CPU time | 197.62 seconds |
| Started | Jul 20 07:48:51 PM PDT 24 |
| Finished | Jul 20 07:52:09 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-f361663f-faa8-440d-b20b-9d9137f555c3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733 221097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1733221097 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2722889560 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5783522100 ps |
| CPU time | 474.52 seconds |
| Started | Jul 20 08:25:11 PM PDT 24 |
| Finished | Jul 20 08:33:06 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-96fbae65-ce42-40c4-8583-6b62902c894f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2722889560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2722889560 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.724979812 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4165174245 ps |
| CPU time | 428.41 seconds |
| Started | Jul 20 07:26:11 PM PDT 24 |
| Finished | Jul 20 07:33:21 PM PDT 24 |
| Peak memory | 599664 kb |
| Host | smart-ea806b94-a69a-47ac-8b70-0051553b6494 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724979812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.724979812 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2590871580 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 3446089422 ps |
| CPU time | 290.48 seconds |
| Started | Jul 20 07:48:26 PM PDT 24 |
| Finished | Jul 20 07:53:17 PM PDT 24 |
| Peak memory | 621548 kb |
| Host | smart-2cd98803-759a-4416-8b06-7c0af1ffff81 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590871580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2590871580 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2670820385 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 30479706130 ps |
| CPU time | 4454.24 seconds |
| Started | Jul 20 07:25:12 PM PDT 24 |
| Finished | Jul 20 08:39:28 PM PDT 24 |
| Peak memory | 593084 kb |
| Host | smart-29b824c9-eaa5-4533-aa11-5b7b82a0fccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670820385 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2670820385 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009195868 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 3767520000 ps |
| CPU time | 423.88 seconds |
| Started | Jul 20 08:22:00 PM PDT 24 |
| Finished | Jul 20 08:29:04 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-bc81b804-4f24-4eee-b146-3dde66e059e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009195868 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1009195868 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.985877376 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 134806563846 ps |
| CPU time | 2553.24 seconds |
| Started | Jul 20 07:40:06 PM PDT 24 |
| Finished | Jul 20 08:22:41 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-8c40977e-6e36-447c-bb22-6b37ac50ec8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985877376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d evice_slow_rsp.985877376 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3399248686 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4745985984 ps |
| CPU time | 538.98 seconds |
| Started | Jul 20 08:31:03 PM PDT 24 |
| Finished | Jul 20 08:40:02 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-2693b37a-f7aa-469f-99db-8770abbea060 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3399248686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3399248686 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.2716662120 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 5169557498 ps |
| CPU time | 659.53 seconds |
| Started | Jul 20 08:23:08 PM PDT 24 |
| Finished | Jul 20 08:34:48 PM PDT 24 |
| Peak memory | 650548 kb |
| Host | smart-a4622398-61a8-4cca-9393-f6dabc7199be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2716662120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2716662120 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3558905006 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5055173444 ps |
| CPU time | 332.27 seconds |
| Started | Jul 20 07:55:40 PM PDT 24 |
| Finished | Jul 20 08:01:13 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-c2af976e-b9a7-420d-9e5c-3d5825f6d2a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558905006 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3558905006 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.584565195 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 134180327739 ps |
| CPU time | 2251.24 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 08:00:17 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-76f74e1d-c0a8-4e9c-ac77-9f6aa4b7c5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584565195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_de vice_slow_rsp.584565195 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.766535331 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 42774982140 ps |
| CPU time | 5173.16 seconds |
| Started | Jul 20 07:56:27 PM PDT 24 |
| Finished | Jul 20 09:22:41 PM PDT 24 |
| Peak memory | 619716 kb |
| Host | smart-9c11e514-5160-47e0-a0a5-5aecb9c5dea9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=766535331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.766535331 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3331157500 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 6344277122 ps |
| CPU time | 898.91 seconds |
| Started | Jul 20 07:48:55 PM PDT 24 |
| Finished | Jul 20 08:03:55 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-f0c4b02d-04c8-4b2c-9c3e-5c133339cba9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3331157500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.3331157500 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.619245509 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 8093877830 ps |
| CPU time | 994.28 seconds |
| Started | Jul 20 08:16:08 PM PDT 24 |
| Finished | Jul 20 08:32:43 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-f17b6c27-fa9f-4974-b03a-b7cf64ff349a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61924550 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.619245509 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.2832432605 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 3752313344 ps |
| CPU time | 316.35 seconds |
| Started | Jul 20 08:17:24 PM PDT 24 |
| Finished | Jul 20 08:22:41 PM PDT 24 |
| Peak memory | 620964 kb |
| Host | smart-d5ef3496-4ce2-4a7d-b205-c4c45f865db9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832432605 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2832432605 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4205304938 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2679150574 ps |
| CPU time | 491.79 seconds |
| Started | Jul 20 07:30:20 PM PDT 24 |
| Finished | Jul 20 07:38:32 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-439c8db0-3f5f-497a-b233-7c8bd6fea22e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205304938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.4205304938 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.2929795601 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 5582069090 ps |
| CPU time | 915.24 seconds |
| Started | Jul 20 08:13:30 PM PDT 24 |
| Finished | Jul 20 08:28:46 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-de36a520-ebfc-4ab0-a0ed-2a854a8d9968 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929795601 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.2929795601 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1800025082 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4723930282 ps |
| CPU time | 571.25 seconds |
| Started | Jul 20 08:06:36 PM PDT 24 |
| Finished | Jul 20 08:16:08 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-87db9cbc-0719-4cc7-9c1f-f697c12cf250 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18 00025082 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.1800025082 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3310686319 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 6616055556 ps |
| CPU time | 397.5 seconds |
| Started | Jul 20 07:22:24 PM PDT 24 |
| Finished | Jul 20 07:29:04 PM PDT 24 |
| Peak memory | 659632 kb |
| Host | smart-fc1d7372-0994-447a-8b3e-563312b2dfc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310686319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.3310686319 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.545176663 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 4484484038 ps |
| CPU time | 571.43 seconds |
| Started | Jul 20 07:22:14 PM PDT 24 |
| Finished | Jul 20 07:31:46 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-48cd7184-109a-4e17-8a0f-0e9dbf0a2601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545176663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.545176663 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3900793420 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6163326648 ps |
| CPU time | 513.18 seconds |
| Started | Jul 20 07:50:58 PM PDT 24 |
| Finished | Jul 20 07:59:32 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-717ab869-f244-4c71-bb91-e27399643cea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900793420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.3900793420 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.635964847 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 4781926153 ps |
| CPU time | 601.61 seconds |
| Started | Jul 20 07:39:41 PM PDT 24 |
| Finished | Jul 20 07:49:43 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-1e7fd7e6-14b9-4cb1-8315-b3bec5570bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635964847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.635964847 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3341810460 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 4867048648 ps |
| CPU time | 390.42 seconds |
| Started | Jul 20 07:27:00 PM PDT 24 |
| Finished | Jul 20 07:33:31 PM PDT 24 |
| Peak memory | 599664 kb |
| Host | smart-1188f7ae-d047-4f9f-b45d-f99bbfcdbbd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341810460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3341810460 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1926176501 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 31306497624 ps |
| CPU time | 6740.18 seconds |
| Started | Jul 20 07:49:00 PM PDT 24 |
| Finished | Jul 20 09:41:22 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-4ee1f6a2-ef56-4077-b76f-c395b2e94092 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1926176501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1926176501 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.420060460 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 44015377234 ps |
| CPU time | 5333.09 seconds |
| Started | Jul 20 08:06:51 PM PDT 24 |
| Finished | Jul 20 09:35:45 PM PDT 24 |
| Peak memory | 620316 kb |
| Host | smart-695e1918-f46b-497c-81fb-d80cdc439a0e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=420060460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.420060460 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.1168410001 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5699768006 ps |
| CPU time | 1398 seconds |
| Started | Jul 20 07:52:39 PM PDT 24 |
| Finished | Jul 20 08:15:58 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-6bcf0405-d965-4076-adba-b4714200a322 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168410001 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.1168410001 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3358037538 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 20567599095 ps |
| CPU time | 1041.87 seconds |
| Started | Jul 20 07:37:43 PM PDT 24 |
| Finished | Jul 20 07:55:05 PM PDT 24 |
| Peak memory | 577740 kb |
| Host | smart-08189e4c-3d40-44f9-bcee-ed77daccad06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358037538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.3358037538 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3377120345 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3064892114 ps |
| CPU time | 329.71 seconds |
| Started | Jul 20 08:06:24 PM PDT 24 |
| Finished | Jul 20 08:11:54 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-4b2cdff9-7ff7-4db5-a17b-a3c80291d805 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377120345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3377120345 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3215534080 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3786423172 ps |
| CPU time | 586.74 seconds |
| Started | Jul 20 08:11:11 PM PDT 24 |
| Finished | Jul 20 08:20:58 PM PDT 24 |
| Peak memory | 612880 kb |
| Host | smart-d93e4c56-4b31-449c-84dc-6ef5f891e1c1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215534080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3215534080 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1486467994 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 69959229655 ps |
| CPU time | 1323.44 seconds |
| Started | Jul 20 07:37:41 PM PDT 24 |
| Finished | Jul 20 07:59:45 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c99d475f-aa6d-4ea5-b9a3-8796d102805b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486467994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.1486467994 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3942734819 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1783788567 ps |
| CPU time | 202.88 seconds |
| Started | Jul 20 07:33:55 PM PDT 24 |
| Finished | Jul 20 07:37:21 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-5a48b5ad-f912-4c31-8b66-2f7e26135c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942734819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.3942734819 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2792066706 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4594575176 ps |
| CPU time | 848.48 seconds |
| Started | Jul 20 08:00:51 PM PDT 24 |
| Finished | Jul 20 08:15:00 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-c77902d0-4ac1-4038-9916-262d482e951c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792066706 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2792066706 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2376473960 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6178181536 ps |
| CPU time | 600.4 seconds |
| Started | Jul 20 07:54:39 PM PDT 24 |
| Finished | Jul 20 08:04:41 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-436f1672-e5a3-4c48-b2c7-80ba001fc101 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764739 60 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2376473960 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3854638098 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 6611054430 ps |
| CPU time | 656.23 seconds |
| Started | Jul 20 07:29:03 PM PDT 24 |
| Finished | Jul 20 07:40:00 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-fbbcfdc0-4fdd-4248-aa7b-0dfbc6a58353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854638098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3854638098 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3555512624 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 5118815921 ps |
| CPU time | 362.83 seconds |
| Started | Jul 20 07:22:29 PM PDT 24 |
| Finished | Jul 20 07:28:32 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-32374f61-2f0c-48da-a400-4f42dc4ddbb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555512624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.3555512624 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1115640888 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 2684382536 ps |
| CPU time | 235.63 seconds |
| Started | Jul 20 07:55:27 PM PDT 24 |
| Finished | Jul 20 07:59:23 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-824489b4-c3b4-4da5-b1fa-bc3a1ae2a49e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115640888 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.1115640888 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2793045151 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 8652396673 ps |
| CPU time | 886.98 seconds |
| Started | Jul 20 07:23:09 PM PDT 24 |
| Finished | Jul 20 07:37:59 PM PDT 24 |
| Peak memory | 639596 kb |
| Host | smart-d0759167-5acf-42b5-a7b4-cfa28131cdfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793045151 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.2793045151 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2741379636 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 3104682770 ps |
| CPU time | 226.71 seconds |
| Started | Jul 20 07:58:42 PM PDT 24 |
| Finished | Jul 20 08:02:29 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-94abe8ea-e5ee-4434-ae85-5e7aa8d032bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741379636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2741379636 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3215043656 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1906686948 ps |
| CPU time | 84.75 seconds |
| Started | Jul 20 07:57:09 PM PDT 24 |
| Finished | Jul 20 07:58:34 PM PDT 24 |
| Peak memory | 621820 kb |
| Host | smart-91e48be0-db96-42c7-a1e3-53b5cb1e5ebf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215043656 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3215043656 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2801577784 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 16020285025 ps |
| CPU time | 1979.67 seconds |
| Started | Jul 20 07:54:06 PM PDT 24 |
| Finished | Jul 20 08:27:07 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-f4d6523b-6833-4277-89cf-a2cb6f6fd61d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801577784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2801577784 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.146856337 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 14812126130 ps |
| CPU time | 546.48 seconds |
| Started | Jul 20 07:22:22 PM PDT 24 |
| Finished | Jul 20 07:31:31 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-d1b35a91-f4f9-4756-ad7e-6bba6d71beb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146856337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.146856337 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1433198924 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 42587487160 ps |
| CPU time | 5494.33 seconds |
| Started | Jul 20 07:54:35 PM PDT 24 |
| Finished | Jul 20 09:26:10 PM PDT 24 |
| Peak memory | 624792 kb |
| Host | smart-7266a955-ea4b-4984-b1e8-d46014dce0f4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1433198924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.1433198924 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.103035996 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 4034064696 ps |
| CPU time | 241.62 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:45:52 PM PDT 24 |
| Peak memory | 656328 kb |
| Host | smart-acaa8009-6888-41f2-a381-b4cd50e4b366 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103035996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.103035996 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2655106023 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 5556793389 ps |
| CPU time | 274.84 seconds |
| Started | Jul 20 07:38:19 PM PDT 24 |
| Finished | Jul 20 07:42:55 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ab01d220-367a-4b78-82ad-c11cc53f6c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655106023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2655106023 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2071115881 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3795820718 ps |
| CPU time | 623.32 seconds |
| Started | Jul 20 08:06:44 PM PDT 24 |
| Finished | Jul 20 08:17:09 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-70765b4e-1f36-4beb-be5e-43f3165a0fe1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2071115881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2071115881 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3708002180 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 6275140252 ps |
| CPU time | 494.15 seconds |
| Started | Jul 20 08:09:27 PM PDT 24 |
| Finished | Jul 20 08:17:42 PM PDT 24 |
| Peak memory | 616844 kb |
| Host | smart-f836b55f-ccd7-4f4c-8833-34639bb25b2d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3708002180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3708002180 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.349890602 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 1475962626 ps |
| CPU time | 286.78 seconds |
| Started | Jul 20 07:25:39 PM PDT 24 |
| Finished | Jul 20 07:30:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-754baec7-96f9-48c8-b6b0-616b30ab3484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349890602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_ with_rand_reset.349890602 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2014024524 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 14826464146 ps |
| CPU time | 633.52 seconds |
| Started | Jul 20 07:28:38 PM PDT 24 |
| Finished | Jul 20 07:39:12 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9e1f1f31-a678-4a66-b826-3f24c1626742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014024524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2014024524 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1999999584 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 331187404 ps |
| CPU time | 132.47 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:39:39 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-6b316857-95e8-4b4c-ac1a-62ccb3d34945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999999584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.1999999584 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2292319705 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 51701558010 ps |
| CPU time | 5937.04 seconds |
| Started | Jul 20 07:48:43 PM PDT 24 |
| Finished | Jul 20 09:27:41 PM PDT 24 |
| Peak memory | 619212 kb |
| Host | smart-d67ec5ae-1ef1-41ca-afbc-de3b5c37e902 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292319705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.2292319705 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1269241879 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 9036661612 ps |
| CPU time | 559.02 seconds |
| Started | Jul 20 07:33:42 PM PDT 24 |
| Finished | Jul 20 07:43:03 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-40de4e11-ebd8-439d-bf8d-41bec9c2359e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269241879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1269241879 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.1403249935 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 3415771032 ps |
| CPU time | 224.56 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:26:31 PM PDT 24 |
| Peak memory | 599972 kb |
| Host | smart-5e724677-926a-4237-9f4c-57c7813bd224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403249935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.1403249935 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1355586697 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 4149559080 ps |
| CPU time | 529.61 seconds |
| Started | Jul 20 07:49:18 PM PDT 24 |
| Finished | Jul 20 07:58:09 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-0b6fe00b-6817-4977-a538-04dce75996c1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135558 6697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1355586697 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.3428443354 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3865578800 ps |
| CPU time | 505.43 seconds |
| Started | Jul 20 07:52:08 PM PDT 24 |
| Finished | Jul 20 08:00:35 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-242671a9-65e2-4413-b514-aff7ba8d7f7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428443354 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.3428443354 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2593509025 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 4294320074 ps |
| CPU time | 554.77 seconds |
| Started | Jul 20 07:58:21 PM PDT 24 |
| Finished | Jul 20 08:07:37 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-e9a1114c-6701-4f30-9ee0-41c31575defb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593509025 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2593509025 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.391065861 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3501586260 ps |
| CPU time | 280.02 seconds |
| Started | Jul 20 07:50:09 PM PDT 24 |
| Finished | Jul 20 07:54:49 PM PDT 24 |
| Peak memory | 621584 kb |
| Host | smart-c0f51d57-757e-497d-9bac-1c6637d53dce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391065861 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.391065861 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2672817462 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 14831776330 ps |
| CPU time | 3383.02 seconds |
| Started | Jul 20 08:08:58 PM PDT 24 |
| Finished | Jul 20 09:05:22 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-b39fbc4c-30d6-4e97-a77f-d29978793211 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672817462 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.2672817462 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.917987562 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6989714727 ps |
| CPU time | 371.97 seconds |
| Started | Jul 20 07:22:26 PM PDT 24 |
| Finished | Jul 20 07:28:39 PM PDT 24 |
| Peak memory | 664032 kb |
| Host | smart-a724f411-9fc0-40c7-88ec-3de3b5a1c2a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917987562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_re set.917987562 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.487315523 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5768765430 ps |
| CPU time | 792.96 seconds |
| Started | Jul 20 07:52:58 PM PDT 24 |
| Finished | Jul 20 08:06:12 PM PDT 24 |
| Peak memory | 620348 kb |
| Host | smart-fee49609-68c7-44f8-b265-661acc6b6786 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487315 523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.487315523 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.1342083542 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5352929898 ps |
| CPU time | 636.56 seconds |
| Started | Jul 20 08:17:43 PM PDT 24 |
| Finished | Jul 20 08:28:20 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-db85f13f-8f98-4b5a-b36c-2f97256198f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1342083542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.1342083542 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.969952843 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3352191816 ps |
| CPU time | 364.69 seconds |
| Started | Jul 20 07:49:17 PM PDT 24 |
| Finished | Jul 20 07:55:23 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-a4b5cf82-f8ca-4e06-a3d1-488a65819c67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969952843 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.969952843 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.2918929083 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 2969583808 ps |
| CPU time | 313.13 seconds |
| Started | Jul 20 07:54:31 PM PDT 24 |
| Finished | Jul 20 07:59:44 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-92530aa2-e1d3-473d-b25e-6b5821adc6e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918929083 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.2918929083 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.647329771 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 2084760315 ps |
| CPU time | 97.67 seconds |
| Started | Jul 20 07:26:20 PM PDT 24 |
| Finished | Jul 20 07:27:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3a6d71f1-4303-4c74-9682-bd6fab10f66e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647329771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 647329771 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.4158245090 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 3340134303 ps |
| CPU time | 147.36 seconds |
| Started | Jul 20 07:23:58 PM PDT 24 |
| Finished | Jul 20 07:26:26 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-001b4961-7c78-4b05-8f86-b7019c990306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158245090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.4158245090 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.4060385971 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 3896222719 ps |
| CPU time | 175.15 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:25:31 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-8c0b38e9-1bce-440a-b070-021cf7e10765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060385971 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.4060385971 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1023464055 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 1893587805 ps |
| CPU time | 78.13 seconds |
| Started | Jul 20 07:35:24 PM PDT 24 |
| Finished | Jul 20 07:36:43 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-266c7256-655f-402f-b93f-ee0f57d613a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023464055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1023464055 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.3502875820 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3575267480 ps |
| CPU time | 573.19 seconds |
| Started | Jul 20 08:13:10 PM PDT 24 |
| Finished | Jul 20 08:22:43 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-b85cda71-5350-49d9-bf6c-693aa74ea1b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502875820 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.3502875820 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.3595325741 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4089398064 ps |
| CPU time | 774.41 seconds |
| Started | Jul 20 08:11:27 PM PDT 24 |
| Finished | Jul 20 08:24:22 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-c77c921f-bbb7-4dfe-8451-d8ee3a1b93fe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595325741 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.3595325741 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.214966526 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 24710872132 ps |
| CPU time | 4166.95 seconds |
| Started | Jul 20 07:51:33 PM PDT 24 |
| Finished | Jul 20 09:01:01 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-232bd88f-c0c6-4607-a324-e83569dee94b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214966526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.214966526 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.855859992 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5143386328 ps |
| CPU time | 914.88 seconds |
| Started | Jul 20 07:49:38 PM PDT 24 |
| Finished | Jul 20 08:04:54 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-355b880a-16b3-4f6d-b429-901ee9b9d5ba |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855859992 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.855859992 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.2708530423 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2766385800 ps |
| CPU time | 220.56 seconds |
| Started | Jul 20 07:55:02 PM PDT 24 |
| Finished | Jul 20 07:58:43 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-79a61b4f-2d5b-4d82-a4e9-cbab5d07479c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708530423 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.2708530423 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2327191286 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3534934770 ps |
| CPU time | 429.36 seconds |
| Started | Jul 20 08:24:08 PM PDT 24 |
| Finished | Jul 20 08:31:19 PM PDT 24 |
| Peak memory | 648824 kb |
| Host | smart-23d4c209-1c83-4faa-8562-bd171e3c80ee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327191286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2327191286 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.605185064 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 10712686178 ps |
| CPU time | 484.94 seconds |
| Started | Jul 20 08:05:59 PM PDT 24 |
| Finished | Jul 20 08:14:05 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-9772ba4c-325f-4635-a7fb-4e37018dacf5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605185064 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.605185064 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3195259289 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 800169629 ps |
| CPU time | 227.09 seconds |
| Started | Jul 20 07:25:08 PM PDT 24 |
| Finished | Jul 20 07:28:55 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-5e5d6831-4aa6-4705-a60c-fceb2388396d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195259289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3195259289 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2517199882 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4470823450 ps |
| CPU time | 479.47 seconds |
| Started | Jul 20 07:50:55 PM PDT 24 |
| Finished | Jul 20 07:58:55 PM PDT 24 |
| Peak memory | 649088 kb |
| Host | smart-9d379001-4868-4628-9f83-cab9d6861c18 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517199882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.2517199882 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.948243350 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5232387480 ps |
| CPU time | 696.01 seconds |
| Started | Jul 20 07:49:20 PM PDT 24 |
| Finished | Jul 20 08:00:57 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-3c497ec6-68e9-4d73-8c2f-694f52f4589e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 948243350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.948243350 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3897645736 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4113873944 ps |
| CPU time | 528.35 seconds |
| Started | Jul 20 08:00:34 PM PDT 24 |
| Finished | Jul 20 08:09:23 PM PDT 24 |
| Peak memory | 648676 kb |
| Host | smart-ec4d0b62-c7f2-4c9e-8fc6-cc4a69a8f7af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897645736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3897645736 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.275197828 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4695824176 ps |
| CPU time | 804.86 seconds |
| Started | Jul 20 07:54:30 PM PDT 24 |
| Finished | Jul 20 08:07:56 PM PDT 24 |
| Peak memory | 649832 kb |
| Host | smart-157e18e7-855e-4686-8051-9993bda9b94d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 275197828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.275197828 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.749233280 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4558082206 ps |
| CPU time | 487.01 seconds |
| Started | Jul 20 08:22:17 PM PDT 24 |
| Finished | Jul 20 08:30:30 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-284fc95c-eb1d-4fd7-b448-888350681fb6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749233280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_s w_alert_handler_lpg_sleep_mode_alerts.749233280 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.2773361360 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4362741880 ps |
| CPU time | 548.94 seconds |
| Started | Jul 20 08:18:56 PM PDT 24 |
| Finished | Jul 20 08:28:05 PM PDT 24 |
| Peak memory | 650028 kb |
| Host | smart-fcf68a95-e2fb-4128-bab7-4831910df626 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2773361360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.2773361360 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.790363953 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3548603072 ps |
| CPU time | 440.45 seconds |
| Started | Jul 20 08:20:03 PM PDT 24 |
| Finished | Jul 20 08:27:23 PM PDT 24 |
| Peak memory | 648760 kb |
| Host | smart-9caa1fe0-fc85-4f9c-99e1-edf29c4432cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790363953 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.790363953 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.839275321 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 5482146344 ps |
| CPU time | 549.78 seconds |
| Started | Jul 20 08:18:20 PM PDT 24 |
| Finished | Jul 20 08:27:30 PM PDT 24 |
| Peak memory | 649724 kb |
| Host | smart-6a69aa6f-135c-4697-bcb4-d5fee2f8a57a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 839275321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.839275321 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.767483334 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4721077154 ps |
| CPU time | 597.33 seconds |
| Started | Jul 20 08:18:43 PM PDT 24 |
| Finished | Jul 20 08:28:41 PM PDT 24 |
| Peak memory | 650064 kb |
| Host | smart-6e9a5e6a-1af9-4e1e-a276-2b7e91c243dd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 767483334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.767483334 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.1509022320 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5705560182 ps |
| CPU time | 667.85 seconds |
| Started | Jul 20 08:17:58 PM PDT 24 |
| Finished | Jul 20 08:29:06 PM PDT 24 |
| Peak memory | 649800 kb |
| Host | smart-2783b642-10c7-41d7-b0cc-3dc28a5dfd68 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1509022320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.1509022320 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.2109802140 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 5510605784 ps |
| CPU time | 795.84 seconds |
| Started | Jul 20 08:19:07 PM PDT 24 |
| Finished | Jul 20 08:32:23 PM PDT 24 |
| Peak memory | 650040 kb |
| Host | smart-55e30202-a6a1-409e-907b-40c955611728 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2109802140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.2109802140 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2335276712 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 5205178120 ps |
| CPU time | 734.43 seconds |
| Started | Jul 20 08:18:57 PM PDT 24 |
| Finished | Jul 20 08:31:12 PM PDT 24 |
| Peak memory | 650360 kb |
| Host | smart-36159c7e-1dba-4718-9afd-9228249596f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2335276712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2335276712 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000439622 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 3681912184 ps |
| CPU time | 384.66 seconds |
| Started | Jul 20 08:19:21 PM PDT 24 |
| Finished | Jul 20 08:25:46 PM PDT 24 |
| Peak memory | 648720 kb |
| Host | smart-19dbfe28-65f4-4c5e-b0d5-53525f333e90 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000439622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4000439622 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.739452230 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 4274742688 ps |
| CPU time | 618.03 seconds |
| Started | Jul 20 08:20:04 PM PDT 24 |
| Finished | Jul 20 08:30:23 PM PDT 24 |
| Peak memory | 649760 kb |
| Host | smart-3cab785a-2707-4f4c-a60d-b0a1ed145258 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 739452230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.739452230 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3905206271 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 3636791224 ps |
| CPU time | 422.69 seconds |
| Started | Jul 20 08:20:31 PM PDT 24 |
| Finished | Jul 20 08:27:34 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-790e3a2b-5b4e-4612-a7f6-519d9d040e6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905206271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3905206271 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2621478043 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5142946050 ps |
| CPU time | 746 seconds |
| Started | Jul 20 08:20:24 PM PDT 24 |
| Finished | Jul 20 08:32:51 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-4e85ced6-eb85-4328-894b-96ae97d857f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2621478043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2621478043 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131894569 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 3698018860 ps |
| CPU time | 333.92 seconds |
| Started | Jul 20 08:10:47 PM PDT 24 |
| Finished | Jul 20 08:16:21 PM PDT 24 |
| Peak memory | 648548 kb |
| Host | smart-bfb8999f-d161-443a-87e3-33771c11afb0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131894569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.1131894569 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.295362125 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3925558430 ps |
| CPU time | 383.99 seconds |
| Started | Jul 20 08:19:55 PM PDT 24 |
| Finished | Jul 20 08:26:19 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-61320307-bd04-468d-b207-939b8a4de03d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295362125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_s w_alert_handler_lpg_sleep_mode_alerts.295362125 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.3000822928 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 5395266434 ps |
| CPU time | 616.72 seconds |
| Started | Jul 20 08:20:42 PM PDT 24 |
| Finished | Jul 20 08:31:00 PM PDT 24 |
| Peak memory | 650012 kb |
| Host | smart-6d031f96-7a5a-41a5-897a-0dd62dcf4bf5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3000822928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.3000822928 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398623795 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3946322360 ps |
| CPU time | 325.54 seconds |
| Started | Jul 20 08:21:41 PM PDT 24 |
| Finished | Jul 20 08:27:07 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-ce71b1a9-74a3-42a0-9168-4121da235744 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398623795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3398623795 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.54787741 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4889847048 ps |
| CPU time | 630.58 seconds |
| Started | Jul 20 08:23:33 PM PDT 24 |
| Finished | Jul 20 08:34:23 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-617bfa40-e47c-45d8-8236-735aeb8e7e66 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 54787741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.54787741 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2826540530 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3546463220 ps |
| CPU time | 320.91 seconds |
| Started | Jul 20 08:20:31 PM PDT 24 |
| Finished | Jul 20 08:25:53 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-5f1b528e-47a9-4518-a274-36b52b5b1c8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826540530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2826540530 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.3141279304 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 4754401212 ps |
| CPU time | 725.25 seconds |
| Started | Jul 20 08:20:18 PM PDT 24 |
| Finished | Jul 20 08:32:23 PM PDT 24 |
| Peak memory | 650124 kb |
| Host | smart-2556c949-9889-4361-a5cc-aa7a0c92b2d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3141279304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.3141279304 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952500919 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 3262814488 ps |
| CPU time | 420.21 seconds |
| Started | Jul 20 08:21:58 PM PDT 24 |
| Finished | Jul 20 08:28:59 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-434e0093-337c-4eae-ba79-92ea53aee682 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952500919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1952500919 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3180510691 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 3848638212 ps |
| CPU time | 307.56 seconds |
| Started | Jul 20 08:22:20 PM PDT 24 |
| Finished | Jul 20 08:28:00 PM PDT 24 |
| Peak memory | 648708 kb |
| Host | smart-d7a9e3ce-1ef5-4691-8c2b-57aa318582c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180510691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3180510691 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.832831145 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5864443304 ps |
| CPU time | 495.35 seconds |
| Started | Jul 20 08:22:05 PM PDT 24 |
| Finished | Jul 20 08:30:21 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-26146abf-f980-4788-8b73-b3c213e69331 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 832831145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.832831145 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.154054538 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3429918552 ps |
| CPU time | 334.13 seconds |
| Started | Jul 20 08:21:17 PM PDT 24 |
| Finished | Jul 20 08:26:51 PM PDT 24 |
| Peak memory | 648608 kb |
| Host | smart-ee8e8b66-ba65-40a3-a690-f5892bb10206 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154054538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_s w_alert_handler_lpg_sleep_mode_alerts.154054538 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3390096551 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5336282732 ps |
| CPU time | 661.56 seconds |
| Started | Jul 20 08:22:00 PM PDT 24 |
| Finished | Jul 20 08:33:02 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-5e0ba9ae-129e-4892-b220-efd78b5b83ec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3390096551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3390096551 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030448234 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3117397640 ps |
| CPU time | 414.32 seconds |
| Started | Jul 20 08:20:35 PM PDT 24 |
| Finished | Jul 20 08:27:29 PM PDT 24 |
| Peak memory | 648884 kb |
| Host | smart-3484a529-218b-4142-a227-2761984ed121 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030448234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4030448234 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.1418249879 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4560793300 ps |
| CPU time | 646.38 seconds |
| Started | Jul 20 08:20:52 PM PDT 24 |
| Finished | Jul 20 08:31:39 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-d83c5806-9fcb-40f8-bc17-184b6b2ddd8c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1418249879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.1418249879 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1889576734 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 4025117790 ps |
| CPU time | 378.99 seconds |
| Started | Jul 20 08:22:01 PM PDT 24 |
| Finished | Jul 20 08:28:21 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-00a61910-2784-4d05-9ef7-f751e83bc6af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889576734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1889576734 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522110741 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 3772733736 ps |
| CPU time | 467.95 seconds |
| Started | Jul 20 08:21:30 PM PDT 24 |
| Finished | Jul 20 08:29:18 PM PDT 24 |
| Peak memory | 648572 kb |
| Host | smart-968bc422-e65a-475e-835f-9feb6e83ba82 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522110741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3522110741 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3492176079 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3473454096 ps |
| CPU time | 408.24 seconds |
| Started | Jul 20 08:23:23 PM PDT 24 |
| Finished | Jul 20 08:30:40 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-975871e6-1c03-4468-8a5d-45fab40f8664 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492176079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3492176079 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182906132 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3166204660 ps |
| CPU time | 388.5 seconds |
| Started | Jul 20 08:21:56 PM PDT 24 |
| Finished | Jul 20 08:28:25 PM PDT 24 |
| Peak memory | 648620 kb |
| Host | smart-bc79b910-795e-47e1-ab6d-5a86eb520893 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182906132 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4182906132 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.2787292143 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 6132806948 ps |
| CPU time | 732.5 seconds |
| Started | Jul 20 08:22:22 PM PDT 24 |
| Finished | Jul 20 08:35:19 PM PDT 24 |
| Peak memory | 649716 kb |
| Host | smart-937bf79c-b62d-41db-be67-fc983277cd93 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2787292143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2787292143 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3476078258 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4262545580 ps |
| CPU time | 464.81 seconds |
| Started | Jul 20 08:16:24 PM PDT 24 |
| Finished | Jul 20 08:24:09 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-eae7c639-0209-471c-a87d-6753986b0802 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476078258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3476078258 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3064304537 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4383162648 ps |
| CPU time | 448.2 seconds |
| Started | Jul 20 08:21:37 PM PDT 24 |
| Finished | Jul 20 08:29:06 PM PDT 24 |
| Peak memory | 649192 kb |
| Host | smart-7c7fb2b7-e322-40e8-ba8a-3bb79d86f1d0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064304537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3064304537 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.2490268594 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4301497150 ps |
| CPU time | 548.8 seconds |
| Started | Jul 20 08:24:02 PM PDT 24 |
| Finished | Jul 20 08:33:12 PM PDT 24 |
| Peak memory | 650012 kb |
| Host | smart-3bd9c48e-b381-4b8f-9df8-36563440cade |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2490268594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.2490268594 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.13945628 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3895513642 ps |
| CPU time | 388.81 seconds |
| Started | Jul 20 08:24:53 PM PDT 24 |
| Finished | Jul 20 08:31:22 PM PDT 24 |
| Peak memory | 648920 kb |
| Host | smart-b086ae17-8d21-46e9-93a9-869efe9572f2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13945628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw _alert_handler_lpg_sleep_mode_alerts.13945628 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2714686220 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3226956288 ps |
| CPU time | 354.53 seconds |
| Started | Jul 20 08:22:29 PM PDT 24 |
| Finished | Jul 20 08:29:14 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-c9dc8bae-fa57-419d-a491-2c5136230134 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714686220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2714686220 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2840175333 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3977701944 ps |
| CPU time | 410.56 seconds |
| Started | Jul 20 08:22:08 PM PDT 24 |
| Finished | Jul 20 08:28:59 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-1fd213e1-680e-47e7-867b-a8c9ad7ede77 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840175333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2840175333 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248664509 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4199198816 ps |
| CPU time | 365.75 seconds |
| Started | Jul 20 08:22:34 PM PDT 24 |
| Finished | Jul 20 08:29:33 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-c8ecc202-2947-4111-9281-1bea41801619 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248664509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2248664509 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.2488046342 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4180285806 ps |
| CPU time | 506.09 seconds |
| Started | Jul 20 08:24:40 PM PDT 24 |
| Finished | Jul 20 08:33:07 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-3b0af386-9d6f-4cc5-ad34-c533a5a31483 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2488046342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.2488046342 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3745656405 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 3547233816 ps |
| CPU time | 332.5 seconds |
| Started | Jul 20 08:22:51 PM PDT 24 |
| Finished | Jul 20 08:29:13 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-267a9dec-3328-4886-a3ca-3addeff1fada |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745656405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3745656405 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489069616 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3443414778 ps |
| CPU time | 496.56 seconds |
| Started | Jul 20 08:27:38 PM PDT 24 |
| Finished | Jul 20 08:35:55 PM PDT 24 |
| Peak memory | 648676 kb |
| Host | smart-1fd889c8-f4f9-4ad8-8b4c-66cef9e5e1f9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489069616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3489069616 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679379477 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3781268264 ps |
| CPU time | 443.1 seconds |
| Started | Jul 20 08:23:48 PM PDT 24 |
| Finished | Jul 20 08:31:17 PM PDT 24 |
| Peak memory | 648748 kb |
| Host | smart-5818d0f9-dd48-4103-bdf6-f452a372c33f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679379477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2679379477 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2006765138 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 4775743424 ps |
| CPU time | 605.24 seconds |
| Started | Jul 20 08:22:13 PM PDT 24 |
| Finished | Jul 20 08:32:21 PM PDT 24 |
| Peak memory | 650236 kb |
| Host | smart-afe376ce-2386-4c56-9198-11a07ce4cb3b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2006765138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2006765138 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3899920332 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 4167048698 ps |
| CPU time | 353.88 seconds |
| Started | Jul 20 08:23:57 PM PDT 24 |
| Finished | Jul 20 08:29:52 PM PDT 24 |
| Peak memory | 648860 kb |
| Host | smart-cc93fb09-c263-4bdd-a5d8-1f50730c6faa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899920332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3899920332 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.1962853788 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 4087849200 ps |
| CPU time | 589.03 seconds |
| Started | Jul 20 08:26:16 PM PDT 24 |
| Finished | Jul 20 08:36:06 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-06927c49-220a-42d2-840b-50a589a4e9ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1962853788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.1962853788 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.319656619 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5831979440 ps |
| CPU time | 548.14 seconds |
| Started | Jul 20 08:29:43 PM PDT 24 |
| Finished | Jul 20 08:38:52 PM PDT 24 |
| Peak memory | 650628 kb |
| Host | smart-206d1ebc-1b2b-4de9-babf-9c8928e88542 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 319656619 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.319656619 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.192146883 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 5942848712 ps |
| CPU time | 697.3 seconds |
| Started | Jul 20 08:18:32 PM PDT 24 |
| Finished | Jul 20 08:30:10 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-bf0eca73-3e7a-4f56-88a6-efe121a5111f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 192146883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.192146883 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.2361190092 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 5882674616 ps |
| CPU time | 485.91 seconds |
| Started | Jul 20 08:23:00 PM PDT 24 |
| Finished | Jul 20 08:31:50 PM PDT 24 |
| Peak memory | 650104 kb |
| Host | smart-3b858e02-9c03-4999-a872-9de71ffb034c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2361190092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2361190092 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1141033913 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 5418531088 ps |
| CPU time | 512.62 seconds |
| Started | Jul 20 08:25:26 PM PDT 24 |
| Finished | Jul 20 08:33:59 PM PDT 24 |
| Peak memory | 649788 kb |
| Host | smart-666e31ad-15cb-4541-a54f-5deb6a69d633 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1141033913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1141033913 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2517464914 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 3244839650 ps |
| CPU time | 351.84 seconds |
| Started | Jul 20 08:31:08 PM PDT 24 |
| Finished | Jul 20 08:37:00 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-e8d22795-c1e1-4673-acbe-98b1c74ce42e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517464914 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2517464914 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3472660023 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 5692100674 ps |
| CPU time | 639.9 seconds |
| Started | Jul 20 08:23:29 PM PDT 24 |
| Finished | Jul 20 08:34:32 PM PDT 24 |
| Peak memory | 650116 kb |
| Host | smart-152d69d6-b42e-4762-8501-ac6cdfb7737f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3472660023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3472660023 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.299691723 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 5998132400 ps |
| CPU time | 528.16 seconds |
| Started | Jul 20 08:26:22 PM PDT 24 |
| Finished | Jul 20 08:35:11 PM PDT 24 |
| Peak memory | 650064 kb |
| Host | smart-6c692383-fd6f-4391-823f-78fb5a6933ae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 299691723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.299691723 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.2155952043 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 5319766284 ps |
| CPU time | 514.08 seconds |
| Started | Jul 20 08:24:02 PM PDT 24 |
| Finished | Jul 20 08:32:37 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-6cdba346-58aa-4075-aeeb-5d804f05bb3f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2155952043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2155952043 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3371867994 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 3251876468 ps |
| CPU time | 382.5 seconds |
| Started | Jul 20 08:25:10 PM PDT 24 |
| Finished | Jul 20 08:31:33 PM PDT 24 |
| Peak memory | 648772 kb |
| Host | smart-af6e28c1-6727-44ec-8e64-342cd943934f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371867994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3371867994 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.2668081895 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4481622302 ps |
| CPU time | 524.04 seconds |
| Started | Jul 20 08:27:33 PM PDT 24 |
| Finished | Jul 20 08:36:17 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-ccc01a2a-f26f-46e2-b176-4b846abb2b76 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2668081895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.2668081895 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.3985556177 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 4390169432 ps |
| CPU time | 506.96 seconds |
| Started | Jul 20 07:51:07 PM PDT 24 |
| Finished | Jul 20 07:59:35 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-29ff0485-299b-4e0c-a38b-750c0596fcdf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985556177 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.3985556177 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3015539012 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5187559776 ps |
| CPU time | 409.78 seconds |
| Started | Jul 20 07:53:49 PM PDT 24 |
| Finished | Jul 20 08:00:40 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-46ff30c4-5f27-4203-a93f-43594464ab27 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3015539012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3015539012 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.674076484 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 11815743160 ps |
| CPU time | 1677.32 seconds |
| Started | Jul 20 07:49:45 PM PDT 24 |
| Finished | Jul 20 08:17:43 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-bda31825-417c-4066-96ce-f89cdc3dad9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=674076484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.674076484 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.377623464 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 4543899220 ps |
| CPU time | 453.29 seconds |
| Started | Jul 20 08:02:02 PM PDT 24 |
| Finished | Jul 20 08:09:36 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-63c3bb0a-9ee0-4b6f-9202-a39eeea6d299 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377623464 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.377623464 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.101212172 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4965535090 ps |
| CPU time | 629.54 seconds |
| Started | Jul 20 08:23:09 PM PDT 24 |
| Finished | Jul 20 08:34:18 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-f676c45a-0104-4968-baa7-9d1568f95752 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 101212172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.101212172 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2466393945 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5298570686 ps |
| CPU time | 627.77 seconds |
| Started | Jul 20 08:05:01 PM PDT 24 |
| Finished | Jul 20 08:15:30 PM PDT 24 |
| Peak memory | 623764 kb |
| Host | smart-b4a28828-8810-42fb-9a72-9998ff36321c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466393945 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2466393945 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3815309041 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 6806572945 ps |
| CPU time | 497.64 seconds |
| Started | Jul 20 07:49:33 PM PDT 24 |
| Finished | Jul 20 07:57:51 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-16f3e6a7-c766-42e4-bb9e-164718fe4ad5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815309041 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.3815309041 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3403923366 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3516256144 ps |
| CPU time | 242.91 seconds |
| Started | Jul 20 08:10:59 PM PDT 24 |
| Finished | Jul 20 08:15:02 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-823a21d5-5c9b-44e2-ae7f-6cbba81b8a59 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403923366 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.3403923366 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3017465046 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 66526708511 ps |
| CPU time | 1217.47 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:42:43 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-cebab42c-b90b-474a-b3e7-3c8a219d313f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017465046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.3017465046 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.3264562766 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 8827718260 ps |
| CPU time | 341.39 seconds |
| Started | Jul 20 07:27:16 PM PDT 24 |
| Finished | Jul 20 07:32:58 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-6fb0ddff-0245-4225-87c5-2987c1e76945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264562766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3264562766 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.956316826 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 86820838046 ps |
| CPU time | 1702.09 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 08:08:11 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-098a5e26-edfb-4fa1-8610-51475d800c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956316826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.956316826 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.389963613 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 7865942552 ps |
| CPU time | 2100.11 seconds |
| Started | Jul 20 07:51:15 PM PDT 24 |
| Finished | Jul 20 08:26:16 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-38c8bf95-717a-4057-b471-878fee85b79a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=389963613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.389963613 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3996852230 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 5101279554 ps |
| CPU time | 633.43 seconds |
| Started | Jul 20 07:59:39 PM PDT 24 |
| Finished | Jul 20 08:10:13 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-25133228-00e3-4077-8506-6fd2f1b1a710 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3996852230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3996852230 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4155450805 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 18048742284 ps |
| CPU time | 503.38 seconds |
| Started | Jul 20 07:52:59 PM PDT 24 |
| Finished | Jul 20 08:01:23 PM PDT 24 |
| Peak memory | 619148 kb |
| Host | smart-cf0e2b40-9dd9-4d98-a07f-5d80f861ddda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=4155450805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4155450805 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2839651923 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 12445338440 ps |
| CPU time | 1467.68 seconds |
| Started | Jul 20 07:50:43 PM PDT 24 |
| Finished | Jul 20 08:15:11 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-ac74ad4e-0032-4233-bdaf-163da5db4cdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839651923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2839651923 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1645086008 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4643561922 ps |
| CPU time | 792.88 seconds |
| Started | Jul 20 07:49:51 PM PDT 24 |
| Finished | Jul 20 08:03:05 PM PDT 24 |
| Peak memory | 609556 kb |
| Host | smart-55c900fd-d8b5-4b62-aa88-49522bd8ac90 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645086008 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1645086008 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2284583989 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 10298789451 ps |
| CPU time | 364.94 seconds |
| Started | Jul 20 07:22:18 PM PDT 24 |
| Finished | Jul 20 07:28:24 PM PDT 24 |
| Peak memory | 591160 kb |
| Host | smart-d46e5dca-d1dc-4e1d-9d08-cab91a680f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284583989 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.2284583989 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1433821828 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4144237510 ps |
| CPU time | 486.98 seconds |
| Started | Jul 20 07:52:30 PM PDT 24 |
| Finished | Jul 20 08:00:37 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-a604bfe6-4698-4b67-b9d7-e64cf53c1490 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1433821828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1433821828 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2392227336 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2197164397 ps |
| CPU time | 106.53 seconds |
| Started | Jul 20 08:09:07 PM PDT 24 |
| Finished | Jul 20 08:10:54 PM PDT 24 |
| Peak memory | 621884 kb |
| Host | smart-0782775a-58db-4ac5-8cc5-328424d83e10 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392227336 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2392227336 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.3471930136 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 4037762092 ps |
| CPU time | 221.08 seconds |
| Started | Jul 20 07:23:49 PM PDT 24 |
| Finished | Jul 20 07:27:31 PM PDT 24 |
| Peak memory | 603736 kb |
| Host | smart-eeb0156c-36b6-4c95-ae68-0807bfa87295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471930136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.3471930136 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.946641666 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3511582312 ps |
| CPU time | 292.16 seconds |
| Started | Jul 20 07:29:48 PM PDT 24 |
| Finished | Jul 20 07:34:41 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-fdd37574-90ff-4661-8f4f-3e8598cbcee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946641666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.946641666 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3824165551 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3317885614 ps |
| CPU time | 339.49 seconds |
| Started | Jul 20 07:30:11 PM PDT 24 |
| Finished | Jul 20 07:35:51 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-2a56719e-6387-4e75-a0cb-8b61313c2370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824165551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3824165551 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.3194607823 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 13346387793 ps |
| CPU time | 652.58 seconds |
| Started | Jul 20 07:31:56 PM PDT 24 |
| Finished | Jul 20 07:42:49 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-8c63f32e-adad-4cb9-8e13-42e7e3db1a14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194607823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.3194607823 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.3474038779 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 3397326560 ps |
| CPU time | 266.61 seconds |
| Started | Jul 20 07:32:35 PM PDT 24 |
| Finished | Jul 20 07:37:03 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a53920c7-a495-42bd-bc05-9c1be6d4011f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474038779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.3474038779 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.704663041 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 16724146598 ps |
| CPU time | 619.36 seconds |
| Started | Jul 20 07:35:55 PM PDT 24 |
| Finished | Jul 20 07:46:16 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-ed6bbbc5-25fc-4e06-9e5a-bf8b10f002e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704663041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.704663041 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2394811898 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 4061585832 ps |
| CPU time | 375.55 seconds |
| Started | Jul 20 07:52:02 PM PDT 24 |
| Finished | Jul 20 07:58:19 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-095737e0-fe1d-46a9-9077-cacab6176787 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394811898 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2394811898 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4198365705 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4721169000 ps |
| CPU time | 790.71 seconds |
| Started | Jul 20 07:51:11 PM PDT 24 |
| Finished | Jul 20 08:04:22 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-779ad477-1c10-4f5e-b908-8c194a0c6e51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41983 65705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.4198365705 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.862317553 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 12400891974 ps |
| CPU time | 1839.11 seconds |
| Started | Jul 20 07:56:00 PM PDT 24 |
| Finished | Jul 20 08:26:40 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-63446eae-64d5-479d-b83b-d2742d586ddd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=862317553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.862317553 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1072024039 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3504404214 ps |
| CPU time | 233.18 seconds |
| Started | Jul 20 08:12:48 PM PDT 24 |
| Finished | Jul 20 08:16:42 PM PDT 24 |
| Peak memory | 620944 kb |
| Host | smart-0fda9e87-1b75-4692-8649-10b7f49fda2e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072024039 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1072024039 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.612626109 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5093979264 ps |
| CPU time | 222.26 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:26:16 PM PDT 24 |
| Peak memory | 663668 kb |
| Host | smart-20833f6a-e26c-48b1-aeed-7ba1e4f4b7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612626109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_re set.612626109 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3236536541 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4503687350 ps |
| CPU time | 958.62 seconds |
| Started | Jul 20 07:49:01 PM PDT 24 |
| Finished | Jul 20 08:05:01 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-d1180317-9956-4259-b55d-5701e03ddad7 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236536541 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.3236536541 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2600832884 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2999030280 ps |
| CPU time | 770.96 seconds |
| Started | Jul 20 07:52:28 PM PDT 24 |
| Finished | Jul 20 08:05:20 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-f1df45a2-094e-4e44-9708-a037e9028f7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600832884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2600832884 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1107549720 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 10416456672 ps |
| CPU time | 2435.95 seconds |
| Started | Jul 20 07:52:54 PM PDT 24 |
| Finished | Jul 20 08:33:31 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-18854434-0b52-4f44-b257-da01356d8b50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110754 9720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1107549720 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2586227417 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 10659827076 ps |
| CPU time | 2996.82 seconds |
| Started | Jul 20 07:51:19 PM PDT 24 |
| Finished | Jul 20 08:41:17 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-2970d847-9caf-4b05-b6d3-dab4a1908e6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25862 27417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2586227417 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1614056632 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 52198700951 ps |
| CPU time | 7623.67 seconds |
| Started | Jul 20 08:03:30 PM PDT 24 |
| Finished | Jul 20 10:10:35 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-73e4be94-3009-46a7-9abe-cb1c339afc7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1614056632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.1614056632 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2282602986 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3083569350 ps |
| CPU time | 241.88 seconds |
| Started | Jul 20 08:02:55 PM PDT 24 |
| Finished | Jul 20 08:06:58 PM PDT 24 |
| Peak memory | 617352 kb |
| Host | smart-bb3d41ff-802f-400f-8aab-961354e24206 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282602986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.2282602986 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3713254638 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 31392582599 ps |
| CPU time | 6271.61 seconds |
| Started | Jul 20 07:22:13 PM PDT 24 |
| Finished | Jul 20 09:06:46 PM PDT 24 |
| Peak memory | 593560 kb |
| Host | smart-28ecab42-7ce5-4220-aa90-bbaf2bfddbaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713254638 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3713254638 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3821107469 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 11801372416 ps |
| CPU time | 1102.06 seconds |
| Started | Jul 20 07:22:08 PM PDT 24 |
| Finished | Jul 20 07:40:31 PM PDT 24 |
| Peak memory | 590740 kb |
| Host | smart-fe17fb2e-3a47-487d-9a17-f1aa3feba821 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821107469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3821107469 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2818468090 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 6146982219 ps |
| CPU time | 507.4 seconds |
| Started | Jul 20 07:22:13 PM PDT 24 |
| Finished | Jul 20 07:30:41 PM PDT 24 |
| Peak memory | 641984 kb |
| Host | smart-45b21a16-a8ee-4510-a665-31463127e0b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818468090 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.2818468090 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1987467749 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 5926813617 ps |
| CPU time | 501.43 seconds |
| Started | Jul 20 07:22:14 PM PDT 24 |
| Finished | Jul 20 07:30:36 PM PDT 24 |
| Peak memory | 598392 kb |
| Host | smart-8fd54466-d683-4e45-99d0-54b0a34f6169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987467749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1987467749 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1472518783 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 10769309544 ps |
| CPU time | 442.78 seconds |
| Started | Jul 20 07:22:17 PM PDT 24 |
| Finished | Jul 20 07:29:41 PM PDT 24 |
| Peak memory | 590428 kb |
| Host | smart-36be644b-dff1-4ed5-9fd4-ad9ad6a3dae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472518783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1472518783 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1943053561 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 30000853268 ps |
| CPU time | 4471.52 seconds |
| Started | Jul 20 07:22:13 PM PDT 24 |
| Finished | Jul 20 08:36:46 PM PDT 24 |
| Peak memory | 592720 kb |
| Host | smart-53a3ea6a-167d-41ad-87a4-257814b44fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943053561 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1943053561 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2765460152 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 2774841382 ps |
| CPU time | 110.29 seconds |
| Started | Jul 20 07:22:13 PM PDT 24 |
| Finished | Jul 20 07:24:04 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c87d2782-568c-48bc-97b3-972dd5a8e311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765460152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2765460152 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2468851275 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 121137835697 ps |
| CPU time | 2110.4 seconds |
| Started | Jul 20 07:22:17 PM PDT 24 |
| Finished | Jul 20 07:57:28 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-3f1f010a-b2fb-4dc7-b643-b2b6884338a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468851275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2468851275 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2675902146 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 607126234 ps |
| CPU time | 25.1 seconds |
| Started | Jul 20 07:22:18 PM PDT 24 |
| Finished | Jul 20 07:22:44 PM PDT 24 |
| Peak memory | 575096 kb |
| Host | smart-b9501332-5319-4437-be72-6924b6908116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675902146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2675902146 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.2735978518 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 1731415491 ps |
| CPU time | 59.24 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:23:20 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d96cb0cd-2bcc-4139-bf35-26df42c4c700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735978518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.2735978518 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.21688919 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 567654626 ps |
| CPU time | 53.51 seconds |
| Started | Jul 20 07:22:16 PM PDT 24 |
| Finished | Jul 20 07:23:10 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-ec692cfe-f762-4644-a933-0d4b0f7298be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.21688919 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2609678647 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 13527468522 ps |
| CPU time | 152.65 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:25:06 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-147e0aa7-1a97-4924-b83a-2521d052ef11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609678647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.2609678647 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4128314616 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 45095946204 ps |
| CPU time | 807.39 seconds |
| Started | Jul 20 07:22:17 PM PDT 24 |
| Finished | Jul 20 07:35:46 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-30727e9e-9b27-400c-8ec8-35d0e400a0e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128314616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.4128314616 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4277416114 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 229403838 ps |
| CPU time | 20.68 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:22:55 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-5562eb59-25d0-4f53-9309-e24887e7ee50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277416114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.4277416114 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.1821092336 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 203255927 ps |
| CPU time | 9.64 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:22:30 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-15a7d6d3-e0b1-489e-93fd-94c2b08a69db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821092336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.1821092336 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.542153982 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 227555866 ps |
| CPU time | 9.54 seconds |
| Started | Jul 20 07:22:14 PM PDT 24 |
| Finished | Jul 20 07:22:24 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-c27e1e81-3e19-477f-8b14-eb10449bb9cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542153982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.542153982 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4247531618 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 7449499947 ps |
| CPU time | 83.56 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:23:56 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-952ac84d-bf9d-4701-aaa0-d264e6688c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247531618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.4247531618 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2269344921 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 3751557455 ps |
| CPU time | 62.65 seconds |
| Started | Jul 20 07:22:19 PM PDT 24 |
| Finished | Jul 20 07:23:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-768f9db7-2788-4855-87cb-e8fa3a22cf3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269344921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2269344921 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4043930541 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 49209965 ps |
| CPU time | 6.51 seconds |
| Started | Jul 20 07:22:12 PM PDT 24 |
| Finished | Jul 20 07:22:19 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-1d2001b7-640a-4a99-bb65-662a5a6eca70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043930541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .4043930541 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1536586124 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 1116564755 ps |
| CPU time | 100.01 seconds |
| Started | Jul 20 07:22:14 PM PDT 24 |
| Finished | Jul 20 07:23:55 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-96eecf7f-96f3-4e1a-9a45-91183502c0cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536586124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1536586124 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.70657318 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 3163277883 ps |
| CPU time | 259.36 seconds |
| Started | Jul 20 07:22:14 PM PDT 24 |
| Finished | Jul 20 07:26:34 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-d43f1fae-5a3d-4a74-a0da-89f4f9c1b4c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70657318 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.70657318 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.74975480 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 100947880 ps |
| CPU time | 22.39 seconds |
| Started | Jul 20 07:22:13 PM PDT 24 |
| Finished | Jul 20 07:22:37 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-94b52b2a-f063-46ad-b7e1-4eec51bf6a8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74975480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_reset_error.74975480 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3874712989 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 908205721 ps |
| CPU time | 42.15 seconds |
| Started | Jul 20 07:22:12 PM PDT 24 |
| Finished | Jul 20 07:22:55 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-cbdb5758-fa58-4d28-a46a-8f6a46f2205f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874712989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3874712989 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3872729523 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 37129575280 ps |
| CPU time | 5932.63 seconds |
| Started | Jul 20 07:22:11 PM PDT 24 |
| Finished | Jul 20 09:01:05 PM PDT 24 |
| Peak memory | 593988 kb |
| Host | smart-cba34dde-75f3-479b-8dde-b08a76117a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872729523 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.3872729523 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4280535443 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 5717813509 ps |
| CPU time | 543.04 seconds |
| Started | Jul 20 07:22:16 PM PDT 24 |
| Finished | Jul 20 07:31:20 PM PDT 24 |
| Peak memory | 592632 kb |
| Host | smart-03009c8e-8776-4461-be4c-17d365a53b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280535443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.4280535443 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3164297876 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 10902849294 ps |
| CPU time | 954.73 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:38:20 PM PDT 24 |
| Peak memory | 652624 kb |
| Host | smart-8c860a75-017a-4e20-9fa6-19a4ae8e5645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164297876 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.3164297876 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.4209241142 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 6042733496 ps |
| CPU time | 492.02 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:30:34 PM PDT 24 |
| Peak memory | 598684 kb |
| Host | smart-5c340a82-b376-4fbe-997b-9becbdd9eb70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209241142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.4209241142 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.823317539 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 12943943900 ps |
| CPU time | 428.04 seconds |
| Started | Jul 20 07:22:16 PM PDT 24 |
| Finished | Jul 20 07:29:24 PM PDT 24 |
| Peak memory | 590120 kb |
| Host | smart-a61c175c-00ef-404e-b8bd-8ebca1e1fa11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823317539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.823317539 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1739099785 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 20824789114 ps |
| CPU time | 981.03 seconds |
| Started | Jul 20 07:22:16 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 591144 kb |
| Host | smart-95872982-6955-441f-9c9a-3886794d4fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739099785 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.1739099785 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2616933423 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 14300511336 ps |
| CPU time | 1798.15 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:52:20 PM PDT 24 |
| Peak memory | 592756 kb |
| Host | smart-def9b5d0-6097-497d-81b5-bf3882f029ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616933423 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.2616933423 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3213055646 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3890398146 ps |
| CPU time | 175.22 seconds |
| Started | Jul 20 07:22:16 PM PDT 24 |
| Finished | Jul 20 07:25:12 PM PDT 24 |
| Peak memory | 603716 kb |
| Host | smart-46c3a824-b021-46b3-89d6-64e8b185ab1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213055646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3213055646 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4161850884 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 2549846566 ps |
| CPU time | 47.84 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:23:14 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-92cfe411-2e7b-4c25-88ab-b4137f0bc255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161850884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.4161850884 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1018206865 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 329194273 ps |
| CPU time | 35.75 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:22:59 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-efd30b9a-8ec1-44c2-9b31-476576e76d1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018206865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1018206865 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.2380594331 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 406915536 ps |
| CPU time | 15.99 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:22:41 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-66803869-5868-4b85-a87d-6bbf20837755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380594331 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2380594331 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.3586549837 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 567966289 ps |
| CPU time | 48.64 seconds |
| Started | Jul 20 07:22:17 PM PDT 24 |
| Finished | Jul 20 07:23:06 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-86eb8774-147c-4b20-9f86-f440a5e2cbf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586549837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.3586549837 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2701078532 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 18480166383 ps |
| CPU time | 193.97 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:25:48 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-e0237bd5-1228-4ed3-9035-bf4295e720b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701078532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2701078532 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1448752945 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 230384326 ps |
| CPU time | 21.06 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 07:22:48 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-b02a9f24-5ba4-4764-8bd0-af1b1abfbed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448752945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1448752945 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.32082394 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 2679714462 ps |
| CPU time | 83.37 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:23:46 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-14710788-782f-4b45-a63f-ee7a26851310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32082394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.32082394 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1199664348 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 155064948 ps |
| CPU time | 7.55 seconds |
| Started | Jul 20 07:22:18 PM PDT 24 |
| Finished | Jul 20 07:22:26 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-11e81b31-cb8c-40e6-89ae-4f5ed3be8205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199664348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1199664348 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1795699408 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 9765573610 ps |
| CPU time | 108.35 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:24:10 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7b8cc97d-cbae-4fba-864d-f821d3e38326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795699408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.1795699408 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.319895070 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 5570009612 ps |
| CPU time | 96.69 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:24:09 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-3aca2ba0-7a94-4006-a82a-8ecf17adfb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319895070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.319895070 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.728280004 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 45412269 ps |
| CPU time | 6.33 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:22:28 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-fecddd4b-008e-4992-8fcf-b7bf74a1333e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728280004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 728280004 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2924348109 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 11724329971 ps |
| CPU time | 447.14 seconds |
| Started | Jul 20 07:22:28 PM PDT 24 |
| Finished | Jul 20 07:29:56 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-aa3578ce-0be4-4b1d-ada9-04954d59ed94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924348109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2924348109 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.688008209 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 3308604105 ps |
| CPU time | 112.66 seconds |
| Started | Jul 20 07:22:28 PM PDT 24 |
| Finished | Jul 20 07:24:22 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c5e91be4-a743-438c-aa43-f1f985fbaaad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688008209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.688008209 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2274006275 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 225443241 ps |
| CPU time | 155.48 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:24:57 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-64299620-6fa8-442c-bf6c-950f274e4216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274006275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2274006275 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2985936922 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 1194798841 ps |
| CPU time | 208.08 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:25:50 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-bb7a5173-ecfd-4bd3-98b3-160b5f4ba245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985936922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.2985936922 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.108094221 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 925506284 ps |
| CPU time | 41.08 seconds |
| Started | Jul 20 07:22:26 PM PDT 24 |
| Finished | Jul 20 07:23:08 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d03ea0e7-86c7-4474-9818-738657494a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108094221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.108094221 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.368575357 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 6224797142 ps |
| CPU time | 693.31 seconds |
| Started | Jul 20 07:24:06 PM PDT 24 |
| Finished | Jul 20 07:35:40 PM PDT 24 |
| Peak memory | 598716 kb |
| Host | smart-c190e38b-62de-4179-98e1-c2a6e1261105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368575357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.368575357 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2690225130 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 14875089423 ps |
| CPU time | 1885.71 seconds |
| Started | Jul 20 07:23:51 PM PDT 24 |
| Finished | Jul 20 07:55:18 PM PDT 24 |
| Peak memory | 593228 kb |
| Host | smart-8fc68eca-954f-4b65-ace1-dc905ab8e78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690225130 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.2690225130 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.531142183 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1601781626 ps |
| CPU time | 61.53 seconds |
| Started | Jul 20 07:23:59 PM PDT 24 |
| Finished | Jul 20 07:25:01 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-dbe2a0ec-786c-4b96-b082-430435804e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531142183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device. 531142183 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1207237248 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 101784427619 ps |
| CPU time | 1951.6 seconds |
| Started | Jul 20 07:23:55 PM PDT 24 |
| Finished | Jul 20 07:56:28 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-65898e09-f5dc-47e8-b158-ee429875e64a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207237248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1207237248 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2115131924 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 81566805 ps |
| CPU time | 12.67 seconds |
| Started | Jul 20 07:23:58 PM PDT 24 |
| Finished | Jul 20 07:24:11 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-838881be-f1b0-4f08-b9f6-51060b89b45d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115131924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.2115131924 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.4203496753 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 847426093 ps |
| CPU time | 27 seconds |
| Started | Jul 20 07:23:59 PM PDT 24 |
| Finished | Jul 20 07:24:27 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-1d3c1065-f58b-4855-87e6-26e4d0f52c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203496753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4203496753 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.423685474 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 283376023 ps |
| CPU time | 29.1 seconds |
| Started | Jul 20 07:23:49 PM PDT 24 |
| Finished | Jul 20 07:24:19 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-7712d506-c3bb-4a93-b009-80a806a0231b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423685474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.423685474 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3119153787 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 71784038205 ps |
| CPU time | 781.39 seconds |
| Started | Jul 20 07:23:58 PM PDT 24 |
| Finished | Jul 20 07:37:00 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-c804a9f0-82c1-454c-9c82-ac1301d014fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119153787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3119153787 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1314852862 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 49306259260 ps |
| CPU time | 828.99 seconds |
| Started | Jul 20 07:23:58 PM PDT 24 |
| Finished | Jul 20 07:37:47 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-cf04724e-0bf7-4e42-8670-09b8ec6cf270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314852862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1314852862 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1784984416 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 34985371 ps |
| CPU time | 6.06 seconds |
| Started | Jul 20 07:23:59 PM PDT 24 |
| Finished | Jul 20 07:24:06 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-9c1f1170-6bc1-4766-8e6d-c2725243f049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784984416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1784984416 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.1059130122 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 453649420 ps |
| CPU time | 33.79 seconds |
| Started | Jul 20 07:23:57 PM PDT 24 |
| Finished | Jul 20 07:24:31 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-fb2b73f9-c076-411e-b6d9-59268ebdc7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059130122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.1059130122 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2635710175 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 45527721 ps |
| CPU time | 6.17 seconds |
| Started | Jul 20 07:23:51 PM PDT 24 |
| Finished | Jul 20 07:23:58 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-fb2c95ca-2dae-405b-9cad-bb3b4d969236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635710175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2635710175 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.973743026 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 8521562862 ps |
| CPU time | 99.9 seconds |
| Started | Jul 20 07:23:55 PM PDT 24 |
| Finished | Jul 20 07:25:36 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-112556ac-6fee-4996-9728-5a16f8039516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973743026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.973743026 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2202839633 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 5172269771 ps |
| CPU time | 90.61 seconds |
| Started | Jul 20 07:23:55 PM PDT 24 |
| Finished | Jul 20 07:25:26 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a3b0e1cf-ef7c-4d1a-8238-12328cd7e5e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202839633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.2202839633 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2612547205 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 52344797 ps |
| CPU time | 7.24 seconds |
| Started | Jul 20 07:23:50 PM PDT 24 |
| Finished | Jul 20 07:23:58 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-a236b5ab-6e10-4de6-ad79-ae125c41375b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612547205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.2612547205 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3645420746 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 1435669888 ps |
| CPU time | 119.03 seconds |
| Started | Jul 20 07:24:01 PM PDT 24 |
| Finished | Jul 20 07:26:01 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-cb961610-3062-4d3e-9436-ba5d5bebcdf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645420746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.3645420746 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.851184152 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 4615741854 ps |
| CPU time | 529.34 seconds |
| Started | Jul 20 07:23:56 PM PDT 24 |
| Finished | Jul 20 07:32:46 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-66bcd03c-4cb6-4710-9764-e35d8bf43bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851184152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_ with_rand_reset.851184152 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4248310040 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 2083346352 ps |
| CPU time | 289.39 seconds |
| Started | Jul 20 07:24:01 PM PDT 24 |
| Finished | Jul 20 07:28:51 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-3027ae72-7786-42da-8d04-ed822d5e083a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248310040 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.4248310040 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3931964540 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 295997855 ps |
| CPU time | 32.56 seconds |
| Started | Jul 20 07:23:59 PM PDT 24 |
| Finished | Jul 20 07:24:32 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-d4633c92-2b90-44ec-8ae6-42c6d8f9a6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931964540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3931964540 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2541489905 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 12730147680 ps |
| CPU time | 954.99 seconds |
| Started | Jul 20 07:24:24 PM PDT 24 |
| Finished | Jul 20 07:40:20 PM PDT 24 |
| Peak memory | 645252 kb |
| Host | smart-1a9b007e-cd1a-48b0-ba5a-9ad3e23973a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541489905 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.2541489905 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.78018898 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 4358259610 ps |
| CPU time | 345.72 seconds |
| Started | Jul 20 07:24:22 PM PDT 24 |
| Finished | Jul 20 07:30:08 PM PDT 24 |
| Peak memory | 598956 kb |
| Host | smart-4d4ec04f-acef-405c-9dcc-b5058cb32b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78018898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.78018898 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1674443373 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 27699787829 ps |
| CPU time | 3734.55 seconds |
| Started | Jul 20 07:24:03 PM PDT 24 |
| Finished | Jul 20 08:26:19 PM PDT 24 |
| Peak memory | 592744 kb |
| Host | smart-58a4943c-3f42-4be2-826a-ebd4df39ee84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674443373 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.1674443373 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.2062633831 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2072461208 ps |
| CPU time | 72.32 seconds |
| Started | Jul 20 07:24:04 PM PDT 24 |
| Finished | Jul 20 07:25:17 PM PDT 24 |
| Peak memory | 599580 kb |
| Host | smart-0bf0715f-1a9b-4168-b445-1da6bb5a5c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062633831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2062633831 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.4119134447 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 679214152 ps |
| CPU time | 28.08 seconds |
| Started | Jul 20 07:24:13 PM PDT 24 |
| Finished | Jul 20 07:24:42 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-7a3f377a-93dd-4557-aec3-03271b3c59ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119134447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .4119134447 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2909655492 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 49284812327 ps |
| CPU time | 846.67 seconds |
| Started | Jul 20 07:24:16 PM PDT 24 |
| Finished | Jul 20 07:38:24 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-647ff4fe-0257-4bf4-aca7-78c22cd951b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909655492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.2909655492 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3992873065 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 1159913108 ps |
| CPU time | 45.84 seconds |
| Started | Jul 20 07:24:15 PM PDT 24 |
| Finished | Jul 20 07:25:01 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-d5736f1f-5c99-4b62-a68f-25177b657497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992873065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3992873065 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.1978668021 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 1075202931 ps |
| CPU time | 34.3 seconds |
| Started | Jul 20 07:24:15 PM PDT 24 |
| Finished | Jul 20 07:24:50 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-eb302bf2-e7b8-41b1-aa47-ff392e923b86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978668021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.1978668021 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.2784707634 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1180151334 ps |
| CPU time | 41.96 seconds |
| Started | Jul 20 07:24:03 PM PDT 24 |
| Finished | Jul 20 07:24:46 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-d24a2365-ffcb-4a06-8988-7018296fc94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784707634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.2784707634 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3958364304 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 46640397532 ps |
| CPU time | 507.27 seconds |
| Started | Jul 20 07:24:14 PM PDT 24 |
| Finished | Jul 20 07:32:42 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-dc5f4cb1-fdb9-4482-ab4a-5645a80b5946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958364304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3958364304 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.790642332 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 41297164712 ps |
| CPU time | 756.42 seconds |
| Started | Jul 20 07:24:15 PM PDT 24 |
| Finished | Jul 20 07:36:53 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-860d6a6c-8ded-48af-8085-39ca4bc06710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790642332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.790642332 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3408302010 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 330697573 ps |
| CPU time | 31.41 seconds |
| Started | Jul 20 07:24:15 PM PDT 24 |
| Finished | Jul 20 07:24:48 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-fe41d48d-5c57-4adf-afda-f76193d9676a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408302010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.3408302010 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.3393244577 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 288466951 ps |
| CPU time | 23.53 seconds |
| Started | Jul 20 07:24:21 PM PDT 24 |
| Finished | Jul 20 07:24:45 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-b8017283-3d00-4a33-8a06-492c9ffd15dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393244577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.3393244577 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1963036322 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 217918619 ps |
| CPU time | 9.6 seconds |
| Started | Jul 20 07:24:06 PM PDT 24 |
| Finished | Jul 20 07:24:16 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-8a25fcf3-5cd5-4674-a65c-71ca7584398a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963036322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1963036322 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.920098164 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 8750220161 ps |
| CPU time | 96.33 seconds |
| Started | Jul 20 07:24:04 PM PDT 24 |
| Finished | Jul 20 07:25:41 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-39935bdc-a960-4706-90dd-9e0423179116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920098164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.920098164 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.953963167 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 5257424163 ps |
| CPU time | 97.42 seconds |
| Started | Jul 20 07:24:04 PM PDT 24 |
| Finished | Jul 20 07:25:43 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-cb3c0d08-092a-4139-be31-de644f107043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953963167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.953963167 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.324528602 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 43341088 ps |
| CPU time | 6.54 seconds |
| Started | Jul 20 07:24:05 PM PDT 24 |
| Finished | Jul 20 07:24:12 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-76b2b8e4-f039-4db4-9806-96b72f98bdf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324528602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays .324528602 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.3261584794 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 10168501640 ps |
| CPU time | 402.85 seconds |
| Started | Jul 20 07:24:16 PM PDT 24 |
| Finished | Jul 20 07:31:00 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-31466f20-aac9-4ab4-9da7-ca0f08a5b507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261584794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.3261584794 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1487959430 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 784096639 ps |
| CPU time | 284.44 seconds |
| Started | Jul 20 07:24:13 PM PDT 24 |
| Finished | Jul 20 07:28:59 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d41c459c-6dba-4d99-ac97-e18c92e85611 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487959430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.1487959430 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1439638060 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1097775398 ps |
| CPU time | 146.99 seconds |
| Started | Jul 20 07:24:17 PM PDT 24 |
| Finished | Jul 20 07:26:45 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a04ebbd3-dfd3-4c0d-a169-9b09e923a03c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439638060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.1439638060 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1155661724 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 60392649 ps |
| CPU time | 6.25 seconds |
| Started | Jul 20 07:24:14 PM PDT 24 |
| Finished | Jul 20 07:24:21 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-9aae4857-98bc-493a-bf18-174daffa5fc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155661724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.1155661724 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2763398402 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 7295755132 ps |
| CPU time | 487.08 seconds |
| Started | Jul 20 07:24:35 PM PDT 24 |
| Finished | Jul 20 07:32:44 PM PDT 24 |
| Peak memory | 641808 kb |
| Host | smart-a6cf7fa0-9a9b-4731-b8db-ca2c212180f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763398402 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.2763398402 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.20253863 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 4476773786 ps |
| CPU time | 420.41 seconds |
| Started | Jul 20 07:24:35 PM PDT 24 |
| Finished | Jul 20 07:31:37 PM PDT 24 |
| Peak memory | 596780 kb |
| Host | smart-bc5405a1-e398-4525-9022-b552a221d6f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.20253863 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3068684097 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 15193725018 ps |
| CPU time | 1678.73 seconds |
| Started | Jul 20 07:24:24 PM PDT 24 |
| Finished | Jul 20 07:52:24 PM PDT 24 |
| Peak memory | 592800 kb |
| Host | smart-f741437b-cb1d-4717-b0b3-7c35664f94ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068684097 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3068684097 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.4068187846 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3602077462 ps |
| CPU time | 148.03 seconds |
| Started | Jul 20 07:24:23 PM PDT 24 |
| Finished | Jul 20 07:26:52 PM PDT 24 |
| Peak memory | 603724 kb |
| Host | smart-40dbd1e5-3160-4aac-936b-4846363a5a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068187846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.4068187846 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.3287441129 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 386881887 ps |
| CPU time | 31.45 seconds |
| Started | Jul 20 07:24:25 PM PDT 24 |
| Finished | Jul 20 07:24:58 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-9a6cd071-bdcf-4477-b633-a5716b0eea89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287441129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .3287441129 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3962319758 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 13666382525 ps |
| CPU time | 236.98 seconds |
| Started | Jul 20 07:24:22 PM PDT 24 |
| Finished | Jul 20 07:28:20 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-31161c9f-d64f-4e49-bd6f-ee169bf7fcbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962319758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.3962319758 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2808480741 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 143887630 ps |
| CPU time | 8.48 seconds |
| Started | Jul 20 07:24:29 PM PDT 24 |
| Finished | Jul 20 07:24:39 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-17e0fc9f-723f-4420-8c1d-4f99ababfe2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808480741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.2808480741 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1714236536 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 136333239 ps |
| CPU time | 12.44 seconds |
| Started | Jul 20 07:24:29 PM PDT 24 |
| Finished | Jul 20 07:24:43 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-024d9752-1694-4d3b-a5d2-f99156e3defa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714236536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1714236536 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.142902815 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 1048947727 ps |
| CPU time | 38.49 seconds |
| Started | Jul 20 07:24:25 PM PDT 24 |
| Finished | Jul 20 07:25:05 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-70bad251-0406-432d-a5fe-31d04602f0fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142902815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.142902815 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3995004443 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 57382304638 ps |
| CPU time | 646.29 seconds |
| Started | Jul 20 07:24:22 PM PDT 24 |
| Finished | Jul 20 07:35:09 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-11719e2e-bfa0-426f-aab8-a7461dfb9918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995004443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3995004443 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2907393327 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 33166287720 ps |
| CPU time | 585.9 seconds |
| Started | Jul 20 07:24:21 PM PDT 24 |
| Finished | Jul 20 07:34:08 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-ca40dda5-5291-4de6-8a17-7df30968c94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907393327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2907393327 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1735867461 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 294128302 ps |
| CPU time | 27.85 seconds |
| Started | Jul 20 07:24:22 PM PDT 24 |
| Finished | Jul 20 07:24:51 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-2af600b1-5bcb-4199-ac91-5b5c98c4356b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735867461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.1735867461 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3789973449 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 587281828 ps |
| CPU time | 19.55 seconds |
| Started | Jul 20 07:24:29 PM PDT 24 |
| Finished | Jul 20 07:24:50 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-37264504-0a6d-43a1-aba1-3e64186cefa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789973449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3789973449 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.3497414616 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 228709584 ps |
| CPU time | 9.77 seconds |
| Started | Jul 20 07:24:24 PM PDT 24 |
| Finished | Jul 20 07:24:35 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-b54f74e5-5932-4daa-975c-20044c721776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497414616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.3497414616 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2843354264 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 8791481744 ps |
| CPU time | 100.76 seconds |
| Started | Jul 20 07:24:27 PM PDT 24 |
| Finished | Jul 20 07:26:09 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-cb430b90-d41b-4d35-a6a0-11aee3418b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843354264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.2843354264 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3042539990 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 4234768831 ps |
| CPU time | 75.21 seconds |
| Started | Jul 20 07:24:23 PM PDT 24 |
| Finished | Jul 20 07:25:39 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-5a05360b-d1ef-43ed-ae48-7d9ab36f9809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042539990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.3042539990 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.240515323 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 47885004 ps |
| CPU time | 6.53 seconds |
| Started | Jul 20 07:24:21 PM PDT 24 |
| Finished | Jul 20 07:24:29 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-02014dfe-eea5-404d-b353-0515fb7a1170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240515323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delays .240515323 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.3341992230 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 8067955043 ps |
| CPU time | 283.21 seconds |
| Started | Jul 20 07:24:28 PM PDT 24 |
| Finished | Jul 20 07:29:13 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-d80f485c-995d-4353-87ac-eeb1a22e38c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341992230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.3341992230 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.510985513 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 10748257826 ps |
| CPU time | 386.99 seconds |
| Started | Jul 20 07:24:29 PM PDT 24 |
| Finished | Jul 20 07:30:57 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-4507f459-ef6d-4a45-936a-daf3b4f73e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510985513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.510985513 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.53013431 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 9955364181 ps |
| CPU time | 629.11 seconds |
| Started | Jul 20 07:24:30 PM PDT 24 |
| Finished | Jul 20 07:35:01 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-f29e3bb2-77e0-46b5-8cd3-5a1c99e08883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53013431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_w ith_rand_reset.53013431 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1196206607 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1273363250 ps |
| CPU time | 168.77 seconds |
| Started | Jul 20 07:24:29 PM PDT 24 |
| Finished | Jul 20 07:27:19 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-6bfbd676-9e88-4ac1-af37-3be872e7453a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196206607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.1196206607 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4130035602 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 90755063 ps |
| CPU time | 13.14 seconds |
| Started | Jul 20 07:24:28 PM PDT 24 |
| Finished | Jul 20 07:24:43 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-28cd1f2c-ce26-414f-b77a-a3fef261c750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130035602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.4130035602 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3889413287 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 9770330736 ps |
| CPU time | 919.35 seconds |
| Started | Jul 20 07:25:00 PM PDT 24 |
| Finished | Jul 20 07:40:20 PM PDT 24 |
| Peak memory | 652976 kb |
| Host | smart-9c54554d-62ca-40de-95ab-1a00d39ebd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889413287 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.3889413287 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.423470569 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5302435302 ps |
| CPU time | 633.19 seconds |
| Started | Jul 20 07:24:59 PM PDT 24 |
| Finished | Jul 20 07:35:33 PM PDT 24 |
| Peak memory | 598372 kb |
| Host | smart-607f5da3-4610-4ec7-8544-19372f110574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423470569 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.423470569 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1059850101 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 32282439490 ps |
| CPU time | 4677.07 seconds |
| Started | Jul 20 07:24:37 PM PDT 24 |
| Finished | Jul 20 08:42:36 PM PDT 24 |
| Peak memory | 593388 kb |
| Host | smart-e90fa832-fbcd-452f-b48e-f8e415d6ac68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059850101 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.1059850101 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1223909739 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 4330817628 ps |
| CPU time | 385.27 seconds |
| Started | Jul 20 07:24:36 PM PDT 24 |
| Finished | Jul 20 07:31:02 PM PDT 24 |
| Peak memory | 591908 kb |
| Host | smart-4e6991bb-048e-4905-b635-7557de820a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223909739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1223909739 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.3373308580 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2474387757 ps |
| CPU time | 102.14 seconds |
| Started | Jul 20 07:24:48 PM PDT 24 |
| Finished | Jul 20 07:26:31 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3dc2ff8b-b454-432a-a0b2-378c388dc7ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373308580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .3373308580 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2456806309 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 92721705015 ps |
| CPU time | 1718.13 seconds |
| Started | Jul 20 07:24:47 PM PDT 24 |
| Finished | Jul 20 07:53:26 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-3c43cd0e-0839-4686-bcd0-a7339752c34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456806309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.2456806309 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3252216888 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 339009386 ps |
| CPU time | 15.66 seconds |
| Started | Jul 20 07:24:46 PM PDT 24 |
| Finished | Jul 20 07:25:02 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-272d72ac-0369-493a-b28b-d19d5ddd15bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252216888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3252216888 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.2544219377 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 216588573 ps |
| CPU time | 19.14 seconds |
| Started | Jul 20 07:24:47 PM PDT 24 |
| Finished | Jul 20 07:25:07 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-54fdc6c9-85da-4952-88ac-65908b449d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544219377 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.2544219377 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.761397078 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 95653576 ps |
| CPU time | 10.58 seconds |
| Started | Jul 20 07:24:36 PM PDT 24 |
| Finished | Jul 20 07:24:47 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-bc071b61-3343-4e4c-b895-b6b8c84e6e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761397078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.761397078 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1949196136 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 59351709685 ps |
| CPU time | 658.43 seconds |
| Started | Jul 20 07:24:37 PM PDT 24 |
| Finished | Jul 20 07:35:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-ba5d035e-485c-4e6b-964c-7198deac926e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949196136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1949196136 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2607118305 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 17355371246 ps |
| CPU time | 315.9 seconds |
| Started | Jul 20 07:24:46 PM PDT 24 |
| Finished | Jul 20 07:30:03 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-09dda578-62f2-4d20-9fb6-8a59c3f94272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607118305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2607118305 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.870511493 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 39308391 ps |
| CPU time | 5.99 seconds |
| Started | Jul 20 07:24:38 PM PDT 24 |
| Finished | Jul 20 07:24:45 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-52079acb-df4c-4050-b24a-edb18abb2790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870511493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.870511493 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.4031710573 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1854647791 ps |
| CPU time | 58.28 seconds |
| Started | Jul 20 07:24:48 PM PDT 24 |
| Finished | Jul 20 07:25:47 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-b5dfeffe-e73c-4714-9f37-18db7049f387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031710573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.4031710573 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.4069116592 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 48090273 ps |
| CPU time | 6.1 seconds |
| Started | Jul 20 07:24:37 PM PDT 24 |
| Finished | Jul 20 07:24:44 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-843e2bd0-ce4d-4af7-862a-fbeaf48513ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069116592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.4069116592 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2999619040 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 6568625342 ps |
| CPU time | 66.86 seconds |
| Started | Jul 20 07:24:35 PM PDT 24 |
| Finished | Jul 20 07:25:42 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-39b8cf64-89ae-4b0d-8eb1-d0dcbff32874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999619040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.2999619040 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2805813044 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 4235756212 ps |
| CPU time | 75.34 seconds |
| Started | Jul 20 07:24:34 PM PDT 24 |
| Finished | Jul 20 07:25:51 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-074ff216-2c10-49db-84d2-71530d51b97f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805813044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.2805813044 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3267949003 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 56210302 ps |
| CPU time | 6.92 seconds |
| Started | Jul 20 07:24:35 PM PDT 24 |
| Finished | Jul 20 07:24:42 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-faddbcb8-3b59-403f-bab1-b4376fcb8361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267949003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3267949003 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.3801569786 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 3826885303 ps |
| CPU time | 120.38 seconds |
| Started | Jul 20 07:24:46 PM PDT 24 |
| Finished | Jul 20 07:26:47 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-12cb664d-e220-4e28-a66a-f8837e6be538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801569786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.3801569786 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2951016569 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 5860709941 ps |
| CPU time | 221.24 seconds |
| Started | Jul 20 07:24:46 PM PDT 24 |
| Finished | Jul 20 07:28:28 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-41c45913-2fe8-4fbe-bac0-370e501de56f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951016569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.2951016569 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3577724135 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 287487231 ps |
| CPU time | 128.7 seconds |
| Started | Jul 20 07:24:45 PM PDT 24 |
| Finished | Jul 20 07:26:54 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-989ad51f-a557-42b7-abfd-9cde24e8fabf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577724135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.3577724135 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.904787579 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 355622298 ps |
| CPU time | 42.62 seconds |
| Started | Jul 20 07:24:47 PM PDT 24 |
| Finished | Jul 20 07:25:30 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b47e38db-fd61-49ed-a5ab-17c90b889e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904787579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_reset_error.904787579 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.599770792 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 686647060 ps |
| CPU time | 30.94 seconds |
| Started | Jul 20 07:24:46 PM PDT 24 |
| Finished | Jul 20 07:25:18 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-0e412e85-d4fe-4b67-be03-60a2432a58f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599770792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.599770792 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2493843762 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 6803374728 ps |
| CPU time | 528.56 seconds |
| Started | Jul 20 07:25:09 PM PDT 24 |
| Finished | Jul 20 07:33:59 PM PDT 24 |
| Peak memory | 639076 kb |
| Host | smart-a49d2e93-8fba-4542-abf6-626aa9e6d13a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493843762 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2493843762 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.2029378493 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 5711794086 ps |
| CPU time | 692.1 seconds |
| Started | Jul 20 07:25:09 PM PDT 24 |
| Finished | Jul 20 07:36:42 PM PDT 24 |
| Peak memory | 598800 kb |
| Host | smart-e86e1f90-c250-454a-984f-f748eb94c18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029378493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.2029378493 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3531818645 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 28284724347 ps |
| CPU time | 3910 seconds |
| Started | Jul 20 07:24:54 PM PDT 24 |
| Finished | Jul 20 08:30:05 PM PDT 24 |
| Peak memory | 593112 kb |
| Host | smart-03937513-4d5f-43c2-96ed-a70fecc6cf68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531818645 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.3531818645 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.472948375 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 3873506072 ps |
| CPU time | 297.21 seconds |
| Started | Jul 20 07:24:56 PM PDT 24 |
| Finished | Jul 20 07:29:54 PM PDT 24 |
| Peak memory | 599620 kb |
| Host | smart-c796091d-eff5-4794-95f6-e17dcea4ee74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472948375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.472948375 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.3074777908 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 240403656 ps |
| CPU time | 19.54 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:25:21 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c74c18d1-c417-4827-953a-6fd52862dbde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074777908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .3074777908 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1941800782 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 99961998325 ps |
| CPU time | 1771.46 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:54:34 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-0d75d119-77b9-4c6a-a318-3054720dff77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941800782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1941800782 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1068677871 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 1384725130 ps |
| CPU time | 49.78 seconds |
| Started | Jul 20 07:25:10 PM PDT 24 |
| Finished | Jul 20 07:26:01 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-65401729-064f-4f7d-bd33-f7fa9b792796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068677871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.1068677871 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.932044153 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 646153139 ps |
| CPU time | 45.42 seconds |
| Started | Jul 20 07:25:02 PM PDT 24 |
| Finished | Jul 20 07:25:49 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-bb8b6625-28f3-4465-a4af-82e5216f7540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932044153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.932044153 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2536610481 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 769362508 ps |
| CPU time | 33.82 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:25:36 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-b43907d7-1d63-46bd-8806-1eaf1b5743c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536610481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2536610481 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1853174780 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 33954620726 ps |
| CPU time | 381.46 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:31:24 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b9ac2337-395a-4e55-b466-269c3c96ceef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853174780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1853174780 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.875387017 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 12043900007 ps |
| CPU time | 194.64 seconds |
| Started | Jul 20 07:25:03 PM PDT 24 |
| Finished | Jul 20 07:28:18 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-91fd36a0-d617-4e7a-8b01-d6e3836563bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875387017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.875387017 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.780161948 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 578314776 ps |
| CPU time | 49.34 seconds |
| Started | Jul 20 07:25:02 PM PDT 24 |
| Finished | Jul 20 07:25:53 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-6bca0abb-3914-4cf7-ab7b-e2b6bd3c4097 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780161948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.780161948 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.2064874418 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2280271827 ps |
| CPU time | 66.17 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:26:08 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-46e91dbd-5ad4-4136-8e77-bd42fdfb381e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064874418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2064874418 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.749018171 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 204883625 ps |
| CPU time | 8.43 seconds |
| Started | Jul 20 07:24:59 PM PDT 24 |
| Finished | Jul 20 07:25:08 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-ccd91abc-1774-4c33-bd18-1dfa7d2f251e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749018171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.749018171 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.280278380 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 5731229300 ps |
| CPU time | 62.27 seconds |
| Started | Jul 20 07:25:01 PM PDT 24 |
| Finished | Jul 20 07:26:04 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e048016b-0d47-44d4-a989-6095cd70b42f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280278380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.280278380 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2869981548 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 5359743954 ps |
| CPU time | 97.14 seconds |
| Started | Jul 20 07:25:02 PM PDT 24 |
| Finished | Jul 20 07:26:40 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-2fbb284e-cf1d-4100-952a-860ff6be0554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869981548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.2869981548 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2455077316 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 51177257 ps |
| CPU time | 6.37 seconds |
| Started | Jul 20 07:25:02 PM PDT 24 |
| Finished | Jul 20 07:25:10 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-6b3f5bbf-443b-4023-8264-05ca8084dcf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455077316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.2455077316 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.4241456768 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3964598281 ps |
| CPU time | 149.16 seconds |
| Started | Jul 20 07:25:11 PM PDT 24 |
| Finished | Jul 20 07:27:41 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-b1278a0f-be1a-436a-9cdc-9c3cca4c5d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241456768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.4241456768 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3506173440 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 112801955 ps |
| CPU time | 43.75 seconds |
| Started | Jul 20 07:25:12 PM PDT 24 |
| Finished | Jul 20 07:25:56 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-0b763e82-f6e1-4e01-a431-4e436cb81877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506173440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3506173440 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2257042315 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 292906997 ps |
| CPU time | 34.5 seconds |
| Started | Jul 20 07:25:02 PM PDT 24 |
| Finished | Jul 20 07:25:37 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-af7df2a1-e442-4081-8451-2b6591534c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257042315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2257042315 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1288952324 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 5443007914 ps |
| CPU time | 465.18 seconds |
| Started | Jul 20 07:25:28 PM PDT 24 |
| Finished | Jul 20 07:33:14 PM PDT 24 |
| Peak memory | 639344 kb |
| Host | smart-58f6aa5f-cef3-46d8-a754-fd5a0751db3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288952324 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.1288952324 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.939454791 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 4409589386 ps |
| CPU time | 441.55 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:32:49 PM PDT 24 |
| Peak memory | 597992 kb |
| Host | smart-17553cd4-5c37-47a0-8e00-5141c53342d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939454791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.939454791 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.1927720084 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 3948195442 ps |
| CPU time | 242.23 seconds |
| Started | Jul 20 07:25:09 PM PDT 24 |
| Finished | Jul 20 07:29:12 PM PDT 24 |
| Peak memory | 603632 kb |
| Host | smart-f22ba856-3be0-4696-a3d6-237084400371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927720084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.1927720084 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.3424854048 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 1341559259 ps |
| CPU time | 51.92 seconds |
| Started | Jul 20 07:25:31 PM PDT 24 |
| Finished | Jul 20 07:26:24 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-aecf643c-8a0a-4d7c-ac81-d09a73f1cbb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424854048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .3424854048 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.27820401 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 5310667357 ps |
| CPU time | 91.61 seconds |
| Started | Jul 20 07:25:31 PM PDT 24 |
| Finished | Jul 20 07:27:03 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-7dc0ea0b-509d-4870-9f2c-2a6becef76a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27820401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_de vice_slow_rsp.27820401 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4113139866 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 346490366 ps |
| CPU time | 30.24 seconds |
| Started | Jul 20 07:25:29 PM PDT 24 |
| Finished | Jul 20 07:26:00 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-c5c2318e-8bdb-4199-9f6d-93e535c7f3b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113139866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.4113139866 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.1919476430 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 424664653 ps |
| CPU time | 18.1 seconds |
| Started | Jul 20 07:25:17 PM PDT 24 |
| Finished | Jul 20 07:25:35 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-14dcbc25-799a-41eb-a08f-cfe4d29d8031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919476430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1919476430 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.874283570 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 166520673 ps |
| CPU time | 15.36 seconds |
| Started | Jul 20 07:25:15 PM PDT 24 |
| Finished | Jul 20 07:25:31 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-d285e9cb-061b-4b7c-8922-4a7731222f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874283570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.874283570 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.784718694 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 25649591048 ps |
| CPU time | 273.29 seconds |
| Started | Jul 20 07:25:17 PM PDT 24 |
| Finished | Jul 20 07:29:51 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-377ec182-db9f-462e-9a77-7424e376966f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784718694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.784718694 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3131963814 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 22687250416 ps |
| CPU time | 363.6 seconds |
| Started | Jul 20 07:25:30 PM PDT 24 |
| Finished | Jul 20 07:31:35 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-6fad9123-a3ca-4a68-a489-f18d3ba76add |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131963814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3131963814 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3385560277 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 299357677 ps |
| CPU time | 26.2 seconds |
| Started | Jul 20 07:25:16 PM PDT 24 |
| Finished | Jul 20 07:25:43 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-d46c751a-86a4-4fc5-b362-33d2efdb0891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385560277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.3385560277 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2981901643 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 270952048 ps |
| CPU time | 22.08 seconds |
| Started | Jul 20 07:25:18 PM PDT 24 |
| Finished | Jul 20 07:25:41 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-dddddd53-778d-41ed-a1cc-35f749c9102c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981901643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2981901643 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.1953902791 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 48122013 ps |
| CPU time | 6.06 seconds |
| Started | Jul 20 07:25:11 PM PDT 24 |
| Finished | Jul 20 07:25:17 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-6491fcbc-c01a-4d66-8fed-e47bae19993e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953902791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.1953902791 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3365005252 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 9158120785 ps |
| CPU time | 109.11 seconds |
| Started | Jul 20 07:25:15 PM PDT 24 |
| Finished | Jul 20 07:27:05 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-d15d1053-0067-4b46-af1f-2d6db0221abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365005252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.3365005252 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2167192096 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 3716218038 ps |
| CPU time | 64.66 seconds |
| Started | Jul 20 07:25:30 PM PDT 24 |
| Finished | Jul 20 07:26:36 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-bd06075c-fa01-4f38-b970-35a855a3d605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167192096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.2167192096 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.567123032 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 43522659 ps |
| CPU time | 5.85 seconds |
| Started | Jul 20 07:25:31 PM PDT 24 |
| Finished | Jul 20 07:25:38 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-549b2e04-53e8-4e36-9cde-ed8258983bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567123032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .567123032 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2632442517 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2273945213 ps |
| CPU time | 88.09 seconds |
| Started | Jul 20 07:25:18 PM PDT 24 |
| Finished | Jul 20 07:26:47 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-332e2623-5f35-45bb-9d2a-12007753024d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632442517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2632442517 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.663700248 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 4655393527 ps |
| CPU time | 411.33 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:32:18 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-3ee09e90-e4af-4897-9724-7e7eae3eeae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663700248 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.663700248 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3764429124 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 3343914907 ps |
| CPU time | 452.36 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:33:00 PM PDT 24 |
| Peak memory | 580996 kb |
| Host | smart-1a887f2e-b590-42d5-9e98-dad536ebb85d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764429124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3764429124 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1122020403 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 952206528 ps |
| CPU time | 47 seconds |
| Started | Jul 20 07:25:16 PM PDT 24 |
| Finished | Jul 20 07:26:03 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-8caba4bf-4dae-4740-9c36-b11051119393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122020403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1122020403 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1406812623 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 7155802942 ps |
| CPU time | 484.26 seconds |
| Started | Jul 20 07:25:42 PM PDT 24 |
| Finished | Jul 20 07:33:48 PM PDT 24 |
| Peak memory | 638140 kb |
| Host | smart-d631bb86-c517-4525-b631-2204cd4160e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406812623 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.1406812623 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.2078546393 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 5354675984 ps |
| CPU time | 516.93 seconds |
| Started | Jul 20 07:25:32 PM PDT 24 |
| Finished | Jul 20 07:34:10 PM PDT 24 |
| Peak memory | 598396 kb |
| Host | smart-8c52c5fe-d143-41e7-bbbb-b0fc4f9107f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078546393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.2078546393 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1229026509 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 30457712266 ps |
| CPU time | 3975.8 seconds |
| Started | Jul 20 07:25:39 PM PDT 24 |
| Finished | Jul 20 08:31:57 PM PDT 24 |
| Peak memory | 593488 kb |
| Host | smart-1bad0b70-2d60-4b9a-81b0-498453411b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229026509 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.1229026509 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.2472169492 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 3941150832 ps |
| CPU time | 257.41 seconds |
| Started | Jul 20 07:25:30 PM PDT 24 |
| Finished | Jul 20 07:29:48 PM PDT 24 |
| Peak memory | 598612 kb |
| Host | smart-13841c5c-604a-4d02-a8a7-1f7e37de31db |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472169492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.2472169492 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.2929318836 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 932635184 ps |
| CPU time | 44.77 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:26:11 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-d340a4be-8f39-498f-8aeb-c36abc3cf4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929318836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .2929318836 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4009818460 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 73304235287 ps |
| CPU time | 1307.94 seconds |
| Started | Jul 20 07:25:28 PM PDT 24 |
| Finished | Jul 20 07:47:17 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-c5da64f9-4631-4772-937f-1e581c9c1c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009818460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.4009818460 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.497233349 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 794961932 ps |
| CPU time | 33.88 seconds |
| Started | Jul 20 07:25:37 PM PDT 24 |
| Finished | Jul 20 07:26:12 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-0cc8bc53-e95c-491c-8db3-0ffd14d8263b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497233349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .497233349 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.3476628276 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 2130989069 ps |
| CPU time | 65.25 seconds |
| Started | Jul 20 07:25:32 PM PDT 24 |
| Finished | Jul 20 07:26:39 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-5c7eafdd-3ac5-454f-b99c-77bef0f83c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476628276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.3476628276 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1992329204 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 511705571 ps |
| CPU time | 48.17 seconds |
| Started | Jul 20 07:25:27 PM PDT 24 |
| Finished | Jul 20 07:26:16 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-bb4c278d-e4b2-495c-8cfb-c540477f274d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992329204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1992329204 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2481356256 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 106210183536 ps |
| CPU time | 1185.69 seconds |
| Started | Jul 20 07:25:39 PM PDT 24 |
| Finished | Jul 20 07:45:26 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-44ee37fd-d16f-4c66-9d04-a47f98eb1c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481356256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2481356256 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3597598168 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 69143437870 ps |
| CPU time | 1332.67 seconds |
| Started | Jul 20 07:25:27 PM PDT 24 |
| Finished | Jul 20 07:47:41 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-6b63b254-1d32-4004-ab6a-36eea783c47f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597598168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3597598168 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3994287051 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 30405598 ps |
| CPU time | 5.68 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:25:33 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-2690e0bf-dbc8-40db-8f6d-613b7588d6c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994287051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3994287051 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.3560758434 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 339994004 ps |
| CPU time | 25.47 seconds |
| Started | Jul 20 07:25:26 PM PDT 24 |
| Finished | Jul 20 07:25:53 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-4b250529-e0d2-4109-ac3a-ef57f7fc43e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560758434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.3560758434 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.1523912756 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 48939006 ps |
| CPU time | 5.95 seconds |
| Started | Jul 20 07:25:38 PM PDT 24 |
| Finished | Jul 20 07:25:45 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-99b197f9-0199-4c38-9267-99499acfe91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523912756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.1523912756 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3639837728 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 7510674744 ps |
| CPU time | 80.89 seconds |
| Started | Jul 20 07:25:31 PM PDT 24 |
| Finished | Jul 20 07:26:53 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-8ec359eb-ddee-4d66-ab57-d2d43e12c83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639837728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.3639837728 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4270923250 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 6515628649 ps |
| CPU time | 107.38 seconds |
| Started | Jul 20 07:25:39 PM PDT 24 |
| Finished | Jul 20 07:27:27 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-dfddd2ea-bb90-4f46-b51a-52f4270ff0fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270923250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.4270923250 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3102786739 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 47797808 ps |
| CPU time | 5.94 seconds |
| Started | Jul 20 07:25:39 PM PDT 24 |
| Finished | Jul 20 07:25:46 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-ec3f789f-f6d3-4bc6-bba8-f438e9c704a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102786739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.3102786739 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3313538771 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 1773881493 ps |
| CPU time | 158.61 seconds |
| Started | Jul 20 07:25:34 PM PDT 24 |
| Finished | Jul 20 07:28:13 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-2afa6d3d-fcf8-48fb-8a47-006ae393ba97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313538771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3313538771 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1074491542 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 9448790361 ps |
| CPU time | 374.32 seconds |
| Started | Jul 20 07:25:33 PM PDT 24 |
| Finished | Jul 20 07:31:48 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-89065560-e141-4a2b-8ce9-a340e4dc3c81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074491542 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1074491542 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2553180168 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 12003919362 ps |
| CPU time | 688.66 seconds |
| Started | Jul 20 07:25:34 PM PDT 24 |
| Finished | Jul 20 07:37:03 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-8872e986-7cae-4f0a-ae40-f783d8f04794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553180168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2553180168 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2497720767 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 299878380 ps |
| CPU time | 57.55 seconds |
| Started | Jul 20 07:25:32 PM PDT 24 |
| Finished | Jul 20 07:26:30 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-6f277ec5-3b0b-41ca-b2a5-9ed0bc900da6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497720767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2497720767 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1005014678 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 1487361712 ps |
| CPU time | 55.5 seconds |
| Started | Jul 20 07:25:33 PM PDT 24 |
| Finished | Jul 20 07:26:29 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2138dd45-4c18-4fbf-98c4-b026aafb9d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005014678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1005014678 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.851155078 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 11092394376 ps |
| CPU time | 714.69 seconds |
| Started | Jul 20 07:25:58 PM PDT 24 |
| Finished | Jul 20 07:37:54 PM PDT 24 |
| Peak memory | 645856 kb |
| Host | smart-18086c86-3a1e-4eb1-9f34-1c5b20b20e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851155078 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.851155078 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.586250739 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 3768916608 ps |
| CPU time | 287.45 seconds |
| Started | Jul 20 07:25:58 PM PDT 24 |
| Finished | Jul 20 07:30:47 PM PDT 24 |
| Peak memory | 596344 kb |
| Host | smart-c6e0db7d-adb3-49cb-bb6d-6c143a33cc6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586250739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.586250739 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2847895034 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 31201645604 ps |
| CPU time | 4192.42 seconds |
| Started | Jul 20 07:25:45 PM PDT 24 |
| Finished | Jul 20 08:35:38 PM PDT 24 |
| Peak memory | 593024 kb |
| Host | smart-b1ab7f98-f065-4b7b-9444-4cfa953cffd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847895034 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.2847895034 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1794730760 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5061326311 ps |
| CPU time | 460.17 seconds |
| Started | Jul 20 07:25:40 PM PDT 24 |
| Finished | Jul 20 07:33:21 PM PDT 24 |
| Peak memory | 598620 kb |
| Host | smart-2c8a2dda-2315-4f0d-b6e2-f1dc2ac62b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794730760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1794730760 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.4240698290 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 2362915377 ps |
| CPU time | 95.43 seconds |
| Started | Jul 20 07:25:49 PM PDT 24 |
| Finished | Jul 20 07:27:25 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-df7b93fd-48e7-4ee2-975c-b6e1819dbee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240698290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .4240698290 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.589562212 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 101239356690 ps |
| CPU time | 1883.67 seconds |
| Started | Jul 20 07:25:53 PM PDT 24 |
| Finished | Jul 20 07:57:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ec6a78f1-9e89-441a-aad7-81c2a118bd92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589562212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_d evice_slow_rsp.589562212 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1392415429 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 433423555 ps |
| CPU time | 19.91 seconds |
| Started | Jul 20 07:25:52 PM PDT 24 |
| Finished | Jul 20 07:26:13 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-7ec4985c-b6b9-4ad5-b6f9-0eea51553de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392415429 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1392415429 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3754746079 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 2142807457 ps |
| CPU time | 74.24 seconds |
| Started | Jul 20 07:25:51 PM PDT 24 |
| Finished | Jul 20 07:27:07 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d21bada8-3f0b-4684-ae41-2f5d22d59004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754746079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3754746079 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.2571483699 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 160111092 ps |
| CPU time | 17.47 seconds |
| Started | Jul 20 07:25:41 PM PDT 24 |
| Finished | Jul 20 07:25:59 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-e53fa796-344c-406e-88fa-f5934c4f43e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571483699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.2571483699 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1916083253 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 37343393432 ps |
| CPU time | 398 seconds |
| Started | Jul 20 07:25:43 PM PDT 24 |
| Finished | Jul 20 07:32:22 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-8d64ebf1-254b-4264-80c2-669fcb4110d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916083253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.1916083253 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.820509127 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 1893627109 ps |
| CPU time | 34.35 seconds |
| Started | Jul 20 07:25:41 PM PDT 24 |
| Finished | Jul 20 07:26:18 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-95eb70ef-e3be-493f-838f-9c2fdd3cd03f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820509127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.820509127 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3101306534 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 471491579 ps |
| CPU time | 45.31 seconds |
| Started | Jul 20 07:25:40 PM PDT 24 |
| Finished | Jul 20 07:26:26 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-de044440-f2b1-4124-8ff0-e7c8655801f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101306534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3101306534 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3499392728 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 382587968 ps |
| CPU time | 30.63 seconds |
| Started | Jul 20 07:25:51 PM PDT 24 |
| Finished | Jul 20 07:26:22 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-aeb99725-b0bd-4326-b9b1-71797c610dc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499392728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3499392728 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2399273366 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 216176627 ps |
| CPU time | 9.58 seconds |
| Started | Jul 20 07:25:41 PM PDT 24 |
| Finished | Jul 20 07:25:53 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-a8665c56-7895-4ff1-be0f-1fa89699ecdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399273366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2399273366 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.233103792 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 10219275129 ps |
| CPU time | 112.55 seconds |
| Started | Jul 20 07:25:45 PM PDT 24 |
| Finished | Jul 20 07:27:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-5aabe717-c31e-4703-b094-69f826c6b0f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233103792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.233103792 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.147125495 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 5698511761 ps |
| CPU time | 94.73 seconds |
| Started | Jul 20 07:25:42 PM PDT 24 |
| Finished | Jul 20 07:27:18 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-3729c6c8-c841-4136-a291-72e7f9b1745a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147125495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.147125495 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1023027015 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 39178256 ps |
| CPU time | 5.6 seconds |
| Started | Jul 20 07:25:42 PM PDT 24 |
| Finished | Jul 20 07:25:49 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-941495d6-104e-4914-a8eb-f9d5d93c32bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023027015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1023027015 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.2770726163 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 11869884828 ps |
| CPU time | 451.73 seconds |
| Started | Jul 20 07:25:53 PM PDT 24 |
| Finished | Jul 20 07:33:25 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3d81c1c7-ac66-4a83-8a5f-38b9135c552d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770726163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.2770726163 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1909809995 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 4754067910 ps |
| CPU time | 327.16 seconds |
| Started | Jul 20 07:25:59 PM PDT 24 |
| Finished | Jul 20 07:31:27 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-14eb7e19-2078-4bf5-ae0a-62c3e5f5ccf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909809995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1909809995 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2169882359 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 257055309 ps |
| CPU time | 99.93 seconds |
| Started | Jul 20 07:25:50 PM PDT 24 |
| Finished | Jul 20 07:27:30 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-865a7964-e2af-4b37-b282-91a05db71a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169882359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.2169882359 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.881504643 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 391106097 ps |
| CPU time | 167.5 seconds |
| Started | Jul 20 07:25:58 PM PDT 24 |
| Finished | Jul 20 07:28:47 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-08c64177-5256-4440-83ad-eb3e447eba0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881504643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.881504643 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1882781571 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 82532896 ps |
| CPU time | 13.69 seconds |
| Started | Jul 20 07:25:53 PM PDT 24 |
| Finished | Jul 20 07:26:07 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-6b748445-f9b2-47ee-9d30-5c104f0342fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882781571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.1882781571 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1019183078 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 7005445350 ps |
| CPU time | 422.6 seconds |
| Started | Jul 20 07:26:13 PM PDT 24 |
| Finished | Jul 20 07:33:17 PM PDT 24 |
| Peak memory | 641692 kb |
| Host | smart-483aadab-51bf-4f52-8d22-4b5018bd7173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019183078 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.1019183078 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.3908327768 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 6615827728 ps |
| CPU time | 622.45 seconds |
| Started | Jul 20 07:26:12 PM PDT 24 |
| Finished | Jul 20 07:36:36 PM PDT 24 |
| Peak memory | 599184 kb |
| Host | smart-f5dd2b96-86cb-41d4-a1e9-9253aa165059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908327768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.3908327768 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1820057037 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 29647923233 ps |
| CPU time | 3984.49 seconds |
| Started | Jul 20 07:26:01 PM PDT 24 |
| Finished | Jul 20 08:32:27 PM PDT 24 |
| Peak memory | 593144 kb |
| Host | smart-6e69386e-7c10-4835-910f-372ea56d7d6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820057037 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1820057037 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3098451975 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 3626971327 ps |
| CPU time | 155.62 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:28:33 PM PDT 24 |
| Peak memory | 603704 kb |
| Host | smart-d5777348-729f-4c10-a0fb-eda632dabcde |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098451975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3098451975 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.445101749 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 748769495 ps |
| CPU time | 65.74 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:27:03 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f8204dec-86d5-43d6-b4b0-085cc83dd627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445101749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device. 445101749 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2487924163 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 63894752127 ps |
| CPU time | 1184.66 seconds |
| Started | Jul 20 07:26:04 PM PDT 24 |
| Finished | Jul 20 07:45:49 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-e2686a77-b3b6-497b-ab97-b2a364c56a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487924163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.2487924163 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2473174816 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 300916875 ps |
| CPU time | 13.56 seconds |
| Started | Jul 20 07:26:04 PM PDT 24 |
| Finished | Jul 20 07:26:18 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-443bb17f-13bf-4136-b196-e934b9aa0dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473174816 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2473174816 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.344236026 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 310908854 ps |
| CPU time | 28.65 seconds |
| Started | Jul 20 07:26:03 PM PDT 24 |
| Finished | Jul 20 07:26:33 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-2479b704-02fb-48a5-8517-260ace91e8ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344236026 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.344236026 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.2732315822 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 2268563292 ps |
| CPU time | 84.55 seconds |
| Started | Jul 20 07:25:56 PM PDT 24 |
| Finished | Jul 20 07:27:21 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-9f2b754c-4520-4e85-a105-cbb2ed2c4939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732315822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.2732315822 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1931060187 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 15172697546 ps |
| CPU time | 175.94 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:28:53 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c14cd3dc-1bec-431f-8416-935f6dacd452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931060187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1931060187 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1894810564 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 8378120736 ps |
| CPU time | 143.78 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:28:22 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-99a6c8a9-6c04-49fe-a8dc-7b441b8ae725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894810564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1894810564 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3302574034 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 215316187 ps |
| CPU time | 22.5 seconds |
| Started | Jul 20 07:25:58 PM PDT 24 |
| Finished | Jul 20 07:26:21 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-5492946b-b5db-4986-838a-725f2db9b710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302574034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3302574034 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3958234990 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 72079097 ps |
| CPU time | 9.19 seconds |
| Started | Jul 20 07:26:03 PM PDT 24 |
| Finished | Jul 20 07:26:13 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-7bbda44d-012b-4014-984a-c34bd64a4115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958234990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3958234990 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.3882714446 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 46899598 ps |
| CPU time | 6.84 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:26:05 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-6c10c6bb-780c-4174-820e-eb9ed4af968a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882714446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.3882714446 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.440870847 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 8195116190 ps |
| CPU time | 94.95 seconds |
| Started | Jul 20 07:26:01 PM PDT 24 |
| Finished | Jul 20 07:27:36 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e7503aa3-5a06-419d-b724-0821db749b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440870847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.440870847 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2354519946 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 5336782320 ps |
| CPU time | 93.74 seconds |
| Started | Jul 20 07:25:57 PM PDT 24 |
| Finished | Jul 20 07:27:32 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-b868a9ec-e8a3-497b-a831-8ec8c0a3412a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354519946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.2354519946 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2666012295 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 43692452 ps |
| CPU time | 6.64 seconds |
| Started | Jul 20 07:25:59 PM PDT 24 |
| Finished | Jul 20 07:26:07 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-b50c202f-8a90-4a68-9186-e34288eca3b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666012295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.2666012295 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.3015843729 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1214831517 ps |
| CPU time | 98.74 seconds |
| Started | Jul 20 07:26:05 PM PDT 24 |
| Finished | Jul 20 07:27:44 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-f9323973-158f-4839-b3b3-c8575924a5d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015843729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.3015843729 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1288256578 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 3396909879 ps |
| CPU time | 118.8 seconds |
| Started | Jul 20 07:26:04 PM PDT 24 |
| Finished | Jul 20 07:28:04 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-942c4ce4-7e94-412f-83a5-fa0b57931511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288256578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1288256578 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.378167324 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 5368892287 ps |
| CPU time | 694.66 seconds |
| Started | Jul 20 07:26:05 PM PDT 24 |
| Finished | Jul 20 07:37:40 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-36ceb8f3-719d-437d-8920-dba37d06b01e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378167324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_ with_rand_reset.378167324 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2928600015 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 6382608514 ps |
| CPU time | 383.29 seconds |
| Started | Jul 20 07:26:03 PM PDT 24 |
| Finished | Jul 20 07:32:27 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-933cfd14-599f-4311-9fe8-ef0e28b7b506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928600015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.2928600015 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3753621258 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 167014579 ps |
| CPU time | 23.5 seconds |
| Started | Jul 20 07:26:04 PM PDT 24 |
| Finished | Jul 20 07:26:28 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-aa2e79a3-dac0-47a6-9b41-346f1821fa35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753621258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3753621258 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4002866872 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 6974729076 ps |
| CPU time | 549.19 seconds |
| Started | Jul 20 07:26:29 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 638608 kb |
| Host | smart-539fbfca-9cbe-4380-95ee-e8dc3321064b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002866872 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.4002866872 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2730683775 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4889840030 ps |
| CPU time | 545.22 seconds |
| Started | Jul 20 07:26:30 PM PDT 24 |
| Finished | Jul 20 07:35:36 PM PDT 24 |
| Peak memory | 599152 kb |
| Host | smart-bde6a77f-797e-45b3-b0a9-e1eb2d0154a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730683775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2730683775 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.165700642 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 16324308088 ps |
| CPU time | 2458.65 seconds |
| Started | Jul 20 07:26:14 PM PDT 24 |
| Finished | Jul 20 08:07:13 PM PDT 24 |
| Peak memory | 592908 kb |
| Host | smart-132b48f9-6bdf-4b1b-b586-42a2ea7588e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165700642 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 19.chip_same_csr_outstanding.165700642 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1695706163 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 57050773233 ps |
| CPU time | 1049.36 seconds |
| Started | Jul 20 07:26:22 PM PDT 24 |
| Finished | Jul 20 07:43:52 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-a2ed362d-331b-46e7-b6f1-25cf5a3401d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695706163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.1695706163 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.453015835 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 866632120 ps |
| CPU time | 30.5 seconds |
| Started | Jul 20 07:26:22 PM PDT 24 |
| Finished | Jul 20 07:26:53 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5f76f3db-16ce-4661-8235-9494a1eb1a84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453015835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .453015835 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.3647126976 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 1704947806 ps |
| CPU time | 57.53 seconds |
| Started | Jul 20 07:26:21 PM PDT 24 |
| Finished | Jul 20 07:27:20 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-9d93fc91-9c08-4f88-9d68-ec163a93eb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647126976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3647126976 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.4178076284 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 557933766 ps |
| CPU time | 43.34 seconds |
| Started | Jul 20 07:26:11 PM PDT 24 |
| Finished | Jul 20 07:26:55 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-2692066f-20f1-4514-afc2-e18741a7e6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178076284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.4178076284 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2083256437 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 11458234146 ps |
| CPU time | 133.18 seconds |
| Started | Jul 20 07:26:11 PM PDT 24 |
| Finished | Jul 20 07:28:26 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-160f5786-c65e-4671-affd-e40f15895b2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083256437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.2083256437 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1517105539 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 70084654592 ps |
| CPU time | 1268.09 seconds |
| Started | Jul 20 07:26:12 PM PDT 24 |
| Finished | Jul 20 07:47:22 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-4a0720c4-674c-4069-95ce-3618e4a82ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517105539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1517105539 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2094886482 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 462218167 ps |
| CPU time | 40.99 seconds |
| Started | Jul 20 07:26:13 PM PDT 24 |
| Finished | Jul 20 07:26:55 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-aab4bc97-f1ee-49ec-b6e1-0a21f0987c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094886482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.2094886482 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.2350471192 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 144697970 ps |
| CPU time | 7.58 seconds |
| Started | Jul 20 07:26:20 PM PDT 24 |
| Finished | Jul 20 07:26:29 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8a1a8fc8-9e59-4f14-b75f-e5c033b2b1bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350471192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.2350471192 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.30378807 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 58719208 ps |
| CPU time | 6.87 seconds |
| Started | Jul 20 07:26:15 PM PDT 24 |
| Finished | Jul 20 07:26:22 PM PDT 24 |
| Peak memory | 575220 kb |
| Host | smart-7b182e77-720f-42ba-b517-46e14f7fb6aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30378807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.30378807 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.3319843225 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 8750746025 ps |
| CPU time | 96.51 seconds |
| Started | Jul 20 07:26:12 PM PDT 24 |
| Finished | Jul 20 07:27:49 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-5ae0bd7a-3e88-48f7-9192-1162172e26fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319843225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.3319843225 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.566444748 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 4053444886 ps |
| CPU time | 71.52 seconds |
| Started | Jul 20 07:26:14 PM PDT 24 |
| Finished | Jul 20 07:27:27 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-7cf481b7-0b32-4a7c-81b3-413ea8498ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566444748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.566444748 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3550007812 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 52988045 ps |
| CPU time | 7.07 seconds |
| Started | Jul 20 07:26:12 PM PDT 24 |
| Finished | Jul 20 07:26:21 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-7714c66a-7c50-4086-acb9-f1941f0f5053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550007812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3550007812 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1808300603 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 2171250767 ps |
| CPU time | 188.83 seconds |
| Started | Jul 20 07:26:32 PM PDT 24 |
| Finished | Jul 20 07:29:41 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-0a0976f7-7559-4bda-8c68-18873660aeb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808300603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1808300603 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.771218281 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 3361687590 ps |
| CPU time | 242.29 seconds |
| Started | Jul 20 07:26:30 PM PDT 24 |
| Finished | Jul 20 07:30:34 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ad538c6c-c882-4ce5-a16e-e082163ee86c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771218281 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.771218281 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2357761019 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 495304236 ps |
| CPU time | 147.46 seconds |
| Started | Jul 20 07:26:29 PM PDT 24 |
| Finished | Jul 20 07:28:58 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-6bc2dbfe-fa6c-4e35-b535-96201e77a1cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357761019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.2357761019 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.201713569 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 286870618 ps |
| CPU time | 160.71 seconds |
| Started | Jul 20 07:26:29 PM PDT 24 |
| Finished | Jul 20 07:29:12 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-7cf7f625-59ae-48e7-a01b-a658a268f36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201713569 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_reset_error.201713569 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.2923814564 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 83736552 ps |
| CPU time | 13.4 seconds |
| Started | Jul 20 07:26:21 PM PDT 24 |
| Finished | Jul 20 07:26:36 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-dc8e7bcb-dca8-4c9e-89f4-da7035203a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923814564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.2923814564 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.129429025 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 61203941200 ps |
| CPU time | 10225.3 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 10:12:52 PM PDT 24 |
| Peak memory | 642772 kb |
| Host | smart-72491d95-3882-4936-9004-9499e3f5d3c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129429025 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.129429025 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.4017218170 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 10476914860 ps |
| CPU time | 1272.66 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:43:34 PM PDT 24 |
| Peak memory | 592248 kb |
| Host | smart-d20d2502-82ac-46b4-bd47-f2f2f001ccac |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017218170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.4017218170 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.2837076269 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 8179952729 ps |
| CPU time | 401.35 seconds |
| Started | Jul 20 07:22:24 PM PDT 24 |
| Finished | Jul 20 07:29:07 PM PDT 24 |
| Peak memory | 638612 kb |
| Host | smart-debb3eaa-0725-4611-841f-a72e596102e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837076269 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.2837076269 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2984813369 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 5647759840 ps |
| CPU time | 551.2 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 07:31:38 PM PDT 24 |
| Peak memory | 598064 kb |
| Host | smart-46e9439a-635d-4ea5-84db-09820092f8f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984813369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2984813369 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2938357297 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 8536943564 ps |
| CPU time | 400.63 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 07:29:08 PM PDT 24 |
| Peak memory | 590108 kb |
| Host | smart-b997090a-dd6f-4fe3-8563-abe4fc5790b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938357297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2938357297 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.3457272330 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 10329449206 ps |
| CPU time | 371.36 seconds |
| Started | Jul 20 07:22:27 PM PDT 24 |
| Finished | Jul 20 07:28:39 PM PDT 24 |
| Peak memory | 591184 kb |
| Host | smart-92338d95-8ea7-452d-9456-a3edc25bcfa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457272330 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.3457272330 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3368958839 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 17242395036 ps |
| CPU time | 2222.69 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:59:29 PM PDT 24 |
| Peak memory | 593136 kb |
| Host | smart-d407d128-f547-4caf-a591-450d0bf11f2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368958839 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.3368958839 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1254213138 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 3120105587 ps |
| CPU time | 145.68 seconds |
| Started | Jul 20 07:22:22 PM PDT 24 |
| Finished | Jul 20 07:24:49 PM PDT 24 |
| Peak memory | 592384 kb |
| Host | smart-0d989c0e-14eb-4d1a-a31e-6b7c94737383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254213138 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1254213138 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.1808806854 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 3527486641 ps |
| CPU time | 135.73 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:24:41 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-73dec89f-8737-413e-bcdd-c7baf6314cae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808806854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 1808806854 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2704355002 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 35315722102 ps |
| CPU time | 613.05 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 07:32:40 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-130b9bc4-6236-4576-a98f-c8f92cdb95c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704355002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.2704355002 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2483033749 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 334306623 ps |
| CPU time | 38.28 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:23:01 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-6118e56d-429b-4b3c-a275-a25620a570ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483033749 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .2483033749 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.2588765122 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 782943206 ps |
| CPU time | 30.4 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:22:53 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-fea45417-02a6-47fe-99ce-58c72c9f4b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588765122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.2588765122 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.2380554802 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 698016392 ps |
| CPU time | 22.69 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:22:55 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1efabd17-a75f-490a-ac05-16a24a547efa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380554802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.2380554802 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.1849008836 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 11964435806 ps |
| CPU time | 130.37 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:24:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-26a9cacb-2178-4b8e-a512-4395adaa44fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849008836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.1849008836 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.4152335011 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 63573360597 ps |
| CPU time | 1211.53 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:42:36 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-2a4bb1db-46b2-4415-8d5a-141a66623f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152335011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.4152335011 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1997398353 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 525156034 ps |
| CPU time | 48.67 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:23:11 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-e63f606f-a98d-4d4f-b9a4-326370ca9b8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997398353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1997398353 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.1527630562 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 553494415 ps |
| CPU time | 39.21 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 07:23:06 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-1e22a7ec-02c8-4347-84c8-212d50589125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527630562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.1527630562 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.3447932358 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 152003153 ps |
| CPU time | 7.77 seconds |
| Started | Jul 20 07:22:22 PM PDT 24 |
| Finished | Jul 20 07:22:32 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-8eebbe73-f888-452a-a765-bc5e722ab9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447932358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3447932358 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.4275218870 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 9179617722 ps |
| CPU time | 101.26 seconds |
| Started | Jul 20 07:22:23 PM PDT 24 |
| Finished | Jul 20 07:24:07 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-cfdce6f3-ddc0-4d7d-940b-48c177710f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275218870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.4275218870 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3179522841 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 6064955365 ps |
| CPU time | 104.44 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:24:18 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-0b2142db-93ae-45f5-8797-a24e6c0c5f27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179522841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3179522841 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3928521724 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 49041668 ps |
| CPU time | 6.42 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:22:29 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-8c23390b-903b-48cb-8fbc-db009e7a1089 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928521724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3928521724 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1274231709 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 7050221552 ps |
| CPU time | 219.47 seconds |
| Started | Jul 20 07:22:28 PM PDT 24 |
| Finished | Jul 20 07:26:09 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-93b7a332-53fe-4722-b4ec-dcbbadfa5098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274231709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1274231709 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.2568586194 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 13763584923 ps |
| CPU time | 734.79 seconds |
| Started | Jul 20 07:22:24 PM PDT 24 |
| Finished | Jul 20 07:34:41 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-4e51674a-c7a8-400e-9902-91543e9fe42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568586194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.2568586194 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4292806012 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 614081483 ps |
| CPU time | 162.72 seconds |
| Started | Jul 20 07:22:28 PM PDT 24 |
| Finished | Jul 20 07:25:12 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-88f99d5c-6bb4-4df9-8deb-7c39f3d8f31e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292806012 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.4292806012 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.2717786598 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 254516829 ps |
| CPU time | 28.09 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:22:51 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-9cf42761-47d3-429a-8a27-e96a53041c40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717786598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.2717786598 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2075321335 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 4053432406 ps |
| CPU time | 281.38 seconds |
| Started | Jul 20 07:26:30 PM PDT 24 |
| Finished | Jul 20 07:31:13 PM PDT 24 |
| Peak memory | 599648 kb |
| Host | smart-312d4b3f-4335-4853-b0e8-378691d30d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075321335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2075321335 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2828684439 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 299802126 ps |
| CPU time | 26.93 seconds |
| Started | Jul 20 07:26:37 PM PDT 24 |
| Finished | Jul 20 07:27:05 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-db88d5fc-74c8-40ed-a03a-881aa8523305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828684439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2828684439 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3162229192 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 61767199107 ps |
| CPU time | 1170.72 seconds |
| Started | Jul 20 07:26:43 PM PDT 24 |
| Finished | Jul 20 07:46:15 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-2b0effc8-1e5e-4ee7-b33f-8f637c622c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162229192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.3162229192 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.684890547 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 38787439 ps |
| CPU time | 6.6 seconds |
| Started | Jul 20 07:26:43 PM PDT 24 |
| Finished | Jul 20 07:26:51 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-c51b0e1b-b3ae-4f0e-828b-d4961dba8b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684890547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_addr .684890547 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2414792934 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1494636662 ps |
| CPU time | 47.8 seconds |
| Started | Jul 20 07:26:43 PM PDT 24 |
| Finished | Jul 20 07:27:33 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c9d4a019-c3cc-40c7-a90d-00b95d6a6dfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414792934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2414792934 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.573116987 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 64863831 ps |
| CPU time | 7.65 seconds |
| Started | Jul 20 07:26:37 PM PDT 24 |
| Finished | Jul 20 07:26:47 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-8b7f41b3-9ade-4932-a568-f0bca64843fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573116987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.573116987 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.326489201 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 77074135483 ps |
| CPU time | 896.62 seconds |
| Started | Jul 20 07:26:37 PM PDT 24 |
| Finished | Jul 20 07:41:36 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-2aa54c6d-a854-4266-9b9d-c8e0dcfdfeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326489201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.326489201 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.2226465488 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 38739227289 ps |
| CPU time | 646.07 seconds |
| Started | Jul 20 07:26:37 PM PDT 24 |
| Finished | Jul 20 07:37:24 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-4b5200be-a0de-45cf-a87f-c9a188358b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226465488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.2226465488 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.345284586 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 615141781 ps |
| CPU time | 48.15 seconds |
| Started | Jul 20 07:26:40 PM PDT 24 |
| Finished | Jul 20 07:27:29 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-055482d9-8678-4936-aefd-068aa58f2b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345284586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.345284586 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.2335627897 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 1816908700 ps |
| CPU time | 60.13 seconds |
| Started | Jul 20 07:26:46 PM PDT 24 |
| Finished | Jul 20 07:27:47 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-193060d7-f887-4d8a-a206-eb3d8392418a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335627897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.2335627897 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.201184772 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 54329188 ps |
| CPU time | 6.51 seconds |
| Started | Jul 20 07:26:29 PM PDT 24 |
| Finished | Jul 20 07:26:36 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-1da0b109-c9aa-42c4-90a7-f162278f2a55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201184772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.201184772 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2991212203 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 9307766735 ps |
| CPU time | 106.52 seconds |
| Started | Jul 20 07:26:36 PM PDT 24 |
| Finished | Jul 20 07:28:24 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-bf48ca35-b89a-4114-832c-3a8f76a05c4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991212203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2991212203 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2749122509 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 3664839717 ps |
| CPU time | 67.95 seconds |
| Started | Jul 20 07:26:38 PM PDT 24 |
| Finished | Jul 20 07:27:47 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-4d13e174-86d2-4df7-aaa1-3cb28fbba930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749122509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2749122509 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.4117725198 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 46270300 ps |
| CPU time | 6.45 seconds |
| Started | Jul 20 07:26:30 PM PDT 24 |
| Finished | Jul 20 07:26:38 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d88647bb-725b-4dce-8c12-31480ca9a8c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117725198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.4117725198 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.1341393879 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 9790486073 ps |
| CPU time | 393.89 seconds |
| Started | Jul 20 07:26:42 PM PDT 24 |
| Finished | Jul 20 07:33:18 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-7f08382b-5999-42ed-b785-3e5a6a27a079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341393879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1341393879 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2669379837 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 3988679931 ps |
| CPU time | 317.48 seconds |
| Started | Jul 20 07:26:50 PM PDT 24 |
| Finished | Jul 20 07:32:08 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-0995f884-6ba3-4dad-bf2d-c8e20e0ccaaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669379837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2669379837 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.718700914 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 299819816 ps |
| CPU time | 91.92 seconds |
| Started | Jul 20 07:26:45 PM PDT 24 |
| Finished | Jul 20 07:28:18 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-5192dbf5-e270-49e1-9b47-e563eb8d9f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718700914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.718700914 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.2774046009 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 2072972070 ps |
| CPU time | 318.16 seconds |
| Started | Jul 20 07:26:55 PM PDT 24 |
| Finished | Jul 20 07:32:14 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-2183000b-1fff-4218-a9e3-5131cce1566d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774046009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.2774046009 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1272590053 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 37816665 ps |
| CPU time | 7.05 seconds |
| Started | Jul 20 07:26:44 PM PDT 24 |
| Finished | Jul 20 07:26:52 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-75e9e8e6-d565-4ca7-aeb4-92033a383b01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272590053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1272590053 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.4030240768 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 3368180592 ps |
| CPU time | 166.95 seconds |
| Started | Jul 20 07:26:52 PM PDT 24 |
| Finished | Jul 20 07:29:40 PM PDT 24 |
| Peak memory | 599636 kb |
| Host | smart-8a0b5de5-52cf-4453-beba-2d29f18b9696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030240768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.4030240768 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.2687002142 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 1438589618 ps |
| CPU time | 63.98 seconds |
| Started | Jul 20 07:26:53 PM PDT 24 |
| Finished | Jul 20 07:27:58 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3eeb5def-ed31-4f5a-a6d9-37a451c7e208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687002142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .2687002142 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.3635589714 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 129074813716 ps |
| CPU time | 2669.29 seconds |
| Started | Jul 20 07:26:52 PM PDT 24 |
| Finished | Jul 20 08:11:23 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-3f45cd31-5c0e-4cb2-a5d9-a76d6c38f4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635589714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.3635589714 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.3418125070 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 437549162 ps |
| CPU time | 22.85 seconds |
| Started | Jul 20 07:26:59 PM PDT 24 |
| Finished | Jul 20 07:27:22 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-bbed7681-59eb-47f5-b4e4-cf0b8eed45d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418125070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.3418125070 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.2197678965 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 275413718 ps |
| CPU time | 11.81 seconds |
| Started | Jul 20 07:27:04 PM PDT 24 |
| Finished | Jul 20 07:27:17 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-28e4abb6-bb63-4113-92c5-6f1840d1d93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197678965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.2197678965 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.3108844439 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 2168330385 ps |
| CPU time | 86.76 seconds |
| Started | Jul 20 07:26:53 PM PDT 24 |
| Finished | Jul 20 07:28:21 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-fb551c13-19ba-46de-849f-ec135640ea2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108844439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.3108844439 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.152045535 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 72645756378 ps |
| CPU time | 804.21 seconds |
| Started | Jul 20 07:26:52 PM PDT 24 |
| Finished | Jul 20 07:40:18 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-22ecbd43-da17-47fd-80da-f690b3dbcd9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152045535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.152045535 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.1658844067 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 47995581470 ps |
| CPU time | 835.01 seconds |
| Started | Jul 20 07:26:53 PM PDT 24 |
| Finished | Jul 20 07:40:49 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-c25b4532-3953-455b-9769-d6a08bff7004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658844067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.1658844067 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.1015424112 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 227281052 ps |
| CPU time | 25.59 seconds |
| Started | Jul 20 07:26:52 PM PDT 24 |
| Finished | Jul 20 07:27:18 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-f979e59a-dd49-4644-ad19-a59cbbc3b925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015424112 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.1015424112 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.3829690056 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 2709427832 ps |
| CPU time | 91.96 seconds |
| Started | Jul 20 07:27:01 PM PDT 24 |
| Finished | Jul 20 07:28:33 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-72fc839f-de03-4a00-a1b6-1bb654d87017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829690056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.3829690056 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.2470874307 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 246626162 ps |
| CPU time | 9.65 seconds |
| Started | Jul 20 07:26:53 PM PDT 24 |
| Finished | Jul 20 07:27:03 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-397695f4-61f0-4568-8f2d-8f5c4cfe01d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470874307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.2470874307 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3373197409 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 9099247985 ps |
| CPU time | 100.06 seconds |
| Started | Jul 20 07:26:52 PM PDT 24 |
| Finished | Jul 20 07:28:33 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a12c2500-5724-4486-b4db-c1a2d1147da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373197409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3373197409 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.3736266773 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 5339443518 ps |
| CPU time | 91.28 seconds |
| Started | Jul 20 07:26:56 PM PDT 24 |
| Finished | Jul 20 07:28:28 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-76821dde-4164-4cd3-85ac-67282204f2dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736266773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.3736266773 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1878738632 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 40931432 ps |
| CPU time | 5.5 seconds |
| Started | Jul 20 07:26:51 PM PDT 24 |
| Finished | Jul 20 07:26:57 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-c0855812-a6e4-4428-ac27-9de1e58ae85f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878738632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1878738632 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.696499081 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 10821929421 ps |
| CPU time | 444.19 seconds |
| Started | Jul 20 07:27:01 PM PDT 24 |
| Finished | Jul 20 07:34:26 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-3113f999-b012-49aa-a124-f8683b8b071b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696499081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.696499081 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.617554572 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 1726220397 ps |
| CPU time | 133.8 seconds |
| Started | Jul 20 07:27:02 PM PDT 24 |
| Finished | Jul 20 07:29:16 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d19b249c-79ec-4bf8-bd3a-35004e63256c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617554572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.617554572 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.4226554754 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 18673538 ps |
| CPU time | 15.83 seconds |
| Started | Jul 20 07:26:59 PM PDT 24 |
| Finished | Jul 20 07:27:15 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-9ce47978-7955-48c3-bfa7-1592836ceb88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226554754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.4226554754 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.1841083033 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 25394431402 ps |
| CPU time | 1015.87 seconds |
| Started | Jul 20 07:26:58 PM PDT 24 |
| Finished | Jul 20 07:43:55 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-cdf87818-4e0b-4b9f-b3f3-65918bae5ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841083033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.1841083033 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3635756412 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 1383927947 ps |
| CPU time | 54.27 seconds |
| Started | Jul 20 07:26:59 PM PDT 24 |
| Finished | Jul 20 07:27:53 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-a7ae415c-768f-466f-a924-57a8d78f52f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635756412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3635756412 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.404451586 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 1563840743 ps |
| CPU time | 60.64 seconds |
| Started | Jul 20 07:27:09 PM PDT 24 |
| Finished | Jul 20 07:28:10 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-278cf672-152c-415a-9364-6a35e4f21343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404451586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 404451586 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1260085487 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 63342774904 ps |
| CPU time | 1146.7 seconds |
| Started | Jul 20 07:27:16 PM PDT 24 |
| Finished | Jul 20 07:46:24 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-bb632285-ae11-4ddc-8365-b443ccf91d03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260085487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.1260085487 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1821131957 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 291792967 ps |
| CPU time | 35.78 seconds |
| Started | Jul 20 07:27:16 PM PDT 24 |
| Finished | Jul 20 07:27:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-937e5e33-30df-42f1-9831-b5290e752ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821131957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1821131957 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.3379704181 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 1571976220 ps |
| CPU time | 59.07 seconds |
| Started | Jul 20 07:27:15 PM PDT 24 |
| Finished | Jul 20 07:28:15 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-6a4c0039-350b-4233-b149-fc09a6d7f5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379704181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.3379704181 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.177681322 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 2462749637 ps |
| CPU time | 90.96 seconds |
| Started | Jul 20 07:27:11 PM PDT 24 |
| Finished | Jul 20 07:28:43 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-7fd4f2d1-bf78-4794-b290-dd5381a7fd41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177681322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.177681322 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.3811129749 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 96196492910 ps |
| CPU time | 1114.34 seconds |
| Started | Jul 20 07:27:07 PM PDT 24 |
| Finished | Jul 20 07:45:43 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-cf28bb1a-83ae-4373-8a26-0a2ea1ab4316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811129749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.3811129749 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2368765245 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 46074407886 ps |
| CPU time | 785.58 seconds |
| Started | Jul 20 07:27:09 PM PDT 24 |
| Finished | Jul 20 07:40:16 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-d87644de-44a2-4310-b813-543cc9a4e5ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368765245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2368765245 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1101017513 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 487837396 ps |
| CPU time | 48.63 seconds |
| Started | Jul 20 07:27:08 PM PDT 24 |
| Finished | Jul 20 07:27:57 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-aba58f0e-7c35-4e63-beae-541a9e5378cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101017513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1101017513 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.603912874 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 61556305 ps |
| CPU time | 7.89 seconds |
| Started | Jul 20 07:27:16 PM PDT 24 |
| Finished | Jul 20 07:27:25 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-13361328-a393-4178-9ffe-645ff4e172ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603912874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.603912874 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.1655843686 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 233161959 ps |
| CPU time | 10.77 seconds |
| Started | Jul 20 07:26:57 PM PDT 24 |
| Finished | Jul 20 07:27:09 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-f977e6e4-fa59-497e-8079-915d76231ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655843686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.1655843686 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2907197697 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 9914353894 ps |
| CPU time | 115.55 seconds |
| Started | Jul 20 07:26:59 PM PDT 24 |
| Finished | Jul 20 07:28:55 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-989977b9-7096-49ff-b7b2-db62260528b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907197697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2907197697 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3161740925 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 4017935386 ps |
| CPU time | 73.32 seconds |
| Started | Jul 20 07:27:09 PM PDT 24 |
| Finished | Jul 20 07:28:23 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3db0b16b-a35e-424e-a182-538c3ce4f9bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161740925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3161740925 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1368933391 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 53793035 ps |
| CPU time | 7.16 seconds |
| Started | Jul 20 07:26:59 PM PDT 24 |
| Finished | Jul 20 07:27:07 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-7d184e01-069b-42c8-a22d-db0bfd2644f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368933391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1368933391 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3393473487 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 2086781392 ps |
| CPU time | 153.13 seconds |
| Started | Jul 20 07:27:20 PM PDT 24 |
| Finished | Jul 20 07:29:54 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-73ed2043-4fc2-471b-a728-9c5554bce614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393473487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3393473487 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3549566127 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 842198508 ps |
| CPU time | 278.7 seconds |
| Started | Jul 20 07:27:21 PM PDT 24 |
| Finished | Jul 20 07:32:00 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-ba5d5c56-a276-4394-a307-bd75817fbc52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549566127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.3549566127 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1605919662 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 2134947980 ps |
| CPU time | 216.64 seconds |
| Started | Jul 20 07:27:18 PM PDT 24 |
| Finished | Jul 20 07:30:56 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-b4f8be1e-cdbd-4aa0-b99c-18b3441989a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605919662 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1605919662 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.4280330921 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 1064483285 ps |
| CPU time | 48.46 seconds |
| Started | Jul 20 07:27:15 PM PDT 24 |
| Finished | Jul 20 07:28:04 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b6abd529-23f6-44ad-9037-2ed43fd7c438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280330921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.4280330921 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2677871287 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2410385706 ps |
| CPU time | 78.3 seconds |
| Started | Jul 20 07:27:17 PM PDT 24 |
| Finished | Jul 20 07:28:36 PM PDT 24 |
| Peak memory | 603864 kb |
| Host | smart-d6af35dd-4580-4c0e-966f-4be902334785 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677871287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2677871287 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3493523603 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 551276842 ps |
| CPU time | 26.22 seconds |
| Started | Jul 20 07:27:26 PM PDT 24 |
| Finished | Jul 20 07:27:53 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-4cfa2f44-594c-4538-a84f-6168343e30a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493523603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .3493523603 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.3216992600 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 116352407779 ps |
| CPU time | 2149.85 seconds |
| Started | Jul 20 07:27:28 PM PDT 24 |
| Finished | Jul 20 08:03:19 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-54d5f0a5-a8b3-4b58-a59b-9105481a4e48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216992600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.3216992600 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2479087838 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 600779312 ps |
| CPU time | 23.08 seconds |
| Started | Jul 20 07:27:36 PM PDT 24 |
| Finished | Jul 20 07:28:00 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-c2e281ca-8a81-4e71-96bb-443ab7f9434c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479087838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.2479087838 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.610325287 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 123764778 ps |
| CPU time | 11.8 seconds |
| Started | Jul 20 07:27:28 PM PDT 24 |
| Finished | Jul 20 07:27:40 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-33890255-8541-47e6-8ce6-e6395cb98180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610325287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.610325287 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.2881099133 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 1888323946 ps |
| CPU time | 70.45 seconds |
| Started | Jul 20 07:27:26 PM PDT 24 |
| Finished | Jul 20 07:28:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-41751ae0-d575-45a8-851f-24e3d1aed2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881099133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.2881099133 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2225883829 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 3288909835 ps |
| CPU time | 36.36 seconds |
| Started | Jul 20 07:27:24 PM PDT 24 |
| Finished | Jul 20 07:28:01 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-251cde9c-602a-4629-804c-9f7f8dbfcbc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225883829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2225883829 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3736120888 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 66042588031 ps |
| CPU time | 1109.47 seconds |
| Started | Jul 20 07:27:24 PM PDT 24 |
| Finished | Jul 20 07:45:55 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-2eec5d97-32af-47d9-9d0f-4b6032d3cf28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736120888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3736120888 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3708551272 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 229289560 ps |
| CPU time | 24.03 seconds |
| Started | Jul 20 07:27:23 PM PDT 24 |
| Finished | Jul 20 07:27:48 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-9f4cb55f-05ba-4d52-92d9-772ca1a30449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708551272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3708551272 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3692544785 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 546833835 ps |
| CPU time | 40.26 seconds |
| Started | Jul 20 07:27:26 PM PDT 24 |
| Finished | Jul 20 07:28:07 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-e159a010-4ee7-4b93-8cd3-6c2416e29a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692544785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3692544785 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.1777815284 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 266602084 ps |
| CPU time | 10.69 seconds |
| Started | Jul 20 07:27:18 PM PDT 24 |
| Finished | Jul 20 07:27:29 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-afe1f388-c840-4d2c-a592-7f0a5c9fcd81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777815284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.1777815284 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.847534824 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 8701611677 ps |
| CPU time | 91.84 seconds |
| Started | Jul 20 07:27:22 PM PDT 24 |
| Finished | Jul 20 07:28:54 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-16b9104e-4791-49e8-9685-0edc2df6fa6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847534824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.847534824 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2739103983 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 6426168072 ps |
| CPU time | 112.65 seconds |
| Started | Jul 20 07:27:23 PM PDT 24 |
| Finished | Jul 20 07:29:17 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-c1a7fc79-e7f7-4fa0-ac07-248e83a905e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739103983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2739103983 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.2675503051 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 57240639 ps |
| CPU time | 7.18 seconds |
| Started | Jul 20 07:27:20 PM PDT 24 |
| Finished | Jul 20 07:27:28 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-b00be988-fad6-41f0-9be4-749e381ee2ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675503051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.2675503051 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.4026700283 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 1158369810 ps |
| CPU time | 40.9 seconds |
| Started | Jul 20 07:27:32 PM PDT 24 |
| Finished | Jul 20 07:28:14 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-7f8cb90e-8c9a-428d-b0e8-6f67250ddfc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026700283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.4026700283 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1647550891 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 3230416797 ps |
| CPU time | 126.33 seconds |
| Started | Jul 20 07:27:31 PM PDT 24 |
| Finished | Jul 20 07:29:38 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-bb157684-a762-424c-9f2b-48da21824a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647550891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1647550891 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3181927768 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 7209818555 ps |
| CPU time | 832.92 seconds |
| Started | Jul 20 07:27:33 PM PDT 24 |
| Finished | Jul 20 07:41:26 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-431b0013-4118-4fbc-8f94-70f09036f7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181927768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3181927768 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1935603390 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 171560617 ps |
| CPU time | 45.42 seconds |
| Started | Jul 20 07:27:32 PM PDT 24 |
| Finished | Jul 20 07:28:18 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8f1efb4d-cb11-4b45-ac1e-29f9ec462c03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935603390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1935603390 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1222135832 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 273127524 ps |
| CPU time | 33.87 seconds |
| Started | Jul 20 07:27:31 PM PDT 24 |
| Finished | Jul 20 07:28:06 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9e0e7171-7166-4672-b105-b66c38043b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222135832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.1222135832 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.2866106047 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 3483858290 ps |
| CPU time | 269.54 seconds |
| Started | Jul 20 07:27:31 PM PDT 24 |
| Finished | Jul 20 07:32:02 PM PDT 24 |
| Peak memory | 591576 kb |
| Host | smart-9d7bcd38-ac54-4c75-a54e-b492b96e4013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866106047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.2866106047 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.4084442848 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 528603564 ps |
| CPU time | 42.16 seconds |
| Started | Jul 20 07:27:40 PM PDT 24 |
| Finished | Jul 20 07:28:22 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-7180f891-31d4-44ec-8261-841165f9dff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084442848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .4084442848 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.2908114809 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 76431535110 ps |
| CPU time | 1408.47 seconds |
| Started | Jul 20 07:27:43 PM PDT 24 |
| Finished | Jul 20 07:51:12 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-20b4f7bc-b7e3-411a-9820-7758076a5783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908114809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.2908114809 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.4157398111 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 306432212 ps |
| CPU time | 35.14 seconds |
| Started | Jul 20 07:27:39 PM PDT 24 |
| Finished | Jul 20 07:28:15 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-a0247d64-e1d3-4b26-8e7b-1beae6d7ec60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157398111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.4157398111 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.3915347613 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 392024478 ps |
| CPU time | 30.8 seconds |
| Started | Jul 20 07:27:40 PM PDT 24 |
| Finished | Jul 20 07:28:12 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-82bf359c-fe65-43dc-b0b6-3b71a94e9429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915347613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.3915347613 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.1209580423 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 1145882477 ps |
| CPU time | 39.7 seconds |
| Started | Jul 20 07:27:33 PM PDT 24 |
| Finished | Jul 20 07:28:14 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-df34b385-0e8d-4868-99aa-908e11160bd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209580423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.1209580423 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.2432479204 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 64951936836 ps |
| CPU time | 712.61 seconds |
| Started | Jul 20 07:27:39 PM PDT 24 |
| Finished | Jul 20 07:39:33 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-e073026e-420c-46d6-9307-1a72dd650ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432479204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.2432479204 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.2616723102 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 44228705942 ps |
| CPU time | 785.54 seconds |
| Started | Jul 20 07:27:40 PM PDT 24 |
| Finished | Jul 20 07:40:47 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-fafdf7c4-2f18-4eb4-be40-e4a090f5d486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616723102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.2616723102 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.3267784902 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 279240524 ps |
| CPU time | 27.63 seconds |
| Started | Jul 20 07:27:42 PM PDT 24 |
| Finished | Jul 20 07:28:10 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-9a5f4ed5-6ad0-4772-913a-009f6af2f2aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267784902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.3267784902 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3173474550 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 185379120 ps |
| CPU time | 8.77 seconds |
| Started | Jul 20 07:27:42 PM PDT 24 |
| Finished | Jul 20 07:27:52 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-e492fadc-749b-4f42-8880-91c4a5b25af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173474550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3173474550 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1100841894 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 56052495 ps |
| CPU time | 7.08 seconds |
| Started | Jul 20 07:27:32 PM PDT 24 |
| Finished | Jul 20 07:27:40 PM PDT 24 |
| Peak memory | 575212 kb |
| Host | smart-5ab879b1-45c9-461d-973e-fcf9a294e594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100841894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1100841894 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2934003403 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 8336003607 ps |
| CPU time | 90.92 seconds |
| Started | Jul 20 07:27:32 PM PDT 24 |
| Finished | Jul 20 07:29:04 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-b96a3c8d-e9aa-469c-9c12-dd793a62e66a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934003403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2934003403 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.3084457540 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 6680717550 ps |
| CPU time | 112.85 seconds |
| Started | Jul 20 07:27:31 PM PDT 24 |
| Finished | Jul 20 07:29:25 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-df6b94ac-ccac-45c0-b90a-18e0a66770f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084457540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.3084457540 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.2521251224 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 52178691 ps |
| CPU time | 6.99 seconds |
| Started | Jul 20 07:27:31 PM PDT 24 |
| Finished | Jul 20 07:27:39 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-fe1cc1aa-9765-4c72-b1f5-a7284d80ee2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521251224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.2521251224 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1379924173 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 2354626919 ps |
| CPU time | 166.88 seconds |
| Started | Jul 20 07:27:41 PM PDT 24 |
| Finished | Jul 20 07:30:28 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-c004e35f-e096-47f2-a4ef-197b737397a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379924173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1379924173 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2565188077 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 10329010472 ps |
| CPU time | 334.36 seconds |
| Started | Jul 20 07:27:39 PM PDT 24 |
| Finished | Jul 20 07:33:15 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-5d4c94c1-e2e2-4a04-a03b-504dd9411f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565188077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2565188077 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.1203374755 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 7779636274 ps |
| CPU time | 510.29 seconds |
| Started | Jul 20 07:27:39 PM PDT 24 |
| Finished | Jul 20 07:36:10 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-425ea157-953a-408f-ad6a-b66cd121adb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203374755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.1203374755 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3517171004 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 9272583155 ps |
| CPU time | 471.11 seconds |
| Started | Jul 20 07:27:48 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-aa9c4483-4dd2-4aec-938a-dfea6f24a50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517171004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3517171004 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.3263460711 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 129987425 ps |
| CPU time | 16.76 seconds |
| Started | Jul 20 07:27:41 PM PDT 24 |
| Finished | Jul 20 07:27:58 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1870dc82-96a9-444f-b6cb-e86f049831a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263460711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.3263460711 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2432266921 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 3124355141 ps |
| CPU time | 174.75 seconds |
| Started | Jul 20 07:27:49 PM PDT 24 |
| Finished | Jul 20 07:30:44 PM PDT 24 |
| Peak memory | 598536 kb |
| Host | smart-eb200a2b-a2b6-4670-b3ad-238125e68289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432266921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2432266921 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.888805314 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 839645892 ps |
| CPU time | 45.04 seconds |
| Started | Jul 20 07:27:57 PM PDT 24 |
| Finished | Jul 20 07:28:43 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-f2c9b539-1eb9-47c2-83be-f5dd8cbdf26e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888805314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 888805314 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1249929731 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 63091045851 ps |
| CPU time | 1141.83 seconds |
| Started | Jul 20 07:27:56 PM PDT 24 |
| Finished | Jul 20 07:46:58 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f1966113-26f0-4271-b0c9-f13523d4599c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249929731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1249929731 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1158245265 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 476467620 ps |
| CPU time | 19.97 seconds |
| Started | Jul 20 07:28:03 PM PDT 24 |
| Finished | Jul 20 07:28:23 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-0aa190b6-7eac-4957-a236-ce42d8f4eb2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158245265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.1158245265 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.1155894851 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 2144742450 ps |
| CPU time | 74.18 seconds |
| Started | Jul 20 07:27:55 PM PDT 24 |
| Finished | Jul 20 07:29:09 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-12548615-5d79-48e7-9695-395a918bf45c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155894851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.1155894851 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1092675884 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1237808642 ps |
| CPU time | 42.6 seconds |
| Started | Jul 20 07:27:48 PM PDT 24 |
| Finished | Jul 20 07:28:31 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-414c5f93-edd1-422a-8626-b2e653d56557 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092675884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1092675884 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.222024840 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 14590216493 ps |
| CPU time | 171.93 seconds |
| Started | Jul 20 07:27:54 PM PDT 24 |
| Finished | Jul 20 07:30:47 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-accf7a30-26a2-4c63-a459-ff51fbdb05f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222024840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.222024840 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3075993475 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 20908800286 ps |
| CPU time | 381.24 seconds |
| Started | Jul 20 07:27:57 PM PDT 24 |
| Finished | Jul 20 07:34:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-fb41fd69-d274-4317-8803-2321f99c133a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075993475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3075993475 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.1638160467 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 165662487 ps |
| CPU time | 15.54 seconds |
| Started | Jul 20 07:27:48 PM PDT 24 |
| Finished | Jul 20 07:28:04 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-cdd01508-dae6-4547-90db-282f6d021253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638160467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.1638160467 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.2439077753 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2617369380 ps |
| CPU time | 76.24 seconds |
| Started | Jul 20 07:27:57 PM PDT 24 |
| Finished | Jul 20 07:29:14 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-96930708-b544-483f-a142-35fbac79e0ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439077753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2439077753 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.1350733493 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 162829150 ps |
| CPU time | 7.55 seconds |
| Started | Jul 20 07:27:50 PM PDT 24 |
| Finished | Jul 20 07:27:58 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-b46b6c6d-7bff-4db3-b17b-8ada059fe768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350733493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.1350733493 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.2259045816 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 7315196587 ps |
| CPU time | 76.53 seconds |
| Started | Jul 20 07:27:52 PM PDT 24 |
| Finished | Jul 20 07:29:09 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0eb2b90d-a3da-474a-8a55-05922f8c0573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259045816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2259045816 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.1792328564 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 6168731396 ps |
| CPU time | 110.25 seconds |
| Started | Jul 20 07:27:49 PM PDT 24 |
| Finished | Jul 20 07:29:40 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-8da3b339-330b-4de5-a491-ae2d4e0c3abc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792328564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.1792328564 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.307279658 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 49084380 ps |
| CPU time | 6.6 seconds |
| Started | Jul 20 07:27:48 PM PDT 24 |
| Finished | Jul 20 07:27:55 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-e23a942e-45ab-43fa-81c8-3900dbe97786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307279658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .307279658 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.3372233825 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 5001123221 ps |
| CPU time | 211.39 seconds |
| Started | Jul 20 07:28:04 PM PDT 24 |
| Finished | Jul 20 07:31:36 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-7ba939aa-3d91-4b6e-bd1c-9bf22c6c3647 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372233825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.3372233825 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.4081603065 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 13469219888 ps |
| CPU time | 443.8 seconds |
| Started | Jul 20 07:28:11 PM PDT 24 |
| Finished | Jul 20 07:35:35 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-3b457ae3-dfe1-4c01-a26f-859002058a5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081603065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.4081603065 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.3400377396 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3112543277 ps |
| CPU time | 594.12 seconds |
| Started | Jul 20 07:28:06 PM PDT 24 |
| Finished | Jul 20 07:38:01 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-55ffd5ed-0c44-4ba2-8431-79663d751964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400377396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.3400377396 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2965192626 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 3019751857 ps |
| CPU time | 254.8 seconds |
| Started | Jul 20 07:28:06 PM PDT 24 |
| Finished | Jul 20 07:32:22 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-525ba777-0153-40c2-a64a-61df97a4e3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965192626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2965192626 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1107730130 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 312057866 ps |
| CPU time | 40.34 seconds |
| Started | Jul 20 07:27:56 PM PDT 24 |
| Finished | Jul 20 07:28:37 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-ab5ce74f-b321-450e-8723-13c8827e3f36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107730130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1107730130 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.2855620616 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 4344181105 ps |
| CPU time | 337.03 seconds |
| Started | Jul 20 07:28:06 PM PDT 24 |
| Finished | Jul 20 07:33:43 PM PDT 24 |
| Peak memory | 599644 kb |
| Host | smart-bf63130b-31a4-4aa5-9a34-c86fcf0ff3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855620616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.2855620616 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.959831349 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 940062857 ps |
| CPU time | 84.45 seconds |
| Started | Jul 20 07:28:12 PM PDT 24 |
| Finished | Jul 20 07:29:37 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-1c725158-8d6c-4b85-9dbf-f6d56996194a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959831349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device. 959831349 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3076189113 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 16156865794 ps |
| CPU time | 281.82 seconds |
| Started | Jul 20 07:28:12 PM PDT 24 |
| Finished | Jul 20 07:32:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-270c6f8e-b2c1-40ef-ada6-d11e4b840b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076189113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3076189113 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.1839698003 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 481345350 ps |
| CPU time | 20.43 seconds |
| Started | Jul 20 07:28:22 PM PDT 24 |
| Finished | Jul 20 07:28:43 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-85ef0606-b6ba-4565-81a2-13cd77d6eb03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839698003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.1839698003 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.1518968418 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 1784299572 ps |
| CPU time | 62.97 seconds |
| Started | Jul 20 07:28:11 PM PDT 24 |
| Finished | Jul 20 07:29:15 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-1ac98fdf-caf6-4cf2-8ed3-8faffd97fefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518968418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1518968418 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.17106284 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 551437276 ps |
| CPU time | 43.18 seconds |
| Started | Jul 20 07:28:09 PM PDT 24 |
| Finished | Jul 20 07:28:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-8948d807-3870-4b81-8d97-556e1355b17d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.17106284 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.725110903 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 71857314865 ps |
| CPU time | 867 seconds |
| Started | Jul 20 07:28:11 PM PDT 24 |
| Finished | Jul 20 07:42:39 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-3e3b0d52-98d1-403e-8ceb-704cc7f0c7ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725110903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.725110903 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.2702812723 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 33892499032 ps |
| CPU time | 618.97 seconds |
| Started | Jul 20 07:28:11 PM PDT 24 |
| Finished | Jul 20 07:38:30 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-3da202bc-4bd1-42e1-a258-20ce2af47969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702812723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.2702812723 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.1253763789 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 257401009 ps |
| CPU time | 23.71 seconds |
| Started | Jul 20 07:28:05 PM PDT 24 |
| Finished | Jul 20 07:28:30 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-54a05d0d-0114-49fc-8ad9-a3f9daf0a27e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253763789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.1253763789 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1251031673 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 356727820 ps |
| CPU time | 28 seconds |
| Started | Jul 20 07:28:12 PM PDT 24 |
| Finished | Jul 20 07:28:40 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ed3b2dc1-73b1-4e47-bd52-e3ac0d53275a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251031673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1251031673 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3665535784 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 44772128 ps |
| CPU time | 6.12 seconds |
| Started | Jul 20 07:28:04 PM PDT 24 |
| Finished | Jul 20 07:28:11 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-1cf3aefd-3b5a-4287-9b60-b207808746c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665535784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3665535784 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2589209076 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 6804394197 ps |
| CPU time | 78.23 seconds |
| Started | Jul 20 07:28:04 PM PDT 24 |
| Finished | Jul 20 07:29:23 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-a572fa30-2204-45db-8b20-94433614e67b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589209076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2589209076 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3564451700 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 5664447750 ps |
| CPU time | 92.81 seconds |
| Started | Jul 20 07:28:05 PM PDT 24 |
| Finished | Jul 20 07:29:39 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-035fa40e-b998-43c6-8839-e263c30ee04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564451700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3564451700 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3183101610 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 55541992 ps |
| CPU time | 7.33 seconds |
| Started | Jul 20 07:28:04 PM PDT 24 |
| Finished | Jul 20 07:28:12 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-44b8fd78-d894-4f6d-a9d4-34171dba6657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183101610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3183101610 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.3643650412 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4318798250 ps |
| CPU time | 409.32 seconds |
| Started | Jul 20 07:28:24 PM PDT 24 |
| Finished | Jul 20 07:35:14 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-61f38b78-e493-49d2-b4c4-2a6279d34cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643650412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.3643650412 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.4171841499 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 8632955101 ps |
| CPU time | 307.61 seconds |
| Started | Jul 20 07:28:21 PM PDT 24 |
| Finished | Jul 20 07:33:29 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-52623cf2-e78d-45c6-8667-24c026655241 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171841499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.4171841499 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.2547705466 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 726249031 ps |
| CPU time | 275.97 seconds |
| Started | Jul 20 07:28:22 PM PDT 24 |
| Finished | Jul 20 07:32:59 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-72046dbf-f0a5-4571-8244-5501f2826317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547705466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.2547705466 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3866810201 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 363603792 ps |
| CPU time | 124.24 seconds |
| Started | Jul 20 07:28:22 PM PDT 24 |
| Finished | Jul 20 07:30:27 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-3a8d47b8-73e6-43d3-831d-daab482a1c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866810201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3866810201 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.761734216 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 213690461 ps |
| CPU time | 11.21 seconds |
| Started | Jul 20 07:28:17 PM PDT 24 |
| Finished | Jul 20 07:28:29 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-bcc5ff2c-0386-4d1c-b997-0609d1cc77d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761734216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.761734216 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.1982639263 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 4711620195 ps |
| CPU time | 439.02 seconds |
| Started | Jul 20 07:28:23 PM PDT 24 |
| Finished | Jul 20 07:35:43 PM PDT 24 |
| Peak memory | 598560 kb |
| Host | smart-fe7c3379-ba18-43d5-ab7b-786f3dc89819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982639263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.1982639263 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.3394218573 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 817009905 ps |
| CPU time | 36.99 seconds |
| Started | Jul 20 07:28:30 PM PDT 24 |
| Finished | Jul 20 07:29:07 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-9204caef-47d5-4d27-b33a-d13e30f8846e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394218573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .3394218573 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.721227218 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 10629339939 ps |
| CPU time | 181.92 seconds |
| Started | Jul 20 07:28:31 PM PDT 24 |
| Finished | Jul 20 07:31:33 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-c0aa14cb-ee41-47c5-a433-1081d147bca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721227218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_d evice_slow_rsp.721227218 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.314976634 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 517212804 ps |
| CPU time | 22.91 seconds |
| Started | Jul 20 07:28:38 PM PDT 24 |
| Finished | Jul 20 07:29:01 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a06a3d22-53aa-4d81-85cc-8c4517c4d560 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314976634 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_addr .314976634 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2534070064 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 916704667 ps |
| CPU time | 30.54 seconds |
| Started | Jul 20 07:28:32 PM PDT 24 |
| Finished | Jul 20 07:29:03 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-66da6aae-d664-42a8-a74c-ca4332cc8a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534070064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2534070064 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.732008743 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 1911361959 ps |
| CPU time | 71.79 seconds |
| Started | Jul 20 07:28:29 PM PDT 24 |
| Finished | Jul 20 07:29:41 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-d07ad8d4-14a2-42d0-af1f-fe2e7984a9f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732008743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.732008743 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.4091183982 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 66470556470 ps |
| CPU time | 735.51 seconds |
| Started | Jul 20 07:28:30 PM PDT 24 |
| Finished | Jul 20 07:40:47 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-396a08a9-9941-4932-bfb7-9fc11b9f1f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091183982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.4091183982 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.830321923 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 58685821630 ps |
| CPU time | 992.54 seconds |
| Started | Jul 20 07:28:30 PM PDT 24 |
| Finished | Jul 20 07:45:03 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-2c921806-66fa-43d9-8b83-356a6bcd8964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830321923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.830321923 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.3256364561 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 300949944 ps |
| CPU time | 27.71 seconds |
| Started | Jul 20 07:28:31 PM PDT 24 |
| Finished | Jul 20 07:28:59 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-f4d330b1-cdf3-4224-8226-06b29bb16e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256364561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.3256364561 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1815321570 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 221464483 ps |
| CPU time | 17.37 seconds |
| Started | Jul 20 07:28:29 PM PDT 24 |
| Finished | Jul 20 07:28:47 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-2cfd3f05-279d-4eff-9b29-d0ae285d3a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815321570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1815321570 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.2211775299 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 48393978 ps |
| CPU time | 6.99 seconds |
| Started | Jul 20 07:28:22 PM PDT 24 |
| Finished | Jul 20 07:28:30 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-43238daa-6f67-4be2-b65f-c8f76c2c593c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211775299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.2211775299 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.4239113371 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 6712794425 ps |
| CPU time | 68.51 seconds |
| Started | Jul 20 07:28:24 PM PDT 24 |
| Finished | Jul 20 07:29:33 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-0b9de5f3-b73f-4568-90e2-85789715b078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239113371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.4239113371 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.5069287 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 5941308108 ps |
| CPU time | 101 seconds |
| Started | Jul 20 07:28:22 PM PDT 24 |
| Finished | Jul 20 07:30:04 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f09cfc74-9819-4941-9bc3-1d6ce8f78215 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5069287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.5069287 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3475256899 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 54935355 ps |
| CPU time | 6.68 seconds |
| Started | Jul 20 07:28:24 PM PDT 24 |
| Finished | Jul 20 07:28:32 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-b8212456-785b-45ae-b7a2-f18f9653f18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475256899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.3475256899 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.3065579725 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 1037919138 ps |
| CPU time | 83.79 seconds |
| Started | Jul 20 07:28:38 PM PDT 24 |
| Finished | Jul 20 07:30:03 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-66c97790-e4a2-46ed-bfad-3807c2f6c26d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065579725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.3065579725 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.887777674 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 2026416990 ps |
| CPU time | 147.81 seconds |
| Started | Jul 20 07:28:41 PM PDT 24 |
| Finished | Jul 20 07:31:10 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-239492ea-25ae-4da8-bcc3-56af3a101c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887777674 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.887777674 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4247907918 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 562824248 ps |
| CPU time | 257.26 seconds |
| Started | Jul 20 07:28:36 PM PDT 24 |
| Finished | Jul 20 07:32:54 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b0d3a71d-b4a9-4c45-a2d1-09ab6bc44da4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247907918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.4247907918 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3375490999 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 465161736 ps |
| CPU time | 22.17 seconds |
| Started | Jul 20 07:28:43 PM PDT 24 |
| Finished | Jul 20 07:29:05 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-809a085a-0341-428c-80af-2a0611c36c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375490999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3375490999 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.2824715317 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3394058596 ps |
| CPU time | 137.72 seconds |
| Started | Jul 20 07:28:50 PM PDT 24 |
| Finished | Jul 20 07:31:08 PM PDT 24 |
| Peak memory | 593228 kb |
| Host | smart-d61fa195-a0f0-42c0-bf3b-760fbadc2b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824715317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.2824715317 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.767220268 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 415737099 ps |
| CPU time | 34.34 seconds |
| Started | Jul 20 07:28:47 PM PDT 24 |
| Finished | Jul 20 07:29:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-6504a64a-e428-4723-bad3-0984f625d78e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767220268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 767220268 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3710469852 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 44160954607 ps |
| CPU time | 814.52 seconds |
| Started | Jul 20 07:28:52 PM PDT 24 |
| Finished | Jul 20 07:42:27 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-8439bd62-059e-4881-af25-324520856f62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710469852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3710469852 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.2288474120 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 1100486457 ps |
| CPU time | 42.95 seconds |
| Started | Jul 20 07:28:53 PM PDT 24 |
| Finished | Jul 20 07:29:37 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-68d2f383-59a6-4ea0-828d-dd442e3f2066 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288474120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.2288474120 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2862113148 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 1208765184 ps |
| CPU time | 42.73 seconds |
| Started | Jul 20 07:28:55 PM PDT 24 |
| Finished | Jul 20 07:29:38 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-2276b529-2f27-4728-885d-41b89dc3e13f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862113148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2862113148 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1505589593 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 68124756 ps |
| CPU time | 8.59 seconds |
| Started | Jul 20 07:28:51 PM PDT 24 |
| Finished | Jul 20 07:29:00 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-2a8dd5af-080f-470d-b0d7-a09ac740b436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505589593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1505589593 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3701432600 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 80971120268 ps |
| CPU time | 970.66 seconds |
| Started | Jul 20 07:28:51 PM PDT 24 |
| Finished | Jul 20 07:45:02 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-e4f99c7e-3703-4dc5-8d19-2991660c4b3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701432600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3701432600 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1172263968 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 38350302594 ps |
| CPU time | 678.26 seconds |
| Started | Jul 20 07:28:49 PM PDT 24 |
| Finished | Jul 20 07:40:07 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-7e8fde54-e731-4117-b73c-7d68972f789f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172263968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1172263968 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3452050286 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 455879393 ps |
| CPU time | 44.6 seconds |
| Started | Jul 20 07:28:47 PM PDT 24 |
| Finished | Jul 20 07:29:32 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-60264537-f87c-480d-8bea-c95751399e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452050286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3452050286 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.1419514607 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 521216837 ps |
| CPU time | 40.95 seconds |
| Started | Jul 20 07:28:46 PM PDT 24 |
| Finished | Jul 20 07:29:28 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a79c8e6c-3821-4428-b30f-441a3238fc39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419514607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.1419514607 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.210166021 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 183717234 ps |
| CPU time | 8.92 seconds |
| Started | Jul 20 07:28:45 PM PDT 24 |
| Finished | Jul 20 07:28:55 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-04b871fb-d2a9-4425-9390-96bb7abb55a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210166021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.210166021 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2570556761 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 7880805949 ps |
| CPU time | 91.57 seconds |
| Started | Jul 20 07:28:44 PM PDT 24 |
| Finished | Jul 20 07:30:16 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-2dc5d532-51f4-4b64-9676-c3c624479c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570556761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2570556761 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2002372391 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 4510889360 ps |
| CPU time | 75.4 seconds |
| Started | Jul 20 07:28:47 PM PDT 24 |
| Finished | Jul 20 07:30:03 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-7b34575e-10f2-41a2-b459-9ee6c4c7cca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002372391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2002372391 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3698890584 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 45607836 ps |
| CPU time | 6 seconds |
| Started | Jul 20 07:28:47 PM PDT 24 |
| Finished | Jul 20 07:28:53 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-16af9c07-707f-415f-9e37-9004388264a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698890584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3698890584 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.356495675 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 481115481 ps |
| CPU time | 59.88 seconds |
| Started | Jul 20 07:28:52 PM PDT 24 |
| Finished | Jul 20 07:29:53 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-5beefd3d-7bcb-4488-8b84-cda63e357574 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356495675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.356495675 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.576416224 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 705052474 ps |
| CPU time | 56.71 seconds |
| Started | Jul 20 07:29:01 PM PDT 24 |
| Finished | Jul 20 07:29:58 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-53833c2f-afaf-4913-9521-42cad7eb28f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576416224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.576416224 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2979534188 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 12182663263 ps |
| CPU time | 691.32 seconds |
| Started | Jul 20 07:28:53 PM PDT 24 |
| Finished | Jul 20 07:40:25 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e199ad0a-82de-4d01-abf9-f745f1a09ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979534188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.2979534188 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1317959819 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 5221510119 ps |
| CPU time | 281.29 seconds |
| Started | Jul 20 07:29:01 PM PDT 24 |
| Finished | Jul 20 07:33:43 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-8aa48717-76ce-4f13-8542-729580175873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317959819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1317959819 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1288289667 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 860316146 ps |
| CPU time | 37.66 seconds |
| Started | Jul 20 07:28:52 PM PDT 24 |
| Finished | Jul 20 07:29:31 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-76719287-7367-42b1-b030-323aa3cebf5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288289667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1288289667 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.475171411 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 505597273 ps |
| CPU time | 39.56 seconds |
| Started | Jul 20 07:29:08 PM PDT 24 |
| Finished | Jul 20 07:29:48 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-fb6dc89a-66f9-405f-b174-6bdb5d063d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475171411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device. 475171411 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.3206501744 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 26136296 ps |
| CPU time | 5.36 seconds |
| Started | Jul 20 07:29:09 PM PDT 24 |
| Finished | Jul 20 07:29:15 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-a3648db7-f95c-4109-8a69-8fd91aef7e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206501744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.3206501744 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.537254810 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 481680668 ps |
| CPU time | 32.99 seconds |
| Started | Jul 20 07:29:10 PM PDT 24 |
| Finished | Jul 20 07:29:44 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-24931cb9-092e-409f-96e0-7660a56bc269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537254810 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.537254810 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.790636460 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 414850481 ps |
| CPU time | 15.85 seconds |
| Started | Jul 20 07:29:03 PM PDT 24 |
| Finished | Jul 20 07:29:20 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-98bbffc5-916a-46b0-97d3-053418680fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790636460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.790636460 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.1036097518 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 62812401438 ps |
| CPU time | 641.75 seconds |
| Started | Jul 20 07:29:09 PM PDT 24 |
| Finished | Jul 20 07:39:52 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-d82ee9e2-3947-47a4-abbe-90291c16b2ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036097518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.1036097518 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.1973721095 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 37012287336 ps |
| CPU time | 692.91 seconds |
| Started | Jul 20 07:29:08 PM PDT 24 |
| Finished | Jul 20 07:40:41 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-7fb4851a-1500-49cf-bc63-413d30ee5377 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973721095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.1973721095 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.4287798202 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 470959000 ps |
| CPU time | 41.55 seconds |
| Started | Jul 20 07:29:09 PM PDT 24 |
| Finished | Jul 20 07:29:51 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-8b683fbd-82fa-4353-bc80-095ea083d585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287798202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.4287798202 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.3992086512 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 203374708 ps |
| CPU time | 9.47 seconds |
| Started | Jul 20 07:29:08 PM PDT 24 |
| Finished | Jul 20 07:29:18 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-7472eb81-b2e9-4c30-9291-3d3cdf5a3ef2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992086512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.3992086512 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2650669420 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 181388042 ps |
| CPU time | 8.75 seconds |
| Started | Jul 20 07:29:01 PM PDT 24 |
| Finished | Jul 20 07:29:11 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-980731bd-22f2-4d97-b58d-9889452cce44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650669420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2650669420 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3626742448 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 7052415040 ps |
| CPU time | 75.47 seconds |
| Started | Jul 20 07:29:06 PM PDT 24 |
| Finished | Jul 20 07:30:22 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-adc5798a-3fae-4073-ad36-f3634d389198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626742448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3626742448 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.1212840437 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 2981629794 ps |
| CPU time | 51.98 seconds |
| Started | Jul 20 07:29:02 PM PDT 24 |
| Finished | Jul 20 07:29:55 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-5a9ec7f6-c337-4e20-875d-57880b5a1196 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212840437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.1212840437 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.1833192838 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 43051824 ps |
| CPU time | 5.79 seconds |
| Started | Jul 20 07:29:05 PM PDT 24 |
| Finished | Jul 20 07:29:12 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-617a1f0a-08da-4914-a01e-8f1a88290bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833192838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.1833192838 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.2112434289 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 10329719835 ps |
| CPU time | 419.96 seconds |
| Started | Jul 20 07:29:09 PM PDT 24 |
| Finished | Jul 20 07:36:10 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-f0743ad4-46cd-478f-ba63-a86ae2942dea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112434289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.2112434289 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3343035632 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 13596833775 ps |
| CPU time | 485.4 seconds |
| Started | Jul 20 07:29:16 PM PDT 24 |
| Finished | Jul 20 07:37:22 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-352943bb-d276-4093-a197-637cfc928f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343035632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3343035632 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.676295551 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 5055773212 ps |
| CPU time | 642.22 seconds |
| Started | Jul 20 07:29:16 PM PDT 24 |
| Finished | Jul 20 07:39:59 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-33b01e66-047b-439b-ab7a-27eb2dcdbbe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676295551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_ with_rand_reset.676295551 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3295870771 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 4403284599 ps |
| CPU time | 369.83 seconds |
| Started | Jul 20 07:29:15 PM PDT 24 |
| Finished | Jul 20 07:35:26 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-f8914a52-88e0-4f35-bee0-3f7741e28c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295870771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3295870771 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.2325924199 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 167907149 ps |
| CPU time | 19.65 seconds |
| Started | Jul 20 07:29:09 PM PDT 24 |
| Finished | Jul 20 07:29:30 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-0507aa83-f054-4bb0-ac1f-04a02c2f2f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325924199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.2325924199 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.2156659804 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 28798860497 ps |
| CPU time | 4654.6 seconds |
| Started | Jul 20 07:22:25 PM PDT 24 |
| Finished | Jul 20 08:40:02 PM PDT 24 |
| Peak memory | 593988 kb |
| Host | smart-c091c652-7ad1-4815-8d1c-471bb33ca85a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156659804 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.2156659804 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.355107773 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 10744277338 ps |
| CPU time | 1534.72 seconds |
| Started | Jul 20 07:22:21 PM PDT 24 |
| Finished | Jul 20 07:47:57 PM PDT 24 |
| Peak memory | 592696 kb |
| Host | smart-60027112-c896-40db-8db1-ea34b0b5149d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355107773 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.355107773 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2066276002 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4942469070 ps |
| CPU time | 256.57 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:26:53 PM PDT 24 |
| Peak memory | 662384 kb |
| Host | smart-8d8bdcde-4b53-4e13-970a-2b7d62b6237d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066276002 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2066276002 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3341431299 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 5423047268 ps |
| CPU time | 432.58 seconds |
| Started | Jul 20 07:22:33 PM PDT 24 |
| Finished | Jul 20 07:29:47 PM PDT 24 |
| Peak memory | 640360 kb |
| Host | smart-6d6345f0-4fbd-4127-a585-4b15c256a7b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341431299 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3341431299 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.286280145 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 3896777800 ps |
| CPU time | 311.62 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:27:49 PM PDT 24 |
| Peak memory | 596968 kb |
| Host | smart-15fac227-0976-45eb-b920-342e0a19fe9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286280145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.286280145 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3693620734 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 16604649704 ps |
| CPU time | 2230.15 seconds |
| Started | Jul 20 07:22:22 PM PDT 24 |
| Finished | Jul 20 07:59:34 PM PDT 24 |
| Peak memory | 592856 kb |
| Host | smart-a0af4c23-d121-40fb-99ff-6106cfa13d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693620734 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.3693620734 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.3070349378 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 4761109564 ps |
| CPU time | 409.11 seconds |
| Started | Jul 20 07:22:27 PM PDT 24 |
| Finished | Jul 20 07:29:17 PM PDT 24 |
| Peak memory | 599668 kb |
| Host | smart-082f2e52-c6c6-402a-b17a-df70aa1baa07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070349378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3070349378 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1216141204 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 72864451571 ps |
| CPU time | 1219.96 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:42:54 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-4cfe5b7e-abbf-4719-9288-5b0051e20e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216141204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.1216141204 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1365271648 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 1272586292 ps |
| CPU time | 51.98 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:23:26 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-6da4b1b2-8cd0-4620-bde8-b1566108570d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365271648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .1365271648 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3845789887 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 1873889132 ps |
| CPU time | 69.13 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:23:40 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-7ae09130-ec98-4194-bdf8-761e2c1d93c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845789887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3845789887 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.10140581 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 563223150 ps |
| CPU time | 47.67 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:23:27 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-d0e303d0-bced-41e0-81a2-2816e2d08892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10140581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.10140581 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.4083103041 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 71451000899 ps |
| CPU time | 788.53 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:35:41 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-3ca36ca4-e88d-4bf5-9b66-b634ed613301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083103041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.4083103041 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.1513013166 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 58460437240 ps |
| CPU time | 1017.13 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:39:33 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-849cf8bf-20ab-4537-bdd2-a20af9424e93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513013166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.1513013166 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.3308682043 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 380283544 ps |
| CPU time | 33.67 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:23:11 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-9083a02c-3b2b-4a5b-a68d-5e114f9377bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308682043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.3308682043 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.713902586 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 707104943 ps |
| CPU time | 21.76 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:22:55 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-8a65ae1d-dc7e-4eb2-adb3-79b595819dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713902586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.713902586 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3282749241 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 215112384 ps |
| CPU time | 9.14 seconds |
| Started | Jul 20 07:22:20 PM PDT 24 |
| Finished | Jul 20 07:22:30 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-8f633081-3bee-46e8-b51e-d6b34436a701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282749241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3282749241 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2351896541 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 8152924565 ps |
| CPU time | 90.55 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:24:04 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-2eddd006-0355-4421-b00b-a8df51dce2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351896541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2351896541 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.4263178700 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 4016286911 ps |
| CPU time | 69.85 seconds |
| Started | Jul 20 07:22:33 PM PDT 24 |
| Finished | Jul 20 07:23:45 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1352a2e7-1262-43d9-b812-dbb211142c8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263178700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.4263178700 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1733399699 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 45388650 ps |
| CPU time | 6.47 seconds |
| Started | Jul 20 07:22:29 PM PDT 24 |
| Finished | Jul 20 07:22:36 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-69fa6792-b974-4620-831e-5915ab88b990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733399699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1733399699 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.3254463462 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 6005220 ps |
| CPU time | 3.64 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:22:44 PM PDT 24 |
| Peak memory | 565744 kb |
| Host | smart-1a8bafba-19ea-4ee0-a15a-027eaf480de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254463462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3254463462 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3839685596 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 8924226104 ps |
| CPU time | 339.34 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:28:15 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-224d3117-4c89-44bd-b509-746bfa4af30c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839685596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3839685596 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3388283074 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 2508311381 ps |
| CPU time | 449.55 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:30:06 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-ac99cbde-8657-42f6-b0e4-c5dd720a3932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388283074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.3388283074 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2081313762 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 262847897 ps |
| CPU time | 16.43 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:22:48 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-b26e08b5-3586-418b-be2c-62fb8d3ed033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081313762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2081313762 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.620999142 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 514305847 ps |
| CPU time | 39.12 seconds |
| Started | Jul 20 07:29:27 PM PDT 24 |
| Finished | Jul 20 07:30:07 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-c1a41724-951a-4e57-b026-4d372a45954c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620999142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 620999142 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.699337246 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 1381719659 ps |
| CPU time | 56.64 seconds |
| Started | Jul 20 07:29:23 PM PDT 24 |
| Finished | Jul 20 07:30:21 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-12ea139c-ece8-47e9-8d46-afdaa446fbf3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699337246 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_addr .699337246 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.4009390960 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 1228325749 ps |
| CPU time | 44.43 seconds |
| Started | Jul 20 07:29:23 PM PDT 24 |
| Finished | Jul 20 07:30:09 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-1da714af-fe83-4907-aacd-868755e590f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009390960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.4009390960 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.3473070218 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 740118406 ps |
| CPU time | 30.71 seconds |
| Started | Jul 20 07:29:17 PM PDT 24 |
| Finished | Jul 20 07:29:49 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-6e579df0-45b2-4720-a679-83bf18e26878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473070218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.3473070218 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2635578349 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 33501492564 ps |
| CPU time | 371.88 seconds |
| Started | Jul 20 07:29:18 PM PDT 24 |
| Finished | Jul 20 07:35:31 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-4c05a63f-c90d-4159-ba15-dbdf17604798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635578349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2635578349 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.575433709 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 32399399047 ps |
| CPU time | 572.93 seconds |
| Started | Jul 20 07:29:18 PM PDT 24 |
| Finished | Jul 20 07:38:52 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-dd40269a-814b-46c4-b1de-39bfaf74fcf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575433709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.575433709 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2564057423 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 41918403 ps |
| CPU time | 5.83 seconds |
| Started | Jul 20 07:29:15 PM PDT 24 |
| Finished | Jul 20 07:29:21 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-d04aeb49-5d6b-4dfd-98df-1b24fd73e724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564057423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2564057423 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2543303444 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 2047832937 ps |
| CPU time | 67.11 seconds |
| Started | Jul 20 07:29:24 PM PDT 24 |
| Finished | Jul 20 07:30:32 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c1e6480d-f71c-4c03-8a42-c55deecc226f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543303444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2543303444 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.4239025508 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 47421450 ps |
| CPU time | 6.36 seconds |
| Started | Jul 20 07:29:17 PM PDT 24 |
| Finished | Jul 20 07:29:24 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-486fe88c-5523-4654-9e6f-f2afe18cb37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239025508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.4239025508 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.2851989697 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 5172613078 ps |
| CPU time | 59.24 seconds |
| Started | Jul 20 07:29:18 PM PDT 24 |
| Finished | Jul 20 07:30:18 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-9bbcae54-4018-4ae5-9676-16d510b3e3a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851989697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.2851989697 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3898058043 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 5934984555 ps |
| CPU time | 110.86 seconds |
| Started | Jul 20 07:29:17 PM PDT 24 |
| Finished | Jul 20 07:31:09 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-b539472e-13d1-42b6-97b0-ff2577897c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898058043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3898058043 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2976418961 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 41731228 ps |
| CPU time | 6.47 seconds |
| Started | Jul 20 07:29:16 PM PDT 24 |
| Finished | Jul 20 07:29:24 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-ae992f5f-a5e5-47de-853b-0be4e1889b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976418961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2976418961 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.3968181562 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 873807984 ps |
| CPU time | 72.33 seconds |
| Started | Jul 20 07:29:25 PM PDT 24 |
| Finished | Jul 20 07:30:38 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-414bebda-40b5-443e-8233-533d64b41850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968181562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.3968181562 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.649797154 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 21853113464 ps |
| CPU time | 753.88 seconds |
| Started | Jul 20 07:29:26 PM PDT 24 |
| Finished | Jul 20 07:42:00 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-51fb04ec-d22f-4d05-876b-d00a32d3bde4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649797154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.649797154 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.410232859 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 651501325 ps |
| CPU time | 303.36 seconds |
| Started | Jul 20 07:29:23 PM PDT 24 |
| Finished | Jul 20 07:34:28 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-46e53fc8-6914-4aa7-8fa5-f437eecaca0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410232859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_ with_rand_reset.410232859 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1609147782 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 514934878 ps |
| CPU time | 182.39 seconds |
| Started | Jul 20 07:29:25 PM PDT 24 |
| Finished | Jul 20 07:32:28 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-36e2dccc-72a3-4179-a4f0-99f1c223cc8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609147782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.1609147782 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.4001067660 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 104203661 ps |
| CPU time | 14.29 seconds |
| Started | Jul 20 07:29:22 PM PDT 24 |
| Finished | Jul 20 07:29:38 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1a47a4e2-362a-47bd-885e-71ad778614da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001067660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.4001067660 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.4079465079 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2388053248 ps |
| CPU time | 98.79 seconds |
| Started | Jul 20 07:29:37 PM PDT 24 |
| Finished | Jul 20 07:31:16 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-c068197d-3d38-486c-af7d-22d530ed5d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079465079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .4079465079 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1587080663 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 332602845 ps |
| CPU time | 40.78 seconds |
| Started | Jul 20 07:29:43 PM PDT 24 |
| Finished | Jul 20 07:30:24 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-e319a886-410a-4991-b692-60d5f508caf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587080663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1587080663 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1728336067 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 412610042 ps |
| CPU time | 35.24 seconds |
| Started | Jul 20 07:29:33 PM PDT 24 |
| Finished | Jul 20 07:30:09 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a6fab489-095d-4669-858e-34a169003d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728336067 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1728336067 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2234251541 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 449187616 ps |
| CPU time | 40.84 seconds |
| Started | Jul 20 07:29:37 PM PDT 24 |
| Finished | Jul 20 07:30:19 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-0e1ab6c2-1b70-4301-88c8-d287ddb1aba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234251541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2234251541 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3375634370 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 13365896408 ps |
| CPU time | 147.96 seconds |
| Started | Jul 20 07:29:33 PM PDT 24 |
| Finished | Jul 20 07:32:01 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-f4e33678-befc-41f0-8560-5d5c6525dadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375634370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3375634370 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1939429200 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 58893411649 ps |
| CPU time | 1017.17 seconds |
| Started | Jul 20 07:29:32 PM PDT 24 |
| Finished | Jul 20 07:46:30 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-32b833bd-8bee-4218-be73-2d9f2d7125f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939429200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1939429200 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.703762682 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 343916193 ps |
| CPU time | 30.02 seconds |
| Started | Jul 20 07:29:32 PM PDT 24 |
| Finished | Jul 20 07:30:02 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-bf761a1c-d200-42cd-85af-f78fc27d3713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703762682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_dela ys.703762682 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1062170741 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 344582660 ps |
| CPU time | 27.6 seconds |
| Started | Jul 20 07:29:32 PM PDT 24 |
| Finished | Jul 20 07:30:01 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-443226fb-8c5d-40c1-9c81-a1c2837c3325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062170741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1062170741 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.2567935263 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 233336412 ps |
| CPU time | 10.31 seconds |
| Started | Jul 20 07:29:23 PM PDT 24 |
| Finished | Jul 20 07:29:35 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-9ef4dcb2-6afc-40e4-9885-aed6a4da0bd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567935263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.2567935263 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.255443325 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 9185467270 ps |
| CPU time | 106.32 seconds |
| Started | Jul 20 07:29:24 PM PDT 24 |
| Finished | Jul 20 07:31:12 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-f10c782c-3205-4436-8c5e-36718c305d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255443325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.255443325 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.3539319730 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 3157875093 ps |
| CPU time | 57.44 seconds |
| Started | Jul 20 07:29:25 PM PDT 24 |
| Finished | Jul 20 07:30:23 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-9fc59633-8159-4132-80a3-ec5a4ff3e252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539319730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.3539319730 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.3412043297 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 48223174 ps |
| CPU time | 6.32 seconds |
| Started | Jul 20 07:29:25 PM PDT 24 |
| Finished | Jul 20 07:29:32 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-cd02cac9-37e5-4eef-b893-efd2547fac9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412043297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.3412043297 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.2336221525 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 68239148 ps |
| CPU time | 10.84 seconds |
| Started | Jul 20 07:29:41 PM PDT 24 |
| Finished | Jul 20 07:29:53 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-361afa36-3271-4467-9bbf-2fe8901006fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336221525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.2336221525 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3621901822 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 2347734863 ps |
| CPU time | 198.23 seconds |
| Started | Jul 20 07:29:41 PM PDT 24 |
| Finished | Jul 20 07:33:00 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-74c5957f-989a-4efb-a881-3b2566f460d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621901822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3621901822 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.987711670 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 3968318753 ps |
| CPU time | 435.21 seconds |
| Started | Jul 20 07:29:42 PM PDT 24 |
| Finished | Jul 20 07:36:58 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-139c2c67-91ec-4eb7-a7e7-44c0d3f7f085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987711670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.987711670 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.4014500428 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 431421762 ps |
| CPU time | 116.65 seconds |
| Started | Jul 20 07:29:42 PM PDT 24 |
| Finished | Jul 20 07:31:40 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a011c10e-ed6c-4cff-9b4f-3a0ee71f251e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014500428 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.4014500428 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.4039622571 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 610587220 ps |
| CPU time | 27.25 seconds |
| Started | Jul 20 07:29:32 PM PDT 24 |
| Finished | Jul 20 07:30:00 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-279abb93-4cbe-49d2-a9c1-22b05a882d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039622571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.4039622571 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.521306070 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 1921653018 ps |
| CPU time | 79.74 seconds |
| Started | Jul 20 07:29:50 PM PDT 24 |
| Finished | Jul 20 07:31:11 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-af3c6d10-3330-47f8-9c07-6f37b50cf8c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521306070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 521306070 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1947005060 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 91482205767 ps |
| CPU time | 1679.7 seconds |
| Started | Jul 20 07:29:50 PM PDT 24 |
| Finished | Jul 20 07:57:50 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-4a080984-64f3-4602-9c40-30c4618669f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947005060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1947005060 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.2090753417 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 924809526 ps |
| CPU time | 34.33 seconds |
| Started | Jul 20 07:29:52 PM PDT 24 |
| Finished | Jul 20 07:30:27 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-43b8b525-dc15-4d2c-adf0-e115936311cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090753417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.2090753417 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1045034664 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 751291716 ps |
| CPU time | 25.73 seconds |
| Started | Jul 20 07:29:49 PM PDT 24 |
| Finished | Jul 20 07:30:15 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-183b27c0-0925-44b9-8396-358c8a1aa7e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045034664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1045034664 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.3435332178 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 2493737571 ps |
| CPU time | 100.14 seconds |
| Started | Jul 20 07:29:41 PM PDT 24 |
| Finished | Jul 20 07:31:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-18373ba4-6fc0-466b-9ad5-75a8b2e33c5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435332178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.3435332178 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.513753750 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 106171741717 ps |
| CPU time | 1209.38 seconds |
| Started | Jul 20 07:29:50 PM PDT 24 |
| Finished | Jul 20 07:50:01 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-2ce9edc1-dd17-46f1-8397-269a8058c878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513753750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.513753750 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.27208564 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 67919437222 ps |
| CPU time | 1201.82 seconds |
| Started | Jul 20 07:29:48 PM PDT 24 |
| Finished | Jul 20 07:49:51 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-9859ecb9-d464-4988-8609-cf8735c31ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27208564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.27208564 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.394026491 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 273353523 ps |
| CPU time | 26.2 seconds |
| Started | Jul 20 07:29:41 PM PDT 24 |
| Finished | Jul 20 07:30:08 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c4cda964-6b4c-45c0-b067-caadc451d8e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394026491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.394026491 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.1921947069 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 385587210 ps |
| CPU time | 14.83 seconds |
| Started | Jul 20 07:29:51 PM PDT 24 |
| Finished | Jul 20 07:30:06 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-6b2f8c76-7fa8-462d-880e-a7cb883a7e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921947069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1921947069 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.2648457635 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 253938757 ps |
| CPU time | 10.88 seconds |
| Started | Jul 20 07:29:40 PM PDT 24 |
| Finished | Jul 20 07:29:52 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-3e0b60ab-18a8-4fd6-87b0-bccdec9feea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648457635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.2648457635 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.1188683578 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 8269996744 ps |
| CPU time | 90.14 seconds |
| Started | Jul 20 07:29:42 PM PDT 24 |
| Finished | Jul 20 07:31:13 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-ee5b89c1-54f2-4acf-b50a-9b4484919c4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188683578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.1188683578 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.268220790 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 4952423456 ps |
| CPU time | 86.24 seconds |
| Started | Jul 20 07:29:43 PM PDT 24 |
| Finished | Jul 20 07:31:10 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-e025b973-36ba-405d-8c3f-0d5e7934f006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268220790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.268220790 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3403614979 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 44584515 ps |
| CPU time | 6.53 seconds |
| Started | Jul 20 07:29:40 PM PDT 24 |
| Finished | Jul 20 07:29:48 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-b3c1afaa-e2c4-4407-a23b-6c03055a67fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403614979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3403614979 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1166051309 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1298687889 ps |
| CPU time | 45.83 seconds |
| Started | Jul 20 07:29:49 PM PDT 24 |
| Finished | Jul 20 07:30:36 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-0c6ace32-e9c2-4678-872e-77b730e667a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166051309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1166051309 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.1252638859 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 76216439 ps |
| CPU time | 75.35 seconds |
| Started | Jul 20 07:29:49 PM PDT 24 |
| Finished | Jul 20 07:31:05 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-97ac6473-51f6-477e-800e-31649c7253b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252638859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.1252638859 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3278349014 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 12635488264 ps |
| CPU time | 506.97 seconds |
| Started | Jul 20 07:29:51 PM PDT 24 |
| Finished | Jul 20 07:38:18 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-318bebb3-6057-48c3-bac3-fe936205bb61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278349014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3278349014 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.2924383903 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 59668996 ps |
| CPU time | 9.76 seconds |
| Started | Jul 20 07:29:49 PM PDT 24 |
| Finished | Jul 20 07:30:00 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-29411ee8-8cc0-441c-a103-78c63daf37ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924383903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.2924383903 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2476890851 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 474737351 ps |
| CPU time | 43.39 seconds |
| Started | Jul 20 07:29:55 PM PDT 24 |
| Finished | Jul 20 07:30:39 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-315ffbf2-70ed-4a86-bfcb-8e69288599a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476890851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .2476890851 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.699516795 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 137040569552 ps |
| CPU time | 2419.46 seconds |
| Started | Jul 20 07:29:59 PM PDT 24 |
| Finished | Jul 20 08:10:20 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-93d686c4-304a-4574-b239-ad416b674391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699516795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_d evice_slow_rsp.699516795 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1119777664 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 148158931 ps |
| CPU time | 16 seconds |
| Started | Jul 20 07:30:02 PM PDT 24 |
| Finished | Jul 20 07:30:19 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-4df1c26b-ae65-4706-ac70-42f85d59f3c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119777664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1119777664 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.3046406575 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 1953113615 ps |
| CPU time | 61.68 seconds |
| Started | Jul 20 07:29:54 PM PDT 24 |
| Finished | Jul 20 07:30:56 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-6c84c3a2-6c02-4f1e-b3ba-f6d8cf4ded35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046406575 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.3046406575 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.2357698511 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 1902079901 ps |
| CPU time | 61.23 seconds |
| Started | Jul 20 07:29:56 PM PDT 24 |
| Finished | Jul 20 07:30:58 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-add25787-6569-47d0-aed1-0b74fa40d29d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357698511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2357698511 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.1600789313 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 116621713809 ps |
| CPU time | 1303.22 seconds |
| Started | Jul 20 07:29:55 PM PDT 24 |
| Finished | Jul 20 07:51:39 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ac3e534c-a093-4173-ad10-1822887a14d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600789313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.1600789313 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2713125319 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 51673576174 ps |
| CPU time | 881.55 seconds |
| Started | Jul 20 07:29:59 PM PDT 24 |
| Finished | Jul 20 07:44:41 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-445c1ef2-4f4d-4cbf-b76f-d1ea1d05eeb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713125319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2713125319 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.2207633826 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 481700144 ps |
| CPU time | 45.44 seconds |
| Started | Jul 20 07:29:56 PM PDT 24 |
| Finished | Jul 20 07:30:42 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-f4be4fef-0d99-4b99-9db2-88bf20bac3ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207633826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.2207633826 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.1871568904 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 481836452 ps |
| CPU time | 39.01 seconds |
| Started | Jul 20 07:29:56 PM PDT 24 |
| Finished | Jul 20 07:30:36 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a7b798ad-c687-4894-ae35-1c28782c69db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871568904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.1871568904 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1755873956 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 256040932 ps |
| CPU time | 10.87 seconds |
| Started | Jul 20 07:29:52 PM PDT 24 |
| Finished | Jul 20 07:30:04 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-39c2178d-c16f-4e9e-a01a-cf24a30f056f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755873956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1755873956 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.778123128 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 9627489766 ps |
| CPU time | 106.91 seconds |
| Started | Jul 20 07:29:57 PM PDT 24 |
| Finished | Jul 20 07:31:44 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-7f06e053-c72e-4acd-9008-822e2f8a86a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778123128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.778123128 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.344674802 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 3686914835 ps |
| CPU time | 62.03 seconds |
| Started | Jul 20 07:29:56 PM PDT 24 |
| Finished | Jul 20 07:30:59 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-93df20ca-c208-4d05-86aa-c55a38ec37c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344674802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.344674802 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1068602162 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 42830477 ps |
| CPU time | 5.95 seconds |
| Started | Jul 20 07:29:52 PM PDT 24 |
| Finished | Jul 20 07:29:58 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-0391ddc3-ff29-4424-82cd-616eabdd50ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068602162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1068602162 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.654706849 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 2385382182 ps |
| CPU time | 240.69 seconds |
| Started | Jul 20 07:30:05 PM PDT 24 |
| Finished | Jul 20 07:34:06 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-53d82913-5509-47b5-9a73-e475bb244bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654706849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.654706849 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2180611690 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 3866887965 ps |
| CPU time | 115.4 seconds |
| Started | Jul 20 07:30:03 PM PDT 24 |
| Finished | Jul 20 07:31:59 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-c924ffbb-2da6-4b07-835b-0a880e3a96fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180611690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2180611690 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.4294231257 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 3903543246 ps |
| CPU time | 364.76 seconds |
| Started | Jul 20 07:30:03 PM PDT 24 |
| Finished | Jul 20 07:36:09 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-36c9e9a5-597c-4736-b7ec-4cbaed31a2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294231257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.4294231257 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.229634085 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 405976035 ps |
| CPU time | 18.64 seconds |
| Started | Jul 20 07:30:03 PM PDT 24 |
| Finished | Jul 20 07:30:23 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-d9540504-c818-4a5c-a672-c50179173455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229634085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.229634085 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1344342029 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 1043318020 ps |
| CPU time | 67.37 seconds |
| Started | Jul 20 07:30:19 PM PDT 24 |
| Finished | Jul 20 07:31:27 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-75f7dece-042c-4c36-918b-7494110fa75f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344342029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1344342029 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.733337760 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 132414383553 ps |
| CPU time | 2480.56 seconds |
| Started | Jul 20 07:30:19 PM PDT 24 |
| Finished | Jul 20 08:11:41 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-0ef3d024-a089-48be-bd3e-f73d78ce1d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733337760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_d evice_slow_rsp.733337760 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.2585729611 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 212350094 ps |
| CPU time | 23.8 seconds |
| Started | Jul 20 07:30:19 PM PDT 24 |
| Finished | Jul 20 07:30:44 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-00c21465-d45e-45bf-8cd5-d82c6c2a223b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585729611 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.2585729611 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3794765182 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 89616943 ps |
| CPU time | 10.46 seconds |
| Started | Jul 20 07:30:18 PM PDT 24 |
| Finished | Jul 20 07:30:29 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-6a6167c1-9099-46cd-ba3e-ea504cb9193a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794765182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3794765182 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.3334986293 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 605514669 ps |
| CPU time | 54.72 seconds |
| Started | Jul 20 07:30:08 PM PDT 24 |
| Finished | Jul 20 07:31:03 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-25b2e211-451b-4340-9783-23f4c6cf2872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334986293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.3334986293 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1621695182 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 117355780505 ps |
| CPU time | 1418.27 seconds |
| Started | Jul 20 07:30:09 PM PDT 24 |
| Finished | Jul 20 07:53:48 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-e85b7e90-51ac-4477-9dcc-3a464caaf7b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621695182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1621695182 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.340820875 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 72852714514 ps |
| CPU time | 1269.75 seconds |
| Started | Jul 20 07:30:13 PM PDT 24 |
| Finished | Jul 20 07:51:24 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-1aba2831-ad7b-499d-838c-2e8d0c745ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340820875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.340820875 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.974902662 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 613275583 ps |
| CPU time | 52.55 seconds |
| Started | Jul 20 07:30:08 PM PDT 24 |
| Finished | Jul 20 07:31:02 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-cacb6081-d820-4ecc-b79a-1c284071c5a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974902662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.974902662 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1976713794 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1617303734 ps |
| CPU time | 46 seconds |
| Started | Jul 20 07:30:18 PM PDT 24 |
| Finished | Jul 20 07:31:04 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-35fad183-8a26-4cc3-8493-d993f116554f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976713794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1976713794 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.1524875173 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 244379887 ps |
| CPU time | 10.02 seconds |
| Started | Jul 20 07:30:13 PM PDT 24 |
| Finished | Jul 20 07:30:24 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-9628cc8b-446a-46d1-893b-75de18636799 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524875173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.1524875173 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2996947705 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 7647465778 ps |
| CPU time | 88.35 seconds |
| Started | Jul 20 07:30:09 PM PDT 24 |
| Finished | Jul 20 07:31:38 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-58021b2a-61ae-41a9-828f-75619ed77133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996947705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2996947705 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.1212204696 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 5003497956 ps |
| CPU time | 77.58 seconds |
| Started | Jul 20 07:30:08 PM PDT 24 |
| Finished | Jul 20 07:31:27 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-e2818344-da86-4f36-832d-8e9794c8c713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212204696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.1212204696 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.1950978768 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 42406352 ps |
| CPU time | 5.95 seconds |
| Started | Jul 20 07:30:09 PM PDT 24 |
| Finished | Jul 20 07:30:15 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-d2de53bc-5d36-4746-bdcf-94f8b5cd432e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950978768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.1950978768 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1083197017 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 9970288007 ps |
| CPU time | 377.21 seconds |
| Started | Jul 20 07:30:17 PM PDT 24 |
| Finished | Jul 20 07:36:35 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-db539877-3471-430c-be4b-b07b00e3967e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083197017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1083197017 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2386959977 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 4348962902 ps |
| CPU time | 151.8 seconds |
| Started | Jul 20 07:30:20 PM PDT 24 |
| Finished | Jul 20 07:32:52 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6a0825e8-3631-4d3c-8b5b-a0701def77b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386959977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2386959977 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1400904963 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 248599680 ps |
| CPU time | 74.84 seconds |
| Started | Jul 20 07:30:19 PM PDT 24 |
| Finished | Jul 20 07:31:35 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-b8ad9b39-e203-43be-a98c-f37a7148ba7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400904963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1400904963 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.2164068455 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 162386029 ps |
| CPU time | 9.71 seconds |
| Started | Jul 20 07:30:18 PM PDT 24 |
| Finished | Jul 20 07:30:28 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-897e3f0e-4dd4-4221-b97d-a49cfd12ebc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164068455 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.2164068455 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.3731022151 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 569773551 ps |
| CPU time | 24.59 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:30:53 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-e2a4a813-9c95-419d-b5bd-4b1433650c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731022151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .3731022151 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1372869502 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 113921970 ps |
| CPU time | 15.14 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:30:43 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-dcc27f41-e3c7-4e79-9e80-b4ecb7b06685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372869502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1372869502 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.981359511 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 1060886468 ps |
| CPU time | 34.04 seconds |
| Started | Jul 20 07:30:38 PM PDT 24 |
| Finished | Jul 20 07:31:12 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-cbe6848c-6779-4463-beea-38865ad0969c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981359511 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.981359511 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.389226816 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 2046629139 ps |
| CPU time | 69.33 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:31:38 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-2b03032b-c188-4979-ba6f-1959cd9b1ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389226816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.389226816 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.539747612 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 22553829864 ps |
| CPU time | 250.56 seconds |
| Started | Jul 20 07:30:25 PM PDT 24 |
| Finished | Jul 20 07:34:37 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-67263551-a17e-47a1-9a85-7e4ea7e50236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539747612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.539747612 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.160624391 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 38356653292 ps |
| CPU time | 712.41 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:42:21 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-9e04cf5a-e0c7-472f-9ec5-f78c9c8f8f34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160624391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.160624391 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.252035526 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 359909974 ps |
| CPU time | 35.6 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:31:04 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-f7971d83-fdc9-48ed-b5bb-dde2cab5b2f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252035526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.252035526 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.2909380637 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 1127955587 ps |
| CPU time | 32.92 seconds |
| Started | Jul 20 07:30:37 PM PDT 24 |
| Finished | Jul 20 07:31:11 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-3f5e4bcb-956c-4e89-a053-70a578d4ed99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909380637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.2909380637 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.2211584968 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 40005086 ps |
| CPU time | 5.27 seconds |
| Started | Jul 20 07:30:28 PM PDT 24 |
| Finished | Jul 20 07:30:34 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-20e0d19b-2a87-4914-90ca-5ac43bdf60ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211584968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.2211584968 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.2387165527 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 8422111750 ps |
| CPU time | 89.56 seconds |
| Started | Jul 20 07:30:37 PM PDT 24 |
| Finished | Jul 20 07:32:08 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-47d24c00-8b68-429a-9290-25c15e6c3459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387165527 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.2387165527 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.891483779 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 3872499678 ps |
| CPU time | 64.07 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:31:31 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-cf72a740-5718-41de-b15d-64703709ae39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891483779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.891483779 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2171051278 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 44866821 ps |
| CPU time | 6.49 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:30:35 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-42b10793-f291-4414-b5ef-be7d2b00500e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171051278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2171051278 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3898933732 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 780962079 ps |
| CPU time | 71.9 seconds |
| Started | Jul 20 07:30:27 PM PDT 24 |
| Finished | Jul 20 07:31:41 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5648e9f7-9bb4-4506-aa90-0b1169d61cf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898933732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3898933732 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.3594881641 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 6714063801 ps |
| CPU time | 280.83 seconds |
| Started | Jul 20 07:30:28 PM PDT 24 |
| Finished | Jul 20 07:35:10 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f3962475-89af-4b46-b90e-3a86719107d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594881641 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.3594881641 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.184291609 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 103939662 ps |
| CPU time | 56.14 seconds |
| Started | Jul 20 07:30:30 PM PDT 24 |
| Finished | Jul 20 07:31:27 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-8c14389a-dfa9-47c5-99f8-140b34886cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184291609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_ with_rand_reset.184291609 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3459758957 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 2145113428 ps |
| CPU time | 254.73 seconds |
| Started | Jul 20 07:30:36 PM PDT 24 |
| Finished | Jul 20 07:34:51 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-99c96682-4c3d-4d9f-abc8-8923d41e7259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459758957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3459758957 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1240008979 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 97575623 ps |
| CPU time | 7.87 seconds |
| Started | Jul 20 07:30:26 PM PDT 24 |
| Finished | Jul 20 07:30:34 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-e6141d6b-5286-4f4f-9da3-3af383873779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240008979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1240008979 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1104438762 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 1019910358 ps |
| CPU time | 38.6 seconds |
| Started | Jul 20 07:30:34 PM PDT 24 |
| Finished | Jul 20 07:31:13 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-303a0438-17da-41e5-8942-723738fedbf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104438762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .1104438762 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2182356664 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 86366795907 ps |
| CPU time | 1640.29 seconds |
| Started | Jul 20 07:30:33 PM PDT 24 |
| Finished | Jul 20 07:57:54 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-f19e28d4-37c1-4972-a93f-dc3014011c50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182356664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2182356664 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2190346416 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 119643500 ps |
| CPU time | 14.55 seconds |
| Started | Jul 20 07:30:36 PM PDT 24 |
| Finished | Jul 20 07:30:51 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-b734088c-c5e8-4524-9a2d-fd50c79cdefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190346416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.2190346416 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.2750341767 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 728854496 ps |
| CPU time | 27.7 seconds |
| Started | Jul 20 07:30:34 PM PDT 24 |
| Finished | Jul 20 07:31:02 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-17cf1bec-cd66-45ad-abe8-ff3dc523218c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750341767 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2750341767 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.2338999230 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 1705588573 ps |
| CPU time | 63.69 seconds |
| Started | Jul 20 07:30:41 PM PDT 24 |
| Finished | Jul 20 07:31:46 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-d7c5209c-4c58-496a-96d7-43c9d812c06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338999230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.2338999230 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.998987491 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 66877174515 ps |
| CPU time | 755.45 seconds |
| Started | Jul 20 07:30:34 PM PDT 24 |
| Finished | Jul 20 07:43:10 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-e6c07fcb-7f35-409a-92d5-29d39efeec0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998987491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.998987491 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.373563359 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 39176392832 ps |
| CPU time | 663.84 seconds |
| Started | Jul 20 07:30:41 PM PDT 24 |
| Finished | Jul 20 07:41:46 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-b4817885-32ff-4267-b27d-5aeef735f8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373563359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.373563359 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.168784830 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 97896765 ps |
| CPU time | 11.16 seconds |
| Started | Jul 20 07:30:41 PM PDT 24 |
| Finished | Jul 20 07:30:53 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-b63637cf-6fb8-4a28-8406-2a07326a99de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168784830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_dela ys.168784830 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.3908587152 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 308965125 ps |
| CPU time | 22.35 seconds |
| Started | Jul 20 07:30:36 PM PDT 24 |
| Finished | Jul 20 07:30:59 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-511d3ec2-f770-4d79-9e3b-bca33b7e5ea8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908587152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.3908587152 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.42745743 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 222549194 ps |
| CPU time | 9.23 seconds |
| Started | Jul 20 07:30:29 PM PDT 24 |
| Finished | Jul 20 07:30:39 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-d6f4d60d-6af6-4997-8084-26ff1ebbc84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42745743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.42745743 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1467397103 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 7767328242 ps |
| CPU time | 88.08 seconds |
| Started | Jul 20 07:30:26 PM PDT 24 |
| Finished | Jul 20 07:31:55 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c85d0526-f981-40c2-9f58-b2477e59d559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467397103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1467397103 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1650040198 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 4695327791 ps |
| CPU time | 81.01 seconds |
| Started | Jul 20 07:30:35 PM PDT 24 |
| Finished | Jul 20 07:31:57 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-e59d0026-cb2d-4bdf-a49a-c347e38d4430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650040198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1650040198 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1423782693 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 55751097 ps |
| CPU time | 7.39 seconds |
| Started | Jul 20 07:30:26 PM PDT 24 |
| Finished | Jul 20 07:30:34 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-2f266a44-6e55-4056-8941-cf7adc54553d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423782693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1423782693 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.1370579532 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 2360076056 ps |
| CPU time | 182.87 seconds |
| Started | Jul 20 07:30:35 PM PDT 24 |
| Finished | Jul 20 07:33:38 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-72f884e4-eacf-4fb3-8716-ea4945ee6d67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370579532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.1370579532 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.4141405861 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2851557296 ps |
| CPU time | 186.98 seconds |
| Started | Jul 20 07:30:35 PM PDT 24 |
| Finished | Jul 20 07:33:42 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-8c33bc7a-8964-4d02-8c6e-e233322afd39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141405861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.4141405861 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1749769885 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 386399811 ps |
| CPU time | 168.08 seconds |
| Started | Jul 20 07:30:42 PM PDT 24 |
| Finished | Jul 20 07:33:31 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-652cbbe8-c122-41ff-a166-f5ac39102d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749769885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1749769885 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3369838133 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 3791205611 ps |
| CPU time | 381 seconds |
| Started | Jul 20 07:30:51 PM PDT 24 |
| Finished | Jul 20 07:37:12 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-85a7930c-a2ae-4901-9ae0-f8669b6fba87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369838133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3369838133 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.4263075468 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 193376196 ps |
| CPU time | 10.82 seconds |
| Started | Jul 20 07:30:37 PM PDT 24 |
| Finished | Jul 20 07:30:48 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-a7a1088d-c357-45cb-91b4-53f9c851fba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263075468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.4263075468 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.4152357656 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 740712861 ps |
| CPU time | 33.65 seconds |
| Started | Jul 20 07:30:51 PM PDT 24 |
| Finished | Jul 20 07:31:25 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1043a44a-4c67-435e-a912-3eeeb736d5e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152357656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .4152357656 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.2352057704 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 50866900490 ps |
| CPU time | 912.16 seconds |
| Started | Jul 20 07:30:52 PM PDT 24 |
| Finished | Jul 20 07:46:05 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-9d69729b-2601-44f5-b61a-62e2673c76da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352057704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.2352057704 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3960991468 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1261530568 ps |
| CPU time | 49.9 seconds |
| Started | Jul 20 07:30:52 PM PDT 24 |
| Finished | Jul 20 07:31:43 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d8ede3cf-a22e-42de-ade0-18530a6dcce6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960991468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3960991468 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.935237028 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 1013981167 ps |
| CPU time | 41.33 seconds |
| Started | Jul 20 07:30:50 PM PDT 24 |
| Finished | Jul 20 07:31:32 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-5b3042da-7763-42a6-91bc-33c4e4940979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935237028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.935237028 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2790134705 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1493304902 ps |
| CPU time | 55.28 seconds |
| Started | Jul 20 07:30:43 PM PDT 24 |
| Finished | Jul 20 07:31:39 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-9775087f-5860-4007-8810-0c56ed613af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790134705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2790134705 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.4169217346 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 14301777808 ps |
| CPU time | 160.9 seconds |
| Started | Jul 20 07:30:55 PM PDT 24 |
| Finished | Jul 20 07:33:36 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-dfacac4e-a795-4610-9c33-3ab9c698111c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169217346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.4169217346 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.1504024687 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 6806409989 ps |
| CPU time | 119.62 seconds |
| Started | Jul 20 07:30:42 PM PDT 24 |
| Finished | Jul 20 07:32:42 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-66b9924b-a8c8-4307-a8d0-8c004e938f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504024687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.1504024687 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3635745301 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 233168727 ps |
| CPU time | 22.6 seconds |
| Started | Jul 20 07:30:48 PM PDT 24 |
| Finished | Jul 20 07:31:11 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-9f0b1146-57c6-4a47-b67d-6c865e819793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635745301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3635745301 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.188364828 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 2365768932 ps |
| CPU time | 62.5 seconds |
| Started | Jul 20 07:30:51 PM PDT 24 |
| Finished | Jul 20 07:31:54 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-4f1cbc89-5d58-4b66-a7ac-e7b9a965fa0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188364828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.188364828 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.3644439566 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 187281608 ps |
| CPU time | 8.43 seconds |
| Started | Jul 20 07:30:41 PM PDT 24 |
| Finished | Jul 20 07:30:50 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-bb23c45b-d232-418c-8bb1-da379f85998d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644439566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.3644439566 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1245699810 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 6832574289 ps |
| CPU time | 73.02 seconds |
| Started | Jul 20 07:30:42 PM PDT 24 |
| Finished | Jul 20 07:31:56 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-163445e2-fa59-4ca8-b65f-1d4f2e99dac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245699810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1245699810 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1833932506 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 4503925516 ps |
| CPU time | 74.51 seconds |
| Started | Jul 20 07:30:47 PM PDT 24 |
| Finished | Jul 20 07:32:02 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-52c03ee2-1caa-43f8-ba5c-9a78a4ea0597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833932506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1833932506 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.113498601 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 50607615 ps |
| CPU time | 6.02 seconds |
| Started | Jul 20 07:30:50 PM PDT 24 |
| Finished | Jul 20 07:30:56 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-d4362d5a-ddbe-4c4b-9439-2697a547c31b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113498601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delays .113498601 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.3021207261 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 4145977403 ps |
| CPU time | 167.02 seconds |
| Started | Jul 20 07:30:49 PM PDT 24 |
| Finished | Jul 20 07:33:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d441eee4-face-45b0-a218-12361d4ae52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021207261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3021207261 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1289035084 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2681903506 ps |
| CPU time | 201.4 seconds |
| Started | Jul 20 07:30:51 PM PDT 24 |
| Finished | Jul 20 07:34:13 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-9554c920-1121-4129-be18-1eedacc4f709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289035084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.1289035084 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.767982669 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 3013396674 ps |
| CPU time | 216.81 seconds |
| Started | Jul 20 07:30:53 PM PDT 24 |
| Finished | Jul 20 07:34:30 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-c1899bb6-d7c7-4c18-b196-d4ed9c8db738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767982669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_ with_rand_reset.767982669 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.192690369 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 7106648 ps |
| CPU time | 7.91 seconds |
| Started | Jul 20 07:30:51 PM PDT 24 |
| Finished | Jul 20 07:30:59 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-05d4fc2c-2938-458e-893c-e6fc24a27923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192690369 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_reset_error.192690369 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1420523236 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 680790748 ps |
| CPU time | 28.88 seconds |
| Started | Jul 20 07:30:52 PM PDT 24 |
| Finished | Jul 20 07:31:22 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-1e747f61-4c60-482e-b7be-730783138eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420523236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1420523236 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1339038031 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 236658643 ps |
| CPU time | 17.08 seconds |
| Started | Jul 20 07:31:00 PM PDT 24 |
| Finished | Jul 20 07:31:18 PM PDT 24 |
| Peak memory | 575216 kb |
| Host | smart-86c8679f-b93d-40a6-bf3a-6c238b04bb36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339038031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1339038031 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3898821604 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 60306242359 ps |
| CPU time | 984.75 seconds |
| Started | Jul 20 07:31:02 PM PDT 24 |
| Finished | Jul 20 07:47:27 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-0c0af6fc-5cc5-4e24-9ca8-dcfcf8c072c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898821604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.3898821604 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.932341874 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 171291454 ps |
| CPU time | 10.09 seconds |
| Started | Jul 20 07:31:04 PM PDT 24 |
| Finished | Jul 20 07:31:14 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-20c93a38-8667-44e2-bfbd-5d3afb5b27b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932341874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr .932341874 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.2764383781 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 2236479929 ps |
| CPU time | 80.74 seconds |
| Started | Jul 20 07:30:59 PM PDT 24 |
| Finished | Jul 20 07:32:21 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-6b4a9b7c-fcf7-435c-86ff-edc8d02f8e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764383781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2764383781 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2321994311 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 1561178675 ps |
| CPU time | 57.47 seconds |
| Started | Jul 20 07:31:03 PM PDT 24 |
| Finished | Jul 20 07:32:01 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-dcca248a-6567-49af-971f-38611f343f91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321994311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2321994311 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.3628341032 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 19183246913 ps |
| CPU time | 232.63 seconds |
| Started | Jul 20 07:30:59 PM PDT 24 |
| Finished | Jul 20 07:34:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-f5cb573b-0a77-49cc-80f7-a88160fd78c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628341032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.3628341032 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.2309057495 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 36670569140 ps |
| CPU time | 673.52 seconds |
| Started | Jul 20 07:31:00 PM PDT 24 |
| Finished | Jul 20 07:42:15 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-12156a8d-8bf3-4442-a252-fc06f85045e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309057495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.2309057495 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.3876199198 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 298164585 ps |
| CPU time | 27.05 seconds |
| Started | Jul 20 07:31:01 PM PDT 24 |
| Finished | Jul 20 07:31:29 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-9f5c0e87-cd46-4345-a26b-faf675da1ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876199198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.3876199198 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3171544238 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 1809895373 ps |
| CPU time | 58.72 seconds |
| Started | Jul 20 07:30:59 PM PDT 24 |
| Finished | Jul 20 07:31:59 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-97782255-de87-4aa5-a966-884fff3d5c30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171544238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3171544238 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3359800153 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 113155212 ps |
| CPU time | 6.83 seconds |
| Started | Jul 20 07:30:54 PM PDT 24 |
| Finished | Jul 20 07:31:01 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-3d8f3d2f-b4fe-427f-b51a-59c458e39309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359800153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3359800153 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2814414403 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 8123294667 ps |
| CPU time | 87.56 seconds |
| Started | Jul 20 07:30:53 PM PDT 24 |
| Finished | Jul 20 07:32:22 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-1335adf9-53ee-4682-9eff-ce7e0788560d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814414403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2814414403 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.992993772 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 5581822966 ps |
| CPU time | 98.88 seconds |
| Started | Jul 20 07:30:53 PM PDT 24 |
| Finished | Jul 20 07:32:33 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c75f612b-c513-4173-a34e-ebeadee182ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992993772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.992993772 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.1887185218 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 46679137 ps |
| CPU time | 6.23 seconds |
| Started | Jul 20 07:30:53 PM PDT 24 |
| Finished | Jul 20 07:31:00 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-019313e7-266c-4dea-b806-24bbeca5482c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887185218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.1887185218 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1680432910 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 742822039 ps |
| CPU time | 59.94 seconds |
| Started | Jul 20 07:30:58 PM PDT 24 |
| Finished | Jul 20 07:31:59 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-4eb52b3c-2123-4990-be14-802ab2833282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680432910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1680432910 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1422393049 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 16594084818 ps |
| CPU time | 645.83 seconds |
| Started | Jul 20 07:31:08 PM PDT 24 |
| Finished | Jul 20 07:41:54 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-1a3d141e-d357-41f3-9d41-6567e44df41e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422393049 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1422393049 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.3313519082 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 25102158 ps |
| CPU time | 14.28 seconds |
| Started | Jul 20 07:31:00 PM PDT 24 |
| Finished | Jul 20 07:31:15 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-bf2bcd3b-1493-4f23-b817-d60f7a9f99f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313519082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.3313519082 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3521534771 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 21403921 ps |
| CPU time | 13.3 seconds |
| Started | Jul 20 07:31:08 PM PDT 24 |
| Finished | Jul 20 07:31:22 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c9cfdf8f-a6df-48ec-9d87-0ff29e193d8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521534771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.3521534771 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3449587062 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 1208814286 ps |
| CPU time | 46.74 seconds |
| Started | Jul 20 07:31:00 PM PDT 24 |
| Finished | Jul 20 07:31:47 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-5c432821-9d46-45fe-8f33-601926cd58b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449587062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3449587062 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2543183352 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 3295430419 ps |
| CPU time | 143.86 seconds |
| Started | Jul 20 07:31:08 PM PDT 24 |
| Finished | Jul 20 07:33:32 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-50ab143d-8e2e-45a2-8198-6023a67a8349 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543183352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .2543183352 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.4153111912 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 63119791562 ps |
| CPU time | 1217.04 seconds |
| Started | Jul 20 07:31:08 PM PDT 24 |
| Finished | Jul 20 07:51:26 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-859fafee-b0e3-49d7-b68a-64d15be40106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153111912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.4153111912 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3567747301 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1280005658 ps |
| CPU time | 51.63 seconds |
| Started | Jul 20 07:31:20 PM PDT 24 |
| Finished | Jul 20 07:32:12 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-7f9f7e79-5e45-43cb-bab6-d6bb4f3d4d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567747301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3567747301 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.3366640384 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 1414210954 ps |
| CPU time | 57.88 seconds |
| Started | Jul 20 07:31:14 PM PDT 24 |
| Finished | Jul 20 07:32:13 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5d835e30-eda2-4e28-ba51-1d4dc6f7c0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366640384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3366640384 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.120121436 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 1464476029 ps |
| CPU time | 50.36 seconds |
| Started | Jul 20 07:31:19 PM PDT 24 |
| Finished | Jul 20 07:32:10 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-7cfcfc31-7879-455c-a31b-4a19606e9ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120121436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.120121436 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.1325749145 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 97082965894 ps |
| CPU time | 1053.82 seconds |
| Started | Jul 20 07:31:11 PM PDT 24 |
| Finished | Jul 20 07:48:46 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-18e9e5e3-e54d-4095-b408-7858909481ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325749145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.1325749145 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.239112932 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 61410239385 ps |
| CPU time | 1075.58 seconds |
| Started | Jul 20 07:31:11 PM PDT 24 |
| Finished | Jul 20 07:49:08 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-0a1662b1-e9ea-450c-9e4f-c3949b173d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239112932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.239112932 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.269085234 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 594063472 ps |
| CPU time | 51.52 seconds |
| Started | Jul 20 07:31:20 PM PDT 24 |
| Finished | Jul 20 07:32:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-a1939c18-bb5e-4ed8-acbf-fcd338c3cc08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269085234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_dela ys.269085234 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3474258500 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 98792210 ps |
| CPU time | 9.56 seconds |
| Started | Jul 20 07:31:18 PM PDT 24 |
| Finished | Jul 20 07:31:28 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-e41a7ae7-f319-48c5-8188-f56f55daf9ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474258500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3474258500 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.547492424 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 102023603 ps |
| CPU time | 6.7 seconds |
| Started | Jul 20 07:31:07 PM PDT 24 |
| Finished | Jul 20 07:31:14 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-22359211-4c3c-497d-a0cf-ec5c47cd645b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547492424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.547492424 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.3996978940 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 7861970593 ps |
| CPU time | 89.15 seconds |
| Started | Jul 20 07:31:10 PM PDT 24 |
| Finished | Jul 20 07:32:39 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-cfe50075-977a-407d-888e-63447aceab4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996978940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.3996978940 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1114675162 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 4146667054 ps |
| CPU time | 72.94 seconds |
| Started | Jul 20 07:31:08 PM PDT 24 |
| Finished | Jul 20 07:32:21 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-bb6e9b42-184a-4b61-9bcb-fab5feae5620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114675162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1114675162 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2086166249 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 41075567 ps |
| CPU time | 6.03 seconds |
| Started | Jul 20 07:31:06 PM PDT 24 |
| Finished | Jul 20 07:31:12 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-87c441aa-696a-48ce-9d2f-0626774e21ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086166249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2086166249 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.1818413828 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 602560274 ps |
| CPU time | 43.72 seconds |
| Started | Jul 20 07:31:15 PM PDT 24 |
| Finished | Jul 20 07:32:00 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-dec71e8c-66ea-427a-9250-75559a19729f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818413828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1818413828 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.1275688270 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 705783496 ps |
| CPU time | 47.88 seconds |
| Started | Jul 20 07:31:14 PM PDT 24 |
| Finished | Jul 20 07:32:02 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-fce40840-85c5-4355-acef-9e9c1d33f513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275688270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1275688270 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2420201688 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 9269460647 ps |
| CPU time | 558.22 seconds |
| Started | Jul 20 07:31:15 PM PDT 24 |
| Finished | Jul 20 07:40:34 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-ab3b3fd1-1087-49a2-938d-35f81d278836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420201688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2420201688 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.400137352 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 8004858470 ps |
| CPU time | 345.63 seconds |
| Started | Jul 20 07:31:21 PM PDT 24 |
| Finished | Jul 20 07:37:07 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-c65824d8-0576-43b8-bd37-ec6ce8b28ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400137352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_reset_error.400137352 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.407184645 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 284862712 ps |
| CPU time | 14.63 seconds |
| Started | Jul 20 07:31:15 PM PDT 24 |
| Finished | Jul 20 07:31:31 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-834bf246-1210-4d44-a846-d565553a53c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407184645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.407184645 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.2583297241 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 34339173372 ps |
| CPU time | 6327.82 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 09:08:03 PM PDT 24 |
| Peak memory | 593912 kb |
| Host | smart-f93d407b-5ec1-4d8a-90bc-19bf19746217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583297241 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.2583297241 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1655274319 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 10716763816 ps |
| CPU time | 1122.9 seconds |
| Started | Jul 20 07:22:36 PM PDT 24 |
| Finished | Jul 20 07:41:20 PM PDT 24 |
| Peak memory | 591780 kb |
| Host | smart-084b7ff4-819a-48bd-87e7-9d9972ad490b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655274319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1655274319 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1343738700 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4063397144 ps |
| CPU time | 177.02 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:25:30 PM PDT 24 |
| Peak memory | 662212 kb |
| Host | smart-6cc69df7-90f3-408b-ace3-dc947115ef82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343738700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.1343738700 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.896994031 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 7590155880 ps |
| CPU time | 409.58 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:29:25 PM PDT 24 |
| Peak memory | 638660 kb |
| Host | smart-7573bbaf-91cf-4155-9179-55e9ea0ae0ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896994031 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.896994031 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.2068216116 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 4147049954 ps |
| CPU time | 303.4 seconds |
| Started | Jul 20 07:22:33 PM PDT 24 |
| Finished | Jul 20 07:27:38 PM PDT 24 |
| Peak memory | 598876 kb |
| Host | smart-905bab99-0bf8-47da-91a1-3b7401fd6f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068216116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.2068216116 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.181072882 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 29350541964 ps |
| CPU time | 4198.34 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 08:32:36 PM PDT 24 |
| Peak memory | 593460 kb |
| Host | smart-2029a187-fc50-4a7c-8340-353c4cbf0f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181072882 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.chip_same_csr_outstanding.181072882 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.3173897135 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 642025771 ps |
| CPU time | 33.86 seconds |
| Started | Jul 20 07:22:29 PM PDT 24 |
| Finished | Jul 20 07:23:03 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-6c075d06-c87e-4a2a-b358-ad2997b8db76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173897135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 3173897135 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.2713518615 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 34885510374 ps |
| CPU time | 629.4 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:33:03 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-4780e9be-073e-4af3-9e3a-d3de2659a7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713518615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.2713518615 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3987949778 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 152957121 ps |
| CPU time | 17.38 seconds |
| Started | Jul 20 07:22:36 PM PDT 24 |
| Finished | Jul 20 07:22:55 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-912067ac-7cb1-443c-bb18-fcc8a505bd1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987949778 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .3987949778 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.4044704020 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 314136835 ps |
| CPU time | 26.02 seconds |
| Started | Jul 20 07:22:29 PM PDT 24 |
| Finished | Jul 20 07:22:56 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-3a631bb3-1752-4e49-a17d-e4debda690b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044704020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.4044704020 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.802696879 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 26891868 ps |
| CPU time | 5.89 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:22:43 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-edcc479a-31b3-486a-a049-b45032572945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802696879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.802696879 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1275466565 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 11283449812 ps |
| CPU time | 121.29 seconds |
| Started | Jul 20 07:22:33 PM PDT 24 |
| Finished | Jul 20 07:24:36 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f66c326b-ecdf-431e-b409-cbc7fac22a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275466565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1275466565 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2587970168 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 18823399632 ps |
| CPU time | 329.74 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:28:07 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-38914d46-2834-456b-8f83-c33b5c2ca654 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587970168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2587970168 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.636104072 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 135240622 ps |
| CPU time | 12.87 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:22:48 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-eb61368b-982f-4f14-98ba-96b752cc2ee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636104072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.636104072 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.206938559 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 1913400153 ps |
| CPU time | 60.88 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:23:31 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-101da741-fd8e-41d1-b330-d600d9e0b62d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206938559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.206938559 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.210233433 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 39114204 ps |
| CPU time | 6.03 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:22:43 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-67cfce6f-8d36-4f6a-b8df-98c5390acfff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210233433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.210233433 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2173863023 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 6311776855 ps |
| CPU time | 67.77 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:23:44 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-b3fa4480-99c6-40c5-b552-09176257a8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173863023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2173863023 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2185517304 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 4974702366 ps |
| CPU time | 80.06 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:23:56 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-8f6303a5-85ed-438b-a225-ac33fac2d24a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185517304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2185517304 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.682207151 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 52920607 ps |
| CPU time | 6.65 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:22:38 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-ca56682e-673e-46bd-a057-fb510f527e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682207151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 682207151 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.419817217 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 13656710590 ps |
| CPU time | 505.39 seconds |
| Started | Jul 20 07:22:32 PM PDT 24 |
| Finished | Jul 20 07:30:59 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a79491fe-7b46-443d-9915-094268c091e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419817217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.419817217 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3550844862 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 1760361753 ps |
| CPU time | 132.18 seconds |
| Started | Jul 20 07:22:30 PM PDT 24 |
| Finished | Jul 20 07:24:44 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-572995f3-8da1-4b90-a33b-3df737dd6677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550844862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3550844862 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2621449993 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 457835105 ps |
| CPU time | 114.73 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 07:24:31 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-e35561bc-dff7-4395-8946-729f80cec589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621449993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2621449993 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2513839106 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 523596264 ps |
| CPU time | 74.26 seconds |
| Started | Jul 20 07:22:31 PM PDT 24 |
| Finished | Jul 20 07:23:48 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-5f8e3c1b-fb7b-4156-858d-657ac3c97b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513839106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.2513839106 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.146977168 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 128033522 ps |
| CPU time | 7.79 seconds |
| Started | Jul 20 07:22:34 PM PDT 24 |
| Finished | Jul 20 07:22:43 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b09dc2d8-e9a9-41df-9465-426ec7e148ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146977168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.146977168 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.268374042 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 1724409211 ps |
| CPU time | 64.22 seconds |
| Started | Jul 20 07:31:17 PM PDT 24 |
| Finished | Jul 20 07:32:22 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3d50d907-07a5-4152-afee-f65e677820bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268374042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 268374042 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3409936559 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 32974351764 ps |
| CPU time | 570.23 seconds |
| Started | Jul 20 07:31:23 PM PDT 24 |
| Finished | Jul 20 07:40:54 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e7efd2bf-b094-4b3f-8e31-4a6b9f059b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409936559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3409936559 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.924535439 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 54048353 ps |
| CPU time | 8.91 seconds |
| Started | Jul 20 07:31:24 PM PDT 24 |
| Finished | Jul 20 07:31:34 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-0f06e4fe-f136-44d8-ba93-26e98978c10d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924535439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .924535439 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1280290551 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 349589949 ps |
| CPU time | 15.13 seconds |
| Started | Jul 20 07:31:23 PM PDT 24 |
| Finished | Jul 20 07:31:39 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-c0e1ab28-5383-4d9e-843c-3fac73f53e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280290551 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1280290551 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.1842464366 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 2078395245 ps |
| CPU time | 63.9 seconds |
| Started | Jul 20 07:31:14 PM PDT 24 |
| Finished | Jul 20 07:32:18 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-7ddc8d32-8658-44c0-9843-7dc94ad78045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842464366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.1842464366 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.654255631 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 88672118880 ps |
| CPU time | 948.7 seconds |
| Started | Jul 20 07:31:13 PM PDT 24 |
| Finished | Jul 20 07:47:03 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-fb788727-3486-4ccf-be3a-66711a82866f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654255631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.654255631 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.1497104191 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 20954873847 ps |
| CPU time | 395.5 seconds |
| Started | Jul 20 07:31:20 PM PDT 24 |
| Finished | Jul 20 07:37:56 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-404d43c5-db01-42ec-8cdd-aa06161465ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497104191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.1497104191 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.138892835 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 227437379 ps |
| CPU time | 21.16 seconds |
| Started | Jul 20 07:31:21 PM PDT 24 |
| Finished | Jul 20 07:31:43 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-07f2606c-a1a7-40e9-bab4-4bc79c0cb7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138892835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_dela ys.138892835 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.25149444 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 379644962 ps |
| CPU time | 13.82 seconds |
| Started | Jul 20 07:31:24 PM PDT 24 |
| Finished | Jul 20 07:31:38 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-045aa1f6-f2d9-47d0-89b6-6189683ff581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.25149444 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3207592118 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 53392130 ps |
| CPU time | 6.13 seconds |
| Started | Jul 20 07:31:16 PM PDT 24 |
| Finished | Jul 20 07:31:23 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-cd3d277c-86f7-49fb-9b75-9020e408b5a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207592118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3207592118 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.481363681 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 9319068818 ps |
| CPU time | 102.84 seconds |
| Started | Jul 20 07:31:15 PM PDT 24 |
| Finished | Jul 20 07:32:58 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-320d1228-1423-488b-ab0a-198b3c0bdf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481363681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.481363681 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.3626014780 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 5850074934 ps |
| CPU time | 105.58 seconds |
| Started | Jul 20 07:31:16 PM PDT 24 |
| Finished | Jul 20 07:33:02 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-9caf356e-8948-45ce-bd85-96e95c4d7f9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626014780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.3626014780 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.511735094 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 43981845 ps |
| CPU time | 6.1 seconds |
| Started | Jul 20 07:31:21 PM PDT 24 |
| Finished | Jul 20 07:31:27 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-b6820a1e-8f88-4843-ae59-15554aebbbba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511735094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays .511735094 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2829847515 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 5022807146 ps |
| CPU time | 157.73 seconds |
| Started | Jul 20 07:31:23 PM PDT 24 |
| Finished | Jul 20 07:34:01 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-5ec32eed-9dca-4148-b9f6-68e3077cd744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829847515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2829847515 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1568389252 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 8550417766 ps |
| CPU time | 297.13 seconds |
| Started | Jul 20 07:31:23 PM PDT 24 |
| Finished | Jul 20 07:36:21 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-a67ca828-3c77-4b2c-a044-bc7f95c1fe3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568389252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1568389252 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.2726612724 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 345085992 ps |
| CPU time | 105.01 seconds |
| Started | Jul 20 07:31:24 PM PDT 24 |
| Finished | Jul 20 07:33:10 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-0b81bcad-ed0b-4464-926b-118540c58098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726612724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.2726612724 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.4182559363 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 543462141 ps |
| CPU time | 130.72 seconds |
| Started | Jul 20 07:31:29 PM PDT 24 |
| Finished | Jul 20 07:33:40 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-1ed0e8b6-0c7f-4129-9adf-d3c5868d91f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182559363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.4182559363 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.4095698227 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 274489016 ps |
| CPU time | 28.95 seconds |
| Started | Jul 20 07:31:22 PM PDT 24 |
| Finished | Jul 20 07:31:52 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-64d51840-6c94-42b6-a3c6-71e29013554b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095698227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.4095698227 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.2186535474 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 2237018039 ps |
| CPU time | 82.46 seconds |
| Started | Jul 20 07:31:32 PM PDT 24 |
| Finished | Jul 20 07:32:55 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-7ae156f7-ef6c-4811-984a-bf18cc8ace4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186535474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .2186535474 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.1234291605 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 17243273450 ps |
| CPU time | 309.53 seconds |
| Started | Jul 20 07:31:30 PM PDT 24 |
| Finished | Jul 20 07:36:40 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-1a0a700c-7c5e-4ffe-99bb-cc1ee1427aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234291605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.1234291605 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2195842435 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 105156586 ps |
| CPU time | 6.31 seconds |
| Started | Jul 20 07:31:36 PM PDT 24 |
| Finished | Jul 20 07:31:43 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-82bf4595-9336-4e77-8d70-22e602d0f0bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195842435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.2195842435 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.2283702823 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 648152105 ps |
| CPU time | 55.16 seconds |
| Started | Jul 20 07:31:36 PM PDT 24 |
| Finished | Jul 20 07:32:32 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-5abb2ad5-aa6c-4223-a331-118197b3fa74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283702823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.2283702823 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.3560934864 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 2009352761 ps |
| CPU time | 67.46 seconds |
| Started | Jul 20 07:31:31 PM PDT 24 |
| Finished | Jul 20 07:32:39 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-6e2f7da3-e658-4ef7-aeac-28704eaf42bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560934864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.3560934864 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1214615187 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 21979693998 ps |
| CPU time | 246.11 seconds |
| Started | Jul 20 07:31:30 PM PDT 24 |
| Finished | Jul 20 07:35:37 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-852756c3-b4db-4dee-adc3-3f781ed4cdbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214615187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1214615187 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.2545018711 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 35658357421 ps |
| CPU time | 614.92 seconds |
| Started | Jul 20 07:31:31 PM PDT 24 |
| Finished | Jul 20 07:41:46 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-259eaa22-32bb-4a8e-8542-a102d619ca85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545018711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.2545018711 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.949243611 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 215943936 ps |
| CPU time | 22.25 seconds |
| Started | Jul 20 07:31:31 PM PDT 24 |
| Finished | Jul 20 07:31:54 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-90e1fac9-b209-458d-8357-17c34bc3a9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949243611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_dela ys.949243611 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.3061344478 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 946365713 ps |
| CPU time | 32.06 seconds |
| Started | Jul 20 07:31:28 PM PDT 24 |
| Finished | Jul 20 07:32:01 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-e7b48d85-f43f-4352-b13d-d330698522f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061344478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.3061344478 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1676830415 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 150307402 ps |
| CPU time | 7.19 seconds |
| Started | Jul 20 07:31:32 PM PDT 24 |
| Finished | Jul 20 07:31:39 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-01c6004c-4d44-41a3-aee0-2154299d0d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676830415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1676830415 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.3704370400 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 8563781068 ps |
| CPU time | 94.48 seconds |
| Started | Jul 20 07:31:29 PM PDT 24 |
| Finished | Jul 20 07:33:04 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b38153a5-5805-4ea7-9bb9-87be12adf4db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704370400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.3704370400 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1109393963 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 5428430430 ps |
| CPU time | 95.23 seconds |
| Started | Jul 20 07:31:31 PM PDT 24 |
| Finished | Jul 20 07:33:07 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-6ed76664-956f-4a63-b75f-a9e6233c0598 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109393963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1109393963 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2213297408 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 43177584 ps |
| CPU time | 6.23 seconds |
| Started | Jul 20 07:31:30 PM PDT 24 |
| Finished | Jul 20 07:31:37 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-35631c16-af1c-4606-924e-4d85fa176454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213297408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2213297408 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.1897927884 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 12818450964 ps |
| CPU time | 588.59 seconds |
| Started | Jul 20 07:31:36 PM PDT 24 |
| Finished | Jul 20 07:41:26 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f61868b0-9f34-4854-9032-55643a70dec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897927884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1897927884 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2783442343 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 7444718375 ps |
| CPU time | 285.96 seconds |
| Started | Jul 20 07:31:36 PM PDT 24 |
| Finished | Jul 20 07:36:23 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-b0e52fc8-af95-4489-8269-b53436b3b7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783442343 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2783442343 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3041218080 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 9780327760 ps |
| CPU time | 571.92 seconds |
| Started | Jul 20 07:31:37 PM PDT 24 |
| Finished | Jul 20 07:41:09 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-5ce17c04-dd7f-4974-bf19-db71081ad96c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041218080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3041218080 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.3340737279 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 484471939 ps |
| CPU time | 116.06 seconds |
| Started | Jul 20 07:31:38 PM PDT 24 |
| Finished | Jul 20 07:33:34 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-64bd4a8c-78f6-4759-bfcd-87780b3a702d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340737279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.3340737279 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2860076787 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 1247083457 ps |
| CPU time | 52.99 seconds |
| Started | Jul 20 07:31:38 PM PDT 24 |
| Finished | Jul 20 07:32:32 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-eb8a1293-8346-4cbc-a0c9-55c85b2a2c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860076787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2860076787 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.4222646544 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 1608269822 ps |
| CPU time | 52.94 seconds |
| Started | Jul 20 07:31:42 PM PDT 24 |
| Finished | Jul 20 07:32:36 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-545d3532-99d5-41e5-bcf8-998138c7c4a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222646544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .4222646544 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1282019646 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 64038402404 ps |
| CPU time | 1215.71 seconds |
| Started | Jul 20 07:31:46 PM PDT 24 |
| Finished | Jul 20 07:52:02 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-29da05f3-617d-49cf-9fec-11e0a9427272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282019646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.1282019646 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.2503588252 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 586342382 ps |
| CPU time | 22.3 seconds |
| Started | Jul 20 07:31:45 PM PDT 24 |
| Finished | Jul 20 07:32:08 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-450198d6-d705-470a-a6c8-aabbe2ddf61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503588252 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.2503588252 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2992137863 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 419168319 ps |
| CPU time | 32.99 seconds |
| Started | Jul 20 07:31:45 PM PDT 24 |
| Finished | Jul 20 07:32:19 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-37ab817e-a570-4df6-a750-55dce163385d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992137863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2992137863 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.1928077279 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 1567545795 ps |
| CPU time | 55.26 seconds |
| Started | Jul 20 07:31:44 PM PDT 24 |
| Finished | Jul 20 07:32:39 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-f8f22266-43db-4b1a-9e36-8b1fd92c3003 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928077279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.1928077279 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3560358227 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 47900882917 ps |
| CPU time | 544.99 seconds |
| Started | Jul 20 07:31:46 PM PDT 24 |
| Finished | Jul 20 07:40:51 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-ea7a94b4-7711-4e9e-b553-594a222122a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560358227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3560358227 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2200357121 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 67776410303 ps |
| CPU time | 1354.86 seconds |
| Started | Jul 20 07:31:44 PM PDT 24 |
| Finished | Jul 20 07:54:19 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-1c30a63d-9101-4ed5-b536-6791c951afbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200357121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2200357121 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.2686167572 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 288654474 ps |
| CPU time | 28.94 seconds |
| Started | Jul 20 07:31:46 PM PDT 24 |
| Finished | Jul 20 07:32:16 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-24d47d0c-0a43-44c5-850d-a73b5351f264 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686167572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.2686167572 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.1314841522 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 373764160 ps |
| CPU time | 14.1 seconds |
| Started | Jul 20 07:31:48 PM PDT 24 |
| Finished | Jul 20 07:32:02 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-1106571f-3471-4109-86e7-e0a101749dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314841522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.1314841522 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1263046737 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 139363715 ps |
| CPU time | 6.97 seconds |
| Started | Jul 20 07:31:38 PM PDT 24 |
| Finished | Jul 20 07:31:45 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-6a166075-0e2f-40d5-85da-2e7d2cec6ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263046737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1263046737 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.3258000370 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 5445969403 ps |
| CPU time | 60.37 seconds |
| Started | Jul 20 07:31:37 PM PDT 24 |
| Finished | Jul 20 07:32:38 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-36953049-362c-4a95-bfa4-55d788d25961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258000370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.3258000370 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.904408003 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 5371742256 ps |
| CPU time | 99.74 seconds |
| Started | Jul 20 07:31:40 PM PDT 24 |
| Finished | Jul 20 07:33:20 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c770a3be-1e61-464c-9e94-e51aa8fd06ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904408003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.904408003 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.217134844 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 52418469 ps |
| CPU time | 6.44 seconds |
| Started | Jul 20 07:31:41 PM PDT 24 |
| Finished | Jul 20 07:31:48 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-6f84edc1-814c-4da7-8074-5e3a83788544 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217134844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .217134844 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.1335791661 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 1924668120 ps |
| CPU time | 163.09 seconds |
| Started | Jul 20 07:31:54 PM PDT 24 |
| Finished | Jul 20 07:34:38 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-17389545-5862-4937-835e-bd81271bfb5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335791661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.1335791661 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3440137744 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 10019466888 ps |
| CPU time | 345.9 seconds |
| Started | Jul 20 07:31:54 PM PDT 24 |
| Finished | Jul 20 07:37:41 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-97d9ff10-3ef1-4a97-8192-327887dd9176 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440137744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3440137744 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.3491076791 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 8538587478 ps |
| CPU time | 1032.01 seconds |
| Started | Jul 20 07:31:55 PM PDT 24 |
| Finished | Jul 20 07:49:08 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-1aa58bbe-14ad-4066-a41c-4cac58156669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491076791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.3491076791 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2549652745 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 859885291 ps |
| CPU time | 42.11 seconds |
| Started | Jul 20 07:31:43 PM PDT 24 |
| Finished | Jul 20 07:32:25 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-0badb576-a66b-4b99-963e-ea5c4f1e282c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549652745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2549652745 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.283035101 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 592530142 ps |
| CPU time | 43.22 seconds |
| Started | Jul 20 07:32:01 PM PDT 24 |
| Finished | Jul 20 07:32:45 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-962846a7-2483-4784-ad10-f6d94bd76314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283035101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 283035101 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.2554438110 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 108342066307 ps |
| CPU time | 2038.42 seconds |
| Started | Jul 20 07:32:02 PM PDT 24 |
| Finished | Jul 20 08:06:02 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d296b2b4-0d65-4883-a244-62d6c8d9f80f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554438110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.2554438110 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2070130042 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 230363259 ps |
| CPU time | 11.7 seconds |
| Started | Jul 20 07:32:00 PM PDT 24 |
| Finished | Jul 20 07:32:13 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-0cfbd1fe-9fad-44e7-8495-002658995114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070130042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2070130042 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.1730008980 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 778615146 ps |
| CPU time | 31.01 seconds |
| Started | Jul 20 07:32:01 PM PDT 24 |
| Finished | Jul 20 07:32:33 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-d29852b0-5eb8-4849-bfd9-21967803e925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730008980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1730008980 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.2450916176 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 474555637 ps |
| CPU time | 39.88 seconds |
| Started | Jul 20 07:31:53 PM PDT 24 |
| Finished | Jul 20 07:32:33 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-cda77819-259e-4f44-96e3-5bdf48436683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450916176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.2450916176 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.1066098381 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 24327502124 ps |
| CPU time | 288.49 seconds |
| Started | Jul 20 07:32:04 PM PDT 24 |
| Finished | Jul 20 07:36:53 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-e09f194d-70c5-4938-a366-90cf91907b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066098381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.1066098381 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1980583585 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 13609620232 ps |
| CPU time | 230.44 seconds |
| Started | Jul 20 07:32:02 PM PDT 24 |
| Finished | Jul 20 07:35:53 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-927c4978-2fda-4a7a-bb84-984aff67eaa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980583585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1980583585 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3179723263 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 574644160 ps |
| CPU time | 48.76 seconds |
| Started | Jul 20 07:31:53 PM PDT 24 |
| Finished | Jul 20 07:32:42 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-068da83a-76a2-4295-9ad8-0de21d2deb2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179723263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3179723263 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.1797799317 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 2439958689 ps |
| CPU time | 76.16 seconds |
| Started | Jul 20 07:32:01 PM PDT 24 |
| Finished | Jul 20 07:33:19 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-1c5a3d28-930e-4921-a386-1b9dff33fb9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797799317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.1797799317 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1473006730 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 228402900 ps |
| CPU time | 9.41 seconds |
| Started | Jul 20 07:31:54 PM PDT 24 |
| Finished | Jul 20 07:32:04 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-10556617-5e06-4830-8281-ddaa48167048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473006730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1473006730 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.3977865767 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 7678732162 ps |
| CPU time | 88.62 seconds |
| Started | Jul 20 07:31:53 PM PDT 24 |
| Finished | Jul 20 07:33:22 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-e0c5cb22-e80a-46ff-afea-17bb1aab4a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977865767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.3977865767 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2417600069 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 6162859700 ps |
| CPU time | 109.23 seconds |
| Started | Jul 20 07:31:54 PM PDT 24 |
| Finished | Jul 20 07:33:44 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-1424451e-f5db-4f5f-b6b8-4bb2a07e9243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417600069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2417600069 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.1726508777 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 42483438 ps |
| CPU time | 5.79 seconds |
| Started | Jul 20 07:31:52 PM PDT 24 |
| Finished | Jul 20 07:31:58 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-ae09c63f-77e0-4355-87c5-9c2dd841bd8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726508777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.1726508777 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3010336013 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 6019661 ps |
| CPU time | 3.91 seconds |
| Started | Jul 20 07:32:05 PM PDT 24 |
| Finished | Jul 20 07:32:09 PM PDT 24 |
| Peak memory | 565852 kb |
| Host | smart-69fbd9da-93c2-46e3-91d7-ea33055487e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010336013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3010336013 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1442969544 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1375463018 ps |
| CPU time | 97.57 seconds |
| Started | Jul 20 07:32:02 PM PDT 24 |
| Finished | Jul 20 07:33:41 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5c344de3-93fe-40e4-86de-7942bb4770bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442969544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.1442969544 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1914656459 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 1995346805 ps |
| CPU time | 184.66 seconds |
| Started | Jul 20 07:32:00 PM PDT 24 |
| Finished | Jul 20 07:35:06 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-4b7deb91-c750-4a30-b47f-da79bb7ce927 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914656459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1914656459 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1337870783 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 160765601 ps |
| CPU time | 98.07 seconds |
| Started | Jul 20 07:32:01 PM PDT 24 |
| Finished | Jul 20 07:33:40 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-8e8e904e-381b-4624-abe7-6b9a1e2d0318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337870783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1337870783 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1918110794 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 244583119 ps |
| CPU time | 32.08 seconds |
| Started | Jul 20 07:32:01 PM PDT 24 |
| Finished | Jul 20 07:32:34 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3031ce08-97a6-4485-aad9-54434b012a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918110794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1918110794 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.1991431293 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 455616549 ps |
| CPU time | 21.08 seconds |
| Started | Jul 20 07:32:13 PM PDT 24 |
| Finished | Jul 20 07:32:34 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-794d72f7-5c9a-48ca-bf05-135105e96c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991431293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .1991431293 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.393900706 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 137033999576 ps |
| CPU time | 2638.4 seconds |
| Started | Jul 20 07:32:10 PM PDT 24 |
| Finished | Jul 20 08:16:10 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-9d721736-6db0-4c8c-9212-a48e2666dfdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393900706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_d evice_slow_rsp.393900706 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.387466684 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 977942622 ps |
| CPU time | 42.18 seconds |
| Started | Jul 20 07:32:07 PM PDT 24 |
| Finished | Jul 20 07:32:50 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-92fb5eb9-fdcd-40ba-a6c8-b27902551533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387466684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_addr .387466684 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3870193287 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 1167398979 ps |
| CPU time | 45.12 seconds |
| Started | Jul 20 07:32:08 PM PDT 24 |
| Finished | Jul 20 07:32:53 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-2e7140e9-ae3e-46c7-89c8-26670c77a9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870193287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3870193287 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.1830576895 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 187495682 ps |
| CPU time | 17.66 seconds |
| Started | Jul 20 07:32:10 PM PDT 24 |
| Finished | Jul 20 07:32:28 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-a731c661-c126-467d-9727-c515d1ab3c3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830576895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.1830576895 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.3918228820 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 79633323692 ps |
| CPU time | 865.66 seconds |
| Started | Jul 20 07:32:12 PM PDT 24 |
| Finished | Jul 20 07:46:38 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-75b2c591-2081-421d-8bd4-0a20443b2d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918228820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.3918228820 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.3003356901 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 44808312556 ps |
| CPU time | 782.01 seconds |
| Started | Jul 20 07:32:14 PM PDT 24 |
| Finished | Jul 20 07:45:17 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-d4dc9ed4-03d3-48ce-8287-fe9c631f0e38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003356901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.3003356901 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3737090735 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 23410617 ps |
| CPU time | 5.66 seconds |
| Started | Jul 20 07:32:12 PM PDT 24 |
| Finished | Jul 20 07:32:19 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-ef17d44f-1aa2-4ee0-a5ab-c92d4b06d6c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737090735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3737090735 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2843812722 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 1644095730 ps |
| CPU time | 48.8 seconds |
| Started | Jul 20 07:32:11 PM PDT 24 |
| Finished | Jul 20 07:33:00 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-42cd0fc2-0827-42f1-889c-6c4c4f60025d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843812722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2843812722 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.3174139093 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 222660102 ps |
| CPU time | 9.91 seconds |
| Started | Jul 20 07:32:09 PM PDT 24 |
| Finished | Jul 20 07:32:19 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-b19fa9ee-8fe8-45aa-82e0-c29a373538b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174139093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.3174139093 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.3651535758 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 8011750764 ps |
| CPU time | 91.77 seconds |
| Started | Jul 20 07:32:12 PM PDT 24 |
| Finished | Jul 20 07:33:44 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-9789f042-ead0-40a4-b30c-8b372665c4ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651535758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.3651535758 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.440622748 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 6342529719 ps |
| CPU time | 105.17 seconds |
| Started | Jul 20 07:32:10 PM PDT 24 |
| Finished | Jul 20 07:33:56 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-d5b55303-9aa5-4444-9e86-0404c1eea238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440622748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.440622748 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.4273060593 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 54258382 ps |
| CPU time | 7.61 seconds |
| Started | Jul 20 07:32:09 PM PDT 24 |
| Finished | Jul 20 07:32:17 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-5f618037-947e-4969-adfa-a355921c6895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273060593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.4273060593 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.510716000 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 3203945737 ps |
| CPU time | 255.86 seconds |
| Started | Jul 20 07:32:12 PM PDT 24 |
| Finished | Jul 20 07:36:28 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-934ae333-e679-4013-b5d1-f6e9768e5eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510716000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.510716000 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1758033745 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 1671589253 ps |
| CPU time | 136.04 seconds |
| Started | Jul 20 07:32:17 PM PDT 24 |
| Finished | Jul 20 07:34:33 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-75d0d712-4af3-4743-93f9-d4a04bbcfd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758033745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1758033745 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.861267478 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 279720174 ps |
| CPU time | 96.3 seconds |
| Started | Jul 20 07:32:18 PM PDT 24 |
| Finished | Jul 20 07:33:54 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-3ef7bfa8-c208-4a5c-8e29-9e58954f1be5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861267478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_ with_rand_reset.861267478 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3918178143 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 2345276819 ps |
| CPU time | 302.91 seconds |
| Started | Jul 20 07:32:16 PM PDT 24 |
| Finished | Jul 20 07:37:20 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-fec93525-edff-4a94-b6d7-e2840d22f1dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918178143 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3918178143 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2742678706 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 325588212 ps |
| CPU time | 38.3 seconds |
| Started | Jul 20 07:32:11 PM PDT 24 |
| Finished | Jul 20 07:32:50 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-6ce20cf1-5d1c-4ce9-8656-8c7b51221bb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742678706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2742678706 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3755999659 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 1162768856 ps |
| CPU time | 55.93 seconds |
| Started | Jul 20 07:32:22 PM PDT 24 |
| Finished | Jul 20 07:33:19 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-8eff325e-14b3-41bb-af57-b7d24e306e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755999659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3755999659 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1207203291 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 92045943638 ps |
| CPU time | 1855.4 seconds |
| Started | Jul 20 07:32:27 PM PDT 24 |
| Finished | Jul 20 08:03:23 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-9191f2d8-2abc-4395-8b6d-73642267328f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207203291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1207203291 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.49935948 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 152874061 ps |
| CPU time | 18.44 seconds |
| Started | Jul 20 07:32:26 PM PDT 24 |
| Finished | Jul 20 07:32:45 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-14822d4d-9b71-4f4a-ab24-cbda3538f0fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49935948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr.49935948 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3178495788 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 905931134 ps |
| CPU time | 29.56 seconds |
| Started | Jul 20 07:32:26 PM PDT 24 |
| Finished | Jul 20 07:32:56 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-c81ddc6b-d62c-4ffe-89cf-0c61e4c0af84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178495788 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3178495788 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.3941634991 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 431853346 ps |
| CPU time | 17.39 seconds |
| Started | Jul 20 07:32:17 PM PDT 24 |
| Finished | Jul 20 07:32:35 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-b48376fd-1d16-46b2-8bf5-4a29a1da9002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941634991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.3941634991 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.2075173942 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 31270925612 ps |
| CPU time | 326.38 seconds |
| Started | Jul 20 07:32:21 PM PDT 24 |
| Finished | Jul 20 07:37:49 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f703d132-cc3c-47f5-b68b-edd38271f80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075173942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.2075173942 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.2616601022 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 64098273196 ps |
| CPU time | 1223.58 seconds |
| Started | Jul 20 07:32:21 PM PDT 24 |
| Finished | Jul 20 07:52:46 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-6ea79b0b-0505-4f1f-ae35-c5385041f1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616601022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.2616601022 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.118295193 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 423211899 ps |
| CPU time | 35.36 seconds |
| Started | Jul 20 07:32:17 PM PDT 24 |
| Finished | Jul 20 07:32:53 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-f07a9d66-ef1e-4f62-ae8e-85c911421e67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118295193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.118295193 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3514552247 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 57761086 ps |
| CPU time | 6.97 seconds |
| Started | Jul 20 07:32:25 PM PDT 24 |
| Finished | Jul 20 07:32:32 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-18ba4a74-881b-4eee-9c64-0f36cc15f159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514552247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3514552247 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.218508045 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 42365215 ps |
| CPU time | 5.89 seconds |
| Started | Jul 20 07:32:17 PM PDT 24 |
| Finished | Jul 20 07:32:23 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-e67d55ef-2dee-4195-af26-cd833e4ecc33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218508045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.218508045 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2565914998 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 7540192486 ps |
| CPU time | 86.1 seconds |
| Started | Jul 20 07:32:16 PM PDT 24 |
| Finished | Jul 20 07:33:42 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-6d363333-a3da-4a90-8166-a2ae288e3254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565914998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2565914998 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.94675588 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 5648695879 ps |
| CPU time | 95.84 seconds |
| Started | Jul 20 07:32:15 PM PDT 24 |
| Finished | Jul 20 07:33:51 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-74b64f06-22c1-40de-b79e-145b7b5fe3fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94675588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.94675588 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.1699533662 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 45175561 ps |
| CPU time | 6.1 seconds |
| Started | Jul 20 07:32:20 PM PDT 24 |
| Finished | Jul 20 07:32:26 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-93d56bca-c96e-4c50-a30c-fc4e991803c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699533662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delay s.1699533662 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.4249980062 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 4158740335 ps |
| CPU time | 286.53 seconds |
| Started | Jul 20 07:32:24 PM PDT 24 |
| Finished | Jul 20 07:37:12 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-04a5bc7e-bb39-4099-8cfb-85d81c4c3229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249980062 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.4249980062 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.3020788599 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 2177430927 ps |
| CPU time | 67.07 seconds |
| Started | Jul 20 07:32:25 PM PDT 24 |
| Finished | Jul 20 07:33:33 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-98cd52aa-5982-43e3-a2ad-a781920b0e11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020788599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.3020788599 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1314757234 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 102554790 ps |
| CPU time | 35.61 seconds |
| Started | Jul 20 07:32:25 PM PDT 24 |
| Finished | Jul 20 07:33:01 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-0b462e79-cb2b-4697-b7fe-7882cdff40f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314757234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1314757234 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1273585137 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 150306247 ps |
| CPU time | 33.65 seconds |
| Started | Jul 20 07:32:26 PM PDT 24 |
| Finished | Jul 20 07:33:01 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-962bd6a1-a12f-472e-b294-b7936a9ea5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273585137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.1273585137 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3433680144 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 239744122 ps |
| CPU time | 26.8 seconds |
| Started | Jul 20 07:32:26 PM PDT 24 |
| Finished | Jul 20 07:32:54 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-12f1ce46-68bf-4d28-8404-46c768bbc7ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433680144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3433680144 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.181811579 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2346750187 ps |
| CPU time | 91.16 seconds |
| Started | Jul 20 07:32:38 PM PDT 24 |
| Finished | Jul 20 07:34:11 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-d5a8b446-97cf-45fd-b2f2-0d50291769ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181811579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device. 181811579 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.558325855 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 77512894853 ps |
| CPU time | 1506.4 seconds |
| Started | Jul 20 07:32:42 PM PDT 24 |
| Finished | Jul 20 07:57:51 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-897aada9-7fc3-407d-b5f9-877e4dcf0e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558325855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.558325855 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.516573484 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 254003040 ps |
| CPU time | 26.65 seconds |
| Started | Jul 20 07:32:35 PM PDT 24 |
| Finished | Jul 20 07:33:03 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-89af6042-0af9-4de5-bc83-db5a13f9e67c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516573484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_addr .516573484 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.2950406154 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 485907805 ps |
| CPU time | 37.85 seconds |
| Started | Jul 20 07:32:38 PM PDT 24 |
| Finished | Jul 20 07:33:17 PM PDT 24 |
| Peak memory | 575192 kb |
| Host | smart-4e39c1fd-5ebc-4701-8e5d-172b36fcbdef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950406154 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.2950406154 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.3047355045 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 286876919 ps |
| CPU time | 28.7 seconds |
| Started | Jul 20 07:32:25 PM PDT 24 |
| Finished | Jul 20 07:32:54 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-47454a29-830f-4ed8-acd7-cc6143073ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047355045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.3047355045 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.74478385 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 89837845824 ps |
| CPU time | 1141.7 seconds |
| Started | Jul 20 07:32:37 PM PDT 24 |
| Finished | Jul 20 07:51:39 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-2d18d1a6-9025-4116-b5cc-1063c5a80350 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74478385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.74478385 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1198423980 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 26348752418 ps |
| CPU time | 466.38 seconds |
| Started | Jul 20 07:32:37 PM PDT 24 |
| Finished | Jul 20 07:40:25 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-2be55ed9-f62f-49a1-9084-fad97804dc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198423980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1198423980 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.854332672 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 283914436 ps |
| CPU time | 25.33 seconds |
| Started | Jul 20 07:32:38 PM PDT 24 |
| Finished | Jul 20 07:33:05 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8ccf84a0-af63-4a06-b6e7-841e75f5d4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854332672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.854332672 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.2264592473 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 712551039 ps |
| CPU time | 21.26 seconds |
| Started | Jul 20 07:32:36 PM PDT 24 |
| Finished | Jul 20 07:32:58 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-d245f79a-8ec2-46f3-9b0a-f6dc89c7a7ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264592473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.2264592473 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.702200880 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 175005937 ps |
| CPU time | 8.14 seconds |
| Started | Jul 20 07:32:26 PM PDT 24 |
| Finished | Jul 20 07:32:34 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-983e2022-2679-4117-8257-f4ca77140c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702200880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.702200880 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.4287029589 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 7982334261 ps |
| CPU time | 86.36 seconds |
| Started | Jul 20 07:32:30 PM PDT 24 |
| Finished | Jul 20 07:33:57 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c16891c7-ddfe-4729-9056-e703f7ca6b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287029589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.4287029589 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.1212583153 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 5535361754 ps |
| CPU time | 94.81 seconds |
| Started | Jul 20 07:32:30 PM PDT 24 |
| Finished | Jul 20 07:34:06 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-a1fbe50a-29da-4353-9368-7d469924c23f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212583153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.1212583153 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.2834020619 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 44480253 ps |
| CPU time | 6.11 seconds |
| Started | Jul 20 07:32:24 PM PDT 24 |
| Finished | Jul 20 07:32:31 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-9f1d2c30-40c8-4fac-aeb2-3e72a660a0a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834020619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.2834020619 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1888082450 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 15827985348 ps |
| CPU time | 535.98 seconds |
| Started | Jul 20 07:32:36 PM PDT 24 |
| Finished | Jul 20 07:41:33 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-053164c0-9a84-43fa-8947-b9e10cd22a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888082450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1888082450 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1504320310 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 109468929 ps |
| CPU time | 37.03 seconds |
| Started | Jul 20 07:32:41 PM PDT 24 |
| Finished | Jul 20 07:33:19 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-8a057a26-120c-4565-af45-0c1905a44524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504320310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1504320310 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1021370515 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2208517916 ps |
| CPU time | 254.33 seconds |
| Started | Jul 20 07:32:42 PM PDT 24 |
| Finished | Jul 20 07:36:58 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2fd820b1-c180-4ae7-9786-39b6fc184f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021370515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1021370515 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3239771161 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 258124415 ps |
| CPU time | 32.35 seconds |
| Started | Jul 20 07:32:35 PM PDT 24 |
| Finished | Jul 20 07:33:08 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-331daab0-2b1d-46df-aace-7b22139b9968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239771161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3239771161 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1614143189 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 368522827 ps |
| CPU time | 26.64 seconds |
| Started | Jul 20 07:32:44 PM PDT 24 |
| Finished | Jul 20 07:33:13 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-806083a5-be87-4681-9510-fe6eb997dd3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614143189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .1614143189 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2639439641 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 123456218117 ps |
| CPU time | 2458.9 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 08:13:46 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-911d095e-30a4-48e5-b6d7-34a0912bcb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639439641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2639439641 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.2558237741 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 162804729 ps |
| CPU time | 17.92 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:33:12 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-d0d67421-f455-4690-8ac3-8db363d88e18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558237741 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.2558237741 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.2736843081 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 240018379 ps |
| CPU time | 11.21 seconds |
| Started | Jul 20 07:32:44 PM PDT 24 |
| Finished | Jul 20 07:32:57 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-45b00b1c-bea6-490e-b572-f125b5eacd9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736843081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2736843081 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.4136670443 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 501920546 ps |
| CPU time | 44.66 seconds |
| Started | Jul 20 07:32:48 PM PDT 24 |
| Finished | Jul 20 07:33:34 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ebd29791-af67-4d69-a046-312369fd2067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136670443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.4136670443 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.133823461 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 107664993934 ps |
| CPU time | 1224.91 seconds |
| Started | Jul 20 07:32:45 PM PDT 24 |
| Finished | Jul 20 07:53:12 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-fa113795-36c5-48f5-80b1-a52a67e612cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133823461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.133823461 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.4071001323 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 69845190426 ps |
| CPU time | 1224.93 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:53:20 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-ddeeb380-eff4-40a6-98dd-418501a3d9ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071001323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.4071001323 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3858991034 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 83965798 ps |
| CPU time | 10.58 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:32:57 PM PDT 24 |
| Peak memory | 575228 kb |
| Host | smart-44e6fb31-0a38-487b-b874-3ea7a20093c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858991034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3858991034 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.113188775 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 517664396 ps |
| CPU time | 41.71 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:33:27 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-22c3f2d0-ab92-43c5-a361-41e296c9911c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113188775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.113188775 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.4276743217 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 209916248 ps |
| CPU time | 9.51 seconds |
| Started | Jul 20 07:32:44 PM PDT 24 |
| Finished | Jul 20 07:32:56 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-0aa510f2-5cb2-4f98-bf21-f05987b2ef42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276743217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.4276743217 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.686548804 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 6977282818 ps |
| CPU time | 76.24 seconds |
| Started | Jul 20 07:32:42 PM PDT 24 |
| Finished | Jul 20 07:34:00 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-6179b8ff-6e52-42a3-8d95-244eb98f03e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686548804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.686548804 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.2948379173 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 5067887270 ps |
| CPU time | 87.83 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:34:14 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b9b9b6f7-e73d-4009-aa65-19120e4095f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948379173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.2948379173 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.4213284719 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 46754796 ps |
| CPU time | 6.3 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:33:01 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-475556b1-7608-4be0-87e5-34bc31de404e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213284719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delay s.4213284719 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.515612193 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2805181478 ps |
| CPU time | 190.7 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:35:56 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1df799a8-6620-443c-a63b-b7795ee1427e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515612193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.515612193 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2997790621 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 577841697 ps |
| CPU time | 58.93 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:33:44 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-d8b56bf5-7484-408c-812b-c60b5ae71432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997790621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2997790621 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.1961994565 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 1475230774 ps |
| CPU time | 261.3 seconds |
| Started | Jul 20 07:32:42 PM PDT 24 |
| Finished | Jul 20 07:37:06 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-3e83eab5-5942-4ed3-b455-270bf73ca17f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961994565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.1961994565 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3081994549 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 1709256140 ps |
| CPU time | 206.51 seconds |
| Started | Jul 20 07:32:53 PM PDT 24 |
| Finished | Jul 20 07:36:21 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-36c8ff9f-b447-4362-a553-e739503949e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081994549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3081994549 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.3681537829 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 778482202 ps |
| CPU time | 32.9 seconds |
| Started | Jul 20 07:32:49 PM PDT 24 |
| Finished | Jul 20 07:33:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-33119dfd-0bf0-4e4a-8ece-654f13762958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681537829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.3681537829 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.3474092984 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2149498053 ps |
| CPU time | 81.07 seconds |
| Started | Jul 20 07:32:55 PM PDT 24 |
| Finished | Jul 20 07:34:18 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-99e45edf-a7a9-499f-a0e4-07fdf6b00a5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474092984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .3474092984 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.928269765 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 57325292045 ps |
| CPU time | 988.54 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:49:22 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e0d98566-5253-4462-9e27-6608dd2eb42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928269765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_d evice_slow_rsp.928269765 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3634620191 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 153679474 ps |
| CPU time | 9.46 seconds |
| Started | Jul 20 07:32:51 PM PDT 24 |
| Finished | Jul 20 07:33:02 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-540a3e23-7ed4-4b8c-ab85-2219335782f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634620191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.3634620191 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.4176930835 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 2359679758 ps |
| CPU time | 78.86 seconds |
| Started | Jul 20 07:32:49 PM PDT 24 |
| Finished | Jul 20 07:34:09 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a76dec96-daa2-45a6-b8cb-e7f9300374af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176930835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.4176930835 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.2177407609 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 784998451 ps |
| CPU time | 31.87 seconds |
| Started | Jul 20 07:32:50 PM PDT 24 |
| Finished | Jul 20 07:33:23 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c06915f8-852a-4bd1-a940-6120643c2201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177407609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.2177407609 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2775239156 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 104198874168 ps |
| CPU time | 1182.94 seconds |
| Started | Jul 20 07:32:51 PM PDT 24 |
| Finished | Jul 20 07:52:35 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-e2961280-b925-43df-92bf-7341b29a39fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775239156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.2775239156 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.720342289 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 4037267430 ps |
| CPU time | 68.24 seconds |
| Started | Jul 20 07:32:55 PM PDT 24 |
| Finished | Jul 20 07:34:05 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-8521b841-ecd0-446f-9eae-4fd8dfed3b83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720342289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.720342289 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1929787832 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 131556090 ps |
| CPU time | 13.8 seconds |
| Started | Jul 20 07:32:51 PM PDT 24 |
| Finished | Jul 20 07:33:06 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-07fa1bd5-db0f-4fb1-94d0-a496bddb1c1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929787832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1929787832 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.1274746276 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 469755559 ps |
| CPU time | 34.72 seconds |
| Started | Jul 20 07:32:55 PM PDT 24 |
| Finished | Jul 20 07:33:31 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-cdf70156-f9db-4779-8d26-14d1eed0b96d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274746276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.1274746276 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.236796046 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 229984928 ps |
| CPU time | 9.64 seconds |
| Started | Jul 20 07:32:43 PM PDT 24 |
| Finished | Jul 20 07:32:55 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-a04c57ce-8004-4ea7-8c3f-c1779051e31c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236796046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.236796046 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3494489543 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 9327450719 ps |
| CPU time | 100.13 seconds |
| Started | Jul 20 07:32:50 PM PDT 24 |
| Finished | Jul 20 07:34:32 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-d1eaacb0-196d-432e-9ec1-b106d95f3fdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494489543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3494489543 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1349981356 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 6681734168 ps |
| CPU time | 112.89 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:34:47 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f92727b6-66c3-4450-beeb-e10d1c8037b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349981356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1349981356 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.788812605 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 45303054 ps |
| CPU time | 6.11 seconds |
| Started | Jul 20 07:32:52 PM PDT 24 |
| Finished | Jul 20 07:33:00 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-97c321fc-903e-4de1-9962-41e45dabe535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788812605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .788812605 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.1501650795 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 5780242428 ps |
| CPU time | 225.2 seconds |
| Started | Jul 20 07:32:50 PM PDT 24 |
| Finished | Jul 20 07:36:36 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-e384375c-d1ae-45ee-aab6-9b66da93d365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501650795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1501650795 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.1843668285 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 11577406596 ps |
| CPU time | 419.02 seconds |
| Started | Jul 20 07:33:03 PM PDT 24 |
| Finished | Jul 20 07:40:05 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-0d96e8b5-c3db-4e34-8961-48204f2bbc1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843668285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.1843668285 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1002322052 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 259865948 ps |
| CPU time | 102.09 seconds |
| Started | Jul 20 07:32:51 PM PDT 24 |
| Finished | Jul 20 07:34:35 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-129856d2-88f6-46b8-91c1-9ce3f50182d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002322052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.1002322052 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3301410830 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 19939183 ps |
| CPU time | 13.88 seconds |
| Started | Jul 20 07:32:59 PM PDT 24 |
| Finished | Jul 20 07:33:15 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-55d56ab8-dd61-45f8-8b81-f0e462914c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301410830 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.3301410830 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.2406693287 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 39070873 ps |
| CPU time | 6.91 seconds |
| Started | Jul 20 07:32:55 PM PDT 24 |
| Finished | Jul 20 07:33:04 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c8666b1f-8380-4026-a56c-3e616e686245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406693287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.2406693287 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.3552654322 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 412586719 ps |
| CPU time | 30.24 seconds |
| Started | Jul 20 07:33:00 PM PDT 24 |
| Finished | Jul 20 07:33:32 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-c0d4679c-685d-4f07-853f-1f4d5f4ffdf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552654322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .3552654322 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.3806109917 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 74029883970 ps |
| CPU time | 1426.74 seconds |
| Started | Jul 20 07:33:10 PM PDT 24 |
| Finished | Jul 20 07:57:00 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-9d689a69-64de-46b0-8a78-b4d425eaff87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806109917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.3806109917 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1656037345 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 553996338 ps |
| CPU time | 25.78 seconds |
| Started | Jul 20 07:33:08 PM PDT 24 |
| Finished | Jul 20 07:33:37 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-c7f9ca62-fe15-48dc-a827-421bc57887bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656037345 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1656037345 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.4216535007 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 602707933 ps |
| CPU time | 43.54 seconds |
| Started | Jul 20 07:32:59 PM PDT 24 |
| Finished | Jul 20 07:33:44 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-2179186d-928d-4eaf-87bb-be995d0e2503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216535007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.4216535007 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2746215095 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 415847388 ps |
| CPU time | 36.1 seconds |
| Started | Jul 20 07:33:00 PM PDT 24 |
| Finished | Jul 20 07:33:38 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-8fb34ad1-c441-49f4-b049-21d206b30f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746215095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2746215095 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.657344781 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 40177954500 ps |
| CPU time | 455.67 seconds |
| Started | Jul 20 07:33:02 PM PDT 24 |
| Finished | Jul 20 07:40:41 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-477cd212-b08c-4fbb-8f50-41d8416d5199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657344781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.657344781 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.4188086262 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 33272603480 ps |
| CPU time | 530.21 seconds |
| Started | Jul 20 07:33:01 PM PDT 24 |
| Finished | Jul 20 07:41:54 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-a5e99adc-c416-4534-a0fb-172b379701b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188086262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4188086262 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2412844138 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 130057005 ps |
| CPU time | 14.07 seconds |
| Started | Jul 20 07:32:59 PM PDT 24 |
| Finished | Jul 20 07:33:14 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-4d607574-a6cc-469c-8312-e15106bf519e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412844138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2412844138 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2460901961 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 1319803871 ps |
| CPU time | 39.47 seconds |
| Started | Jul 20 07:33:01 PM PDT 24 |
| Finished | Jul 20 07:33:43 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-cf735a45-44cb-4767-aa10-88b6e787fc4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460901961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2460901961 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.2996096882 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 51724541 ps |
| CPU time | 7.01 seconds |
| Started | Jul 20 07:33:02 PM PDT 24 |
| Finished | Jul 20 07:33:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-dadc104c-2bd5-4f2c-81ff-e2f6f25c3d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996096882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.2996096882 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1039904678 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 6706889462 ps |
| CPU time | 75.75 seconds |
| Started | Jul 20 07:33:01 PM PDT 24 |
| Finished | Jul 20 07:34:19 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f1ddbe24-940c-4890-a854-7f4375921c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039904678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1039904678 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.922007759 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 4646620091 ps |
| CPU time | 82.73 seconds |
| Started | Jul 20 07:33:00 PM PDT 24 |
| Finished | Jul 20 07:34:26 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-5d6a71d0-47fe-4c23-8a00-e1da8a4b69b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922007759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.922007759 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.4138098724 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 48969417 ps |
| CPU time | 6.14 seconds |
| Started | Jul 20 07:32:58 PM PDT 24 |
| Finished | Jul 20 07:33:05 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-3977cc51-3d9e-48e5-8a2d-60a8c0a4bd41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138098724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.4138098724 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2160765826 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 156220073 ps |
| CPU time | 20.27 seconds |
| Started | Jul 20 07:33:07 PM PDT 24 |
| Finished | Jul 20 07:33:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-52165327-e6d0-410a-bde8-aaff5bfbde65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160765826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2160765826 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.2840453138 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 8347138293 ps |
| CPU time | 285.04 seconds |
| Started | Jul 20 07:33:08 PM PDT 24 |
| Finished | Jul 20 07:37:55 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-24e82f85-6f21-485f-bba4-e3c194ccca73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840453138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.2840453138 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3908324620 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 18771352618 ps |
| CPU time | 944.85 seconds |
| Started | Jul 20 07:33:10 PM PDT 24 |
| Finished | Jul 20 07:48:58 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-1e7d70d2-e607-47a5-9bad-4c9bf7f9b9bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908324620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.3908324620 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.1689956043 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 4210219416 ps |
| CPU time | 346.79 seconds |
| Started | Jul 20 07:33:07 PM PDT 24 |
| Finished | Jul 20 07:38:57 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-9f844ae5-3baf-4635-8019-d3a096e0cb9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689956043 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.1689956043 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.4231150073 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 111908773 ps |
| CPU time | 14.41 seconds |
| Started | Jul 20 07:33:10 PM PDT 24 |
| Finished | Jul 20 07:33:28 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-98961487-98c4-4f32-b74d-55d94edddb31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231150073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.4231150073 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.1151355149 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 11789948315 ps |
| CPU time | 988.83 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:39:08 PM PDT 24 |
| Peak memory | 652712 kb |
| Host | smart-09fa39b4-0f86-496c-81e1-76a2c8041cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151355149 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.1151355149 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.3417281363 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 6000344260 ps |
| CPU time | 485.03 seconds |
| Started | Jul 20 07:22:42 PM PDT 24 |
| Finished | Jul 20 07:30:47 PM PDT 24 |
| Peak memory | 598684 kb |
| Host | smart-286fcf2c-de55-40a8-8549-9c235888fe5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417281363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.3417281363 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.836728425 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 32208010662 ps |
| CPU time | 3792.71 seconds |
| Started | Jul 20 07:22:35 PM PDT 24 |
| Finished | Jul 20 08:25:50 PM PDT 24 |
| Peak memory | 593352 kb |
| Host | smart-3205fc1c-8477-4c61-aa7b-df62748c9d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836728425 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.836728425 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.4165969358 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 559128776 ps |
| CPU time | 23.88 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:23:04 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-be49bdee-bc22-450d-8dc0-553ab3fa5d45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165969358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 4165969358 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.692313124 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 263942510 ps |
| CPU time | 30.86 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:23:11 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-fa9b3c88-b95c-4cdb-a7e6-8400af44d9d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692313124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr. 692313124 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1992775927 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 2477776706 ps |
| CPU time | 92.31 seconds |
| Started | Jul 20 07:22:41 PM PDT 24 |
| Finished | Jul 20 07:24:14 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-2a79c246-2396-4eb3-992a-32e5be2546ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992775927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1992775927 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.217284104 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 1614880137 ps |
| CPU time | 57.15 seconds |
| Started | Jul 20 07:22:36 PM PDT 24 |
| Finished | Jul 20 07:23:35 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-95d93377-40ec-496e-b4be-af80f3dd784c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217284104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.217284104 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1448244673 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 8757270036 ps |
| CPU time | 103.91 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:24:24 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-36ad3d54-8f7d-47e3-8b6f-67a933e4ee57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448244673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1448244673 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.1145365511 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 11576695470 ps |
| CPU time | 204.06 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:26:04 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-23589c34-4aa1-4828-805c-2d44422aad3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145365511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.1145365511 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2054397396 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 269070068 ps |
| CPU time | 26.06 seconds |
| Started | Jul 20 07:22:39 PM PDT 24 |
| Finished | Jul 20 07:23:06 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-51184a7f-a636-4807-bb22-b7cd4d5f1f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054397396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2054397396 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2979174466 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 2199018590 ps |
| CPU time | 63.76 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:59 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d6601dd8-54f3-4e00-80bf-b8dc8cf017e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979174466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2979174466 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.901045372 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 188386864 ps |
| CPU time | 8.29 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:03 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-1305601a-6b7d-420f-b329-a599aa68a665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901045372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.901045372 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.3040969741 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 10594994048 ps |
| CPU time | 117.46 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:24:52 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-8bf3a99d-67e9-475a-b99c-03200a804a86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040969741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.3040969741 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.13098623 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 3706979802 ps |
| CPU time | 62.16 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:57 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-158ee201-18ea-4b91-86cd-776517517112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13098623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.13098623 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.4142081805 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 50775209 ps |
| CPU time | 6.81 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 07:22:47 PM PDT 24 |
| Peak memory | 575236 kb |
| Host | smart-d6cbf6dd-d7f6-4a3e-8b59-3b51147bd786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142081805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .4142081805 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.660707744 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3256548883 ps |
| CPU time | 289.5 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:27:29 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-e8c10675-eb06-44f1-b200-7570f3c8e521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660707744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.660707744 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.3043369161 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 4080026568 ps |
| CPU time | 143.88 seconds |
| Started | Jul 20 07:22:36 PM PDT 24 |
| Finished | Jul 20 07:25:02 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a59e2b61-b41d-4e7c-96e2-cdec77483284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043369161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.3043369161 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1744498302 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 233063788 ps |
| CPU time | 89.44 seconds |
| Started | Jul 20 07:22:44 PM PDT 24 |
| Finished | Jul 20 07:24:14 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-4b8e96d4-4c2a-46b1-bfb0-65f830840bcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744498302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.1744498302 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.853917034 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 78370073 ps |
| CPU time | 41.27 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 07:23:22 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-b470dc8c-9992-4ea6-ba00-34219ebe611e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853917034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_reset_error.853917034 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.1265465583 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1361043207 ps |
| CPU time | 55.53 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 07:23:36 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-dd05f2bf-6419-4b13-9f89-6feb8d4b647c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265465583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.1265465583 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.2381471304 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 834142935 ps |
| CPU time | 32.03 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:33:53 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-df958e42-572a-4dbd-a13c-d115cff17607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381471304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .2381471304 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.3547790367 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 143789795739 ps |
| CPU time | 2897.09 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 08:21:39 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-20052140-d860-4a9d-b48e-af8a327d98a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547790367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.3547790367 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1215896806 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 780279661 ps |
| CPU time | 31.76 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:33:53 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-2e4a9672-f247-4673-9910-fe4300a663d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215896806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1215896806 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.4288534458 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 2621370746 ps |
| CPU time | 86.92 seconds |
| Started | Jul 20 07:33:15 PM PDT 24 |
| Finished | Jul 20 07:34:46 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-c60f44ab-9fdd-4529-bb88-98eb037f901e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288534458 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.4288534458 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3085094611 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2166362212 ps |
| CPU time | 76.56 seconds |
| Started | Jul 20 07:33:07 PM PDT 24 |
| Finished | Jul 20 07:34:26 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-506a28d2-ca0f-4672-9d93-9a15fcbce712 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085094611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3085094611 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3546021808 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 70505854083 ps |
| CPU time | 815.04 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:46:57 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-15e80a81-80d6-403e-96fd-2274fb4e474d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546021808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3546021808 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.666731267 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 46228781330 ps |
| CPU time | 850.97 seconds |
| Started | Jul 20 07:33:18 PM PDT 24 |
| Finished | Jul 20 07:47:33 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-d4d39527-3f0e-435a-821b-8dc47f125584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666731267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.666731267 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1250299239 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 142383971 ps |
| CPU time | 13.22 seconds |
| Started | Jul 20 07:33:19 PM PDT 24 |
| Finished | Jul 20 07:33:36 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-fdf00cae-083d-4354-9d7f-a3dfbb561e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250299239 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1250299239 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.2333281405 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 1346691796 ps |
| CPU time | 39.76 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:34:01 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d7f10709-fee5-4f78-89bd-808ddb60195d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333281405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.2333281405 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.721708228 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 41273070 ps |
| CPU time | 6.4 seconds |
| Started | Jul 20 07:33:06 PM PDT 24 |
| Finished | Jul 20 07:33:15 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-260bdf24-9cc8-4e94-b259-2a5321ebc21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721708228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.721708228 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.2687166246 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 11121727842 ps |
| CPU time | 124.8 seconds |
| Started | Jul 20 07:33:10 PM PDT 24 |
| Finished | Jul 20 07:35:18 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-1a1aa97e-8b32-44cf-9cf3-2d7f41619b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687166246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.2687166246 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.3810081355 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 6594773173 ps |
| CPU time | 115.56 seconds |
| Started | Jul 20 07:33:12 PM PDT 24 |
| Finished | Jul 20 07:35:11 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-a6b688b3-237a-41a9-906f-e905dac7148b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810081355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.3810081355 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3487331071 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 51562756 ps |
| CPU time | 6.66 seconds |
| Started | Jul 20 07:33:10 PM PDT 24 |
| Finished | Jul 20 07:33:20 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-8b2dfd01-244a-4b16-bef4-798cb1b4ed80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487331071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3487331071 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.3321344359 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2535887377 ps |
| CPU time | 102.13 seconds |
| Started | Jul 20 07:33:16 PM PDT 24 |
| Finished | Jul 20 07:35:02 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-b52b7860-f749-4ad9-8184-65a0760cc707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321344359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.3321344359 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1042694553 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 1214198206 ps |
| CPU time | 87.72 seconds |
| Started | Jul 20 07:33:18 PM PDT 24 |
| Finished | Jul 20 07:34:49 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-20405169-a45d-4a8c-8a98-b9598c480892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042694553 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.1042694553 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1267217295 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 501535178 ps |
| CPU time | 195.69 seconds |
| Started | Jul 20 07:33:15 PM PDT 24 |
| Finished | Jul 20 07:36:35 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-1d9bf5f7-4f95-4f9a-864b-54a716308127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267217295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1267217295 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.78753076 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 108844455 ps |
| CPU time | 57.53 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:34:18 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4a598bd9-8c82-4f97-ba97-74035ab8989d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78753076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_ with_reset_error.78753076 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.2713724409 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 544660084 ps |
| CPU time | 24.32 seconds |
| Started | Jul 20 07:33:17 PM PDT 24 |
| Finished | Jul 20 07:33:45 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-af54c93e-1c8b-42b9-aa4e-11cd99e7c76c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713724409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.2713724409 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.3073236131 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2163185267 ps |
| CPU time | 82.19 seconds |
| Started | Jul 20 07:33:27 PM PDT 24 |
| Finished | Jul 20 07:34:50 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-7cb49963-5f64-406a-9c89-52aee1119ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073236131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .3073236131 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1566082771 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 56149179321 ps |
| CPU time | 1000 seconds |
| Started | Jul 20 07:33:24 PM PDT 24 |
| Finished | Jul 20 07:50:06 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-81bc1622-d0ba-40f7-a7ef-90730940ecea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566082771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.1566082771 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2792745050 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 1189603672 ps |
| CPU time | 44.63 seconds |
| Started | Jul 20 07:33:33 PM PDT 24 |
| Finished | Jul 20 07:34:21 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-f74dbd5b-4e36-42a3-a7c2-f7c7b54507b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792745050 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2792745050 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.4241751388 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 558230288 ps |
| CPU time | 24.2 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:33:58 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-4111c03c-20ad-4f8c-b867-4ab7e423b786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241751388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4241751388 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.4009139855 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 260555932 ps |
| CPU time | 11.88 seconds |
| Started | Jul 20 07:33:24 PM PDT 24 |
| Finished | Jul 20 07:33:37 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-601873db-cc09-4d72-8fb5-294b6748acde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009139855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.4009139855 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2260215182 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 41345774641 ps |
| CPU time | 483.26 seconds |
| Started | Jul 20 07:33:23 PM PDT 24 |
| Finished | Jul 20 07:41:28 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e58dc8a2-170c-459f-a09a-0a1314e71219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260215182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2260215182 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2805941955 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 21192768024 ps |
| CPU time | 388.36 seconds |
| Started | Jul 20 07:33:22 PM PDT 24 |
| Finished | Jul 20 07:39:53 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-137b1082-3f89-48ae-9f21-9ad6a1857b11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805941955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2805941955 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.1448292379 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 404653142 ps |
| CPU time | 32.55 seconds |
| Started | Jul 20 07:33:23 PM PDT 24 |
| Finished | Jul 20 07:33:57 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-157b035d-912a-43d7-bce5-3b750d162051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448292379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.1448292379 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.4191928556 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 353239386 ps |
| CPU time | 27.63 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:34:01 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-d8f89597-ed5b-49da-93fe-1e95dc3cbf53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191928556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.4191928556 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.2597673312 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 48531289 ps |
| CPU time | 6.5 seconds |
| Started | Jul 20 07:33:25 PM PDT 24 |
| Finished | Jul 20 07:33:33 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a282f242-52b0-42de-bc4a-473cb69a033f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597673312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.2597673312 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2298708906 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 6699095046 ps |
| CPU time | 72.55 seconds |
| Started | Jul 20 07:33:21 PM PDT 24 |
| Finished | Jul 20 07:34:36 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-db0197e7-7b41-4f32-baac-0048c6163336 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298708906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2298708906 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1696942449 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 4446090597 ps |
| CPU time | 82.9 seconds |
| Started | Jul 20 07:33:22 PM PDT 24 |
| Finished | Jul 20 07:34:47 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-dd5bb2f2-835a-4f54-ab2b-d9cba7caa7c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696942449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1696942449 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.666565028 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 39490155 ps |
| CPU time | 6.44 seconds |
| Started | Jul 20 07:33:21 PM PDT 24 |
| Finished | Jul 20 07:33:30 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-bebb4459-2391-4dc3-b503-0b0016f6a6c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666565028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delays .666565028 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.3258208297 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 10694091306 ps |
| CPU time | 368.45 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:39:44 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-650aad7d-47ef-43df-b062-8879a0b0007e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258208297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.3258208297 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3811489167 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 6059816324 ps |
| CPU time | 174.77 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:36:29 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-6ae95f45-fb3f-472d-876e-d4f9c0a8d1c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811489167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3811489167 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1562240739 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 4943389192 ps |
| CPU time | 422.32 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:40:37 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-2d99aa24-ff10-47f4-825f-b8d51ffe3fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562240739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1562240739 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.532155537 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2397439421 ps |
| CPU time | 373.11 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:39:49 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-cb827619-fac5-4319-9fb9-6f3ac7584aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532155537 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.532155537 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.45380706 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 1163037201 ps |
| CPU time | 52.19 seconds |
| Started | Jul 20 07:33:33 PM PDT 24 |
| Finished | Jul 20 07:34:29 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-dc3199b4-cc5f-4ae5-ba1f-2a5dd8ee8b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45380706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.45380706 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.915492499 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 661715422 ps |
| CPU time | 57.67 seconds |
| Started | Jul 20 07:33:40 PM PDT 24 |
| Finished | Jul 20 07:34:39 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-c1c361d2-4ef2-4489-a887-a7b81877e0aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915492499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device. 915492499 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3977552918 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 122585947151 ps |
| CPU time | 2436.4 seconds |
| Started | Jul 20 07:33:43 PM PDT 24 |
| Finished | Jul 20 08:14:21 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-9ba99799-61d0-4e4a-bbe7-144a5239aad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977552918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3977552918 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2847982495 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 777152395 ps |
| CPU time | 34.13 seconds |
| Started | Jul 20 07:33:41 PM PDT 24 |
| Finished | Jul 20 07:34:17 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-faf7453a-27fe-417c-aa3b-2bd2c7a770a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847982495 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2847982495 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.2562057424 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 360360991 ps |
| CPU time | 13 seconds |
| Started | Jul 20 07:33:41 PM PDT 24 |
| Finished | Jul 20 07:33:54 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-e4fb0560-2902-43e7-9685-882cf2a0d934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562057424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.2562057424 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1221457152 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 2384283589 ps |
| CPU time | 74.34 seconds |
| Started | Jul 20 07:33:39 PM PDT 24 |
| Finished | Jul 20 07:34:54 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-7f541db5-481e-4c01-a816-0ff874279269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221457152 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1221457152 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1245033796 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 98439318486 ps |
| CPU time | 1107.13 seconds |
| Started | Jul 20 07:33:39 PM PDT 24 |
| Finished | Jul 20 07:52:08 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-07ff8604-6409-4985-82dd-22b5d144cba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245033796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1245033796 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.655158274 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 43192867865 ps |
| CPU time | 755.44 seconds |
| Started | Jul 20 07:33:44 PM PDT 24 |
| Finished | Jul 20 07:46:21 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-ee715092-5251-4236-989e-f65778a9a8d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655158274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.655158274 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.3430355236 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 592946599 ps |
| CPU time | 45.92 seconds |
| Started | Jul 20 07:33:42 PM PDT 24 |
| Finished | Jul 20 07:34:30 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-dfa360ef-04f4-446b-b15a-bf87879e84b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430355236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.3430355236 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.1008488995 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 2224427963 ps |
| CPU time | 59.88 seconds |
| Started | Jul 20 07:33:41 PM PDT 24 |
| Finished | Jul 20 07:34:42 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-3480bef5-94ba-4618-bd73-c6dafce032c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008488995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.1008488995 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.549642942 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 48569153 ps |
| CPU time | 6.9 seconds |
| Started | Jul 20 07:33:31 PM PDT 24 |
| Finished | Jul 20 07:33:40 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-66d7d82f-440e-495c-ac90-87470c451258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549642942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.549642942 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.1382383965 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 10135143176 ps |
| CPU time | 111.59 seconds |
| Started | Jul 20 07:33:31 PM PDT 24 |
| Finished | Jul 20 07:35:23 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-ce6907cb-1e9d-4909-bb0b-9589cfe48577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382383965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.1382383965 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1350127544 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 5286898823 ps |
| CPU time | 92.97 seconds |
| Started | Jul 20 07:33:33 PM PDT 24 |
| Finished | Jul 20 07:35:10 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-45bfff80-3c5b-4eb8-8fdc-b0d1568e4a89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350127544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1350127544 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1685626841 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 52750725 ps |
| CPU time | 7.18 seconds |
| Started | Jul 20 07:33:32 PM PDT 24 |
| Finished | Jul 20 07:33:42 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-661f5c9e-0fb1-41da-b3d6-3634137658cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685626841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.1685626841 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3230893388 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2515796878 ps |
| CPU time | 220.56 seconds |
| Started | Jul 20 07:33:39 PM PDT 24 |
| Finished | Jul 20 07:37:21 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-d8f6e8b6-135d-47da-833b-d53507892acb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230893388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3230893388 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.1695519809 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 8525916050 ps |
| CPU time | 275.57 seconds |
| Started | Jul 20 07:33:42 PM PDT 24 |
| Finished | Jul 20 07:38:19 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-2b8783b9-bd2e-4521-a78a-e7d3ce0c9c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695519809 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.1695519809 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.455676150 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 152635214 ps |
| CPU time | 25.66 seconds |
| Started | Jul 20 07:33:42 PM PDT 24 |
| Finished | Jul 20 07:34:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-85dc930d-f0ee-49f7-98b0-5d43107c5b28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455676150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_reset_error.455676150 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1258381533 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 839727816 ps |
| CPU time | 38.83 seconds |
| Started | Jul 20 07:33:39 PM PDT 24 |
| Finished | Jul 20 07:34:19 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-ddd74833-15fd-4a7f-9cb4-b7ab9fa6bb98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258381533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1258381533 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.4017934110 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 779740597 ps |
| CPU time | 59.05 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:34:50 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-b3d5027f-ab6b-45f3-b1a5-29c9ffb757d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017934110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .4017934110 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.899669133 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 99161321924 ps |
| CPU time | 1712.57 seconds |
| Started | Jul 20 07:33:53 PM PDT 24 |
| Finished | Jul 20 08:02:30 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-cb89c446-771b-4e73-8218-41ba7c72fd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899669133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_d evice_slow_rsp.899669133 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.642902388 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 80655885 ps |
| CPU time | 10.94 seconds |
| Started | Jul 20 07:33:52 PM PDT 24 |
| Finished | Jul 20 07:34:07 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-a142c51b-fb54-4916-bf4b-6da465d00526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642902388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr .642902388 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.1143169147 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 1310650592 ps |
| CPU time | 43.87 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:34:35 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-a8f28d42-20bd-4218-b8ce-2aec70177dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143169147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.1143169147 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.3012986658 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 113897780 ps |
| CPU time | 14.21 seconds |
| Started | Jul 20 07:33:47 PM PDT 24 |
| Finished | Jul 20 07:34:02 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-fc447b53-f304-436d-9fce-c85c4d5a350a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012986658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.3012986658 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.811089383 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 20540426197 ps |
| CPU time | 234.86 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:37:46 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-adb7febb-99f5-476b-ada0-78c4b4b88e5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811089383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.811089383 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2081574219 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 40686814430 ps |
| CPU time | 715.03 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:45:47 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-d512d6f3-832a-4fa8-b4d3-16cf5905494f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081574219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2081574219 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.974208275 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 128903130 ps |
| CPU time | 14.29 seconds |
| Started | Jul 20 07:33:49 PM PDT 24 |
| Finished | Jul 20 07:34:06 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-c4e1e551-2897-457e-aae3-a7c7f0cc18cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974208275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_dela ys.974208275 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.3876147273 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 1417503180 ps |
| CPU time | 47.1 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:34:39 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-429bb5d6-021e-4026-b2de-4571c888ba9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876147273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3876147273 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.2036546907 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 220021680 ps |
| CPU time | 8.73 seconds |
| Started | Jul 20 07:33:41 PM PDT 24 |
| Finished | Jul 20 07:33:52 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-d40e6681-10af-449a-84fe-fd2222d4d83a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036546907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2036546907 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.911807656 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 8013392764 ps |
| CPU time | 90.55 seconds |
| Started | Jul 20 07:33:49 PM PDT 24 |
| Finished | Jul 20 07:35:23 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1901ea99-c1e9-458c-9d8b-07c196b86a5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911807656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.911807656 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1225830209 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 4688368280 ps |
| CPU time | 85.17 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:35:16 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-216eb054-9520-4575-8df0-0410ff6c371a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225830209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1225830209 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.1303884083 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 38429168 ps |
| CPU time | 5.53 seconds |
| Started | Jul 20 07:33:48 PM PDT 24 |
| Finished | Jul 20 07:33:56 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-c51518b1-1aba-4e95-aa9f-b917abf70841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303884083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.1303884083 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.921606862 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 6263773934 ps |
| CPU time | 223.83 seconds |
| Started | Jul 20 07:33:57 PM PDT 24 |
| Finished | Jul 20 07:37:43 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-887fef2e-f698-4b8d-ac07-7d0d26b2ef02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921606862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.921606862 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1977112416 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 14492180221 ps |
| CPU time | 525.2 seconds |
| Started | Jul 20 07:33:55 PM PDT 24 |
| Finished | Jul 20 07:42:43 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-06eaa217-667f-494f-aead-b9ec2dca0062 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977112416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.1977112416 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.1908179581 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 214248663 ps |
| CPU time | 67.71 seconds |
| Started | Jul 20 07:34:00 PM PDT 24 |
| Finished | Jul 20 07:35:09 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-30b7ec77-50c9-46d2-a988-0cb3cabffc96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908179581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.1908179581 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.4290408110 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 207562226 ps |
| CPU time | 11.21 seconds |
| Started | Jul 20 07:33:47 PM PDT 24 |
| Finished | Jul 20 07:33:59 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5206b7c3-38e4-4c36-b379-b74387c848ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290408110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.4290408110 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.1642619314 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 1666054634 ps |
| CPU time | 59.43 seconds |
| Started | Jul 20 07:33:55 PM PDT 24 |
| Finished | Jul 20 07:34:58 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5fed1461-0c49-4845-b67d-f5f5c4272acc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642619314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .1642619314 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2105016921 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 66834224581 ps |
| CPU time | 1163.71 seconds |
| Started | Jul 20 07:33:55 PM PDT 24 |
| Finished | Jul 20 07:53:22 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-8b969640-3e9b-474e-a8b6-db230bae1a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105016921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2105016921 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2774941441 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 990491321 ps |
| CPU time | 40.67 seconds |
| Started | Jul 20 07:34:14 PM PDT 24 |
| Finished | Jul 20 07:34:57 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-bf129972-43fd-4e1c-89b2-54aa3d41531f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774941441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2774941441 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.512241588 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 455031642 ps |
| CPU time | 20.92 seconds |
| Started | Jul 20 07:34:03 PM PDT 24 |
| Finished | Jul 20 07:34:25 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-58dc9d62-e5d1-4d0b-b4d2-aa22a419b509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512241588 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.512241588 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.3544121706 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 43509112 ps |
| CPU time | 7.41 seconds |
| Started | Jul 20 07:33:57 PM PDT 24 |
| Finished | Jul 20 07:34:07 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-ffc0e37f-1b1a-40a3-8cb3-2cf54c976088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544121706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.3544121706 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.1965085313 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 27639657884 ps |
| CPU time | 319.73 seconds |
| Started | Jul 20 07:33:58 PM PDT 24 |
| Finished | Jul 20 07:39:19 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-9df2563d-b94a-4225-b56e-51f04b26f6fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965085313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.1965085313 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1403458368 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 56089489641 ps |
| CPU time | 1043.17 seconds |
| Started | Jul 20 07:33:59 PM PDT 24 |
| Finished | Jul 20 07:51:24 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-8159bac2-7fff-40f7-b565-e770347646df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403458368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1403458368 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.2031895122 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 464921201 ps |
| CPU time | 40.48 seconds |
| Started | Jul 20 07:34:01 PM PDT 24 |
| Finished | Jul 20 07:34:42 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-c96f0b9d-9207-4702-a1ef-33161b8c94fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031895122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_del ays.2031895122 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.4271966541 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 1372981412 ps |
| CPU time | 43.04 seconds |
| Started | Jul 20 07:34:04 PM PDT 24 |
| Finished | Jul 20 07:34:49 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-4013ed82-354e-41bf-915f-7a4beb2b03b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271966541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.4271966541 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.2838520886 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 38170111 ps |
| CPU time | 5.98 seconds |
| Started | Jul 20 07:33:56 PM PDT 24 |
| Finished | Jul 20 07:34:05 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-e5bfb4fa-1037-4733-bf6e-8cb17a1fc911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838520886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2838520886 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.1965923011 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 9754010153 ps |
| CPU time | 105.35 seconds |
| Started | Jul 20 07:33:56 PM PDT 24 |
| Finished | Jul 20 07:35:44 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-275f23a9-0cc4-4df3-83a8-5bf51fe716ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965923011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.1965923011 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.4013255714 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 5488544271 ps |
| CPU time | 97.58 seconds |
| Started | Jul 20 07:33:57 PM PDT 24 |
| Finished | Jul 20 07:35:37 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-4ba8a10e-b888-407a-ab13-0d897590ce9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013255714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.4013255714 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.2093752139 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 49191010 ps |
| CPU time | 7.05 seconds |
| Started | Jul 20 07:33:56 PM PDT 24 |
| Finished | Jul 20 07:34:06 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-e823ac5a-9f1e-4793-8d0b-8238a33251f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093752139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.2093752139 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.1522193915 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2172023801 ps |
| CPU time | 177.65 seconds |
| Started | Jul 20 07:34:14 PM PDT 24 |
| Finished | Jul 20 07:37:14 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-792b48f3-5e89-47ed-a96d-543a702b287e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522193915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1522193915 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.3968903237 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 5319793740 ps |
| CPU time | 180.84 seconds |
| Started | Jul 20 07:34:06 PM PDT 24 |
| Finished | Jul 20 07:37:09 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-1c9cad09-aa42-49d2-8128-1150ad01c044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968903237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.3968903237 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3645109208 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 2792317333 ps |
| CPU time | 322.51 seconds |
| Started | Jul 20 07:34:08 PM PDT 24 |
| Finished | Jul 20 07:39:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d4f67e86-fb49-4068-8367-68d5f81256c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645109208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3645109208 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4126925578 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 15798496706 ps |
| CPU time | 685.69 seconds |
| Started | Jul 20 07:34:05 PM PDT 24 |
| Finished | Jul 20 07:45:32 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-27c28ec1-2a75-48e1-9a56-8ed59c6a7f8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126925578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.4126925578 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1015958894 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 235865187 ps |
| CPU time | 27.63 seconds |
| Started | Jul 20 07:34:05 PM PDT 24 |
| Finished | Jul 20 07:34:34 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-fcfb32e8-75ac-4006-bfc9-1b582faeae90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015958894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1015958894 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.4165621439 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 582686876 ps |
| CPU time | 54.4 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:35:10 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3efdb114-e8c7-4019-96bb-31c3eb09c614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165621439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .4165621439 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2738408460 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 86132729977 ps |
| CPU time | 1574.53 seconds |
| Started | Jul 20 07:34:17 PM PDT 24 |
| Finished | Jul 20 08:00:35 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-10e56c56-7d7e-4443-81a8-8ac2a3cd5ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738408460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.2738408460 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1671127536 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 56229657 ps |
| CPU time | 5.61 seconds |
| Started | Jul 20 07:34:12 PM PDT 24 |
| Finished | Jul 20 07:34:20 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-1939d11e-2efc-47b3-a0e9-24c2f399fe17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671127536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1671127536 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1436407357 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 551813751 ps |
| CPU time | 40.59 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:34:56 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-0d7c291c-9a1b-4d10-858d-5799d2d22986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436407357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1436407357 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1216315446 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 252337899 ps |
| CPU time | 23.76 seconds |
| Started | Jul 20 07:34:04 PM PDT 24 |
| Finished | Jul 20 07:34:29 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-08c62379-95a1-42dd-8775-9a69b72d3dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216315446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1216315446 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1135887591 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 5451131615 ps |
| CPU time | 60.81 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:35:16 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-43135221-9ad4-480e-9814-04fc4e15f9f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135887591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1135887591 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.1837709742 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 54277408086 ps |
| CPU time | 978.67 seconds |
| Started | Jul 20 07:34:16 PM PDT 24 |
| Finished | Jul 20 07:50:38 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-75e64e01-775e-469a-9459-7c6a55930e91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837709742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.1837709742 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.4227492733 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 545814016 ps |
| CPU time | 51.83 seconds |
| Started | Jul 20 07:34:17 PM PDT 24 |
| Finished | Jul 20 07:35:12 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-3f9353de-fe18-4dbf-adbc-a4ea7ad63597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227492733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.4227492733 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1142670254 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 2300933294 ps |
| CPU time | 65.31 seconds |
| Started | Jul 20 07:34:16 PM PDT 24 |
| Finished | Jul 20 07:35:25 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-038ea208-9f66-474a-8c48-a521068cc00d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142670254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1142670254 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1786494018 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 49285861 ps |
| CPU time | 5.99 seconds |
| Started | Jul 20 07:34:07 PM PDT 24 |
| Finished | Jul 20 07:34:16 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-65b1349d-3c35-4ef8-ad47-f7f8e145cdbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786494018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1786494018 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2555192696 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 9118093368 ps |
| CPU time | 103.12 seconds |
| Started | Jul 20 07:34:06 PM PDT 24 |
| Finished | Jul 20 07:35:50 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-d409a87f-ba3b-4175-895c-b1935f8ebc67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555192696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2555192696 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.3494723244 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 5820842849 ps |
| CPU time | 103.15 seconds |
| Started | Jul 20 07:34:07 PM PDT 24 |
| Finished | Jul 20 07:35:52 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-0dcfe353-585d-41f3-8d2f-03b0692f85ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494723244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.3494723244 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3025900135 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 49099257 ps |
| CPU time | 6.42 seconds |
| Started | Jul 20 07:34:08 PM PDT 24 |
| Finished | Jul 20 07:34:17 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-96639185-fdb8-42ec-9bc5-906da604d8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025900135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3025900135 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.3015343374 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 3315854912 ps |
| CPU time | 118.48 seconds |
| Started | Jul 20 07:34:17 PM PDT 24 |
| Finished | Jul 20 07:36:19 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-70c097ec-033c-4f6d-bf04-4d9458bb3902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015343374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.3015343374 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3746537751 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 6578283190 ps |
| CPU time | 214.96 seconds |
| Started | Jul 20 07:34:16 PM PDT 24 |
| Finished | Jul 20 07:37:55 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-43a36401-1604-4e95-b078-3c3e6d36ad0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746537751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3746537751 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2805904398 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 10359479888 ps |
| CPU time | 538.02 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:43:14 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-5bf7ae13-d660-43ae-a64e-fe6e6c06b6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805904398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2805904398 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.152701661 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 737697422 ps |
| CPU time | 235.78 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:38:11 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-b16d56ee-664c-4937-92da-8b01e4af801f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152701661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.152701661 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.1936567517 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 85326565 ps |
| CPU time | 13.29 seconds |
| Started | Jul 20 07:34:12 PM PDT 24 |
| Finished | Jul 20 07:34:28 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a887fc53-7b71-4c6c-a938-3aa35627b5f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936567517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.1936567517 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.2975719670 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 2661436247 ps |
| CPU time | 119.68 seconds |
| Started | Jul 20 07:34:11 PM PDT 24 |
| Finished | Jul 20 07:36:14 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-3a28ac64-b223-4c77-af8a-527beeff86b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975719670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .2975719670 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1393746596 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 22429088513 ps |
| CPU time | 409.56 seconds |
| Started | Jul 20 07:34:12 PM PDT 24 |
| Finished | Jul 20 07:41:04 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-3425226c-8440-46e8-b5c0-bd542e5f3892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393746596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1393746596 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.3703418025 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 44054854 ps |
| CPU time | 7.45 seconds |
| Started | Jul 20 07:34:23 PM PDT 24 |
| Finished | Jul 20 07:34:31 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-034a4117-4c76-4691-8a0e-d40f0e9201cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703418025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.3703418025 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.1876357122 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 1977605753 ps |
| CPU time | 59.98 seconds |
| Started | Jul 20 07:34:24 PM PDT 24 |
| Finished | Jul 20 07:35:27 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-b002d5ef-bf67-4744-a7c4-ad3c8832879a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876357122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.1876357122 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3527103048 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 271450621 ps |
| CPU time | 24.37 seconds |
| Started | Jul 20 07:34:14 PM PDT 24 |
| Finished | Jul 20 07:34:41 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-6fb0ddee-9395-42f9-9d1f-dc394ded15c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527103048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3527103048 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.3424667423 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 69954692847 ps |
| CPU time | 790.88 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:47:27 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-289bc138-8eaf-4bdf-a652-03774ff0ac9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424667423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.3424667423 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1784642279 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 46050102413 ps |
| CPU time | 788.09 seconds |
| Started | Jul 20 07:34:14 PM PDT 24 |
| Finished | Jul 20 07:47:25 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-4395d5e7-9a7c-43a7-a052-eedc215d3bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784642279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1784642279 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1954812038 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 604821459 ps |
| CPU time | 56.74 seconds |
| Started | Jul 20 07:34:12 PM PDT 24 |
| Finished | Jul 20 07:35:12 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-087509f5-b951-4662-8dff-a203b2f89f9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954812038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1954812038 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.43702117 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 383290182 ps |
| CPU time | 23.77 seconds |
| Started | Jul 20 07:34:16 PM PDT 24 |
| Finished | Jul 20 07:34:44 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f7439654-5658-4393-a37a-be4414d3f76f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43702117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.43702117 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.907297792 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 38804603 ps |
| CPU time | 6.05 seconds |
| Started | Jul 20 07:34:15 PM PDT 24 |
| Finished | Jul 20 07:34:24 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-ba657db2-45c6-4743-8b4f-b7e6905ae3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907297792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.907297792 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.281867696 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 8708542514 ps |
| CPU time | 94.98 seconds |
| Started | Jul 20 07:34:16 PM PDT 24 |
| Finished | Jul 20 07:35:55 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-bf566cf8-d501-46a4-bda4-91eed6c7af10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281867696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.281867696 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.951204385 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 3735750041 ps |
| CPU time | 66.97 seconds |
| Started | Jul 20 07:34:14 PM PDT 24 |
| Finished | Jul 20 07:35:24 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-50ed58ef-7c01-4123-908c-53bd0f142fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951204385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.951204385 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.4059433273 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 55707731 ps |
| CPU time | 6.77 seconds |
| Started | Jul 20 07:34:13 PM PDT 24 |
| Finished | Jul 20 07:34:23 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-46891736-b5a7-453a-88ac-c61a97ca025c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059433273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.4059433273 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3971540293 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 1050273479 ps |
| CPU time | 33.02 seconds |
| Started | Jul 20 07:34:23 PM PDT 24 |
| Finished | Jul 20 07:34:57 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-c822be16-6eb4-4531-a034-abc3612f4f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971540293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3971540293 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.327240570 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4365422630 ps |
| CPU time | 346.29 seconds |
| Started | Jul 20 07:34:20 PM PDT 24 |
| Finished | Jul 20 07:40:09 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-2fc4d1e2-37cd-43ba-a63b-baae552bdf93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327240570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.327240570 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2786279766 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 10516891971 ps |
| CPU time | 620.8 seconds |
| Started | Jul 20 07:34:22 PM PDT 24 |
| Finished | Jul 20 07:44:45 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-4c6a1fc0-c0b9-45d0-94ff-8b672009ebe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786279766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2786279766 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.3202055313 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 87771821 ps |
| CPU time | 18.96 seconds |
| Started | Jul 20 07:34:21 PM PDT 24 |
| Finished | Jul 20 07:34:42 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-c42bdc0f-3c44-4fbb-b14e-8f89d8c8e3d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202055313 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.3202055313 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.110065849 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 741676316 ps |
| CPU time | 35.08 seconds |
| Started | Jul 20 07:34:22 PM PDT 24 |
| Finished | Jul 20 07:34:59 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-517784fd-691c-47f3-a03f-205733e8ecfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110065849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.110065849 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1222429643 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2548407432 ps |
| CPU time | 97.42 seconds |
| Started | Jul 20 07:34:31 PM PDT 24 |
| Finished | Jul 20 07:36:10 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-f4d107c5-6bcc-43b2-b1fa-00f6cf612fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222429643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1222429643 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.4280399471 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 46814342264 ps |
| CPU time | 883.16 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:49:14 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-dd8df8e6-a3b6-45c9-b5d5-1493461dc422 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280399471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.4280399471 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1801730705 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 251530290 ps |
| CPU time | 30.44 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:35:00 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-610a378b-69e9-4445-9b58-94c040a6b9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801730705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1801730705 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.365062255 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 520406631 ps |
| CPU time | 37.34 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:35:07 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-5bc90a53-028a-4c72-976f-ee86a6f08d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365062255 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.365062255 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.85807747 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 215445888 ps |
| CPU time | 20.49 seconds |
| Started | Jul 20 07:34:27 PM PDT 24 |
| Finished | Jul 20 07:34:51 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-cafa0b3b-2bbf-4004-b4d1-cfe88a4788c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85807747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.85807747 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.2562218497 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 91913236812 ps |
| CPU time | 1114.46 seconds |
| Started | Jul 20 07:34:31 PM PDT 24 |
| Finished | Jul 20 07:53:07 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-261fe71c-7df7-4690-b834-7e14dc9ebe97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562218497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.2562218497 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.2115947474 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 58034085750 ps |
| CPU time | 1163.45 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:53:54 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-d5f93ece-fe92-450e-a6cd-e6d1d04a6b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115947474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.2115947474 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.944756403 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 409239531 ps |
| CPU time | 37.64 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:35:08 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-64968fdb-2c29-4673-96cc-f824d7679fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944756403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.944756403 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.1180519922 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 192156568 ps |
| CPU time | 15.67 seconds |
| Started | Jul 20 07:34:27 PM PDT 24 |
| Finished | Jul 20 07:34:46 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-42c97dc0-b45f-4463-a6e2-1d4fe1499a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180519922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.1180519922 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.1743698215 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 43608404 ps |
| CPU time | 6.19 seconds |
| Started | Jul 20 07:34:24 PM PDT 24 |
| Finished | Jul 20 07:34:32 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-ae85df29-247a-4917-8abd-1bbbfcb7e5f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743698215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.1743698215 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.892255305 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 4924331309 ps |
| CPU time | 57.84 seconds |
| Started | Jul 20 07:34:25 PM PDT 24 |
| Finished | Jul 20 07:35:27 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-80a038ea-65cd-42e6-ac51-3328aab3d966 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892255305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.892255305 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.173551158 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 5576125045 ps |
| CPU time | 92.55 seconds |
| Started | Jul 20 07:34:29 PM PDT 24 |
| Finished | Jul 20 07:36:04 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-516e67c2-f99f-4521-a2b4-9d77b48484ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173551158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.173551158 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.557969441 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 46750567 ps |
| CPU time | 6.16 seconds |
| Started | Jul 20 07:34:20 PM PDT 24 |
| Finished | Jul 20 07:34:28 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-891753aa-fc17-4129-ac29-242dd634ad67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557969441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .557969441 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.247210211 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 14243340915 ps |
| CPU time | 566.45 seconds |
| Started | Jul 20 07:34:28 PM PDT 24 |
| Finished | Jul 20 07:43:58 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b0cd3b95-55fc-456f-b155-2f8230406270 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247210211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.247210211 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2419664734 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 346844613 ps |
| CPU time | 25.16 seconds |
| Started | Jul 20 07:34:30 PM PDT 24 |
| Finished | Jul 20 07:34:57 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-aa02db1f-de90-4b54-a8fb-d66a8798726c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419664734 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2419664734 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3485696373 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 5827451059 ps |
| CPU time | 656.76 seconds |
| Started | Jul 20 07:34:32 PM PDT 24 |
| Finished | Jul 20 07:45:30 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f16bfa51-5049-4a68-8893-538a0d3119b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485696373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3485696373 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3042067747 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 22325537911 ps |
| CPU time | 1039.34 seconds |
| Started | Jul 20 07:34:28 PM PDT 24 |
| Finished | Jul 20 07:51:51 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-ba0e749b-5e11-41d1-b3c9-80a2f99026c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042067747 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.3042067747 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2181632148 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 1031738014 ps |
| CPU time | 42.92 seconds |
| Started | Jul 20 07:34:26 PM PDT 24 |
| Finished | Jul 20 07:35:13 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-24958a4a-f6d2-4f21-85aa-60bcfd3cb608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181632148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2181632148 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3354784886 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 861079164 ps |
| CPU time | 38.94 seconds |
| Started | Jul 20 07:34:38 PM PDT 24 |
| Finished | Jul 20 07:35:19 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-6b39aa62-ca5a-40e0-9f18-fa149f87c484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354784886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3354784886 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.589245659 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 290250659 ps |
| CPU time | 32.6 seconds |
| Started | Jul 20 07:34:46 PM PDT 24 |
| Finished | Jul 20 07:35:20 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-e24d86d8-fccf-497c-9961-3f72e7613b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589245659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_addr .589245659 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1002619739 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 527366867 ps |
| CPU time | 40.39 seconds |
| Started | Jul 20 07:34:41 PM PDT 24 |
| Finished | Jul 20 07:35:24 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-dae70bf2-b7cf-4c0e-92ba-8d82f853f1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002619739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1002619739 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.497666773 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 825985381 ps |
| CPU time | 32.87 seconds |
| Started | Jul 20 07:34:38 PM PDT 24 |
| Finished | Jul 20 07:35:13 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-0618ec77-01cb-486f-9a34-751703dcee4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497666773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.497666773 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.7278719 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 5140710745 ps |
| CPU time | 54.29 seconds |
| Started | Jul 20 07:34:37 PM PDT 24 |
| Finished | Jul 20 07:35:34 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-7a40dd30-a0be-479c-aedf-cf62d905aff5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7278719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.7278719 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.3259607197 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 46834526224 ps |
| CPU time | 801.05 seconds |
| Started | Jul 20 07:34:37 PM PDT 24 |
| Finished | Jul 20 07:48:01 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-214c66cf-fd59-490a-b206-7696ffa72aaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259607197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.3259607197 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.3325425345 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 558753302 ps |
| CPU time | 50.1 seconds |
| Started | Jul 20 07:34:36 PM PDT 24 |
| Finished | Jul 20 07:35:29 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-f6658674-2722-4a9a-9b8e-369b34862ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325425345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.3325425345 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3183689176 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1961523425 ps |
| CPU time | 58.29 seconds |
| Started | Jul 20 07:34:38 PM PDT 24 |
| Finished | Jul 20 07:35:38 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-c5ca7543-f3b3-4371-820c-44bf4bec6ad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183689176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3183689176 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1784431858 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 40872826 ps |
| CPU time | 5.61 seconds |
| Started | Jul 20 07:34:38 PM PDT 24 |
| Finished | Jul 20 07:34:46 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-f6c71d7a-f7fd-44c3-ae94-7b585d2d3aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784431858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1784431858 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3912379797 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 7356934587 ps |
| CPU time | 79.7 seconds |
| Started | Jul 20 07:34:39 PM PDT 24 |
| Finished | Jul 20 07:36:01 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-5ffddb6d-40d5-49c5-bef2-ed464d45e648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912379797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3912379797 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.1160873579 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 5939876675 ps |
| CPU time | 104.39 seconds |
| Started | Jul 20 07:34:38 PM PDT 24 |
| Finished | Jul 20 07:36:25 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-0e9cd5f3-e9f4-4feb-adfd-bd6c6e6391a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160873579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.1160873579 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.957376872 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 39696196 ps |
| CPU time | 5.82 seconds |
| Started | Jul 20 07:34:37 PM PDT 24 |
| Finished | Jul 20 07:34:45 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-fd00c4f1-b9de-4f80-9ef7-6577be946df5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957376872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays .957376872 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.1152225249 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 1491387192 ps |
| CPU time | 56.15 seconds |
| Started | Jul 20 07:34:46 PM PDT 24 |
| Finished | Jul 20 07:35:44 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-3a6f5df7-534a-423f-936c-a7f095d26ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152225249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.1152225249 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.1779365692 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 7637055996 ps |
| CPU time | 270.65 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:39:20 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1763ab86-4fef-4777-a001-9f1d915f3161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779365692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.1779365692 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.1391082786 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 5543156089 ps |
| CPU time | 355.74 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:40:49 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-27844ed3-04f8-4e67-bd2f-6ce6cbbbf460 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391082786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.1391082786 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.3164893565 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 9697493801 ps |
| CPU time | 383.56 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:41:18 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-75050320-9578-4764-942d-0dba4c41fc12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164893565 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.3164893565 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1822893503 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 169511297 ps |
| CPU time | 22.85 seconds |
| Started | Jul 20 07:34:36 PM PDT 24 |
| Finished | Jul 20 07:35:02 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-18afdff5-e399-41ca-8b62-fb2c719ceedc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822893503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1822893503 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.1720335169 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 932445913 ps |
| CPU time | 81.38 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:36:15 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-b8635a6d-d0ff-4875-bb5c-adf0730eea69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720335169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .1720335169 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2686700828 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 24613154104 ps |
| CPU time | 409.97 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:41:43 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-b64467f4-6f4b-45c7-9971-bf7c46ffbf76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686700828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.2686700828 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3190238596 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 1265750521 ps |
| CPU time | 50.69 seconds |
| Started | Jul 20 07:34:46 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-bf072d1f-ad23-4d4b-b612-5a563d4de42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190238596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3190238596 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.3932773946 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 37354675 ps |
| CPU time | 5.8 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:34:54 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-d85ab799-8b7a-4607-a913-3e59810f4236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932773946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3932773946 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1098502086 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 306088660 ps |
| CPU time | 14.44 seconds |
| Started | Jul 20 07:34:48 PM PDT 24 |
| Finished | Jul 20 07:35:04 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-ef073ffd-2b85-4771-87f6-15eb972627c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098502086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1098502086 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.86980673 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 96777642442 ps |
| CPU time | 1172.61 seconds |
| Started | Jul 20 07:34:51 PM PDT 24 |
| Finished | Jul 20 07:54:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-2f91b6df-19c0-4f89-bf8d-1a5e2bb4eac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86980673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.86980673 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3162507304 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 12999834655 ps |
| CPU time | 220.74 seconds |
| Started | Jul 20 07:34:50 PM PDT 24 |
| Finished | Jul 20 07:38:32 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d8b685aa-53f0-4427-b7e0-7f5638389331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162507304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3162507304 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.854783299 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 216991221 ps |
| CPU time | 20.25 seconds |
| Started | Jul 20 07:34:50 PM PDT 24 |
| Finished | Jul 20 07:35:12 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-eb453028-9f1c-4b06-a079-f562e3b0d376 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854783299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.854783299 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3610793427 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 2384521662 ps |
| CPU time | 66.74 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:35:55 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-84eee740-372c-456b-a3c3-01917005ac79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610793427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3610793427 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.2231653450 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 46251989 ps |
| CPU time | 6.23 seconds |
| Started | Jul 20 07:34:48 PM PDT 24 |
| Finished | Jul 20 07:34:56 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-80f581ab-594b-4fab-ba53-f15facfe7803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231653450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.2231653450 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.4157263392 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 8917240510 ps |
| CPU time | 96.83 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:36:25 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-7d9426bf-79eb-44fb-8018-25ba1d6fa071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157263392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.4157263392 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.874957424 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 6131634132 ps |
| CPU time | 112.5 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:36:41 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-4f9c8743-1793-4759-a6bd-aa2f2e37347a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874957424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.874957424 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1051126354 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 50440579 ps |
| CPU time | 6.17 seconds |
| Started | Jul 20 07:34:47 PM PDT 24 |
| Finished | Jul 20 07:34:55 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-723bc04b-6f90-4199-a871-04101d8162e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051126354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1051126354 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1333821811 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 3002696677 ps |
| CPU time | 102.11 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:36:35 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-04d8f8d3-289d-4224-976a-3435018ea483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333821811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1333821811 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.482719943 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 12557753314 ps |
| CPU time | 430.76 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:42:05 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-5789ad60-8db8-4650-8c27-fcb84cc8f2fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482719943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.482719943 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.1051189753 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 4143026694 ps |
| CPU time | 445.04 seconds |
| Started | Jul 20 07:34:55 PM PDT 24 |
| Finished | Jul 20 07:42:22 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-a3fcafcd-1287-47ed-8e98-a0fb31c944f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051189753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_rand_reset.1051189753 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.598688408 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 1204351407 ps |
| CPU time | 157.88 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:37:33 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-a69caddc-60a0-47db-a127-d43045688ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598688408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all _with_reset_error.598688408 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.3285184269 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 962569824 ps |
| CPU time | 42.27 seconds |
| Started | Jul 20 07:34:49 PM PDT 24 |
| Finished | Jul 20 07:35:33 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-a737bd12-0ea0-41ec-98f6-5e6e6fc66765 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285184269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.3285184269 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2938346295 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 7725589596 ps |
| CPU time | 510.68 seconds |
| Started | Jul 20 07:22:49 PM PDT 24 |
| Finished | Jul 20 07:31:20 PM PDT 24 |
| Peak memory | 637912 kb |
| Host | smart-dffb8193-f2fc-487f-a145-145f9639d913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938346295 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2938346295 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.438230577 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 4238493904 ps |
| CPU time | 386.26 seconds |
| Started | Jul 20 07:22:47 PM PDT 24 |
| Finished | Jul 20 07:29:14 PM PDT 24 |
| Peak memory | 596920 kb |
| Host | smart-d1731daa-7547-4b4b-8252-ba0e21ff2995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438230577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.438230577 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.3166070052 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4301725754 ps |
| CPU time | 294.55 seconds |
| Started | Jul 20 07:22:36 PM PDT 24 |
| Finished | Jul 20 07:27:32 PM PDT 24 |
| Peak memory | 603652 kb |
| Host | smart-9e7c03df-9d0f-4bac-955d-50f38123d623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166070052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.3166070052 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.2710643907 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 320554510 ps |
| CPU time | 24.3 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 07:23:05 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-60fba4d9-7bce-4d86-bfa1-4f95ffdaa943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710643907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 2710643907 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3291609705 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 144667362701 ps |
| CPU time | 2548.43 seconds |
| Started | Jul 20 07:22:43 PM PDT 24 |
| Finished | Jul 20 08:05:13 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-4f60a7ce-16ad-4894-9117-d3bf2d9734bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291609705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.3291609705 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2182532257 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 91489171 ps |
| CPU time | 10.5 seconds |
| Started | Jul 20 07:22:55 PM PDT 24 |
| Finished | Jul 20 07:23:07 PM PDT 24 |
| Peak memory | 575116 kb |
| Host | smart-782adcc8-c0e7-4020-81c9-15ce5e1e95bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182532257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .2182532257 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.378808864 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 1083190887 ps |
| CPU time | 36.76 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 07:23:33 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-51916f2e-75a0-4db6-a1b8-b3523c8bed32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378808864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.378808864 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.2644049658 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 189140272 ps |
| CPU time | 19.63 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:22:59 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-d7b16583-ceca-40f0-a6df-e51397467269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644049658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.2644049658 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2481482700 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 12561958257 ps |
| CPU time | 138.38 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:24:57 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-ef8ab5a7-4c75-45bd-a048-970f4a9d5d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481482700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2481482700 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.485112904 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 58764224079 ps |
| CPU time | 946.2 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:38:41 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-f695efb7-677c-4ba4-8f3d-7a663306a315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485112904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.485112904 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.2600348121 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 514854886 ps |
| CPU time | 42.58 seconds |
| Started | Jul 20 07:22:40 PM PDT 24 |
| Finished | Jul 20 07:23:23 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2bac4d91-6e92-4950-9791-5aeec8e70e7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600348121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.2600348121 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3325129768 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 93465719 ps |
| CPU time | 9.49 seconds |
| Started | Jul 20 07:22:47 PM PDT 24 |
| Finished | Jul 20 07:22:57 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-c17cf789-bb9a-4cde-b536-f14260b75b99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325129768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3325129768 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1046142935 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 41227223 ps |
| CPU time | 5.83 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:22:45 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-98f93b1f-6466-41a3-a6d2-df6d7c7e8697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046142935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1046142935 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.486100090 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 7424257604 ps |
| CPU time | 76.27 seconds |
| Started | Jul 20 07:22:44 PM PDT 24 |
| Finished | Jul 20 07:24:01 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-3f0434f0-b27d-45cf-9942-dc9dfa000fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486100090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.486100090 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.939299097 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4865698287 ps |
| CPU time | 85.22 seconds |
| Started | Jul 20 07:22:38 PM PDT 24 |
| Finished | Jul 20 07:24:04 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-188a0e24-bfee-4291-82f8-bdebb1b14b45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939299097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.939299097 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3126990394 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 50481287 ps |
| CPU time | 6.28 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:01 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-8bf12249-4a94-4676-94a5-ae31d6722a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126990394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3126990394 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.3582899279 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 266056742 ps |
| CPU time | 31.83 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:23:18 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-084295d3-697b-4323-94a7-c0bd42ef8cbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582899279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3582899279 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.4102175381 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 14770428490 ps |
| CPU time | 564.21 seconds |
| Started | Jul 20 07:22:46 PM PDT 24 |
| Finished | Jul 20 07:32:12 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-a895a77c-85ef-49bf-ae7a-8f17e22559b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102175381 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4102175381 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3749362295 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 283122470 ps |
| CPU time | 128.09 seconds |
| Started | Jul 20 07:22:47 PM PDT 24 |
| Finished | Jul 20 07:24:56 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-81529eb8-d349-4117-9008-19acc94c18fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749362295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.3749362295 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2531471265 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 5998051231 ps |
| CPU time | 332.53 seconds |
| Started | Jul 20 07:22:46 PM PDT 24 |
| Finished | Jul 20 07:28:19 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-d993d791-bfe9-4478-a141-7f4be9c414f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531471265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.2531471265 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1171634137 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 1426967652 ps |
| CPU time | 62.26 seconds |
| Started | Jul 20 07:22:44 PM PDT 24 |
| Finished | Jul 20 07:23:47 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-fe0826ef-7670-40ec-bd31-b219f72edd52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171634137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1171634137 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1895545665 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 252271142 ps |
| CPU time | 24.57 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:19 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-25d25aef-3073-4392-a1c6-22970fbd72e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895545665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1895545665 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.2944398801 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 135987441402 ps |
| CPU time | 2691.82 seconds |
| Started | Jul 20 07:34:59 PM PDT 24 |
| Finished | Jul 20 08:19:52 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f6d85d7b-0859-447d-a541-6f4d56f37d0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944398801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.2944398801 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.274813654 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 630732608 ps |
| CPU time | 26.22 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:21 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-29f88ef3-b4bf-47e1-825b-610a0eae3de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274813654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_addr .274813654 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.3119255502 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 31506471 ps |
| CPU time | 6.3 seconds |
| Started | Jul 20 07:34:55 PM PDT 24 |
| Finished | Jul 20 07:35:04 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-40b0ac3a-a143-40e6-8f11-6b7c065d5e31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119255502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3119255502 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.3983975168 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 2394127794 ps |
| CPU time | 94.1 seconds |
| Started | Jul 20 07:34:55 PM PDT 24 |
| Finished | Jul 20 07:36:31 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-8cf14d7a-2e5c-4808-9e38-019779b82cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983975168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.3983975168 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.11764337 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 10299338446 ps |
| CPU time | 110.32 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:36:47 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-efbeda27-a4ca-4f30-ba0f-ea48205a913d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11764337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.11764337 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.2394716589 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 21717922324 ps |
| CPU time | 362.2 seconds |
| Started | Jul 20 07:35:00 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-399a3bec-f085-44e5-bed9-201a5200e997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394716589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.2394716589 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.3567830110 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 469453570 ps |
| CPU time | 43.82 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-434b24b9-d801-435f-b8c2-d2a37d49cc76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567830110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.3567830110 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.2126477462 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 339436630 ps |
| CPU time | 26.46 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:35:23 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-f30711e9-3915-4795-8ce9-d151f02c49d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126477462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.2126477462 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1564479585 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 210652021 ps |
| CPU time | 9.24 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:05 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-047c649b-ecc3-4577-8dfe-edf30d847bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564479585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1564479585 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.1420096322 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 8383114283 ps |
| CPU time | 92.14 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:36:27 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-341c001b-daa5-4827-af5d-45d24a2bbadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420096322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.1420096322 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.621170366 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 4868278799 ps |
| CPU time | 90.56 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:36:27 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-95780889-9fe1-4ddd-bd40-07e43e25d7ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621170366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.621170366 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.4085773736 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 51163966 ps |
| CPU time | 5.99 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:01 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-e8974928-cc75-4a92-90d0-0f64051c41f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085773736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.4085773736 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2467080054 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 46804877 ps |
| CPU time | 6.39 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:35:00 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-251c87f1-4604-4908-9e7e-40e82fc54068 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467080054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2467080054 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2885707404 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4142014524 ps |
| CPU time | 140.87 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:37:17 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-29a480c4-a999-493a-8704-9c91662f6868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885707404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2885707404 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.572351445 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 8270645360 ps |
| CPU time | 487.4 seconds |
| Started | Jul 20 07:34:56 PM PDT 24 |
| Finished | Jul 20 07:43:05 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5c6a2e56-a604-478c-bed7-9c0cc4020585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572351445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.572351445 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1213016929 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 86527665 ps |
| CPU time | 42.86 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-37e00baf-81c2-4b97-9a0d-4551cf0b1dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213016929 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1213016929 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2266028336 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 307022203 ps |
| CPU time | 16.78 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:35:13 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-eb4ccd95-e6ad-4797-ae7c-55fe1eca0df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266028336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.2266028336 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.4084775872 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 907972157 ps |
| CPU time | 37.04 seconds |
| Started | Jul 20 07:35:00 PM PDT 24 |
| Finished | Jul 20 07:35:37 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-0fec01ae-7f2f-476f-a440-ac5aa41d4f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084775872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .4084775872 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1889371482 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 115359404744 ps |
| CPU time | 2304.39 seconds |
| Started | Jul 20 07:35:03 PM PDT 24 |
| Finished | Jul 20 08:13:28 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-40e34685-d665-42f8-8efd-9cb91d873ee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889371482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1889371482 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.799783275 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 180339211 ps |
| CPU time | 19.43 seconds |
| Started | Jul 20 07:35:08 PM PDT 24 |
| Finished | Jul 20 07:35:28 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-16896d0f-50a1-4ac6-931f-61bb2f0c89c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799783275 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_addr .799783275 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.1058503755 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 237480154 ps |
| CPU time | 11.84 seconds |
| Started | Jul 20 07:35:01 PM PDT 24 |
| Finished | Jul 20 07:35:13 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-c8e69291-03cb-43df-9cc7-5f9010b7acab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058503755 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.1058503755 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.1282780937 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 379766674 ps |
| CPU time | 17.66 seconds |
| Started | Jul 20 07:34:54 PM PDT 24 |
| Finished | Jul 20 07:35:14 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-43ee7e06-e2b9-423a-8fc5-34ab6f599fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282780937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.1282780937 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2207227136 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 9637822252 ps |
| CPU time | 101.05 seconds |
| Started | Jul 20 07:34:55 PM PDT 24 |
| Finished | Jul 20 07:36:38 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-d8bb5f32-2c20-46f2-8120-44c5ea413ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207227136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2207227136 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.4121990606 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 34282579658 ps |
| CPU time | 632.86 seconds |
| Started | Jul 20 07:35:03 PM PDT 24 |
| Finished | Jul 20 07:45:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-b68722bd-7c29-41b8-95e9-b682b1d5da84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121990606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.4121990606 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3466698952 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 631365879 ps |
| CPU time | 51.78 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:47 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-cd5585c6-20e5-4848-b376-0e682096044f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466698952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3466698952 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.3099523671 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 559681353 ps |
| CPU time | 35.78 seconds |
| Started | Jul 20 07:35:02 PM PDT 24 |
| Finished | Jul 20 07:35:38 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-d0bf74b6-4e07-42b2-95f7-81354330369a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099523671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.3099523671 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.2852825404 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 39624436 ps |
| CPU time | 6.06 seconds |
| Started | Jul 20 07:34:53 PM PDT 24 |
| Finished | Jul 20 07:35:01 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-d126732c-e676-41d9-9390-0608c2a59ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852825404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2852825404 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.2532272921 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 6328923990 ps |
| CPU time | 74.11 seconds |
| Started | Jul 20 07:34:55 PM PDT 24 |
| Finished | Jul 20 07:36:11 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-47d757c0-2d59-420e-b5da-7f086c2b46ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532272921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.2532272921 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.4180470119 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 5989731930 ps |
| CPU time | 101.46 seconds |
| Started | Jul 20 07:34:59 PM PDT 24 |
| Finished | Jul 20 07:36:41 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ba0dc022-1c0a-417a-85c4-a475c4a38d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180470119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.4180470119 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3452395513 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 59999195 ps |
| CPU time | 7.41 seconds |
| Started | Jul 20 07:34:52 PM PDT 24 |
| Finished | Jul 20 07:35:01 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-8d6753e9-ccdd-4e79-b31a-2844d231486b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452395513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3452395513 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.573279066 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 11746527422 ps |
| CPU time | 409.11 seconds |
| Started | Jul 20 07:35:06 PM PDT 24 |
| Finished | Jul 20 07:41:56 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-51516c58-cf94-4ad3-b106-fa4e76d3c746 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573279066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.573279066 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3421673610 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 4027842931 ps |
| CPU time | 144.02 seconds |
| Started | Jul 20 07:35:09 PM PDT 24 |
| Finished | Jul 20 07:37:35 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-65601f8a-7406-462d-b54d-a147f8d19b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421673610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3421673610 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1430742612 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2477103946 ps |
| CPU time | 245.9 seconds |
| Started | Jul 20 07:35:07 PM PDT 24 |
| Finished | Jul 20 07:39:14 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-f1d306dc-c48b-40d0-b402-87e28a54c31d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430742612 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1430742612 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1139133753 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 882854147 ps |
| CPU time | 201.24 seconds |
| Started | Jul 20 07:35:07 PM PDT 24 |
| Finished | Jul 20 07:38:29 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-a7690e2b-6024-40c2-920f-aca13456317e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139133753 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1139133753 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.752807471 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 333732582 ps |
| CPU time | 15.61 seconds |
| Started | Jul 20 07:35:11 PM PDT 24 |
| Finished | Jul 20 07:35:27 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-3876e1b5-7f1c-4fa2-81db-557f20dee5d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752807471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.752807471 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3904512979 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 2074014514 ps |
| CPU time | 79.24 seconds |
| Started | Jul 20 07:35:16 PM PDT 24 |
| Finished | Jul 20 07:36:37 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-f1231466-bf02-475d-8423-fb3c5d180a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904512979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .3904512979 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.844277264 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 72610606745 ps |
| CPU time | 1361.04 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:57:59 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-4fdcfe97-26a8-470d-9180-ddf1966d2eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844277264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_d evice_slow_rsp.844277264 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2539701675 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 317050200 ps |
| CPU time | 32.19 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:35:51 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-e83d7bc3-03a5-4c7d-9241-bf4bc9caabc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539701675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2539701675 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.1024931688 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 1625809449 ps |
| CPU time | 58.13 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:36:16 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-9657842e-f481-4d2b-8d45-293154b14447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024931688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.1024931688 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3417930683 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 858726032 ps |
| CPU time | 32.29 seconds |
| Started | Jul 20 07:35:08 PM PDT 24 |
| Finished | Jul 20 07:35:40 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-ead80f8e-9e47-4397-8598-722b163720c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417930683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3417930683 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.3529170422 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 60533096221 ps |
| CPU time | 670.89 seconds |
| Started | Jul 20 07:35:18 PM PDT 24 |
| Finished | Jul 20 07:46:30 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-91251aa1-6b96-429e-ab49-80db4fec067f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529170422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.3529170422 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.698250728 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 60707191599 ps |
| CPU time | 1076.53 seconds |
| Started | Jul 20 07:35:18 PM PDT 24 |
| Finished | Jul 20 07:53:16 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-bb8cd7db-7591-481b-a5fc-6d135174abe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698250728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.698250728 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3112552949 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 293027256 ps |
| CPU time | 23.53 seconds |
| Started | Jul 20 07:35:12 PM PDT 24 |
| Finished | Jul 20 07:35:36 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-23db5b28-77b5-4894-ab7a-4f870f63c3e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112552949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3112552949 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.735926308 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 933380348 ps |
| CPU time | 29.28 seconds |
| Started | Jul 20 07:35:16 PM PDT 24 |
| Finished | Jul 20 07:35:46 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-41821418-5e32-44d1-baa7-751ee71829ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735926308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.735926308 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.350630894 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 54654052 ps |
| CPU time | 7.47 seconds |
| Started | Jul 20 07:35:09 PM PDT 24 |
| Finished | Jul 20 07:35:17 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-185c47f9-3c86-43c7-9071-12bb65b30837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350630894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.350630894 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.26508726 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 8493261365 ps |
| CPU time | 97.18 seconds |
| Started | Jul 20 07:35:06 PM PDT 24 |
| Finished | Jul 20 07:36:44 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f1b3f874-94f3-400b-bb7c-2c3a462fa220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26508726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.26508726 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2148741435 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 6764913177 ps |
| CPU time | 112.03 seconds |
| Started | Jul 20 07:35:10 PM PDT 24 |
| Finished | Jul 20 07:37:03 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-ff291886-d6d3-4efd-bd08-6848aa9b0ce3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148741435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2148741435 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2306632830 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 35731433 ps |
| CPU time | 6.23 seconds |
| Started | Jul 20 07:35:08 PM PDT 24 |
| Finished | Jul 20 07:35:15 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-8e8ddff1-ec97-4c36-b50d-33ca4bba5d5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306632830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2306632830 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.3427421220 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 6731650194 ps |
| CPU time | 250.74 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:39:29 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8f40f159-9055-4830-8c08-a2d6879891ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427421220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.3427421220 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3307364801 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 3037748136 ps |
| CPU time | 240.94 seconds |
| Started | Jul 20 07:35:15 PM PDT 24 |
| Finished | Jul 20 07:39:17 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-c980f926-68ed-4b37-a1ca-69132cdd997b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307364801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3307364801 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3424030742 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2585736492 ps |
| CPU time | 389.88 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:41:48 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-128804f3-efc0-4d0c-bac2-adeccb9f9faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424030742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.3424030742 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.554460412 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 10168644651 ps |
| CPU time | 574.7 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:44:53 PM PDT 24 |
| Peak memory | 582084 kb |
| Host | smart-ea5e5d82-50b2-4ab0-bfdd-3f44c92d2ebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554460412 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_reset_error.554460412 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3731400423 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 1149409870 ps |
| CPU time | 51.4 seconds |
| Started | Jul 20 07:35:21 PM PDT 24 |
| Finished | Jul 20 07:36:13 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-08f0516d-f840-459e-8fe6-c9b2dbd20eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731400423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3731400423 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2761280022 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 3228550194 ps |
| CPU time | 58.35 seconds |
| Started | Jul 20 07:35:24 PM PDT 24 |
| Finished | Jul 20 07:36:24 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-dd2d24b5-eeaa-4708-b955-2e3da7b0cc1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761280022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.2761280022 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.2546683559 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 209703206 ps |
| CPU time | 23.41 seconds |
| Started | Jul 20 07:35:30 PM PDT 24 |
| Finished | Jul 20 07:35:54 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-03dab054-a168-4ce8-8986-425b502bba8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546683559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.2546683559 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2050039852 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 762944542 ps |
| CPU time | 29.65 seconds |
| Started | Jul 20 07:35:26 PM PDT 24 |
| Finished | Jul 20 07:35:56 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-84ada215-68c7-4e57-a896-59d1f13c1115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050039852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2050039852 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.1616402687 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 649821833 ps |
| CPU time | 26.64 seconds |
| Started | Jul 20 07:35:25 PM PDT 24 |
| Finished | Jul 20 07:35:53 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-fe146f69-619a-45c6-8c50-c6f012681f21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616402687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.1616402687 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3299165471 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 49634130681 ps |
| CPU time | 555.03 seconds |
| Started | Jul 20 07:35:26 PM PDT 24 |
| Finished | Jul 20 07:44:41 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-5765d327-d89f-4f13-9d0b-dcc0586ab3cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299165471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3299165471 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1505801363 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 66050428357 ps |
| CPU time | 1106.64 seconds |
| Started | Jul 20 07:35:25 PM PDT 24 |
| Finished | Jul 20 07:53:52 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-4b4bf45d-ab26-411c-90f2-8f02441cecbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505801363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1505801363 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.598625800 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 113576758 ps |
| CPU time | 12.99 seconds |
| Started | Jul 20 07:35:25 PM PDT 24 |
| Finished | Jul 20 07:35:39 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-470e50c9-3c46-4a49-b1e9-1b5e737417cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598625800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.598625800 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2012623978 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1023731411 ps |
| CPU time | 27.16 seconds |
| Started | Jul 20 07:35:24 PM PDT 24 |
| Finished | Jul 20 07:35:52 PM PDT 24 |
| Peak memory | 575248 kb |
| Host | smart-fad7e89f-bc77-44ae-9b14-c0d5b2c4bcf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012623978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2012623978 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.2969782494 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 44279944 ps |
| CPU time | 6.36 seconds |
| Started | Jul 20 07:35:17 PM PDT 24 |
| Finished | Jul 20 07:35:24 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-589c623d-ec9e-44f7-b4e9-04ff1f89f57e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969782494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.2969782494 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.328112504 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 9277785438 ps |
| CPU time | 99.1 seconds |
| Started | Jul 20 07:35:24 PM PDT 24 |
| Finished | Jul 20 07:37:04 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-0732a855-5b71-476a-8cef-570fe9e37347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328112504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.328112504 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.1942816304 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 4969815599 ps |
| CPU time | 83.77 seconds |
| Started | Jul 20 07:35:23 PM PDT 24 |
| Finished | Jul 20 07:36:48 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-c1b3ec3a-1ca8-42d4-a2fe-31608755c4cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942816304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.1942816304 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.3769577440 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 38712164 ps |
| CPU time | 6.01 seconds |
| Started | Jul 20 07:35:16 PM PDT 24 |
| Finished | Jul 20 07:35:23 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-c7b84fba-1e83-4690-8460-714c29100621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769577440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.3769577440 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2040919178 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 8898192066 ps |
| CPU time | 361.02 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:41:41 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-ab3be576-321e-4278-a6f7-d899916ec157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040919178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2040919178 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.253393825 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 1141870620 ps |
| CPU time | 90 seconds |
| Started | Jul 20 07:35:32 PM PDT 24 |
| Finished | Jul 20 07:37:02 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-2810f935-6fd2-4474-9bf1-c6242fb72d18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253393825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.253393825 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3310037812 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 827713461 ps |
| CPU time | 207.13 seconds |
| Started | Jul 20 07:35:37 PM PDT 24 |
| Finished | Jul 20 07:39:04 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-1884f946-3b88-437d-a34d-dde7666d86b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310037812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3310037812 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.1969262961 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 87631597 ps |
| CPU time | 25.15 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:36:04 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-4fbed221-f322-47a1-9201-91575e25dfa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969262961 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.1969262961 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3550820607 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1313792753 ps |
| CPU time | 57.98 seconds |
| Started | Jul 20 07:35:25 PM PDT 24 |
| Finished | Jul 20 07:36:24 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-617c5a50-9e77-4d6b-bc44-411b78b7b655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550820607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3550820607 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2644283008 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 3356962470 ps |
| CPU time | 141.4 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:38:01 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3e1b503f-f7ad-4b5a-aac7-c92e2cb3473e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644283008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2644283008 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.561596096 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 46214556638 ps |
| CPU time | 871.07 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:50:11 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-6ae3e14a-d043-452a-8f4a-8bf4f75340f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561596096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.561596096 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.2536819150 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 88202886 ps |
| CPU time | 11.2 seconds |
| Started | Jul 20 07:35:40 PM PDT 24 |
| Finished | Jul 20 07:35:53 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-df515364-03b1-4152-adcf-04100ab552a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536819150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.2536819150 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2092135945 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 384625050 ps |
| CPU time | 15.5 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:35:55 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-fb7164c5-34c1-45b1-a715-0aead5cd2708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092135945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2092135945 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.3485830285 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 613964694 ps |
| CPU time | 48.51 seconds |
| Started | Jul 20 07:35:36 PM PDT 24 |
| Finished | Jul 20 07:36:25 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-6f09109e-e356-4e4e-b154-7c98b9cd48c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485830285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.3485830285 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.212235827 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 30494524123 ps |
| CPU time | 336.95 seconds |
| Started | Jul 20 07:35:39 PM PDT 24 |
| Finished | Jul 20 07:41:17 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-d8b84f1c-e9c6-4826-b4d5-57be38c692c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212235827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.212235827 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2460741806 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 35657093368 ps |
| CPU time | 611.73 seconds |
| Started | Jul 20 07:35:47 PM PDT 24 |
| Finished | Jul 20 07:46:00 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-ee9c4a61-4a27-4c75-aaaf-1355b5075240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460741806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2460741806 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1054555801 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 406996616 ps |
| CPU time | 37.85 seconds |
| Started | Jul 20 07:35:36 PM PDT 24 |
| Finished | Jul 20 07:36:15 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-32653c08-7c4e-4b3d-aa15-c8f60cd43c5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054555801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.1054555801 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2845244235 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1383775844 ps |
| CPU time | 42.11 seconds |
| Started | Jul 20 07:35:47 PM PDT 24 |
| Finished | Jul 20 07:36:30 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-89da64fe-37ae-4469-a5c6-20ecd5e069d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845244235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2845244235 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.430314625 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 55116935 ps |
| CPU time | 6.09 seconds |
| Started | Jul 20 07:35:33 PM PDT 24 |
| Finished | Jul 20 07:35:40 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-6dab07ee-f338-4239-841d-ba8bde5dc0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430314625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.430314625 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.487220250 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 8122232761 ps |
| CPU time | 94.58 seconds |
| Started | Jul 20 07:35:34 PM PDT 24 |
| Finished | Jul 20 07:37:09 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-43802b67-3bd9-4a3e-84a8-19b57b3c12a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487220250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.487220250 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.1836365056 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 5693665925 ps |
| CPU time | 103.05 seconds |
| Started | Jul 20 07:35:34 PM PDT 24 |
| Finished | Jul 20 07:37:17 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-14de57e9-089c-455f-a562-eeb3d09f6b3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836365056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.1836365056 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.335345763 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 51195276 ps |
| CPU time | 6.43 seconds |
| Started | Jul 20 07:35:34 PM PDT 24 |
| Finished | Jul 20 07:35:41 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-4c51bbbf-3566-41b0-93e4-6f3ffd21697b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335345763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .335345763 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3044728883 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 6491484679 ps |
| CPU time | 240.2 seconds |
| Started | Jul 20 07:35:46 PM PDT 24 |
| Finished | Jul 20 07:39:47 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-c273f715-a589-4177-8576-4cecf74c74b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044728883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3044728883 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.723447400 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 17430162884 ps |
| CPU time | 589.6 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:45:28 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-62a9e2f7-9106-4ac9-8352-348fccd22518 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723447400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.723447400 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.727429020 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 104206470 ps |
| CPU time | 108.01 seconds |
| Started | Jul 20 07:35:40 PM PDT 24 |
| Finished | Jul 20 07:37:29 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-d0f5f3de-e731-453d-a260-322cf090fcfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727429020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.727429020 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.322307826 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 3838267684 ps |
| CPU time | 428.1 seconds |
| Started | Jul 20 07:35:41 PM PDT 24 |
| Finished | Jul 20 07:42:50 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-36f3eb1c-e120-4229-90fb-debea2120f5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322307826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.322307826 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3585921565 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 161035874 ps |
| CPU time | 20.51 seconds |
| Started | Jul 20 07:35:47 PM PDT 24 |
| Finished | Jul 20 07:36:09 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-2b517713-4a64-4ea4-942e-3f25f69decf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585921565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3585921565 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2753855496 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 77472245 ps |
| CPU time | 7.92 seconds |
| Started | Jul 20 07:35:51 PM PDT 24 |
| Finished | Jul 20 07:35:59 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-7546ec19-8407-410e-a351-223eaf60f3a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753855496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2753855496 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.3968801834 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 118674469208 ps |
| CPU time | 2462.31 seconds |
| Started | Jul 20 07:35:51 PM PDT 24 |
| Finished | Jul 20 08:16:55 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-9b8c91dc-f2b0-4ee6-ab4a-701338dc2541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968801834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.3968801834 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.4275358970 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 1050199210 ps |
| CPU time | 43.92 seconds |
| Started | Jul 20 07:36:03 PM PDT 24 |
| Finished | Jul 20 07:36:48 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-85d16bd4-7366-4b00-83be-69622d1ca61c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275358970 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_add r.4275358970 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2769373205 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 588756330 ps |
| CPU time | 23.09 seconds |
| Started | Jul 20 07:35:49 PM PDT 24 |
| Finished | Jul 20 07:36:13 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d3d5f4bd-4ae3-428a-90d5-a9b82a009fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769373205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2769373205 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.713768657 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 2485699866 ps |
| CPU time | 102.29 seconds |
| Started | Jul 20 07:35:48 PM PDT 24 |
| Finished | Jul 20 07:37:31 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-abfbbc85-29d3-4bb8-8723-c82346a2184b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713768657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.713768657 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2331524945 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 3854283153 ps |
| CPU time | 43.51 seconds |
| Started | Jul 20 07:35:53 PM PDT 24 |
| Finished | Jul 20 07:36:37 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-8b6745da-66b6-47cd-8b4c-317af999e5c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331524945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2331524945 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.2469204372 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 41784207682 ps |
| CPU time | 707.52 seconds |
| Started | Jul 20 07:35:48 PM PDT 24 |
| Finished | Jul 20 07:47:37 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-2c83b8dc-c41a-4936-a1b1-ee23d9c773c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469204372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.2469204372 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3628464478 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 128123371 ps |
| CPU time | 14.49 seconds |
| Started | Jul 20 07:35:53 PM PDT 24 |
| Finished | Jul 20 07:36:08 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-b8db7bc1-7edc-4f60-ab9f-d9f9b3a8349f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628464478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3628464478 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1964974412 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 2128631768 ps |
| CPU time | 60.46 seconds |
| Started | Jul 20 07:35:49 PM PDT 24 |
| Finished | Jul 20 07:36:50 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-105123bc-b1d7-469c-9ae0-345f0196e20d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964974412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1964974412 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.4220487327 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 46624930 ps |
| CPU time | 6.36 seconds |
| Started | Jul 20 07:35:38 PM PDT 24 |
| Finished | Jul 20 07:35:45 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-cccc2ed9-4278-41ed-8f4d-f435d23f52ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220487327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.4220487327 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.874532670 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 9787360662 ps |
| CPU time | 106.88 seconds |
| Started | Jul 20 07:35:48 PM PDT 24 |
| Finished | Jul 20 07:37:36 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-f1a94833-1784-407a-af0b-9f5c558c6b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874532670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.874532670 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.4144053344 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 5327248276 ps |
| CPU time | 92.62 seconds |
| Started | Jul 20 07:35:49 PM PDT 24 |
| Finished | Jul 20 07:37:22 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-6a59d9bd-0fb6-4fbe-9e9d-b13900815f24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144053344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.4144053344 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3425864779 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 51026808 ps |
| CPU time | 6.71 seconds |
| Started | Jul 20 07:35:40 PM PDT 24 |
| Finished | Jul 20 07:35:48 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-2767a27a-71c4-4688-bfa7-7fead58f032a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425864779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.3425864779 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.365303874 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1945933480 ps |
| CPU time | 160.97 seconds |
| Started | Jul 20 07:35:55 PM PDT 24 |
| Finished | Jul 20 07:38:37 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-1b5b7f09-f8f0-4fc5-9d6c-11f3d57d2e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365303874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.365303874 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2184637165 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 9611888496 ps |
| CPU time | 509.62 seconds |
| Started | Jul 20 07:35:57 PM PDT 24 |
| Finished | Jul 20 07:44:27 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-f966c2c5-52f7-4d9f-b67f-881e2403a47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184637165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2184637165 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2425928417 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 4766332104 ps |
| CPU time | 384.38 seconds |
| Started | Jul 20 07:36:02 PM PDT 24 |
| Finished | Jul 20 07:42:27 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-6d81e8e1-4497-4447-8e42-a11332619045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425928417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2425928417 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.3098548702 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 329489405 ps |
| CPU time | 15.02 seconds |
| Started | Jul 20 07:35:58 PM PDT 24 |
| Finished | Jul 20 07:36:14 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-687c0655-4aa4-41f9-93f1-0824d8f0618e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098548702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.3098548702 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.332512845 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 952111062 ps |
| CPU time | 66.83 seconds |
| Started | Jul 20 07:35:56 PM PDT 24 |
| Finished | Jul 20 07:37:03 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c519822e-3ac5-4b0f-8bbd-dec449f368e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332512845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device. 332512845 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.2062111327 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 152056101291 ps |
| CPU time | 3026.18 seconds |
| Started | Jul 20 07:35:54 PM PDT 24 |
| Finished | Jul 20 08:26:21 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-16e82c97-11eb-495d-97d8-268c682ae00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062111327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.2062111327 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3062855431 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 125280084 ps |
| CPU time | 14.65 seconds |
| Started | Jul 20 07:36:03 PM PDT 24 |
| Finished | Jul 20 07:36:18 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-912dac76-46a7-4247-ac7b-18a63e42dea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062855431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.3062855431 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2917762455 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 2325705789 ps |
| CPU time | 86.1 seconds |
| Started | Jul 20 07:36:09 PM PDT 24 |
| Finished | Jul 20 07:37:36 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-4476e4ec-8085-47be-a20c-4729a2fd179f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917762455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2917762455 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1216084598 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 239521092 ps |
| CPU time | 18.76 seconds |
| Started | Jul 20 07:35:57 PM PDT 24 |
| Finished | Jul 20 07:36:17 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-02be44b1-5131-4b4a-8f0a-583ad42a2ea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216084598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1216084598 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.640474059 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 75726467801 ps |
| CPU time | 852.72 seconds |
| Started | Jul 20 07:35:59 PM PDT 24 |
| Finished | Jul 20 07:50:12 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-81d6c658-aa57-4350-8ca1-57132fc73683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640474059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.640474059 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.455479697 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 31789835716 ps |
| CPU time | 591.51 seconds |
| Started | Jul 20 07:35:56 PM PDT 24 |
| Finished | Jul 20 07:45:49 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-9fdb99b1-cff7-436f-90cd-ff2588996780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455479697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.455479697 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.215266148 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 592670380 ps |
| CPU time | 56.56 seconds |
| Started | Jul 20 07:35:57 PM PDT 24 |
| Finished | Jul 20 07:36:54 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-b4bb52c7-7888-4003-9fec-8128f19b7ee9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215266148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_dela ys.215266148 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.777659048 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 1548343489 ps |
| CPU time | 50.76 seconds |
| Started | Jul 20 07:36:05 PM PDT 24 |
| Finished | Jul 20 07:36:56 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-befa0db0-b6b5-4b04-a7ae-21f699e3bc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777659048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.777659048 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1659149430 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 38630125 ps |
| CPU time | 5.78 seconds |
| Started | Jul 20 07:35:55 PM PDT 24 |
| Finished | Jul 20 07:36:02 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-48dfb30d-05c9-42c3-869e-b255f7f7a52e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659149430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1659149430 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.3089303627 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 8645267495 ps |
| CPU time | 101.41 seconds |
| Started | Jul 20 07:35:56 PM PDT 24 |
| Finished | Jul 20 07:37:38 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-c9307e9f-0c80-4e9c-be6c-5c129239653e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089303627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.3089303627 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.3042896712 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 5297977240 ps |
| CPU time | 94.99 seconds |
| Started | Jul 20 07:35:55 PM PDT 24 |
| Finished | Jul 20 07:37:31 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-e662cb85-bdb1-4b96-971a-f1fb007237c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042896712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.3042896712 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.2467985599 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 42745292 ps |
| CPU time | 6.45 seconds |
| Started | Jul 20 07:36:02 PM PDT 24 |
| Finished | Jul 20 07:36:09 PM PDT 24 |
| Peak memory | 575256 kb |
| Host | smart-fe290108-b143-4020-8c0f-f0f6ee6e7ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467985599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.2467985599 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.4256087355 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 1900375361 ps |
| CPU time | 151.4 seconds |
| Started | Jul 20 07:36:03 PM PDT 24 |
| Finished | Jul 20 07:38:35 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-4b79991c-5ec7-4169-b2ba-a0c45ba20e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256087355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.4256087355 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3017113029 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 221017616 ps |
| CPU time | 23.96 seconds |
| Started | Jul 20 07:36:09 PM PDT 24 |
| Finished | Jul 20 07:36:33 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-8b7f4b56-0da5-4701-b2c7-eb258ee91a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017113029 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3017113029 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2871199417 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 8007322507 ps |
| CPU time | 937.65 seconds |
| Started | Jul 20 07:36:09 PM PDT 24 |
| Finished | Jul 20 07:51:48 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-26569c33-ad24-4f26-9c2f-392e0e220695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871199417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2871199417 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2001978813 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 2766578464 ps |
| CPU time | 241.82 seconds |
| Started | Jul 20 07:36:09 PM PDT 24 |
| Finished | Jul 20 07:40:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-238678d5-cdeb-43c8-89cd-f7efa4955974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001978813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2001978813 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3197924492 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 213070866 ps |
| CPU time | 23.95 seconds |
| Started | Jul 20 07:36:03 PM PDT 24 |
| Finished | Jul 20 07:36:27 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-6a609c19-5077-4790-9a4b-f41fd5ebf724 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197924492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3197924492 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.1950715715 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 491472946 ps |
| CPU time | 55.26 seconds |
| Started | Jul 20 07:36:12 PM PDT 24 |
| Finished | Jul 20 07:37:09 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-f7e206c5-bda6-4d40-a0f6-487352c4140f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950715715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .1950715715 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.2177958579 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 11070669277 ps |
| CPU time | 175.49 seconds |
| Started | Jul 20 07:36:11 PM PDT 24 |
| Finished | Jul 20 07:39:08 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-688bf7eb-a259-4687-a4eb-4b0b78e9508e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177958579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.2177958579 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2421687237 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 277869349 ps |
| CPU time | 30.77 seconds |
| Started | Jul 20 07:36:13 PM PDT 24 |
| Finished | Jul 20 07:36:45 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f1e32fc5-582b-4334-899f-21de99454c6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421687237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2421687237 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.1516989844 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 1246696777 ps |
| CPU time | 39.67 seconds |
| Started | Jul 20 07:36:11 PM PDT 24 |
| Finished | Jul 20 07:36:52 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-bf403edc-7e25-4301-b7b6-e601e2157868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516989844 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.1516989844 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.728449924 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 40911805 ps |
| CPU time | 6.65 seconds |
| Started | Jul 20 07:36:12 PM PDT 24 |
| Finished | Jul 20 07:36:20 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-2da4c6e3-3a6a-4f14-9b48-8eea85d108ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728449924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.728449924 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.4056666927 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 82368110499 ps |
| CPU time | 986.56 seconds |
| Started | Jul 20 07:36:14 PM PDT 24 |
| Finished | Jul 20 07:52:42 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-d057e3bb-881b-43a8-9593-5f0d0244582a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056666927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.4056666927 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3338945929 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 54945100040 ps |
| CPU time | 1053.41 seconds |
| Started | Jul 20 07:36:12 PM PDT 24 |
| Finished | Jul 20 07:53:47 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-452d513e-6e6e-4937-9078-5c0731657dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338945929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3338945929 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2383844003 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 492323686 ps |
| CPU time | 39.78 seconds |
| Started | Jul 20 07:36:13 PM PDT 24 |
| Finished | Jul 20 07:36:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-d4fd6f48-f789-4de7-a15d-a3270cee7623 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383844003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.2383844003 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.211808458 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 90195048 ps |
| CPU time | 8.96 seconds |
| Started | Jul 20 07:36:12 PM PDT 24 |
| Finished | Jul 20 07:36:23 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-02bb1db7-6254-467b-9c6b-c07c6f401a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211808458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.211808458 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.4202830645 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 236599968 ps |
| CPU time | 10.55 seconds |
| Started | Jul 20 07:36:03 PM PDT 24 |
| Finished | Jul 20 07:36:15 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-bd9b2ade-6198-498c-8319-55b9fc4971dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202830645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.4202830645 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.4114412375 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 8576421270 ps |
| CPU time | 94.24 seconds |
| Started | Jul 20 07:36:11 PM PDT 24 |
| Finished | Jul 20 07:37:46 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-b4c2516e-d086-4829-bd05-bd1fe09123d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114412375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.4114412375 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2185769535 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 3889093889 ps |
| CPU time | 67.19 seconds |
| Started | Jul 20 07:36:13 PM PDT 24 |
| Finished | Jul 20 07:37:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-30d954de-5bcd-4d57-9f0b-1851e50ee507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185769535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2185769535 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.1198819719 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 45141538 ps |
| CPU time | 6.05 seconds |
| Started | Jul 20 07:36:05 PM PDT 24 |
| Finished | Jul 20 07:36:12 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-55414f2e-0ff9-4e57-a532-89e47538ff18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198819719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.1198819719 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1097751110 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 2066045063 ps |
| CPU time | 78.9 seconds |
| Started | Jul 20 07:36:17 PM PDT 24 |
| Finished | Jul 20 07:37:37 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-155716b5-d4d2-43a7-b96d-9048dabbae03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097751110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1097751110 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.1717456636 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 1355639453 ps |
| CPU time | 44.1 seconds |
| Started | Jul 20 07:36:12 PM PDT 24 |
| Finished | Jul 20 07:36:58 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-59ceff4d-6172-4f80-912a-88649a00c613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717456636 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.1717456636 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4039219525 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 402933954 ps |
| CPU time | 143.18 seconds |
| Started | Jul 20 07:36:14 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-5c0670ad-7228-4996-9aff-6df00503f406 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039219525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.4039219525 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3121803607 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 7840473821 ps |
| CPU time | 310.67 seconds |
| Started | Jul 20 07:36:13 PM PDT 24 |
| Finished | Jul 20 07:41:25 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-b230447a-f7ee-461f-9b07-aeb81da88dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121803607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3121803607 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1035591119 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 928428754 ps |
| CPU time | 36.42 seconds |
| Started | Jul 20 07:36:16 PM PDT 24 |
| Finished | Jul 20 07:36:53 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-ed840238-8b99-4a67-a47e-7e254b414698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035591119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.1035591119 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.2127187637 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1489886702 ps |
| CPU time | 99.37 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:38:10 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-44a9a27b-e157-47af-9f21-f1362451da5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127187637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .2127187637 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.3536040697 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 74627923954 ps |
| CPU time | 1384.04 seconds |
| Started | Jul 20 07:36:32 PM PDT 24 |
| Finished | Jul 20 07:59:37 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-5b1359bb-2b99-44a5-89b8-26323a773516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536040697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.3536040697 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.826553894 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 25489408 ps |
| CPU time | 5.7 seconds |
| Started | Jul 20 07:36:28 PM PDT 24 |
| Finished | Jul 20 07:36:34 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-cb5825eb-f7df-4328-a57b-250d17c91625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826553894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_addr .826553894 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.604253837 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 1921770491 ps |
| CPU time | 72.95 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:37:42 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-54663288-ac89-47a2-a869-7805d55d1fe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604253837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.604253837 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1944837276 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 582993810 ps |
| CPU time | 50.69 seconds |
| Started | Jul 20 07:36:17 PM PDT 24 |
| Finished | Jul 20 07:37:09 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-a6c8b884-ee98-48eb-adf0-d1cd47192061 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944837276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1944837276 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2617578549 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 17500108129 ps |
| CPU time | 208.34 seconds |
| Started | Jul 20 07:36:27 PM PDT 24 |
| Finished | Jul 20 07:39:56 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-43938be7-5ed7-434f-9e5e-6ca6df412fc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617578549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2617578549 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3831527138 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 66470259685 ps |
| CPU time | 1207.67 seconds |
| Started | Jul 20 07:36:27 PM PDT 24 |
| Finished | Jul 20 07:56:36 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-90e4c36d-da32-4f75-a197-b7ab1b89374a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831527138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3831527138 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.753348571 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 149740392 ps |
| CPU time | 17.03 seconds |
| Started | Jul 20 07:36:27 PM PDT 24 |
| Finished | Jul 20 07:36:44 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-1b2494c1-967f-442b-9dcc-7596aa3d670e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753348571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.753348571 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.4057828904 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 2536985797 ps |
| CPU time | 87.52 seconds |
| Started | Jul 20 07:36:27 PM PDT 24 |
| Finished | Jul 20 07:37:55 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-024a461e-9cb9-4912-9c5b-c9345a490f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057828904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.4057828904 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.886648742 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 222738121 ps |
| CPU time | 9.94 seconds |
| Started | Jul 20 07:36:17 PM PDT 24 |
| Finished | Jul 20 07:36:27 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-00004738-392e-4eb8-b5f3-21c4c23d5803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886648742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.886648742 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.202725395 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 7036523582 ps |
| CPU time | 80.53 seconds |
| Started | Jul 20 07:36:13 PM PDT 24 |
| Finished | Jul 20 07:37:35 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-f7ce3e9d-39e6-40c0-8493-41b71e7b1962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202725395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.202725395 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.1001158555 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 6156802164 ps |
| CPU time | 115.12 seconds |
| Started | Jul 20 07:36:11 PM PDT 24 |
| Finished | Jul 20 07:38:07 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-daa4fc87-2f24-4c55-8acd-1443ad0058ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001158555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.1001158555 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.57999437 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 51840021 ps |
| CPU time | 6.74 seconds |
| Started | Jul 20 07:36:11 PM PDT 24 |
| Finished | Jul 20 07:36:19 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-cc583125-2496-48cd-a33e-929fe1ce474d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57999437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays.57999437 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.1667772020 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 1774288313 ps |
| CPU time | 166.64 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:39:17 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-7dce2fa0-f45d-45dc-ae9a-1c8fb9d7290e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667772020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1667772020 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2909722015 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 8635492189 ps |
| CPU time | 357.87 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:42:28 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-dcf61406-6e74-45ec-a781-bed08357a565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909722015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2909722015 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.4194304837 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 72151249 ps |
| CPU time | 17.13 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:36:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-444cbee6-6797-42ff-b246-df0a2dc7d191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194304837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.4194304837 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2580364567 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 574745466 ps |
| CPU time | 210.52 seconds |
| Started | Jul 20 07:36:30 PM PDT 24 |
| Finished | Jul 20 07:40:01 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-c82937da-1028-4a32-be96-2b3fe830f0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580364567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2580364567 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.139663371 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 91163188 ps |
| CPU time | 11.98 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:36:43 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-39d57bed-5085-4a21-a0ec-58502f0b6e6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139663371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.139663371 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1982635449 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 1836706515 ps |
| CPU time | 81.76 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:37:54 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-f5910bb6-e313-443d-974d-e1352d02c048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982635449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1982635449 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.1563254719 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 112283591817 ps |
| CPU time | 2011.3 seconds |
| Started | Jul 20 07:36:32 PM PDT 24 |
| Finished | Jul 20 08:10:04 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-13f3c9c9-42ca-4700-812c-1263cdb382e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563254719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.1563254719 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2644465303 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 843320876 ps |
| CPU time | 35.82 seconds |
| Started | Jul 20 07:36:30 PM PDT 24 |
| Finished | Jul 20 07:37:06 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-15ff9ff0-ee96-42dd-80c5-b395143b643d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644465303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.2644465303 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3071554727 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 260153688 ps |
| CPU time | 21.17 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:36:52 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-082ff25a-8d7e-41b5-9154-b01dc605ec29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071554727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3071554727 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2719546920 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 34407836 ps |
| CPU time | 6.12 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:36:36 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-6b513be0-09b3-489e-90fd-7ab8c9f4b838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719546920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2719546920 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3480694673 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 34666362416 ps |
| CPU time | 384.38 seconds |
| Started | Jul 20 07:36:28 PM PDT 24 |
| Finished | Jul 20 07:42:53 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-8d5ca25f-868d-4fec-829e-38bdef6c56d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480694673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3480694673 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3965650565 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 55990348644 ps |
| CPU time | 1030.97 seconds |
| Started | Jul 20 07:36:28 PM PDT 24 |
| Finished | Jul 20 07:53:40 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-d60db21a-a798-4300-9d43-1d5bf51cb7c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965650565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3965650565 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1002950710 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 584222940 ps |
| CPU time | 49 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:37:21 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-7fb15a12-f072-4a9c-8531-5cb038660e0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002950710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.1002950710 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3551186798 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 199448786 ps |
| CPU time | 17.09 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:36:49 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-b2b37b76-9150-46c5-8e12-469f56cf59a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551186798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3551186798 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3646235614 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 193459545 ps |
| CPU time | 9 seconds |
| Started | Jul 20 07:36:27 PM PDT 24 |
| Finished | Jul 20 07:36:37 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-81b51b68-6020-470d-8379-15bbc015a1c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646235614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3646235614 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.941172366 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 8296541633 ps |
| CPU time | 92.98 seconds |
| Started | Jul 20 07:36:28 PM PDT 24 |
| Finished | Jul 20 07:38:02 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2af861ee-2b98-4891-ac2c-a9090fc16f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941172366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.941172366 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.3254436640 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 5727723595 ps |
| CPU time | 98.47 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:38:11 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-40904409-78ce-471c-bb92-834325b7e412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254436640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.3254436640 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.2062824948 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 39406918 ps |
| CPU time | 6 seconds |
| Started | Jul 20 07:36:28 PM PDT 24 |
| Finished | Jul 20 07:36:35 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-039c0608-29eb-440e-ac0c-3ace538548dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062824948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.2062824948 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.3128663989 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 5712520411 ps |
| CPU time | 467.96 seconds |
| Started | Jul 20 07:36:33 PM PDT 24 |
| Finished | Jul 20 07:44:22 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-62642552-a26a-4b7d-a2fc-211f988617ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128663989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3128663989 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1585585538 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 1177171528 ps |
| CPU time | 117.57 seconds |
| Started | Jul 20 07:36:33 PM PDT 24 |
| Finished | Jul 20 07:38:31 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d140fe67-6519-4a37-87ae-9a438718a040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585585538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1585585538 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.451901740 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1850585163 ps |
| CPU time | 384.63 seconds |
| Started | Jul 20 07:36:30 PM PDT 24 |
| Finished | Jul 20 07:42:56 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-eac99c83-144f-4c01-a1c7-45e3a9c2a4d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451901740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_ with_rand_reset.451901740 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3288893018 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 128652163 ps |
| CPU time | 53.04 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:37:23 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-fb31ce61-5d95-476c-bd4f-68e8e94388e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288893018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3288893018 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.4195129907 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1190839686 ps |
| CPU time | 58.71 seconds |
| Started | Jul 20 07:36:29 PM PDT 24 |
| Finished | Jul 20 07:37:28 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-0aa6f5da-a483-47d8-8a9a-4ece66778599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195129907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.4195129907 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2098913017 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 7423880180 ps |
| CPU time | 590.57 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:32:45 PM PDT 24 |
| Peak memory | 638664 kb |
| Host | smart-a67edb25-3ea5-4b2f-893d-4691becf57fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098913017 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2098913017 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.1767502135 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 4264682400 ps |
| CPU time | 309.11 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:28:02 PM PDT 24 |
| Peak memory | 599356 kb |
| Host | smart-1869e152-5794-4fb4-b8db-87ef1e6fbae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767502135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.1767502135 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1394948439 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 29764209150 ps |
| CPU time | 4371.32 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 08:35:38 PM PDT 24 |
| Peak memory | 593048 kb |
| Host | smart-d1d35b8d-efd4-4368-b38b-193d35e53179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394948439 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1394948439 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.1378248453 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 1532278665 ps |
| CPU time | 62.15 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:23:49 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-a40126eb-4c70-412f-b969-52d8cd17fbe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378248453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 1378248453 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.626324974 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 167084428644 ps |
| CPU time | 3030.2 seconds |
| Started | Jul 20 07:22:55 PM PDT 24 |
| Finished | Jul 20 08:13:27 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-15ccfe60-6af4-4c84-876e-aeb04b863791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626324974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_de vice_slow_rsp.626324974 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1792313450 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 1205751812 ps |
| CPU time | 53.39 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:23:47 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7905149e-d759-40b6-b261-90f88305dcc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792313450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1792313450 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.2267954591 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 2107158348 ps |
| CPU time | 79.4 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 07:24:15 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-9c5c0e1a-5da2-4f2b-996c-96d771c48a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267954591 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.2267954591 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2906309111 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 1657502450 ps |
| CPU time | 58.89 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:23:45 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c13c2da2-7394-4fbb-af4a-b9a0b779b793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906309111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2906309111 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1108704093 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 104288055759 ps |
| CPU time | 1190.54 seconds |
| Started | Jul 20 07:22:47 PM PDT 24 |
| Finished | Jul 20 07:42:39 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1f116a9a-31ba-4a58-ad85-0423ef896723 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108704093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1108704093 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.1509638422 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 44882474403 ps |
| CPU time | 741.43 seconds |
| Started | Jul 20 07:22:47 PM PDT 24 |
| Finished | Jul 20 07:35:10 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-e0877df3-556d-4d3a-a8ce-88bce93024e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509638422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.1509638422 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3316728203 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 384582759 ps |
| CPU time | 35.57 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 07:23:32 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ff99a9bf-5bc1-4c67-9796-902df43f9d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316728203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3316728203 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.1028799235 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 2703090256 ps |
| CPU time | 81.14 seconds |
| Started | Jul 20 07:22:49 PM PDT 24 |
| Finished | Jul 20 07:24:11 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-93df1a6c-42c0-4d67-92f8-05f9fe105e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028799235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1028799235 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.4059819194 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 51855588 ps |
| CPU time | 6.59 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:22:53 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-bf638bed-835b-4427-a10e-9288ed3ed32d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059819194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.4059819194 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1623603952 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 8545463654 ps |
| CPU time | 92.8 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:24:19 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2cfe88d1-d19f-406d-86e6-0a43de4115d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623603952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1623603952 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.1727614344 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 5305741203 ps |
| CPU time | 91.76 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 07:24:28 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-97783d0a-61b8-4420-842b-b1489ef2cbba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727614344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.1727614344 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3478793989 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 37242192 ps |
| CPU time | 6.4 seconds |
| Started | Jul 20 07:22:45 PM PDT 24 |
| Finished | Jul 20 07:22:52 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e197a8fb-f398-4c66-9dc6-f23c72e3c3b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478793989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3478793989 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.4009664508 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 13091591301 ps |
| CPU time | 480.58 seconds |
| Started | Jul 20 07:22:51 PM PDT 24 |
| Finished | Jul 20 07:30:52 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-f77f1bf9-b0f1-4400-8395-ee742d411b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009664508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.4009664508 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1867503534 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 2068963293 ps |
| CPU time | 160.37 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:25:36 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-590f95f6-5e7f-4ac7-b1bf-607436b15303 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867503534 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1867503534 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.578377499 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 3509621856 ps |
| CPU time | 399.2 seconds |
| Started | Jul 20 07:22:56 PM PDT 24 |
| Finished | Jul 20 07:29:36 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-683dee05-e697-4c51-aeb6-294c1f2cdc56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578377499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_reset_error.578377499 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.816164901 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 1203252880 ps |
| CPU time | 51.64 seconds |
| Started | Jul 20 07:22:55 PM PDT 24 |
| Finished | Jul 20 07:23:48 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-12cd851c-c4b9-441c-9654-3c35ba0aaacb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816164901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.816164901 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1818801435 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 1459452987 ps |
| CPU time | 62.15 seconds |
| Started | Jul 20 07:36:38 PM PDT 24 |
| Finished | Jul 20 07:37:41 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-8e1c83fa-035c-43f7-9538-bb66e46f4072 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818801435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1818801435 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.2781229696 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 65998528756 ps |
| CPU time | 1254.91 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:57:35 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-a7724f1f-ea14-40de-a443-08c488e6cc78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781229696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.2781229696 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.800476989 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 205226361 ps |
| CPU time | 20.55 seconds |
| Started | Jul 20 07:36:41 PM PDT 24 |
| Finished | Jul 20 07:37:02 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-3d0caaee-8c52-4aad-b78d-fcf4a28454ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800476989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .800476989 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3867845379 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 886424848 ps |
| CPU time | 29.78 seconds |
| Started | Jul 20 07:36:42 PM PDT 24 |
| Finished | Jul 20 07:37:13 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-20debeab-f44c-40e5-ba80-b5ac523ad592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867845379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3867845379 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.3091896677 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 557572886 ps |
| CPU time | 48.35 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:37:27 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-2dda33ad-9be1-46a7-a579-218baf3b5e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091896677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.3091896677 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.3577404425 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 11747933714 ps |
| CPU time | 136.42 seconds |
| Started | Jul 20 07:36:40 PM PDT 24 |
| Finished | Jul 20 07:38:57 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-4ea6142f-bd8f-4e46-8ea7-3c2a8c856e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577404425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.3577404425 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2259440337 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 42354494889 ps |
| CPU time | 739.62 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:49:00 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-9e04cdf4-bead-4968-82db-ea0f5220e99a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259440337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2259440337 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.3579407086 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 32563690 ps |
| CPU time | 5.75 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:36:46 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-ca575eec-2537-4022-bbd5-dbd66a64b61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579407086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.3579407086 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.3758993132 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 296605323 ps |
| CPU time | 23.72 seconds |
| Started | Jul 20 07:36:42 PM PDT 24 |
| Finished | Jul 20 07:37:07 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-0d23ce70-f1a9-4bc3-a6fd-6acca2f254c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758993132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.3758993132 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.3823410024 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 178935414 ps |
| CPU time | 8.31 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:36:40 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-2ac45093-6fd1-4a4b-8b4b-eea8b7d553f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823410024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3823410024 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.303866549 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 5110411889 ps |
| CPU time | 61.54 seconds |
| Started | Jul 20 07:36:40 PM PDT 24 |
| Finished | Jul 20 07:37:42 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-c359e116-bac9-4508-8835-6a06e4290e2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303866549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.303866549 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.1293424217 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 5923121743 ps |
| CPU time | 103.32 seconds |
| Started | Jul 20 07:36:41 PM PDT 24 |
| Finished | Jul 20 07:38:25 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b20c38a1-9338-4b94-ac06-f971d6dad4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293424217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.1293424217 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.4145379217 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 45822721 ps |
| CPU time | 6.18 seconds |
| Started | Jul 20 07:36:31 PM PDT 24 |
| Finished | Jul 20 07:36:38 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-03c97fdd-e657-48d2-abaf-2cdc7e64958f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145379217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.4145379217 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.456709832 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 10565565055 ps |
| CPU time | 379.62 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:42:59 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-740b064e-07d9-4e0d-a6ef-4444bb098ef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456709832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.456709832 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.973404087 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 1118467665 ps |
| CPU time | 41.36 seconds |
| Started | Jul 20 07:36:50 PM PDT 24 |
| Finished | Jul 20 07:37:31 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-e38ff5d9-afb5-49ea-b7f1-3430c1eea0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973404087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.973404087 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2461728359 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 868534573 ps |
| CPU time | 195.13 seconds |
| Started | Jul 20 07:36:40 PM PDT 24 |
| Finished | Jul 20 07:39:56 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-32b31d1c-8de6-4d65-9f01-16222ddee7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461728359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2461728359 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.1649759937 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 92930135 ps |
| CPU time | 26.13 seconds |
| Started | Jul 20 07:36:39 PM PDT 24 |
| Finished | Jul 20 07:37:06 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-8c490655-b539-4591-8e99-9ef1af14b5ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649759937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.1649759937 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3824467509 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 198312995 ps |
| CPU time | 25.79 seconds |
| Started | Jul 20 07:36:38 PM PDT 24 |
| Finished | Jul 20 07:37:04 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-975412f9-d2ab-4098-a07b-14daa2306afb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824467509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3824467509 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.4269204383 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 982632292 ps |
| CPU time | 46.24 seconds |
| Started | Jul 20 07:36:45 PM PDT 24 |
| Finished | Jul 20 07:37:32 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-28312f97-f606-47ce-a128-7d795fc74e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269204383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .4269204383 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.1538793659 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 72999916341 ps |
| CPU time | 1309.77 seconds |
| Started | Jul 20 07:36:45 PM PDT 24 |
| Finished | Jul 20 07:58:36 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-f4dc9847-d642-476f-8ea7-97ce1f0319bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538793659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.1538793659 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.3373706698 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 311947762 ps |
| CPU time | 32.48 seconds |
| Started | Jul 20 07:36:44 PM PDT 24 |
| Finished | Jul 20 07:37:18 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-42c064ee-2cd0-46ad-bcdb-8dbb966435b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373706698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.3373706698 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.4269795478 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 905808557 ps |
| CPU time | 30.25 seconds |
| Started | Jul 20 07:36:53 PM PDT 24 |
| Finished | Jul 20 07:37:24 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-eb432bcb-0239-49b0-af9f-59a42c1c317f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269795478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.4269795478 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1029153059 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 1919582529 ps |
| CPU time | 65.46 seconds |
| Started | Jul 20 07:36:52 PM PDT 24 |
| Finished | Jul 20 07:37:59 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-be1f9cd5-2777-4e4e-bb02-698b25b36cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029153059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1029153059 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2261495293 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 6737835375 ps |
| CPU time | 72.64 seconds |
| Started | Jul 20 07:36:47 PM PDT 24 |
| Finished | Jul 20 07:38:00 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-fcf83c6f-1a04-4cc8-9c5e-cb9bcb458eb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261495293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2261495293 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.2358040546 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 34404869150 ps |
| CPU time | 602.65 seconds |
| Started | Jul 20 07:36:53 PM PDT 24 |
| Finished | Jul 20 07:46:56 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-ccaf7016-2242-4c22-bdeb-70f32660e64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358040546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.2358040546 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.876290993 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 211545242 ps |
| CPU time | 21.71 seconds |
| Started | Jul 20 07:36:45 PM PDT 24 |
| Finished | Jul 20 07:37:08 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-56a0a574-1fa3-443a-80c0-8ce18250c2a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876290993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_dela ys.876290993 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3548010641 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2358201650 ps |
| CPU time | 66.58 seconds |
| Started | Jul 20 07:36:48 PM PDT 24 |
| Finished | Jul 20 07:37:55 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-94f35542-72fe-4ead-8311-6281a438497f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548010641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3548010641 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.3426673080 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 47002296 ps |
| CPU time | 6.59 seconds |
| Started | Jul 20 07:36:48 PM PDT 24 |
| Finished | Jul 20 07:36:55 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-3febc359-3a8f-457a-8a71-7a6f8a582f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426673080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.3426673080 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.251967808 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 10256181628 ps |
| CPU time | 120.14 seconds |
| Started | Jul 20 07:36:44 PM PDT 24 |
| Finished | Jul 20 07:38:45 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-42d269d5-2cf4-4ad9-b88f-37f16b5d26f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251967808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.251967808 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3594742028 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 5652258123 ps |
| CPU time | 95.9 seconds |
| Started | Jul 20 07:36:46 PM PDT 24 |
| Finished | Jul 20 07:38:22 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-2072f086-4806-493d-b6d2-d9ad91a8e005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594742028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3594742028 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1941202061 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 50452773 ps |
| CPU time | 6.84 seconds |
| Started | Jul 20 07:36:47 PM PDT 24 |
| Finished | Jul 20 07:36:55 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-d7f8c7ab-a808-48ab-97fa-75b5d15c81ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941202061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1941202061 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.1640520880 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 634914890 ps |
| CPU time | 54.96 seconds |
| Started | Jul 20 07:36:53 PM PDT 24 |
| Finished | Jul 20 07:37:49 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3c53c4ab-71a0-4546-9ae2-f0ce8559d28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640520880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.1640520880 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.611115937 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 3844305823 ps |
| CPU time | 136.6 seconds |
| Started | Jul 20 07:36:57 PM PDT 24 |
| Finished | Jul 20 07:39:14 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-9e0b8394-d5bb-445e-b657-66ad65c0aff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611115937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.611115937 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3265355093 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 7704259715 ps |
| CPU time | 489.92 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:45:13 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-b8d2e486-983c-4876-b2be-9a989b1b9f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265355093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.3265355093 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.3214594214 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 866973891 ps |
| CPU time | 102.94 seconds |
| Started | Jul 20 07:36:54 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-8ac1b3d6-cb2a-4923-bef9-1b2d7df499f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214594214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.3214594214 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.1462232929 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 54393470 ps |
| CPU time | 9.01 seconds |
| Started | Jul 20 07:36:46 PM PDT 24 |
| Finished | Jul 20 07:36:55 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-dd88ea3d-fd96-4400-8de5-faa28c7ea052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462232929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.1462232929 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3141823247 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 955719489 ps |
| CPU time | 76.58 seconds |
| Started | Jul 20 07:36:56 PM PDT 24 |
| Finished | Jul 20 07:38:14 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-8cf862c9-c8c4-4d47-8fdc-e0bbe886b39f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141823247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3141823247 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.911814674 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 74274494619 ps |
| CPU time | 1333.17 seconds |
| Started | Jul 20 07:36:55 PM PDT 24 |
| Finished | Jul 20 07:59:09 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ccea0f1b-c343-4bff-9e57-d8cd1b4772fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911814674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_d evice_slow_rsp.911814674 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2356982666 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 753748238 ps |
| CPU time | 31.64 seconds |
| Started | Jul 20 07:36:55 PM PDT 24 |
| Finished | Jul 20 07:37:27 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-ccaa1156-c00a-4a22-baa3-b347b1d12fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356982666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2356982666 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3619092835 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 145333688 ps |
| CPU time | 7.7 seconds |
| Started | Jul 20 07:36:56 PM PDT 24 |
| Finished | Jul 20 07:37:04 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-18f24515-fe62-4435-bda9-334eaff5fc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619092835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3619092835 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.1842377212 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 291597741 ps |
| CPU time | 14.66 seconds |
| Started | Jul 20 07:36:54 PM PDT 24 |
| Finished | Jul 20 07:37:09 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-6bf669bc-a04f-4286-a4b7-1866ae6949aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842377212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.1842377212 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1183929865 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 71755694833 ps |
| CPU time | 855.74 seconds |
| Started | Jul 20 07:36:57 PM PDT 24 |
| Finished | Jul 20 07:51:13 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-f8478491-e1d5-417d-b5dd-728de994e6f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183929865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1183929865 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.3857349456 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 48787477265 ps |
| CPU time | 874.27 seconds |
| Started | Jul 20 07:36:56 PM PDT 24 |
| Finished | Jul 20 07:51:31 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-bed7cf02-b618-4b50-a617-681aaf6adbac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857349456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.3857349456 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.3915383600 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 535111264 ps |
| CPU time | 45.88 seconds |
| Started | Jul 20 07:36:56 PM PDT 24 |
| Finished | Jul 20 07:37:43 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-7e554b32-7503-406c-ade9-1a22949702d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915383600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.3915383600 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.2026463074 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 401660311 ps |
| CPU time | 33.37 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:37:37 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-f31f445d-c0a8-49e0-b8d1-948a705ee42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026463074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2026463074 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.4229571234 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 59711894 ps |
| CPU time | 7.4 seconds |
| Started | Jul 20 07:36:55 PM PDT 24 |
| Finished | Jul 20 07:37:03 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-edd8d3ae-2852-4ccd-96da-1645d8b428da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229571234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.4229571234 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1773897716 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 8979596020 ps |
| CPU time | 93.89 seconds |
| Started | Jul 20 07:37:04 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3e950cf1-fd84-44b3-9a46-958a1d700eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773897716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1773897716 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.1486687235 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 3348209689 ps |
| CPU time | 57.4 seconds |
| Started | Jul 20 07:36:54 PM PDT 24 |
| Finished | Jul 20 07:37:53 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-ab65e5cf-95b4-4078-8cd9-29072448e875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486687235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.1486687235 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.977155185 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 39772773 ps |
| CPU time | 6.09 seconds |
| Started | Jul 20 07:36:54 PM PDT 24 |
| Finished | Jul 20 07:37:01 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-5643eb93-42f0-449a-81e7-f6f7cc4fe8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977155185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .977155185 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.2537741270 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 1047649395 ps |
| CPU time | 80.81 seconds |
| Started | Jul 20 07:37:00 PM PDT 24 |
| Finished | Jul 20 07:38:21 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-2f65de5b-08af-4c83-8a35-c17117b47bda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537741270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.2537741270 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3923911931 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 4131519319 ps |
| CPU time | 155.93 seconds |
| Started | Jul 20 07:37:04 PM PDT 24 |
| Finished | Jul 20 07:39:41 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-f4146f23-766a-4c70-9e07-c6cb7dc6adcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923911931 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3923911931 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2834093493 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 274320470 ps |
| CPU time | 179.92 seconds |
| Started | Jul 20 07:37:06 PM PDT 24 |
| Finished | Jul 20 07:40:07 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-95f9cf28-9af5-4dc7-bb95-c0bae03ab827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834093493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2834093493 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2940365869 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 986271059 ps |
| CPU time | 214.89 seconds |
| Started | Jul 20 07:37:15 PM PDT 24 |
| Finished | Jul 20 07:40:50 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-fc3e959b-99d0-40b8-a5a1-48a93795a4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940365869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.2940365869 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.2258074987 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1174355989 ps |
| CPU time | 52.91 seconds |
| Started | Jul 20 07:36:56 PM PDT 24 |
| Finished | Jul 20 07:37:50 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-2437022b-acd6-4c56-a72c-3f3af9fc0708 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258074987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.2258074987 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.2916948912 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 1734312818 ps |
| CPU time | 76.51 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:38:20 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-88ec0034-0938-4a8f-b23e-f3911df93ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916948912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .2916948912 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.3665614986 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 113389506220 ps |
| CPU time | 2225.76 seconds |
| Started | Jul 20 07:37:06 PM PDT 24 |
| Finished | Jul 20 08:14:14 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-b52b8ef3-fba3-4b45-a394-8e6c44ce9a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665614986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.3665614986 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3149362300 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 675149114 ps |
| CPU time | 27.1 seconds |
| Started | Jul 20 07:37:12 PM PDT 24 |
| Finished | Jul 20 07:37:40 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c93c7a37-4010-4a6c-8487-5b53701a221f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149362300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3149362300 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.4080187123 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 375540137 ps |
| CPU time | 17.21 seconds |
| Started | Jul 20 07:37:02 PM PDT 24 |
| Finished | Jul 20 07:37:19 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-aa17ec3e-c3b7-445b-963d-9c6bf79abec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080187123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.4080187123 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.638718249 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 268325164 ps |
| CPU time | 25.19 seconds |
| Started | Jul 20 07:37:05 PM PDT 24 |
| Finished | Jul 20 07:37:30 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-75afe84a-3c31-449e-b6bc-d4658afe5c3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638718249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.638718249 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.567845052 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 45929729596 ps |
| CPU time | 561.53 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:46:26 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f6d9d090-b640-48fe-a923-abba1bf2da2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567845052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.567845052 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.4157475294 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2895326552 ps |
| CPU time | 47.04 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:37:51 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-0207306b-23ee-434b-96b2-54d6a5a283d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157475294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.4157475294 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.3194731921 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 330065506 ps |
| CPU time | 30.39 seconds |
| Started | Jul 20 07:37:02 PM PDT 24 |
| Finished | Jul 20 07:37:34 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-9d7485e5-7f72-4cf2-ab4e-09e7842b136c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194731921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.3194731921 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3680707281 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 395406221 ps |
| CPU time | 26.95 seconds |
| Started | Jul 20 07:37:07 PM PDT 24 |
| Finished | Jul 20 07:37:35 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-67e4f234-b897-4eea-874a-39a8cd5f5c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680707281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3680707281 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.2228885488 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 222125014 ps |
| CPU time | 8.23 seconds |
| Started | Jul 20 07:37:05 PM PDT 24 |
| Finished | Jul 20 07:37:15 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-2d13fa59-fff5-4241-b4a4-76cb25d4d3a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228885488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.2228885488 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.293221476 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 6911004913 ps |
| CPU time | 73.21 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:38:17 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-453e475f-a769-4f25-9ec4-2c6006239869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293221476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.293221476 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.2356113951 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 3830249625 ps |
| CPU time | 67.31 seconds |
| Started | Jul 20 07:37:01 PM PDT 24 |
| Finished | Jul 20 07:38:09 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-a4a356ad-fa75-495b-92d8-91451314268a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356113951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.2356113951 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2873108574 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 47225451 ps |
| CPU time | 6.49 seconds |
| Started | Jul 20 07:37:03 PM PDT 24 |
| Finished | Jul 20 07:37:11 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-d48cace2-14fa-4807-9f1c-f25ec7e4224a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873108574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2873108574 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.734114585 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 278357614 ps |
| CPU time | 12.37 seconds |
| Started | Jul 20 07:37:10 PM PDT 24 |
| Finished | Jul 20 07:37:23 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-2347d3b8-47d2-4cea-b8b9-2676aee7f35d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734114585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.734114585 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.2712516386 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7396660965 ps |
| CPU time | 262.65 seconds |
| Started | Jul 20 07:37:12 PM PDT 24 |
| Finished | Jul 20 07:41:35 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-563092a3-9746-4271-8904-29258b4a091e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712516386 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.2712516386 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.947028921 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 392295963 ps |
| CPU time | 82.65 seconds |
| Started | Jul 20 07:37:09 PM PDT 24 |
| Finished | Jul 20 07:38:33 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-0fa8ec32-a78b-4df6-9062-150f53d9d9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947028921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.947028921 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3835194660 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 9807640051 ps |
| CPU time | 542.59 seconds |
| Started | Jul 20 07:37:10 PM PDT 24 |
| Finished | Jul 20 07:46:14 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-5d6c51c1-c398-4687-89a9-1f7eba67e0bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835194660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3835194660 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.3296978487 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 826760487 ps |
| CPU time | 37.52 seconds |
| Started | Jul 20 07:37:05 PM PDT 24 |
| Finished | Jul 20 07:37:44 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-3037400f-2ba0-4c13-96ff-8c6bbf44eafc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296978487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.3296978487 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.1397409173 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 2229197398 ps |
| CPU time | 106.58 seconds |
| Started | Jul 20 07:37:18 PM PDT 24 |
| Finished | Jul 20 07:39:05 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-8efb16dd-1530-4057-bad7-9388c498ccc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397409173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .1397409173 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2363124532 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 68247898292 ps |
| CPU time | 1353.98 seconds |
| Started | Jul 20 07:37:17 PM PDT 24 |
| Finished | Jul 20 07:59:51 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-02e1c0bb-9c28-4fee-bcb2-50202c47c21e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363124532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.2363124532 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.4235346550 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 819139527 ps |
| CPU time | 28.66 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:37:54 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-11c8430d-f25b-49b4-8a42-63a656493c4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235346550 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.4235346550 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3102690271 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 1858154392 ps |
| CPU time | 63.58 seconds |
| Started | Jul 20 07:37:36 PM PDT 24 |
| Finished | Jul 20 07:38:40 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-ff76338f-60a4-4c64-ac5c-162cfae0ff4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102690271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3102690271 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.1948662223 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 1653522946 ps |
| CPU time | 54.37 seconds |
| Started | Jul 20 07:37:23 PM PDT 24 |
| Finished | Jul 20 07:38:17 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d4c22558-2943-4e82-a987-0d96c97f9b5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948662223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.1948662223 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.639696925 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 66086485026 ps |
| CPU time | 738.14 seconds |
| Started | Jul 20 07:37:17 PM PDT 24 |
| Finished | Jul 20 07:49:36 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-6929b3f9-1b8b-4bad-b94e-eb07c67fcb59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639696925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.639696925 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1860180744 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 26119220895 ps |
| CPU time | 451.1 seconds |
| Started | Jul 20 07:37:15 PM PDT 24 |
| Finished | Jul 20 07:44:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-8553d7e3-79ca-40d1-89c5-9d6901526b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860180744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1860180744 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2887447946 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 63790191 ps |
| CPU time | 8.28 seconds |
| Started | Jul 20 07:37:11 PM PDT 24 |
| Finished | Jul 20 07:37:20 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-af8c4cea-37f5-4a15-b62f-f26c8d88b774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887447946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2887447946 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1519911773 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 269911855 ps |
| CPU time | 19.22 seconds |
| Started | Jul 20 07:37:19 PM PDT 24 |
| Finished | Jul 20 07:37:39 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-39c9d01f-df4e-467d-b901-8be78597ec79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519911773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1519911773 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.2587286130 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 44481221 ps |
| CPU time | 6.41 seconds |
| Started | Jul 20 07:37:10 PM PDT 24 |
| Finished | Jul 20 07:37:17 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-dff55e95-6a0d-4367-afb5-0ef276579ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587286130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.2587286130 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.1901713110 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 5995432376 ps |
| CPU time | 67.29 seconds |
| Started | Jul 20 07:37:12 PM PDT 24 |
| Finished | Jul 20 07:38:20 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-c8776399-cc48-45b9-b99a-a2fdac53de03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901713110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.1901713110 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1329709503 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 2963177081 ps |
| CPU time | 52.27 seconds |
| Started | Jul 20 07:37:23 PM PDT 24 |
| Finished | Jul 20 07:38:15 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-4c352236-5b04-408e-bb50-3b4ff74194dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329709503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1329709503 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.3202124050 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 44273974 ps |
| CPU time | 5.87 seconds |
| Started | Jul 20 07:37:22 PM PDT 24 |
| Finished | Jul 20 07:37:29 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-4c8b085b-122c-462a-be4e-5cf3dde114a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202124050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.3202124050 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.3831123317 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5752139067 ps |
| CPU time | 194.24 seconds |
| Started | Jul 20 07:37:24 PM PDT 24 |
| Finished | Jul 20 07:40:39 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-57c51f59-5432-42f1-8632-ed02c8a0cd22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831123317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.3831123317 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.3385577686 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 121505392 ps |
| CPU time | 58.9 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:38:25 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-493e652e-e7c0-446d-9a68-665a09440cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385577686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.3385577686 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.1985260783 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 134694392 ps |
| CPU time | 17.34 seconds |
| Started | Jul 20 07:37:37 PM PDT 24 |
| Finished | Jul 20 07:37:55 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-eb321b55-1e4c-437a-acb4-c83ba2ce79b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985260783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.1985260783 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.3528572773 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 2188494651 ps |
| CPU time | 85.82 seconds |
| Started | Jul 20 07:37:36 PM PDT 24 |
| Finished | Jul 20 07:39:03 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-affbefc1-79c2-4212-81d4-a4866d8a3965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528572773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .3528572773 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1057738007 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 74541078441 ps |
| CPU time | 1462.3 seconds |
| Started | Jul 20 07:37:35 PM PDT 24 |
| Finished | Jul 20 08:01:58 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-06500926-a11a-45b8-bcfa-048f9c7d1a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057738007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1057738007 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2122193651 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 175778281 ps |
| CPU time | 9.85 seconds |
| Started | Jul 20 07:37:32 PM PDT 24 |
| Finished | Jul 20 07:37:43 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-2ce94dd6-baa9-426c-ac5d-cbd83a7a5031 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122193651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2122193651 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2715379629 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 1063036303 ps |
| CPU time | 35.41 seconds |
| Started | Jul 20 07:37:33 PM PDT 24 |
| Finished | Jul 20 07:38:09 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-abc8a586-5650-43df-b25e-406800753192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715379629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2715379629 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.3339147110 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 640313039 ps |
| CPU time | 24.95 seconds |
| Started | Jul 20 07:37:37 PM PDT 24 |
| Finished | Jul 20 07:38:02 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-4acc078f-ad4a-4721-8a12-6bcb4915654e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339147110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3339147110 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.639909328 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 13123873634 ps |
| CPU time | 148.72 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:39:54 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-5bb1f43c-a7c7-437f-9df0-9ae8cc32a4fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639909328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.639909328 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1870437932 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 7963108853 ps |
| CPU time | 134.27 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:39:40 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-7a707f80-f194-418d-a0a5-c864b4b6609a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870437932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.1870437932 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.521844335 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 205147949 ps |
| CPU time | 17.31 seconds |
| Started | Jul 20 07:37:28 PM PDT 24 |
| Finished | Jul 20 07:37:46 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-488f3e19-4444-4744-8871-b8aca33ac9a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521844335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_dela ys.521844335 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1324476045 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 162473027 ps |
| CPU time | 8.21 seconds |
| Started | Jul 20 07:37:39 PM PDT 24 |
| Finished | Jul 20 07:37:48 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-c468598e-f9cb-48cd-a9e9-a6b12b612a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324476045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1324476045 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.4136633878 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 52002812 ps |
| CPU time | 6.64 seconds |
| Started | Jul 20 07:37:38 PM PDT 24 |
| Finished | Jul 20 07:37:45 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-f8d3c6dd-9be3-46d4-868f-2d854921b53f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136633878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.4136633878 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.503873768 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 8909884742 ps |
| CPU time | 108.47 seconds |
| Started | Jul 20 07:37:26 PM PDT 24 |
| Finished | Jul 20 07:39:15 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-7129338a-7738-4535-b561-cc977cfefafe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503873768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.503873768 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1598103626 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 5631447592 ps |
| CPU time | 90.32 seconds |
| Started | Jul 20 07:37:36 PM PDT 24 |
| Finished | Jul 20 07:39:07 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-aac76ac7-4e3f-40d2-9822-6be33cf3891e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598103626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1598103626 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2705285776 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 43636193 ps |
| CPU time | 6.18 seconds |
| Started | Jul 20 07:37:25 PM PDT 24 |
| Finished | Jul 20 07:37:32 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-1b8f5352-1133-49a9-9c6e-b6dfab48aeda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705285776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2705285776 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.2733026800 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 14198458523 ps |
| CPU time | 586.3 seconds |
| Started | Jul 20 07:37:32 PM PDT 24 |
| Finished | Jul 20 07:47:19 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3c87ad1a-ae28-4941-aeaf-5b0e084cf1c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733026800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.2733026800 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.2436529772 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 19058687093 ps |
| CPU time | 709.91 seconds |
| Started | Jul 20 07:37:39 PM PDT 24 |
| Finished | Jul 20 07:49:31 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-ae6fe754-99de-48ab-8bc8-cbb9dbede221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436529772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.2436529772 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.321553663 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 133197242 ps |
| CPU time | 39.86 seconds |
| Started | Jul 20 07:37:32 PM PDT 24 |
| Finished | Jul 20 07:38:13 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-ad8792e1-7021-4fd5-8a52-efd919be97af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321553663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_ with_rand_reset.321553663 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1767512148 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 5016124924 ps |
| CPU time | 276.49 seconds |
| Started | Jul 20 07:37:34 PM PDT 24 |
| Finished | Jul 20 07:42:11 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-c1508310-9d4a-4bd6-bcf3-ebb7144baa2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767512148 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1767512148 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.713656867 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 403847220 ps |
| CPU time | 19.49 seconds |
| Started | Jul 20 07:37:33 PM PDT 24 |
| Finished | Jul 20 07:37:53 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-b42f27cd-ca07-419b-8a74-8bf5349175f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713656867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.713656867 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.2397666234 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 1547591346 ps |
| CPU time | 59.33 seconds |
| Started | Jul 20 07:37:44 PM PDT 24 |
| Finished | Jul 20 07:38:44 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ffea17e6-f81e-4031-bcd7-6c332a6db0d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397666234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .2397666234 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.810474943 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 78288464 ps |
| CPU time | 6.13 seconds |
| Started | Jul 20 07:37:41 PM PDT 24 |
| Finished | Jul 20 07:37:47 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-eac89731-dc9c-4711-9874-056410a42add |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810474943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_addr .810474943 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.217837321 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 2319929503 ps |
| CPU time | 88.95 seconds |
| Started | Jul 20 07:37:39 PM PDT 24 |
| Finished | Jul 20 07:39:09 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-ff202657-86c2-441a-a82d-d78242c6e6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217837321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.217837321 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1911036009 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 2472253920 ps |
| CPU time | 90.97 seconds |
| Started | Jul 20 07:37:33 PM PDT 24 |
| Finished | Jul 20 07:39:04 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-f62df3db-3058-4fe5-a17f-ccbf14cac8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911036009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1911036009 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.4266563465 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 87973896918 ps |
| CPU time | 1056.86 seconds |
| Started | Jul 20 07:37:33 PM PDT 24 |
| Finished | Jul 20 07:55:11 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-0185054b-0b16-4c6e-a226-83c525bcfbb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266563465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.4266563465 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.477755100 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 58020304459 ps |
| CPU time | 1077.47 seconds |
| Started | Jul 20 07:37:49 PM PDT 24 |
| Finished | Jul 20 07:55:47 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-be514459-7378-44b3-bc70-c04c1f756b1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477755100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.477755100 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.714770200 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 422561454 ps |
| CPU time | 36.52 seconds |
| Started | Jul 20 07:37:34 PM PDT 24 |
| Finished | Jul 20 07:38:11 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-665686b8-68b8-4508-b5af-71abd0e8ab92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714770200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_dela ys.714770200 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1859549284 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 470502119 ps |
| CPU time | 39.02 seconds |
| Started | Jul 20 07:37:48 PM PDT 24 |
| Finished | Jul 20 07:38:27 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-fd3026f0-0846-4669-9f95-f506f5cd0b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859549284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1859549284 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.2120978627 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 254174578 ps |
| CPU time | 10.25 seconds |
| Started | Jul 20 07:37:35 PM PDT 24 |
| Finished | Jul 20 07:37:46 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-2e2a1b5d-93c7-4d96-8912-326e4c5c5181 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120978627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.2120978627 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.2731207321 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 9570453697 ps |
| CPU time | 113.17 seconds |
| Started | Jul 20 07:37:33 PM PDT 24 |
| Finished | Jul 20 07:39:27 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-de1eb30f-4c7f-4542-acb6-b3e2627e39ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731207321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.2731207321 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.4256583286 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 2774406855 ps |
| CPU time | 48.12 seconds |
| Started | Jul 20 07:37:31 PM PDT 24 |
| Finished | Jul 20 07:38:20 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-1f083965-fcf3-4720-93b2-1217e98bf39d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256583286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.4256583286 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.3651784802 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 56654480 ps |
| CPU time | 6.72 seconds |
| Started | Jul 20 07:37:37 PM PDT 24 |
| Finished | Jul 20 07:37:44 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-69f979ed-c24b-4d48-bac5-f79bf6e22e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651784802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.3651784802 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.2000937606 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 392470623 ps |
| CPU time | 37.24 seconds |
| Started | Jul 20 07:37:48 PM PDT 24 |
| Finished | Jul 20 07:38:26 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-e8314d7f-6f9f-4f53-b8ae-2f9a93ba48e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000937606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2000937606 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.4148531801 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 11073353024 ps |
| CPU time | 419.93 seconds |
| Started | Jul 20 07:37:44 PM PDT 24 |
| Finished | Jul 20 07:44:45 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-2f7b9498-e511-4f20-b9c9-2849561d201b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148531801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.4148531801 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.3134374903 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 193382342 ps |
| CPU time | 48.33 seconds |
| Started | Jul 20 07:37:40 PM PDT 24 |
| Finished | Jul 20 07:38:29 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-a613542f-04ca-47bc-86d4-f9a80a684790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134374903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.3134374903 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.3698644371 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 137287346 ps |
| CPU time | 9.58 seconds |
| Started | Jul 20 07:37:43 PM PDT 24 |
| Finished | Jul 20 07:37:53 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-af377d48-b6ea-4600-abef-a600c5fd48e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698644371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.3698644371 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.3874218826 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 712039892 ps |
| CPU time | 29.61 seconds |
| Started | Jul 20 07:38:00 PM PDT 24 |
| Finished | Jul 20 07:38:31 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d4a8950f-0f43-4ab9-9d2c-efd7f6c48244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874218826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .3874218826 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3290289271 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 61127969694 ps |
| CPU time | 1061.14 seconds |
| Started | Jul 20 07:37:52 PM PDT 24 |
| Finished | Jul 20 07:55:34 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-322c6a63-0b1a-4f7d-bc3e-4f5674457dbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290289271 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3290289271 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2761418938 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 126355927 ps |
| CPU time | 15.94 seconds |
| Started | Jul 20 07:37:50 PM PDT 24 |
| Finished | Jul 20 07:38:07 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-0a35bce7-f3e0-4ab1-8891-3833ce2a2bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761418938 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2761418938 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.994395877 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 2338494779 ps |
| CPU time | 77.82 seconds |
| Started | Jul 20 07:37:48 PM PDT 24 |
| Finished | Jul 20 07:39:07 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-91b4d913-49f4-4e1f-8561-05ff213e8aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994395877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.994395877 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1903384080 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 1931548128 ps |
| CPU time | 76.76 seconds |
| Started | Jul 20 07:37:50 PM PDT 24 |
| Finished | Jul 20 07:39:07 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-846087d0-b31b-416d-b143-c462174ad152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903384080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1903384080 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3856342482 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 46867965234 ps |
| CPU time | 520.05 seconds |
| Started | Jul 20 07:37:49 PM PDT 24 |
| Finished | Jul 20 07:46:30 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-4319c464-4928-4320-8a03-9cc024d06fe7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856342482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3856342482 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2348852158 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 9562887606 ps |
| CPU time | 168.43 seconds |
| Started | Jul 20 07:37:59 PM PDT 24 |
| Finished | Jul 20 07:40:49 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-e64e439d-fa3e-4141-a7e2-87ea3559c278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348852158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2348852158 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.3260137207 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 465541834 ps |
| CPU time | 36.57 seconds |
| Started | Jul 20 07:37:49 PM PDT 24 |
| Finished | Jul 20 07:38:26 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-0743a322-2ebd-4254-ae9a-c7d8c4c56714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260137207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.3260137207 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.4266408976 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 656659601 ps |
| CPU time | 19.75 seconds |
| Started | Jul 20 07:37:47 PM PDT 24 |
| Finished | Jul 20 07:38:08 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-07f3c7e9-d9b3-42ef-9900-24c8ae10ca83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266408976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.4266408976 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1291538548 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 208054952 ps |
| CPU time | 8.84 seconds |
| Started | Jul 20 07:37:48 PM PDT 24 |
| Finished | Jul 20 07:37:58 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-7eb05d25-2041-4501-8c60-bdefd2832064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291538548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1291538548 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3228400215 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 7854139439 ps |
| CPU time | 82.41 seconds |
| Started | Jul 20 07:37:41 PM PDT 24 |
| Finished | Jul 20 07:39:04 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-6ba5b034-1d7a-4702-beee-5215ad8cfcdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228400215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3228400215 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.2675661044 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 4155060615 ps |
| CPU time | 70.95 seconds |
| Started | Jul 20 07:37:52 PM PDT 24 |
| Finished | Jul 20 07:39:04 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-c73aa2e9-d63e-4d14-bce8-87ef9c506ccd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675661044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.2675661044 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2945876105 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 46509424 ps |
| CPU time | 6.13 seconds |
| Started | Jul 20 07:37:43 PM PDT 24 |
| Finished | Jul 20 07:37:50 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-e325d831-424b-457a-a917-a633420ec098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945876105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.2945876105 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.2906051144 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 5990862025 ps |
| CPU time | 206.57 seconds |
| Started | Jul 20 07:37:50 PM PDT 24 |
| Finished | Jul 20 07:41:17 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-2e42d24e-2b8d-4cbb-bf0c-4c3610e93ea1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906051144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.2906051144 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.194541402 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 1922745490 ps |
| CPU time | 140.51 seconds |
| Started | Jul 20 07:37:47 PM PDT 24 |
| Finished | Jul 20 07:40:08 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-dc3a4b25-30f3-4267-8013-9ef0b17a6a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194541402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.194541402 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.3217390875 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 51369507 ps |
| CPU time | 33.23 seconds |
| Started | Jul 20 07:37:58 PM PDT 24 |
| Finished | Jul 20 07:38:32 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-638da42f-ff19-49b0-99fc-f23355ca208a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217390875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all _with_rand_reset.3217390875 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2407317232 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4179543183 ps |
| CPU time | 437.38 seconds |
| Started | Jul 20 07:38:00 PM PDT 24 |
| Finished | Jul 20 07:45:19 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-2c4cd0f7-5084-431d-acd1-fc746ba7e301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407317232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.2407317232 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.2296209707 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 215622332 ps |
| CPU time | 11.94 seconds |
| Started | Jul 20 07:37:49 PM PDT 24 |
| Finished | Jul 20 07:38:01 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-81d5453d-5702-4768-b5f3-001513d5b8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296209707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.2296209707 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.1991850169 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 1137182745 ps |
| CPU time | 44.84 seconds |
| Started | Jul 20 07:37:58 PM PDT 24 |
| Finished | Jul 20 07:38:44 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-d9a910dd-0bf0-4076-93ec-4edf9c5ac198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991850169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .1991850169 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.507392225 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 60194245054 ps |
| CPU time | 1158.71 seconds |
| Started | Jul 20 07:38:00 PM PDT 24 |
| Finished | Jul 20 07:57:20 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-53c2e68d-3fc4-450d-9144-f231bd1851fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507392225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.507392225 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3254735493 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 281686535 ps |
| CPU time | 25.65 seconds |
| Started | Jul 20 07:37:57 PM PDT 24 |
| Finished | Jul 20 07:38:23 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-838a67b4-b59a-43b0-bd97-246dca205dbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254735493 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3254735493 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2594476362 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 248589664 ps |
| CPU time | 11.7 seconds |
| Started | Jul 20 07:38:07 PM PDT 24 |
| Finished | Jul 20 07:38:20 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-e0521d8d-bbc3-4884-8c2c-78f48011c94b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594476362 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2594476362 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.558327952 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 239065928 ps |
| CPU time | 21.69 seconds |
| Started | Jul 20 07:37:58 PM PDT 24 |
| Finished | Jul 20 07:38:21 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-c9e028e8-1efa-4ae3-92b6-f8a9231d0964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558327952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.558327952 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.231434379 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 100656148174 ps |
| CPU time | 1262.56 seconds |
| Started | Jul 20 07:38:00 PM PDT 24 |
| Finished | Jul 20 07:59:04 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-33d51caf-e577-4641-b28c-6a162dc141fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231434379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.231434379 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.3767755860 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 27227896066 ps |
| CPU time | 465.92 seconds |
| Started | Jul 20 07:37:57 PM PDT 24 |
| Finished | Jul 20 07:45:43 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-9a0ac45e-36ab-4242-ac79-2ad165a86a1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767755860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.3767755860 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.4286793566 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 357046425 ps |
| CPU time | 29.16 seconds |
| Started | Jul 20 07:38:07 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-177cee3b-ea12-4a40-afe2-e1b64776462f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286793566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.4286793566 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3230326014 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 197666642 ps |
| CPU time | 16.04 seconds |
| Started | Jul 20 07:37:59 PM PDT 24 |
| Finished | Jul 20 07:38:16 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-09bd566e-59c6-4bb1-88bc-2dc66fbbb3b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230326014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3230326014 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.620407364 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 218412392 ps |
| CPU time | 9.38 seconds |
| Started | Jul 20 07:38:00 PM PDT 24 |
| Finished | Jul 20 07:38:10 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-adac59b3-5ae6-4680-b5eb-55f9b684aa7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620407364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.620407364 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2892295070 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 8181757319 ps |
| CPU time | 90.17 seconds |
| Started | Jul 20 07:38:06 PM PDT 24 |
| Finished | Jul 20 07:39:37 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-75d0def9-bb10-4c5e-b363-9aadcc481fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892295070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2892295070 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.4195724210 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 5692224551 ps |
| CPU time | 93.31 seconds |
| Started | Jul 20 07:38:07 PM PDT 24 |
| Finished | Jul 20 07:39:41 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-3fccf23d-bd77-4831-af0e-b3cf62abd1cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195724210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.4195724210 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.515671443 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 43842771 ps |
| CPU time | 5.82 seconds |
| Started | Jul 20 07:37:59 PM PDT 24 |
| Finished | Jul 20 07:38:05 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-10b79f16-88b4-4f3f-9ee3-022d4ef686e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515671443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays .515671443 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.459765155 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 48971335 ps |
| CPU time | 6.37 seconds |
| Started | Jul 20 07:38:04 PM PDT 24 |
| Finished | Jul 20 07:38:11 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-e05f9e96-c5e4-4f7c-877f-70256120c38f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459765155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.459765155 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3388002132 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 7971048001 ps |
| CPU time | 245.14 seconds |
| Started | Jul 20 07:38:04 PM PDT 24 |
| Finished | Jul 20 07:42:10 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ef88494f-f249-4073-b963-3fd2782747f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388002132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3388002132 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2078067915 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 484539907 ps |
| CPU time | 177.14 seconds |
| Started | Jul 20 07:38:05 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a2b05eee-d2ee-4704-b225-18299813816c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078067915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.2078067915 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.2303713620 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 3265377332 ps |
| CPU time | 153.44 seconds |
| Started | Jul 20 07:38:03 PM PDT 24 |
| Finished | Jul 20 07:40:37 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-c036e4d2-537b-4b85-9ae7-8c583779914e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303713620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.2303713620 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2198644505 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 103352554 ps |
| CPU time | 14.24 seconds |
| Started | Jul 20 07:37:58 PM PDT 24 |
| Finished | Jul 20 07:38:13 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-701f7136-fc32-4163-8d3c-f0b570bcd82e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198644505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2198644505 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2485905240 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1235185752 ps |
| CPU time | 43.92 seconds |
| Started | Jul 20 07:38:11 PM PDT 24 |
| Finished | Jul 20 07:38:56 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-d427eb44-0d5a-4742-a52e-df487075cd24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485905240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2485905240 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2988565418 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 1420963934 ps |
| CPU time | 48.53 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:39:08 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-e4972c21-e5d1-42c7-b3cc-1bde4aa6a93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988565418 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2988565418 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.276784866 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 257118253 ps |
| CPU time | 20.15 seconds |
| Started | Jul 20 07:38:07 PM PDT 24 |
| Finished | Jul 20 07:38:28 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-4ccdb09a-fe0d-4bbf-aedf-467281c62758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276784866 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.276784866 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3339911088 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 1950526376 ps |
| CPU time | 66.72 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:39:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-139fc680-3bbc-402e-99f6-a9226725535b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339911088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3339911088 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3429908831 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 48437557654 ps |
| CPU time | 558 seconds |
| Started | Jul 20 07:38:13 PM PDT 24 |
| Finished | Jul 20 07:47:32 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-690833d3-9cfb-4e87-8cba-41d90830ab5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429908831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3429908831 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.3822045100 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 34341662481 ps |
| CPU time | 582.49 seconds |
| Started | Jul 20 07:38:13 PM PDT 24 |
| Finished | Jul 20 07:47:57 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-33013468-467b-4b8a-b15c-5291b85a0cbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822045100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.3822045100 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.16374097 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 450822078 ps |
| CPU time | 35.68 seconds |
| Started | Jul 20 07:38:14 PM PDT 24 |
| Finished | Jul 20 07:38:51 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-9b7d8678-8d8f-4214-9c98-c742890b3757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16374097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_delay s.16374097 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.1354393161 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 362986512 ps |
| CPU time | 27.5 seconds |
| Started | Jul 20 07:38:06 PM PDT 24 |
| Finished | Jul 20 07:38:34 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-e2d27857-277e-4541-882c-fc8c5ec91cf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354393161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.1354393161 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2220575540 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 212622664 ps |
| CPU time | 9.45 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:38:23 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-d827e65b-2697-4f80-bbbc-1036beba7fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220575540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2220575540 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3012674623 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 8333221886 ps |
| CPU time | 92.25 seconds |
| Started | Jul 20 07:38:15 PM PDT 24 |
| Finished | Jul 20 07:39:48 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-a4232834-c1d4-4556-99b2-2f8414317375 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012674623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3012674623 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.1845385604 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 5922331308 ps |
| CPU time | 104.41 seconds |
| Started | Jul 20 07:38:06 PM PDT 24 |
| Finished | Jul 20 07:39:52 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-1a71cfab-744d-4ea0-a0c0-7adf6079c4e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845385604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.1845385604 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.516804687 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 50088597 ps |
| CPU time | 6.45 seconds |
| Started | Jul 20 07:38:06 PM PDT 24 |
| Finished | Jul 20 07:38:13 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-d4c2802a-32be-49fa-9364-24ec323c4253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516804687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delays .516804687 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.671860679 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5963752859 ps |
| CPU time | 450.15 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:45:44 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-68540956-f2c7-4dc0-9453-8b7a4ab7f8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671860679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.671860679 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1876549443 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 3355680595 ps |
| CPU time | 228.93 seconds |
| Started | Jul 20 07:38:13 PM PDT 24 |
| Finished | Jul 20 07:42:03 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-020292a7-ef57-46f9-b175-663f5ec58580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876549443 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1876549443 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1055065600 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 7151272 ps |
| CPU time | 4.03 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:38:17 PM PDT 24 |
| Peak memory | 565752 kb |
| Host | smart-25d8912c-6bf5-4cbd-b447-23680cfc112c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055065600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.1055065600 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3938283637 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 12115047119 ps |
| CPU time | 583.89 seconds |
| Started | Jul 20 07:38:19 PM PDT 24 |
| Finished | Jul 20 07:48:04 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-5cffbf31-e93e-40f1-a5fb-5c221e998bd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938283637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3938283637 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.1436036872 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 526766995 ps |
| CPU time | 27.41 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:38:41 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-08d2f78b-19c0-47e4-92a0-b1d9ebac2b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436036872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.1436036872 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2202431715 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 4201751052 ps |
| CPU time | 422.53 seconds |
| Started | Jul 20 07:23:09 PM PDT 24 |
| Finished | Jul 20 07:30:14 PM PDT 24 |
| Peak memory | 598500 kb |
| Host | smart-8ea63a75-686c-4230-b61e-fe3176accf30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202431715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2202431715 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.4254009977 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 27498854305 ps |
| CPU time | 3588.67 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 08:22:45 PM PDT 24 |
| Peak memory | 593116 kb |
| Host | smart-4f53c736-d668-474e-a7c9-c4614923ac7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254009977 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.4254009977 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.3719815984 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 3984811499 ps |
| CPU time | 337.51 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:28:31 PM PDT 24 |
| Peak memory | 603708 kb |
| Host | smart-0e947151-5539-4493-81a9-8d68d4dd1517 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719815984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.3719815984 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3005760377 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 777220137 ps |
| CPU time | 70.11 seconds |
| Started | Jul 20 07:22:56 PM PDT 24 |
| Finished | Jul 20 07:24:08 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-2d3f533b-fa19-4f66-820a-5aae87d3a09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005760377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3005760377 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.1303055548 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 126416451244 ps |
| CPU time | 2235.79 seconds |
| Started | Jul 20 07:23:00 PM PDT 24 |
| Finished | Jul 20 08:00:16 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-a149d849-b7f9-4f42-b598-b0e6f075502f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303055548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_d evice_slow_rsp.1303055548 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.1127007731 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 666277777 ps |
| CPU time | 29.49 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:23:29 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-669cdeb8-67c7-46a4-8388-0fbeba1a901e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127007731 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .1127007731 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.747920165 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 32782198 ps |
| CPU time | 6.27 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:23:06 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-5d82926a-c6f9-4bd5-8bb7-c0c9e4355ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747920165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.747920165 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.197737059 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 853474413 ps |
| CPU time | 31.63 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:26 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-d8ee95c1-9108-4ef0-bcdc-cc52fd24fb95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197737059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.197737059 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2409390722 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 106644699298 ps |
| CPU time | 1231.63 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:43:27 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-edd2e803-7288-4d2c-b6e9-20a9e9c4b531 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409390722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2409390722 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1060966093 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 60814554526 ps |
| CPU time | 1096.07 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:41:10 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-b96589d2-dd50-41ae-8f8f-9b4f994b1004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060966093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1060966093 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.2973764107 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 526761548 ps |
| CPU time | 43.48 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:39 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-bb5b8791-ee28-4c68-a5ca-2fbf5f462c67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973764107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.2973764107 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.285219737 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 64181040 ps |
| CPU time | 8.13 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:23:08 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-07e6e1db-aedb-44de-ad4f-809b0fef75ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285219737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.285219737 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3703883984 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 43479873 ps |
| CPU time | 6.23 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:23:01 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-a4f441d0-104f-4c44-83c2-f90dd27e4277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703883984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3703883984 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.311600188 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 7871265226 ps |
| CPU time | 81.29 seconds |
| Started | Jul 20 07:22:53 PM PDT 24 |
| Finished | Jul 20 07:24:17 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-9dddd107-77eb-4061-b7e3-be4baa7ded59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311600188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.311600188 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.933917274 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3709021767 ps |
| CPU time | 69.7 seconds |
| Started | Jul 20 07:22:54 PM PDT 24 |
| Finished | Jul 20 07:24:05 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-dedf5e4d-6ac0-4832-95e2-e7950d9d79e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933917274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.933917274 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.3205870275 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 37418002 ps |
| CPU time | 5.73 seconds |
| Started | Jul 20 07:22:52 PM PDT 24 |
| Finished | Jul 20 07:22:58 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-9743732e-d8e7-44d2-8140-a2255590d401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205870275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .3205870275 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.4086968175 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 814457396 ps |
| CPU time | 69.52 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:24:10 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-e8568a33-45cd-4739-bb46-71e3af661e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086968175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.4086968175 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1120347333 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 1579086005 ps |
| CPU time | 121.56 seconds |
| Started | Jul 20 07:23:09 PM PDT 24 |
| Finished | Jul 20 07:25:14 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-69b06a16-12be-4106-9c1f-52b4a4ffc2a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120347333 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1120347333 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1581037829 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 553099392 ps |
| CPU time | 220.39 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:26:40 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b8c48ccb-2968-4b07-978a-b7ec6baf2e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581037829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1581037829 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3094904513 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 3391991616 ps |
| CPU time | 420.87 seconds |
| Started | Jul 20 07:23:09 PM PDT 24 |
| Finished | Jul 20 07:30:13 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-c18ba1c3-e124-4c38-9493-1e055a614ce9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094904513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.3094904513 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.838718300 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 533772707 ps |
| CPU time | 26.71 seconds |
| Started | Jul 20 07:22:59 PM PDT 24 |
| Finished | Jul 20 07:23:27 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-9de672fe-c70f-4b08-97c6-3e62c8a5a30d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838718300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.838718300 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.921124304 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 800997037 ps |
| CPU time | 34.94 seconds |
| Started | Jul 20 07:38:21 PM PDT 24 |
| Finished | Jul 20 07:38:56 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-78d6f375-00d6-4566-be45-75370eaf9889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921124304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device. 921124304 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.3524688369 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 2525393546 ps |
| CPU time | 45.24 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:39:06 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-08e703c9-4187-4b0d-b2aa-2108388f7f77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524688369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.3524688369 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.3896809147 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 219908279 ps |
| CPU time | 24.85 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:38:46 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-7842883e-6c9a-4a4d-9106-9d9ecabfc405 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896809147 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.3896809147 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1813747444 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 70931110 ps |
| CPU time | 8.14 seconds |
| Started | Jul 20 07:38:19 PM PDT 24 |
| Finished | Jul 20 07:38:29 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-70055746-39d3-4e79-a8ad-33fe36ee32dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813747444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1813747444 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3958048444 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 521677354 ps |
| CPU time | 42.74 seconds |
| Started | Jul 20 07:38:12 PM PDT 24 |
| Finished | Jul 20 07:38:56 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-c262f854-4b29-4985-b68d-b786a5a0cf14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958048444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3958048444 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2558015397 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 52306518945 ps |
| CPU time | 634.38 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:48:54 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-04dfb98f-7442-4b09-a154-45646519cf3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558015397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2558015397 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2505409818 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 46826625958 ps |
| CPU time | 879.03 seconds |
| Started | Jul 20 07:38:11 PM PDT 24 |
| Finished | Jul 20 07:52:51 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-eb7fd4da-5efc-46c1-ad89-8370b6c6f030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505409818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2505409818 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.871552207 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 459812257 ps |
| CPU time | 40.46 seconds |
| Started | Jul 20 07:38:14 PM PDT 24 |
| Finished | Jul 20 07:38:56 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-1163b425-6cdc-4c98-93ee-7ced7c051236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871552207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_dela ys.871552207 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3969409250 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 1602062676 ps |
| CPU time | 47.99 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:39:09 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-56839701-a316-4851-8eee-f1cde864d002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969409250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3969409250 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.355607174 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 172246849 ps |
| CPU time | 8.34 seconds |
| Started | Jul 20 07:38:13 PM PDT 24 |
| Finished | Jul 20 07:38:23 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-6669a514-2ae6-4438-b28a-af5be79bf4b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355607174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.355607174 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.2665020737 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 10663084712 ps |
| CPU time | 119.86 seconds |
| Started | Jul 20 07:38:13 PM PDT 24 |
| Finished | Jul 20 07:40:14 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-9f698fe0-38ce-433e-8918-68d977cb8653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665020737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.2665020737 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3696073298 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 3849143018 ps |
| CPU time | 70.39 seconds |
| Started | Jul 20 07:38:10 PM PDT 24 |
| Finished | Jul 20 07:39:21 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-f3b94622-c38d-4909-b8b0-19b546f1b246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696073298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.3696073298 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3922708901 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 37475671 ps |
| CPU time | 5.81 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:38:26 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-33a6248c-01be-442d-a66c-bf0089fdaef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922708901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.3922708901 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.316706971 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 6178506143 ps |
| CPU time | 202.71 seconds |
| Started | Jul 20 07:38:23 PM PDT 24 |
| Finished | Jul 20 07:41:46 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-4940d184-f79e-496c-a023-198292156c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316706971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.316706971 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.4247877244 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 4460203172 ps |
| CPU time | 141.44 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:40:43 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4566fab3-1d28-489a-a90d-5727efe5b8b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247877244 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.4247877244 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3231432666 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 93018494 ps |
| CPU time | 11.89 seconds |
| Started | Jul 20 07:38:17 PM PDT 24 |
| Finished | Jul 20 07:38:30 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c46a0183-f33f-496f-8d63-b984f5d60a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231432666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3231432666 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.2328096558 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 394480277 ps |
| CPU time | 16.56 seconds |
| Started | Jul 20 07:38:19 PM PDT 24 |
| Finished | Jul 20 07:38:37 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-91e05740-82f0-41b8-8ce7-13d02f2d6211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328096558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.2328096558 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.1928993101 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 122643281 ps |
| CPU time | 9.73 seconds |
| Started | Jul 20 07:38:27 PM PDT 24 |
| Finished | Jul 20 07:38:38 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-f325f925-4bd0-4dd3-b4d0-79845f5c1bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928993101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .1928993101 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3547855189 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 35647376425 ps |
| CPU time | 638.16 seconds |
| Started | Jul 20 07:38:25 PM PDT 24 |
| Finished | Jul 20 07:49:04 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-56f45dcf-fd54-4ac9-b12a-8b2778b94790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547855189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3547855189 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.293799108 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 300665041 ps |
| CPU time | 14.94 seconds |
| Started | Jul 20 07:38:27 PM PDT 24 |
| Finished | Jul 20 07:38:42 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-caf941f5-993b-44ec-bf9b-b236af83f0a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293799108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .293799108 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1491979174 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 289500919 ps |
| CPU time | 24.55 seconds |
| Started | Jul 20 07:38:26 PM PDT 24 |
| Finished | Jul 20 07:38:51 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-056810bd-f1e3-4fc1-8e94-ffc79d129449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491979174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1491979174 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.1097497120 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 815881722 ps |
| CPU time | 28.86 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:38:49 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-428dc05c-1cb3-43f0-9ac0-18fa053adbde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097497120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.1097497120 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.778060650 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 75427563389 ps |
| CPU time | 872.8 seconds |
| Started | Jul 20 07:38:26 PM PDT 24 |
| Finished | Jul 20 07:53:00 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-d1aff0ff-0f5c-4dbe-8fd5-b9430f082849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778060650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.778060650 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3176179518 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 23001738512 ps |
| CPU time | 383.15 seconds |
| Started | Jul 20 07:38:29 PM PDT 24 |
| Finished | Jul 20 07:44:52 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a8eeee96-777c-4600-b8c7-4814b38d23e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176179518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.3176179518 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3238807321 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 592676643 ps |
| CPU time | 56.35 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:39:15 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-70dba204-d92b-45cf-bf8a-062c42314796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238807321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3238807321 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.2052912748 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 62125327 ps |
| CPU time | 7.5 seconds |
| Started | Jul 20 07:38:26 PM PDT 24 |
| Finished | Jul 20 07:38:34 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-4e1535d2-f8bf-40d8-b832-3c80c2fffc40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052912748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.2052912748 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2638523114 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 55288227 ps |
| CPU time | 7.19 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:38:28 PM PDT 24 |
| Peak memory | 575252 kb |
| Host | smart-9b02a376-26a9-479e-99cb-ba67129a66e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638523114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2638523114 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2197496163 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 11127874109 ps |
| CPU time | 122.49 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:40:22 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-b0a12c2e-5378-4cc7-a209-4bcd329d14c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197496163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2197496163 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.4026593922 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 6012728697 ps |
| CPU time | 109.63 seconds |
| Started | Jul 20 07:38:20 PM PDT 24 |
| Finished | Jul 20 07:40:11 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-fe9da238-0198-4368-b4bc-849f5b657c00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026593922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.4026593922 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.2409462355 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 43341276 ps |
| CPU time | 5.92 seconds |
| Started | Jul 20 07:38:18 PM PDT 24 |
| Finished | Jul 20 07:38:25 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-b5ea7c81-fd96-42fe-bd8b-fdd6a8f040b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409462355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.2409462355 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2274324660 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 6259183582 ps |
| CPU time | 210.33 seconds |
| Started | Jul 20 07:38:26 PM PDT 24 |
| Finished | Jul 20 07:41:57 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-8da6a532-e64e-468d-825c-7a3aa4904da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274324660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2274324660 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1878274899 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 829220707 ps |
| CPU time | 58.37 seconds |
| Started | Jul 20 07:38:30 PM PDT 24 |
| Finished | Jul 20 07:39:29 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-110fa14f-98be-46a3-b895-990dccc30b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878274899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1878274899 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.3324979256 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 8503020031 ps |
| CPU time | 487.33 seconds |
| Started | Jul 20 07:38:28 PM PDT 24 |
| Finished | Jul 20 07:46:36 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f1434b3c-6d5d-423c-86ed-05de932fdd8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324979256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.3324979256 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1341601098 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 4691537372 ps |
| CPU time | 212.86 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:42:09 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-649c18dd-10dd-478a-b0fc-4f4a8733decb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341601098 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1341601098 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3173501352 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 927343007 ps |
| CPU time | 41.57 seconds |
| Started | Jul 20 07:38:26 PM PDT 24 |
| Finished | Jul 20 07:39:08 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e29713bb-8dd3-4c32-bf1f-990ab5bc9ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173501352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3173501352 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2316954531 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 3190641128 ps |
| CPU time | 123.21 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:40:40 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-f91f3924-0e7a-4cfb-a3ca-3f40454fe72b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316954531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2316954531 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.902442994 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 66251578097 ps |
| CPU time | 1136.06 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:57:32 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-a9868f75-0f5d-4cf1-9a2b-f85a4fedb5c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902442994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_d evice_slow_rsp.902442994 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.2034170438 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 616392658 ps |
| CPU time | 25.46 seconds |
| Started | Jul 20 07:38:47 PM PDT 24 |
| Finished | Jul 20 07:39:13 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-8ec5f39e-f1be-40a4-907c-8c41e57c5c8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034170438 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.2034170438 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1333983157 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 137554537 ps |
| CPU time | 7.58 seconds |
| Started | Jul 20 07:38:35 PM PDT 24 |
| Finished | Jul 20 07:38:44 PM PDT 24 |
| Peak memory | 573356 kb |
| Host | smart-52b54f4a-7ca7-4e2b-becb-d8f9c25df3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333983157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1333983157 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.387421733 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 381683515 ps |
| CPU time | 35.68 seconds |
| Started | Jul 20 07:38:37 PM PDT 24 |
| Finished | Jul 20 07:39:13 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-c97267b5-319a-42a8-8e2f-2f3068bbe943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387421733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.387421733 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.3090786432 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 66931796110 ps |
| CPU time | 811.12 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:52:08 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-227f0cee-4066-49eb-bf54-6f35f5561ce0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090786432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.3090786432 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2329367274 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 37328591641 ps |
| CPU time | 672.56 seconds |
| Started | Jul 20 07:38:35 PM PDT 24 |
| Finished | Jul 20 07:49:48 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-d05b9709-2913-43a8-aeec-84f0f93e3520 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329367274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2329367274 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.3032590553 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 346443408 ps |
| CPU time | 31.23 seconds |
| Started | Jul 20 07:38:35 PM PDT 24 |
| Finished | Jul 20 07:39:06 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-8a1b9ee4-31bb-401a-8ccb-a1fb3d2d83de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032590553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.3032590553 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.294820770 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2559758002 ps |
| CPU time | 82.23 seconds |
| Started | Jul 20 07:38:35 PM PDT 24 |
| Finished | Jul 20 07:39:58 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-97ed8d6d-913a-4b33-899f-67ea24f047d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294820770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.294820770 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1646878023 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 220876225 ps |
| CPU time | 9.31 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:38:47 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-27ffebe4-04d8-4dfe-8213-dd6e154c70c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646878023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1646878023 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.888283796 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 8601513083 ps |
| CPU time | 101.37 seconds |
| Started | Jul 20 07:38:35 PM PDT 24 |
| Finished | Jul 20 07:40:17 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-3bb21fc1-853f-4559-8a96-b46730ea3d5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888283796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.888283796 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.3625524316 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 6191497142 ps |
| CPU time | 111.59 seconds |
| Started | Jul 20 07:38:36 PM PDT 24 |
| Finished | Jul 20 07:40:28 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-7f052cac-e4b2-4e1f-a794-7a834f1ca667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625524316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.3625524316 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3198960381 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 45178372 ps |
| CPU time | 5.88 seconds |
| Started | Jul 20 07:38:37 PM PDT 24 |
| Finished | Jul 20 07:38:43 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-9eec0db9-3c3e-43b7-914c-356bbbd01475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198960381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.3198960381 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.2345416420 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 8092963432 ps |
| CPU time | 318.75 seconds |
| Started | Jul 20 07:38:45 PM PDT 24 |
| Finished | Jul 20 07:44:04 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5312fdd7-77fc-47cf-b6f9-9e98a8c8af0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345416420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.2345416420 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.3718843797 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 5044547390 ps |
| CPU time | 168.33 seconds |
| Started | Jul 20 07:38:44 PM PDT 24 |
| Finished | Jul 20 07:41:33 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-7c61afd9-e346-4b59-89d2-0b61ff395e34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718843797 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.3718843797 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2186024820 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 206549691 ps |
| CPU time | 69.09 seconds |
| Started | Jul 20 07:38:44 PM PDT 24 |
| Finished | Jul 20 07:39:54 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-8852af12-f546-4cc6-a9d5-f091dd6d4e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186024820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2186024820 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.2913544063 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 5388876429 ps |
| CPU time | 614.6 seconds |
| Started | Jul 20 07:38:45 PM PDT 24 |
| Finished | Jul 20 07:49:00 PM PDT 24 |
| Peak memory | 582380 kb |
| Host | smart-82edb16c-cf00-4497-af81-4850a1895f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913544063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.2913544063 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.2677935884 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 229635466 ps |
| CPU time | 29.43 seconds |
| Started | Jul 20 07:38:47 PM PDT 24 |
| Finished | Jul 20 07:39:17 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-ac29ee04-813f-4ff3-b908-b42bfc4ca5bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677935884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.2677935884 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.120835097 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 1600947318 ps |
| CPU time | 67.63 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:40:04 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-40009cf6-a9d8-47cc-93b5-f7a7d887eeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120835097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 120835097 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.401735223 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 12404693013 ps |
| CPU time | 232.57 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:42:48 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-f2e9dbb3-fc7a-4392-85c9-603e4a8cf9da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401735223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_d evice_slow_rsp.401735223 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3572504156 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 149677074 ps |
| CPU time | 8.43 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:03 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-a750c7a5-1c77-4b72-8870-4afdb0b41f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572504156 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3572504156 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.1418694643 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 2432121483 ps |
| CPU time | 87.63 seconds |
| Started | Jul 20 07:38:53 PM PDT 24 |
| Finished | Jul 20 07:40:21 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-0917fab1-0703-4ee2-ab72-714a0345c4d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418694643 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1418694643 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.329959053 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 482236030 ps |
| CPU time | 43.38 seconds |
| Started | Jul 20 07:38:46 PM PDT 24 |
| Finished | Jul 20 07:39:30 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-7daf8818-5d07-4fca-a5dc-b94653f2e6b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329959053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.329959053 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2458619697 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 30311300826 ps |
| CPU time | 329.09 seconds |
| Started | Jul 20 07:38:46 PM PDT 24 |
| Finished | Jul 20 07:44:16 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-ae45cb6c-8dfa-4bd9-98e3-b8a59c681bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458619697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2458619697 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.3721370338 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 51276077648 ps |
| CPU time | 976.82 seconds |
| Started | Jul 20 07:38:46 PM PDT 24 |
| Finished | Jul 20 07:55:04 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8462c2f8-6b4d-4871-95a0-3d537547620f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721370338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.3721370338 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1299425980 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 575698103 ps |
| CPU time | 46.98 seconds |
| Started | Jul 20 07:38:47 PM PDT 24 |
| Finished | Jul 20 07:39:34 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-320d8bd9-ede7-40da-bc28-3ad65c9345de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299425980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1299425980 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.123315088 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 1841671101 ps |
| CPU time | 54.71 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:39:51 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-16da6629-3c4c-471f-a928-cea9590d4d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123315088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.123315088 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.1893171713 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 46706501 ps |
| CPU time | 6.5 seconds |
| Started | Jul 20 07:38:45 PM PDT 24 |
| Finished | Jul 20 07:38:52 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-3dc71900-6bd6-46c8-8f7e-b992d3e3515e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893171713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.1893171713 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.541896504 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 9115066296 ps |
| CPU time | 107.81 seconds |
| Started | Jul 20 07:38:44 PM PDT 24 |
| Finished | Jul 20 07:40:32 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-80f7c500-d4bc-492a-9d8d-d10b8b6394ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541896504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.541896504 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3251578229 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 5396195794 ps |
| CPU time | 95.47 seconds |
| Started | Jul 20 07:38:47 PM PDT 24 |
| Finished | Jul 20 07:40:23 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-7212d3e3-a8ff-4634-8730-faa7de05d541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251578229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3251578229 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.2494769694 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 44810717 ps |
| CPU time | 5.84 seconds |
| Started | Jul 20 07:38:46 PM PDT 24 |
| Finished | Jul 20 07:38:53 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-fe4ea03c-75cf-457b-bbca-249623f77763 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494769694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.2494769694 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3261217563 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 12328748473 ps |
| CPU time | 488.67 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:47:04 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-637aba66-8f0c-4c07-97c7-11e84beb6f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261217563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3261217563 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.1544646287 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 12593112309 ps |
| CPU time | 453.99 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:46:29 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-d0850b66-1fe2-4855-a703-5a9483f441f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544646287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.1544646287 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.4080284803 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 463736601 ps |
| CPU time | 204.06 seconds |
| Started | Jul 20 07:38:56 PM PDT 24 |
| Finished | Jul 20 07:42:21 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-20d730b9-f62e-43d6-be30-a119620921c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080284803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.4080284803 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3616072805 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 81220669 ps |
| CPU time | 31.91 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:26 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-c20f4710-c397-4257-88cd-d2bbc4ef863e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616072805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3616072805 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3477548795 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 222543135 ps |
| CPU time | 26.28 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:21 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-70b5a27a-de17-4fff-8f92-cdd35f83ec1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477548795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3477548795 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.1220888109 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 865168079 ps |
| CPU time | 37.26 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:32 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-8bbc0f5a-864e-42e5-bd5b-a06c49aed527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220888109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .1220888109 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.4007661983 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 59112481190 ps |
| CPU time | 1123.45 seconds |
| Started | Jul 20 07:39:01 PM PDT 24 |
| Finished | Jul 20 07:57:45 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-b3718699-f98e-48e6-ad59-2ce10241fa38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007661983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.4007661983 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1849318952 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 125823390 ps |
| CPU time | 13.47 seconds |
| Started | Jul 20 07:39:07 PM PDT 24 |
| Finished | Jul 20 07:39:21 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-ca57c8d2-e4e2-4042-b311-5bebd2002c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849318952 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1849318952 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2723777541 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 70060894 ps |
| CPU time | 8.79 seconds |
| Started | Jul 20 07:39:03 PM PDT 24 |
| Finished | Jul 20 07:39:12 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-bf1900af-5353-48f8-9d3f-9dea32bfcb92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723777541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2723777541 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.321939770 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 279589950 ps |
| CPU time | 13.71 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:39:09 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-28fcae8d-4b87-4a67-99de-ccaf71052341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321939770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.321939770 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1767394822 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 85011456596 ps |
| CPU time | 1052.46 seconds |
| Started | Jul 20 07:38:57 PM PDT 24 |
| Finished | Jul 20 07:56:30 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-31f53627-90e7-41ca-b4a6-08db0d3eb0b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767394822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1767394822 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.2105305377 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 46105036452 ps |
| CPU time | 867.82 seconds |
| Started | Jul 20 07:38:52 PM PDT 24 |
| Finished | Jul 20 07:53:20 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e5202ef7-8fcc-4c9b-a8b7-e065645dec11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105305377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.2105305377 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.688605647 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 39620764 ps |
| CPU time | 6.38 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:01 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-498c2108-5c49-4e35-96fa-f3e6c03813de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688605647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_dela ys.688605647 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.594755938 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 2114000331 ps |
| CPU time | 56.48 seconds |
| Started | Jul 20 07:39:02 PM PDT 24 |
| Finished | Jul 20 07:39:59 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-462790cc-79e4-480c-a569-92d16cd0cfe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594755938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.594755938 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.4246830543 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 49575858 ps |
| CPU time | 6.74 seconds |
| Started | Jul 20 07:38:57 PM PDT 24 |
| Finished | Jul 20 07:39:04 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-78a9aa16-1984-4f2c-8abd-10f6b8095088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246830543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.4246830543 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1950552272 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 7993894895 ps |
| CPU time | 83.33 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:40:18 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-c20a7dbf-c853-4c2a-bebc-d3f25919136b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950552272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1950552272 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.915868141 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 6204930949 ps |
| CPU time | 109.31 seconds |
| Started | Jul 20 07:38:55 PM PDT 24 |
| Finished | Jul 20 07:40:45 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-a338f2a8-1184-499a-8942-9a9329eb426b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915868141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.915868141 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.4208777756 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 50360638 ps |
| CPU time | 6.69 seconds |
| Started | Jul 20 07:38:54 PM PDT 24 |
| Finished | Jul 20 07:39:02 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-5d2412e6-b893-4bda-b9a3-8aef3248500a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208777756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.4208777756 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.3818065190 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 13219562694 ps |
| CPU time | 542.12 seconds |
| Started | Jul 20 07:39:01 PM PDT 24 |
| Finished | Jul 20 07:48:04 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-b3492729-76d6-4205-a9e7-4098a39246ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818065190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3818065190 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2684531677 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 16861817947 ps |
| CPU time | 624.66 seconds |
| Started | Jul 20 07:39:05 PM PDT 24 |
| Finished | Jul 20 07:49:30 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-825c98fb-4b51-44d5-96cf-96c925dcec29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684531677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2684531677 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.1172081977 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 531474192 ps |
| CPU time | 203.17 seconds |
| Started | Jul 20 07:39:01 PM PDT 24 |
| Finished | Jul 20 07:42:25 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-817707a2-39d2-49a8-aed0-c8a1312a89dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172081977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.1172081977 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1088188771 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 1092323185 ps |
| CPU time | 104.6 seconds |
| Started | Jul 20 07:39:02 PM PDT 24 |
| Finished | Jul 20 07:40:47 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-e1b2e6d2-f71b-4d92-b6e2-f87f647bc702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088188771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1088188771 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.51337924 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 926707178 ps |
| CPU time | 32.96 seconds |
| Started | Jul 20 07:39:03 PM PDT 24 |
| Finished | Jul 20 07:39:36 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-68da8af3-3c41-4383-b968-35a339306d68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51337924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.51337924 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1259526751 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 1100980803 ps |
| CPU time | 94.24 seconds |
| Started | Jul 20 07:39:14 PM PDT 24 |
| Finished | Jul 20 07:40:49 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-f1e1b820-ab5f-46b4-8a5c-b8e2f58114cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259526751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1259526751 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.1399427686 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 129693693388 ps |
| CPU time | 2442.92 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 08:19:55 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-38f091c9-32d5-4314-abef-8d26b815d5a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399427686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.1399427686 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1647569730 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 296575861 ps |
| CPU time | 32.69 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:39:44 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-59721dfb-5fcf-4ce1-be47-fa323a9a4666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647569730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1647569730 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2292043463 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 1392868284 ps |
| CPU time | 45.92 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:39:58 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-83d758fe-e821-490a-b500-e3adf57fff4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292043463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2292043463 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.164652499 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 136034209 ps |
| CPU time | 14.46 seconds |
| Started | Jul 20 07:39:00 PM PDT 24 |
| Finished | Jul 20 07:39:15 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-2d980eda-fb61-4bf4-ad25-0da3b4785430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164652499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.164652499 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.1127070542 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 59829452483 ps |
| CPU time | 664.22 seconds |
| Started | Jul 20 07:39:04 PM PDT 24 |
| Finished | Jul 20 07:50:09 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-c78fcbd6-1671-414a-92ac-72ccd398313f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127070542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.1127070542 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.3784114660 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 36805845006 ps |
| CPU time | 706.15 seconds |
| Started | Jul 20 07:39:23 PM PDT 24 |
| Finished | Jul 20 07:51:10 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-ef688535-0b05-4f86-adbb-57b254dc647b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784114660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.3784114660 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.1641433815 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 173896372 ps |
| CPU time | 16.21 seconds |
| Started | Jul 20 07:39:07 PM PDT 24 |
| Finished | Jul 20 07:39:24 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f790f394-24dd-4432-8ed1-ee82ff818e03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641433815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.1641433815 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3681313365 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 204176138 ps |
| CPU time | 16.52 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:39:41 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-6af44ceb-106b-48aa-a1cf-646563f0e299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681313365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3681313365 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1240653207 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 48591075 ps |
| CPU time | 6.61 seconds |
| Started | Jul 20 07:39:00 PM PDT 24 |
| Finished | Jul 20 07:39:08 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-a5b752b9-c776-412a-bd26-4f537b3f0a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240653207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1240653207 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.1496403743 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 6548811896 ps |
| CPU time | 72.01 seconds |
| Started | Jul 20 07:39:05 PM PDT 24 |
| Finished | Jul 20 07:40:17 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-994673d3-52ad-4d41-97c6-dd983bade1c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496403743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.1496403743 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.44389443 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 5873515807 ps |
| CPU time | 106.17 seconds |
| Started | Jul 20 07:39:03 PM PDT 24 |
| Finished | Jul 20 07:40:50 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-bc792257-2598-479a-b87e-32c007b4769e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44389443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.44389443 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2655881566 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 35664740 ps |
| CPU time | 5.5 seconds |
| Started | Jul 20 07:39:07 PM PDT 24 |
| Finished | Jul 20 07:39:13 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-bfd66808-e9a1-461c-a899-73d174ea1b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655881566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2655881566 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3444693368 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 7675430042 ps |
| CPU time | 265.1 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:43:37 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-8bdae54e-3051-4ede-8549-57d1658008a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444693368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3444693368 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.3674556507 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2882534359 ps |
| CPU time | 206.64 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:42:51 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-9c658d98-2a9b-4ef9-b75e-e90294623960 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674556507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.3674556507 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1686151705 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 9834565508 ps |
| CPU time | 496.5 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:47:28 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-07a49621-4719-46d7-b7ef-10f5b5801973 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686151705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1686151705 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.767680459 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 428414450 ps |
| CPU time | 112.88 seconds |
| Started | Jul 20 07:39:13 PM PDT 24 |
| Finished | Jul 20 07:41:06 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-bd4debb2-5380-416e-898b-01bb6034a4ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767680459 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.767680459 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.3905432291 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 93620788 ps |
| CPU time | 11.84 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:39:23 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-84fc283f-a10e-45ac-bbd1-9e7df51dd937 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905432291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.3905432291 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2519441320 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2763884567 ps |
| CPU time | 102.93 seconds |
| Started | Jul 20 07:39:20 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-5df7e81e-e5f1-4733-b73d-cd21871cca2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519441320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2519441320 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.1429080702 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 110446919395 ps |
| CPU time | 2057.51 seconds |
| Started | Jul 20 07:39:20 PM PDT 24 |
| Finished | Jul 20 08:13:39 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-ffc98707-f63d-459e-a729-6e10d51f37ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429080702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.1429080702 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3062015648 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 146636185 ps |
| CPU time | 15.47 seconds |
| Started | Jul 20 07:39:19 PM PDT 24 |
| Finished | Jul 20 07:39:36 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-1709d875-3a0b-4b02-b5a7-e93ccc3917d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062015648 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3062015648 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.1902713328 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 430834915 ps |
| CPU time | 15.96 seconds |
| Started | Jul 20 07:39:22 PM PDT 24 |
| Finished | Jul 20 07:39:39 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-d76f8de4-48f5-466f-8d27-d4946e0dbeef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902713328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.1902713328 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2055930133 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 1001678684 ps |
| CPU time | 38.74 seconds |
| Started | Jul 20 07:39:13 PM PDT 24 |
| Finished | Jul 20 07:39:52 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f9287c7b-bd35-499f-8f13-7d0258cf580d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055930133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2055930133 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.3859371994 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 96298460340 ps |
| CPU time | 1127.47 seconds |
| Started | Jul 20 07:39:20 PM PDT 24 |
| Finished | Jul 20 07:58:08 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-a73700d5-2612-4830-ac03-b27f27d7ae3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859371994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.3859371994 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.3710142401 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 27441304442 ps |
| CPU time | 491.82 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:47:37 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-149abd4b-5167-464d-a8e6-4f636f81fd1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710142401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.3710142401 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3409524672 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 38741971 ps |
| CPU time | 5.75 seconds |
| Started | Jul 20 07:39:13 PM PDT 24 |
| Finished | Jul 20 07:39:19 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-babb42a6-d482-4359-9421-267de62426bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409524672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3409524672 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1600521383 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 401377818 ps |
| CPU time | 13.85 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:39:38 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-19be6f6f-7794-4777-93ea-af9edc7cbf82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600521383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1600521383 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3736262313 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 41205401 ps |
| CPU time | 6.15 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:39:18 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-5fef2b1f-f4c6-4a97-bd26-88f1653c5370 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736262313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3736262313 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1925681122 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 9435176521 ps |
| CPU time | 106.19 seconds |
| Started | Jul 20 07:39:11 PM PDT 24 |
| Finished | Jul 20 07:40:57 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-412d502a-5e45-476e-bbdb-39a98e3cabf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925681122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1925681122 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.2371925310 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 2410524291 ps |
| CPU time | 41.72 seconds |
| Started | Jul 20 07:39:10 PM PDT 24 |
| Finished | Jul 20 07:39:53 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-559682c4-89ab-4fae-baf9-33b275d96aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371925310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.2371925310 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.2690035163 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 48441939 ps |
| CPU time | 6.79 seconds |
| Started | Jul 20 07:39:09 PM PDT 24 |
| Finished | Jul 20 07:39:17 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-a3f0501e-bb14-43e3-b388-98abe14a6e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690035163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.2690035163 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.3898271558 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 7995705304 ps |
| CPU time | 304.39 seconds |
| Started | Jul 20 07:39:20 PM PDT 24 |
| Finished | Jul 20 07:44:26 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-3c097a48-5dc7-4fe9-bc82-4f30dffd0c1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898271558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.3898271558 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.1055428513 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 1716289571 ps |
| CPU time | 75.32 seconds |
| Started | Jul 20 07:39:22 PM PDT 24 |
| Finished | Jul 20 07:40:38 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-b2451842-16f8-4cb3-8cb0-ac4918934679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055428513 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.1055428513 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3302990111 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 210141214 ps |
| CPU time | 68.17 seconds |
| Started | Jul 20 07:39:22 PM PDT 24 |
| Finished | Jul 20 07:40:30 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-efe43e1a-c6b8-4b64-92b9-f8408fe13aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302990111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.3302990111 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.2154730041 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 3680761231 ps |
| CPU time | 284.73 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:44:09 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-35ab2008-4395-4679-83ad-c8c647e16bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154730041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_al l_with_reset_error.2154730041 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.448538493 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 659476995 ps |
| CPU time | 32.35 seconds |
| Started | Jul 20 07:39:22 PM PDT 24 |
| Finished | Jul 20 07:39:55 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-4468e32b-4458-42c5-8f80-8d35e24a7cb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448538493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.448538493 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.3068800093 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1027714228 ps |
| CPU time | 62.06 seconds |
| Started | Jul 20 07:39:28 PM PDT 24 |
| Finished | Jul 20 07:40:30 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-88d846ec-098a-4d8f-9699-66bc440da46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068800093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .3068800093 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.4195466896 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 112995461535 ps |
| CPU time | 2058.45 seconds |
| Started | Jul 20 07:39:30 PM PDT 24 |
| Finished | Jul 20 08:13:49 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-922797f7-3468-4f19-9d14-1aab008f68e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195466896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.4195466896 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3045038884 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 106921942 ps |
| CPU time | 12.38 seconds |
| Started | Jul 20 07:39:28 PM PDT 24 |
| Finished | Jul 20 07:39:41 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-51b77bb9-fb2d-4813-b4d9-af109929f5a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045038884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3045038884 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.911015168 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 370459129 ps |
| CPU time | 16.25 seconds |
| Started | Jul 20 07:39:29 PM PDT 24 |
| Finished | Jul 20 07:39:45 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-f381d2ac-0866-4282-b09d-94abc435a97c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911015168 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.911015168 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.2673966501 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1517029334 ps |
| CPU time | 55.81 seconds |
| Started | Jul 20 07:39:25 PM PDT 24 |
| Finished | Jul 20 07:40:21 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-48c06286-6436-4846-b5fc-6043fa8640fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673966501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2673966501 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1436401180 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 36510277727 ps |
| CPU time | 400.01 seconds |
| Started | Jul 20 07:39:27 PM PDT 24 |
| Finished | Jul 20 07:46:08 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-51d09dd8-7025-41f8-b3d6-72bfb9ec52ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436401180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1436401180 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2989424463 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 8810174922 ps |
| CPU time | 154.68 seconds |
| Started | Jul 20 07:39:27 PM PDT 24 |
| Finished | Jul 20 07:42:02 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-64d8691b-abb7-4776-8baa-90c630e97386 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989424463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2989424463 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.2751964312 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 327566386 ps |
| CPU time | 31.41 seconds |
| Started | Jul 20 07:39:25 PM PDT 24 |
| Finished | Jul 20 07:39:57 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-fb3a1b63-3a71-4d4f-9692-28c6243d45ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751964312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.2751964312 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2365976169 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 2572979968 ps |
| CPU time | 83.48 seconds |
| Started | Jul 20 07:39:28 PM PDT 24 |
| Finished | Jul 20 07:40:52 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-c31f78e7-0eac-47d9-93a6-bc1f6a570455 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365976169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2365976169 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.4027375817 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 210477411 ps |
| CPU time | 8.53 seconds |
| Started | Jul 20 07:39:28 PM PDT 24 |
| Finished | Jul 20 07:39:37 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-4eb1ddb0-4ede-4045-99a3-0d823dc260ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027375817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.4027375817 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1650391721 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 9672466028 ps |
| CPU time | 108.85 seconds |
| Started | Jul 20 07:39:25 PM PDT 24 |
| Finished | Jul 20 07:41:14 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-120868d1-2eb8-48e3-8181-cdb650cec5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650391721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1650391721 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.838349857 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 5879092019 ps |
| CPU time | 102.44 seconds |
| Started | Jul 20 07:39:25 PM PDT 24 |
| Finished | Jul 20 07:41:08 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c9ed778f-dd5c-463b-a1c6-e54f324c8086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838349857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.838349857 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3106757432 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 38447479 ps |
| CPU time | 5.82 seconds |
| Started | Jul 20 07:39:24 PM PDT 24 |
| Finished | Jul 20 07:39:31 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-e15adb18-80cc-4d42-9d97-7145d1f0dd94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106757432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3106757432 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2391568156 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 17570815189 ps |
| CPU time | 767.46 seconds |
| Started | Jul 20 07:39:34 PM PDT 24 |
| Finished | Jul 20 07:52:22 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-c131cf44-711b-4f09-bb5b-1a2ad2e951e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391568156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2391568156 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4036150192 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 7740154391 ps |
| CPU time | 298.03 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 07:44:37 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-01849139-31dd-4f82-9915-c17f377bbb5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036150192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4036150192 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1053262709 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 10391612222 ps |
| CPU time | 670 seconds |
| Started | Jul 20 07:39:36 PM PDT 24 |
| Finished | Jul 20 07:50:47 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-4de890ef-c570-4c21-90e9-7dd3502f4e0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053262709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1053262709 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3600914058 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 211339509 ps |
| CPU time | 43.97 seconds |
| Started | Jul 20 07:39:32 PM PDT 24 |
| Finished | Jul 20 07:40:17 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-ee09c32e-d744-427f-b7ca-8446a5a2938d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600914058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3600914058 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2472892571 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 822831974 ps |
| CPU time | 37.2 seconds |
| Started | Jul 20 07:39:25 PM PDT 24 |
| Finished | Jul 20 07:40:02 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-cb66ed20-d430-430a-9eba-70d2d4035f1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472892571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2472892571 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2180970406 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 300457296 ps |
| CPU time | 23.6 seconds |
| Started | Jul 20 07:39:32 PM PDT 24 |
| Finished | Jul 20 07:39:56 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-75ae6b05-50c4-4873-9af1-be44b534a16c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180970406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2180970406 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3583193093 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 113595365696 ps |
| CPU time | 2054.76 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 08:13:54 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-0ad786d6-a7f9-46ea-8487-17196e0fc1b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583193093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.3583193093 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.791351576 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 268226365 ps |
| CPU time | 28.97 seconds |
| Started | Jul 20 07:39:39 PM PDT 24 |
| Finished | Jul 20 07:40:08 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-f60eb77f-900b-466d-848b-9ef0cf5e917a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791351576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .791351576 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1474933112 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 654594250 ps |
| CPU time | 21.01 seconds |
| Started | Jul 20 07:39:29 PM PDT 24 |
| Finished | Jul 20 07:39:51 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-9f2c6154-aa31-4e69-acf9-92fab0b40b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474933112 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1474933112 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2473879203 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 197821411 ps |
| CPU time | 18.55 seconds |
| Started | Jul 20 07:39:34 PM PDT 24 |
| Finished | Jul 20 07:39:54 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-600303c4-01de-4306-833a-fcc5760d99e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473879203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2473879203 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.1394119790 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 51471415449 ps |
| CPU time | 607.68 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 07:49:46 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-35ea1669-76ac-43f1-aba7-5d8981543183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394119790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.1394119790 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.568088259 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 8047340246 ps |
| CPU time | 140.28 seconds |
| Started | Jul 20 07:39:31 PM PDT 24 |
| Finished | Jul 20 07:41:52 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-fd66f091-8745-441a-9325-c7328e31173c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568088259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.568088259 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.3707140168 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 68839218 ps |
| CPU time | 9.49 seconds |
| Started | Jul 20 07:39:35 PM PDT 24 |
| Finished | Jul 20 07:39:45 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-6f26704d-d8ea-4172-bd2b-b918c48968a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707140168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.3707140168 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.1716662374 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 2282079467 ps |
| CPU time | 73.05 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 07:40:52 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-dda54566-eb18-4068-af5c-76ab530662f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716662374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.1716662374 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.514926373 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 237222695 ps |
| CPU time | 10.44 seconds |
| Started | Jul 20 07:39:34 PM PDT 24 |
| Finished | Jul 20 07:39:45 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-37896af5-4ce5-4132-9ecc-bb4042fe1aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514926373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.514926373 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2386442590 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8326621809 ps |
| CPU time | 91.71 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 07:41:11 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-a7149bbc-38e6-45a9-ba6c-b12d43e4c871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386442590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2386442590 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3969471250 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 4456989376 ps |
| CPU time | 69.47 seconds |
| Started | Jul 20 07:39:32 PM PDT 24 |
| Finished | Jul 20 07:40:42 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-a33ef6e4-93ab-4f0c-bd43-8d9aa6f04617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969471250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3969471250 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1861689067 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 40058585 ps |
| CPU time | 5.89 seconds |
| Started | Jul 20 07:39:33 PM PDT 24 |
| Finished | Jul 20 07:39:39 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-5559efa3-77f6-4c9f-8478-c27089c9dc2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861689067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1861689067 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.3059786005 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 7119484732 ps |
| CPU time | 279.02 seconds |
| Started | Jul 20 07:39:47 PM PDT 24 |
| Finished | Jul 20 07:44:26 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a6483d4c-c20c-48ee-a41d-5b4bd7fff8a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059786005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3059786005 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2211227678 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 7858476960 ps |
| CPU time | 315.45 seconds |
| Started | Jul 20 07:39:44 PM PDT 24 |
| Finished | Jul 20 07:45:00 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-2ba19973-c403-432a-9de0-67a0338ccc04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211227678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.2211227678 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2330982523 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 405619695 ps |
| CPU time | 100.39 seconds |
| Started | Jul 20 07:39:40 PM PDT 24 |
| Finished | Jul 20 07:41:21 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-34c9c749-8e33-490f-a356-2ae5180809c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330982523 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2330982523 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.4261044357 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 464774711 ps |
| CPU time | 20.52 seconds |
| Started | Jul 20 07:39:38 PM PDT 24 |
| Finished | Jul 20 07:39:59 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-ef573963-61f6-4eaf-957b-656be5315d96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261044357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.4261044357 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.3853027795 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 282724291 ps |
| CPU time | 11.41 seconds |
| Started | Jul 20 07:39:41 PM PDT 24 |
| Finished | Jul 20 07:39:53 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-233388aa-5c09-43c3-a59f-c38c00b54c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853027795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .3853027795 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.901920927 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 110279473688 ps |
| CPU time | 2128.28 seconds |
| Started | Jul 20 07:39:42 PM PDT 24 |
| Finished | Jul 20 08:15:11 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-9aca4de5-923a-4a9c-b062-650b09fde49f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901920927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.901920927 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.1479702661 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 263537041 ps |
| CPU time | 32.77 seconds |
| Started | Jul 20 07:39:51 PM PDT 24 |
| Finished | Jul 20 07:40:24 PM PDT 24 |
| Peak memory | 575128 kb |
| Host | smart-5fa10c3d-faa0-4289-87fb-b8f65efaa6c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479702661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.1479702661 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.831137975 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 53851303 ps |
| CPU time | 7.97 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 07:39:57 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-b41960dc-fae0-4411-bd6b-9c278b2ae4b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831137975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.831137975 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.855224834 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 1696012507 ps |
| CPU time | 69.5 seconds |
| Started | Jul 20 07:39:44 PM PDT 24 |
| Finished | Jul 20 07:40:54 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-88110d8d-9ec2-4d20-afb6-7e40d0a821e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855224834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.855224834 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.2924097615 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 15001828686 ps |
| CPU time | 164.68 seconds |
| Started | Jul 20 07:39:42 PM PDT 24 |
| Finished | Jul 20 07:42:27 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-73ec446c-b0d6-4306-9ade-c081e2603198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924097615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.2924097615 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.935083558 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 59943977382 ps |
| CPU time | 1116.09 seconds |
| Started | Jul 20 07:39:39 PM PDT 24 |
| Finished | Jul 20 07:58:16 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0b2252d3-f6cd-488b-8fca-89f1901baaa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935083558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.935083558 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.469602978 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 33688706 ps |
| CPU time | 5.73 seconds |
| Started | Jul 20 07:39:43 PM PDT 24 |
| Finished | Jul 20 07:39:49 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-64fc9c31-b65a-4771-bda0-e7e08f09e21c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469602978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.469602978 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.3304962935 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 302496146 ps |
| CPU time | 24.37 seconds |
| Started | Jul 20 07:39:50 PM PDT 24 |
| Finished | Jul 20 07:40:14 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-71d52f3b-724f-48c9-8e86-9112776f47f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304962935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.3304962935 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.564186212 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 166689352 ps |
| CPU time | 8.32 seconds |
| Started | Jul 20 07:39:40 PM PDT 24 |
| Finished | Jul 20 07:39:49 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-59ffc70f-9616-479a-9767-743e17d21ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564186212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.564186212 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.4083297733 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 8606787829 ps |
| CPU time | 99.11 seconds |
| Started | Jul 20 07:39:39 PM PDT 24 |
| Finished | Jul 20 07:41:19 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6b83308e-cca9-4665-97ad-d46034437baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083297733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.4083297733 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.284877089 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 5597991440 ps |
| CPU time | 98.03 seconds |
| Started | Jul 20 07:39:40 PM PDT 24 |
| Finished | Jul 20 07:41:18 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-00082f07-e54f-41d7-b1ef-7bd886d0a122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284877089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.284877089 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.1662398357 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 52817412 ps |
| CPU time | 6.45 seconds |
| Started | Jul 20 07:39:41 PM PDT 24 |
| Finished | Jul 20 07:39:48 PM PDT 24 |
| Peak memory | 575244 kb |
| Host | smart-36d7c23a-2c4d-43a3-83e7-7384333d4238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662398357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.1662398357 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3392114604 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 1479291057 ps |
| CPU time | 56.65 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:40:53 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e09c263a-775a-4f1f-9dd1-3870a6cba28e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392114604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3392114604 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2525824574 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 6084401862 ps |
| CPU time | 227.89 seconds |
| Started | Jul 20 07:39:51 PM PDT 24 |
| Finished | Jul 20 07:43:40 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f9c4a17f-95e5-41ff-a91f-829fc67902fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525824574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2525824574 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.3398413458 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 468664819 ps |
| CPU time | 159.25 seconds |
| Started | Jul 20 07:39:50 PM PDT 24 |
| Finished | Jul 20 07:42:29 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-35efa25a-caad-4d48-a3d8-750b363ac711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398413458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.3398413458 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.4258466036 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 263393563 ps |
| CPU time | 73.2 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-224531e3-1ccd-4bcf-8998-f9529f6c707c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258466036 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.4258466036 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1707015566 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 80055441 ps |
| CPU time | 13.26 seconds |
| Started | Jul 20 07:39:50 PM PDT 24 |
| Finished | Jul 20 07:40:04 PM PDT 24 |
| Peak memory | 575280 kb |
| Host | smart-a6314ae9-2b6a-4824-a535-7478c1c7b5c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707015566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1707015566 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.2874086014 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 7012382372 ps |
| CPU time | 384.23 seconds |
| Started | Jul 20 07:23:48 PM PDT 24 |
| Finished | Jul 20 07:30:13 PM PDT 24 |
| Peak memory | 637904 kb |
| Host | smart-13913c8a-885a-40eb-8956-586f2951d9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874086014 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.2874086014 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.3382609766 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 5885547194 ps |
| CPU time | 596.64 seconds |
| Started | Jul 20 07:23:41 PM PDT 24 |
| Finished | Jul 20 07:33:40 PM PDT 24 |
| Peak memory | 598080 kb |
| Host | smart-bd81bee5-ee86-42be-badb-adcc4d0b603f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382609766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.3382609766 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3178932703 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 15382488723 ps |
| CPU time | 1880.14 seconds |
| Started | Jul 20 07:23:14 PM PDT 24 |
| Finished | Jul 20 07:54:37 PM PDT 24 |
| Peak memory | 592748 kb |
| Host | smart-bb76724f-9de1-4c55-9c7a-188a5389f72a |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178932703 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3178932703 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.299997430 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3025430240 ps |
| CPU time | 189.51 seconds |
| Started | Jul 20 07:23:17 PM PDT 24 |
| Finished | Jul 20 07:26:28 PM PDT 24 |
| Peak memory | 602876 kb |
| Host | smart-2e13fe2a-6c41-4ea1-89cc-8e23b0129043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299997430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.299997430 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2172343710 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 1592056279 ps |
| CPU time | 82.88 seconds |
| Started | Jul 20 07:23:32 PM PDT 24 |
| Finished | Jul 20 07:24:57 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-a44f79be-2480-48ef-9d02-5a57412e6610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172343710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2172343710 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.304462550 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 33063499312 ps |
| CPU time | 598.98 seconds |
| Started | Jul 20 07:23:43 PM PDT 24 |
| Finished | Jul 20 07:33:44 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-9f9ac491-0224-4628-9af2-b40f1754778d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304462550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.304462550 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2146783815 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 1325084496 ps |
| CPU time | 48.35 seconds |
| Started | Jul 20 07:23:41 PM PDT 24 |
| Finished | Jul 20 07:24:32 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-e3851968-5e73-4731-b392-5c58c49345f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146783815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2146783815 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1224417136 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 104729262 ps |
| CPU time | 10.17 seconds |
| Started | Jul 20 07:23:40 PM PDT 24 |
| Finished | Jul 20 07:23:52 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-558e0468-6807-4445-90b2-235dc9a5a849 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224417136 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1224417136 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.1745107795 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 1710124143 ps |
| CPU time | 61.52 seconds |
| Started | Jul 20 07:23:16 PM PDT 24 |
| Finished | Jul 20 07:24:19 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-7ef43d9d-3950-4be8-97a5-b1f1ece0ddd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745107795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1745107795 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.949523090 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 34433678294 ps |
| CPU time | 373.74 seconds |
| Started | Jul 20 07:23:32 PM PDT 24 |
| Finished | Jul 20 07:29:48 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f93c7780-cc71-4c30-a12c-9fdac9e54637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949523090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.949523090 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.1079974897 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 3137183576 ps |
| CPU time | 53.35 seconds |
| Started | Jul 20 07:23:31 PM PDT 24 |
| Finished | Jul 20 07:24:26 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-b02863cb-c6df-4d53-8b31-04b80e544fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079974897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.1079974897 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.3466426510 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 440184851 ps |
| CPU time | 40.69 seconds |
| Started | Jul 20 07:23:24 PM PDT 24 |
| Finished | Jul 20 07:24:05 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-4aeb8605-bb23-4aa1-884b-681b6e4cc6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466426510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.3466426510 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.2361461237 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 1073048621 ps |
| CPU time | 35.05 seconds |
| Started | Jul 20 07:23:40 PM PDT 24 |
| Finished | Jul 20 07:24:16 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-bdf3c2e5-8215-463a-b11a-b66c62578903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361461237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.2361461237 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.2547607086 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 166651297 ps |
| CPU time | 8.71 seconds |
| Started | Jul 20 07:23:16 PM PDT 24 |
| Finished | Jul 20 07:23:26 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-2ae1a88d-1249-4f2c-870b-63675510da68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547607086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.2547607086 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3125990138 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 7354926264 ps |
| CPU time | 85.34 seconds |
| Started | Jul 20 07:23:16 PM PDT 24 |
| Finished | Jul 20 07:24:42 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-f3319094-21d6-461f-b09a-a71861a47dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125990138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3125990138 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.683516136 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 5049882238 ps |
| CPU time | 88.34 seconds |
| Started | Jul 20 07:23:16 PM PDT 24 |
| Finished | Jul 20 07:24:46 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-5a339049-a558-42ed-b3cd-ca6e0dd4e34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683516136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.683516136 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.1520302417 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 52002960 ps |
| CPU time | 6.84 seconds |
| Started | Jul 20 07:23:17 PM PDT 24 |
| Finished | Jul 20 07:23:25 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-08c38a2d-b3b8-4de1-9352-71c0230e548d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520302417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .1520302417 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.1201104033 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 8189390313 ps |
| CPU time | 294.85 seconds |
| Started | Jul 20 07:23:43 PM PDT 24 |
| Finished | Jul 20 07:28:40 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5726fb9c-0358-4350-8639-ba2749f0377e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201104033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.1201104033 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.2691251880 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 1711774540 ps |
| CPU time | 109.28 seconds |
| Started | Jul 20 07:23:41 PM PDT 24 |
| Finished | Jul 20 07:25:32 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-e405e4cf-0846-42ef-ad31-3846c7872171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691251880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.2691251880 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.1428155587 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 94366885 ps |
| CPU time | 50.4 seconds |
| Started | Jul 20 07:23:42 PM PDT 24 |
| Finished | Jul 20 07:24:35 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-0a90022b-4f0f-4294-9b94-9397f6fe76b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428155587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.1428155587 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.773158974 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 109121151 ps |
| CPU time | 29.94 seconds |
| Started | Jul 20 07:23:40 PM PDT 24 |
| Finished | Jul 20 07:24:11 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-3db50741-c22c-456c-bee3-47e71fe9bf9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773158974 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.773158974 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.3850916162 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 289582919 ps |
| CPU time | 31.9 seconds |
| Started | Jul 20 07:23:41 PM PDT 24 |
| Finished | Jul 20 07:24:14 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-d7299557-8a28-4612-88b7-a8a4d592bbf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850916162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.3850916162 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3595909109 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1464748009 ps |
| CPU time | 63.6 seconds |
| Started | Jul 20 07:39:48 PM PDT 24 |
| Finished | Jul 20 07:40:52 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-8f9dce18-79cd-4918-a880-33b9d5bb0590 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595909109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .3595909109 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.3905614909 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 325796455 ps |
| CPU time | 33.5 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:40:31 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-a6caa838-20e4-437a-b94d-ab275a3409ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905614909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.3905614909 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.3165766864 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 2494651954 ps |
| CPU time | 88.85 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 07:41:18 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-99bd6b9c-58b2-4a62-a64b-84d2e61c38d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165766864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3165766864 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.3722870987 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 497696063 ps |
| CPU time | 36.56 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 07:40:26 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-88af3799-87d8-4490-970a-8e09d149aae2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722870987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3722870987 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.723758655 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 45977253961 ps |
| CPU time | 529.19 seconds |
| Started | Jul 20 07:39:47 PM PDT 24 |
| Finished | Jul 20 07:48:37 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-b1db4f64-03c0-4297-b1ff-f426e1b86015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723758655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.723758655 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.3371588690 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 29183005519 ps |
| CPU time | 512.86 seconds |
| Started | Jul 20 07:39:49 PM PDT 24 |
| Finished | Jul 20 07:48:23 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-c9a57d53-c25f-456e-ad76-cd6a36f05a10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371588690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.3371588690 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.4101805742 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 375003119 ps |
| CPU time | 32.42 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:40:29 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-b8254bcd-e8d9-4c2a-a06c-a2222127605a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101805742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.4101805742 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.124618720 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 126781456 ps |
| CPU time | 10.95 seconds |
| Started | Jul 20 07:39:55 PM PDT 24 |
| Finished | Jul 20 07:40:07 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-bea821cf-f8ba-4f3a-8c2a-a76573d43a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124618720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.124618720 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.9976981 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 140420875 ps |
| CPU time | 6.99 seconds |
| Started | Jul 20 07:39:48 PM PDT 24 |
| Finished | Jul 20 07:39:55 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-4f43fb37-ace6-4f2c-ad52-939400929807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9976981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.9976981 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1948925201 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 8018148275 ps |
| CPU time | 87.2 seconds |
| Started | Jul 20 07:39:57 PM PDT 24 |
| Finished | Jul 20 07:41:25 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2a923989-d097-4f77-a99e-40d2383ed62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948925201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1948925201 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.1726961349 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 5705025466 ps |
| CPU time | 97.74 seconds |
| Started | Jul 20 07:39:47 PM PDT 24 |
| Finished | Jul 20 07:41:25 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f5f57220-7041-4e59-8cd7-dd377fadc7d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726961349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.1726961349 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3722912698 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 48978494 ps |
| CPU time | 6.54 seconds |
| Started | Jul 20 07:39:48 PM PDT 24 |
| Finished | Jul 20 07:39:55 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-63c00df3-1e33-457e-ab6d-ff75b3b21456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722912698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.3722912698 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.125011018 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 17831630874 ps |
| CPU time | 788.66 seconds |
| Started | Jul 20 07:39:59 PM PDT 24 |
| Finished | Jul 20 07:53:09 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-1d1ace0b-c14d-4bb7-bf54-d7da02f6682a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125011018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.125011018 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.3889665269 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 1395822585 ps |
| CPU time | 100.79 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:41:38 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-c9860569-41e5-4871-a976-c3c24603403d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889665269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.3889665269 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.2035073588 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 2998410234 ps |
| CPU time | 548.2 seconds |
| Started | Jul 20 07:39:54 PM PDT 24 |
| Finished | Jul 20 07:49:02 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-725f0138-b8ce-4205-b5cf-515ae90e3305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035073588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.2035073588 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3999862671 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 5664563582 ps |
| CPU time | 590.39 seconds |
| Started | Jul 20 07:39:54 PM PDT 24 |
| Finished | Jul 20 07:49:45 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-f98fc57f-53e8-4100-a43d-6293b1543660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999862671 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3999862671 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.1475320602 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 242810771 ps |
| CPU time | 29.94 seconds |
| Started | Jul 20 07:39:48 PM PDT 24 |
| Finished | Jul 20 07:40:19 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-63a1f83f-5a6d-453b-8924-fa3d2d3ef117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475320602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.1475320602 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.4186910558 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 2723886138 ps |
| CPU time | 108.69 seconds |
| Started | Jul 20 07:39:55 PM PDT 24 |
| Finished | Jul 20 07:41:45 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f338e540-8327-459a-af39-f39db6ec0a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186910558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .4186910558 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.313376216 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 111116324 ps |
| CPU time | 12.77 seconds |
| Started | Jul 20 07:40:06 PM PDT 24 |
| Finished | Jul 20 07:40:20 PM PDT 24 |
| Peak memory | 575240 kb |
| Host | smart-b558d5ab-7601-4540-9b84-be5da464b86b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313376216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .313376216 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.3799335848 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 2481767987 ps |
| CPU time | 84.66 seconds |
| Started | Jul 20 07:40:05 PM PDT 24 |
| Finished | Jul 20 07:41:32 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3fa3dda5-a0f4-482d-8f91-aa26d9cf9e56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799335848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3799335848 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.3871115088 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 1548989492 ps |
| CPU time | 58.9 seconds |
| Started | Jul 20 07:39:58 PM PDT 24 |
| Finished | Jul 20 07:40:58 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-98b4a2a8-3f0c-4d57-8d5f-35bae249f18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871115088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.3871115088 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.178908378 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 90458503895 ps |
| CPU time | 991.86 seconds |
| Started | Jul 20 07:39:54 PM PDT 24 |
| Finished | Jul 20 07:56:26 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-b5c7e494-e2c5-42aa-a963-1681f509ee9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178908378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.178908378 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.63148998 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 41564121426 ps |
| CPU time | 802.35 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:53:20 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-229b8864-fc39-4d62-a727-fe5b91b8bcd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63148998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.63148998 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.2511318135 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 441565699 ps |
| CPU time | 44.65 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:40:42 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-ab834318-9d1b-41b7-bd50-3dc2a2e8092d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511318135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.2511318135 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.1214863972 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 141574716 ps |
| CPU time | 11.48 seconds |
| Started | Jul 20 07:40:04 PM PDT 24 |
| Finished | Jul 20 07:40:17 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-e5cfaf62-11c2-4fd4-82c7-91ce71a93eae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214863972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.1214863972 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.1895878040 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 208813637 ps |
| CPU time | 9.1 seconds |
| Started | Jul 20 07:39:59 PM PDT 24 |
| Finished | Jul 20 07:40:09 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-70afa733-27d7-4582-9e00-c9d624f628c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895878040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.1895878040 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.143358385 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 6716277837 ps |
| CPU time | 79.03 seconds |
| Started | Jul 20 07:39:59 PM PDT 24 |
| Finished | Jul 20 07:41:19 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-aa3f2a1c-eed6-49b4-8704-37fe3e652d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143358385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.143358385 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1684524938 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 4088522807 ps |
| CPU time | 70.41 seconds |
| Started | Jul 20 07:39:58 PM PDT 24 |
| Finished | Jul 20 07:41:09 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-a1f3890f-9227-4d99-86b3-edb98d5cf9af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684524938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1684524938 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1388418439 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 58859718 ps |
| CPU time | 7.34 seconds |
| Started | Jul 20 07:39:56 PM PDT 24 |
| Finished | Jul 20 07:40:05 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-d4c14e32-1cbb-4a3b-950b-db3fd95a15bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388418439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1388418439 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.529339418 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 8293232714 ps |
| CPU time | 278.12 seconds |
| Started | Jul 20 07:40:04 PM PDT 24 |
| Finished | Jul 20 07:44:45 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-3e7d5bab-4849-4c92-81a1-f4a725a31c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529339418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.529339418 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3742421849 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 4451166710 ps |
| CPU time | 134.04 seconds |
| Started | Jul 20 07:40:11 PM PDT 24 |
| Finished | Jul 20 07:42:27 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a6307aeb-cdb6-4766-aa45-9b1e32d3d54a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742421849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.3742421849 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.591739981 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 554681956 ps |
| CPU time | 197.48 seconds |
| Started | Jul 20 07:40:03 PM PDT 24 |
| Finished | Jul 20 07:43:22 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-d81060f1-4019-4fab-98c1-4aa7078be1a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591739981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.591739981 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2214051512 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 216708324 ps |
| CPU time | 73.18 seconds |
| Started | Jul 20 07:40:10 PM PDT 24 |
| Finished | Jul 20 07:41:25 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-a57a0417-e34a-46e9-9a4f-69b3c265e61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214051512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2214051512 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.4133993823 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 177361387 ps |
| CPU time | 22.22 seconds |
| Started | Jul 20 07:40:02 PM PDT 24 |
| Finished | Jul 20 07:40:26 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-334b8739-d7dd-465f-8bfe-acef242ca761 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133993823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.4133993823 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3706146494 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 2103646324 ps |
| CPU time | 88.34 seconds |
| Started | Jul 20 07:40:18 PM PDT 24 |
| Finished | Jul 20 07:41:48 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-03fb8c6c-e0bf-4af2-8b87-3eae9cff7ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706146494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .3706146494 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2916034164 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 114895558585 ps |
| CPU time | 2377.52 seconds |
| Started | Jul 20 07:40:23 PM PDT 24 |
| Finished | Jul 20 08:20:05 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-ad057508-b7f3-47ef-9ed8-203a5fa17de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916034164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.2916034164 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.4245511076 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 628809987 ps |
| CPU time | 27.86 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:40:50 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-eef46dd9-a053-4c01-8ed2-2d6d03928265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245511076 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.4245511076 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.228935547 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 123338967 ps |
| CPU time | 10.7 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:40:33 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-a550d1d6-1467-40a9-a5e9-f2d9f99361c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228935547 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.228935547 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.3536962102 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 1652039865 ps |
| CPU time | 60.65 seconds |
| Started | Jul 20 07:40:11 PM PDT 24 |
| Finished | Jul 20 07:41:14 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-5e898dce-6d97-4b47-8d2c-cf0879b9f2f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536962102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.3536962102 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.2530808352 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 22872610428 ps |
| CPU time | 240.74 seconds |
| Started | Jul 20 07:40:11 PM PDT 24 |
| Finished | Jul 20 07:44:14 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-b760a712-edc7-4b14-9372-d1df0094f41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530808352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.2530808352 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.513897903 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 16827313197 ps |
| CPU time | 293.25 seconds |
| Started | Jul 20 07:40:13 PM PDT 24 |
| Finished | Jul 20 07:45:08 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-555bd6c4-4f37-46e5-a828-f8f956f023e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513897903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.513897903 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.112136526 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 193108324 ps |
| CPU time | 19.32 seconds |
| Started | Jul 20 07:40:13 PM PDT 24 |
| Finished | Jul 20 07:40:33 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-67db03f8-5bc1-4a86-b3ca-7105e80648a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112136526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.112136526 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.2677047273 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 371918839 ps |
| CPU time | 28.46 seconds |
| Started | Jul 20 07:40:23 PM PDT 24 |
| Finished | Jul 20 07:40:55 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-58be0371-1718-4caa-98f4-09f4b4a59fbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677047273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.2677047273 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.2594061863 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 44811547 ps |
| CPU time | 6.21 seconds |
| Started | Jul 20 07:40:09 PM PDT 24 |
| Finished | Jul 20 07:40:16 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-cb6b36c8-1233-48e9-a4d1-f5951ecb9ed6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594061863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2594061863 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.2621499131 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 6708874747 ps |
| CPU time | 73.38 seconds |
| Started | Jul 20 07:40:12 PM PDT 24 |
| Finished | Jul 20 07:41:27 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-4722b301-f0a8-4d2c-82e9-117983d18fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621499131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.2621499131 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2823876956 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 5684345351 ps |
| CPU time | 98.96 seconds |
| Started | Jul 20 07:40:13 PM PDT 24 |
| Finished | Jul 20 07:41:53 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-3448362f-98cb-431d-8585-9b0f8817a674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823876956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2823876956 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2151107083 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 47161447 ps |
| CPU time | 6.6 seconds |
| Started | Jul 20 07:40:12 PM PDT 24 |
| Finished | Jul 20 07:40:20 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-49d1b568-7549-4801-a92c-eb1e91d75e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151107083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2151107083 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2383090968 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 1989072145 ps |
| CPU time | 149.96 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:42:52 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1fa2f04e-f142-492e-aa80-1d15b5340ca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383090968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2383090968 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.859390142 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 2041326617 ps |
| CPU time | 133.83 seconds |
| Started | Jul 20 07:40:22 PM PDT 24 |
| Finished | Jul 20 07:42:39 PM PDT 24 |
| Peak memory | 575260 kb |
| Host | smart-27ee7567-bb6c-401a-a37c-89d290c71e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859390142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.859390142 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.2637527511 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 5993377699 ps |
| CPU time | 446.67 seconds |
| Started | Jul 20 07:40:24 PM PDT 24 |
| Finished | Jul 20 07:47:54 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-c81c3916-cb46-4513-9614-da9e9ade8ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637527511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.2637527511 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2475658338 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 2680061572 ps |
| CPU time | 367.4 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:46:30 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-bf02c92e-a19d-4ecf-8888-b1a0d41fbfe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475658338 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.2475658338 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1478245937 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 92823535 ps |
| CPU time | 6.6 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:40:29 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-7f5d9778-1d49-420a-bc67-2b41813b37ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478245937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1478245937 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3369413671 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 131361187 ps |
| CPU time | 10.43 seconds |
| Started | Jul 20 07:40:22 PM PDT 24 |
| Finished | Jul 20 07:40:35 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-6f5a3a3f-eb06-4540-806b-af697c750217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369413671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3369413671 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3731034495 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 16893684938 ps |
| CPU time | 300.61 seconds |
| Started | Jul 20 07:40:17 PM PDT 24 |
| Finished | Jul 20 07:45:20 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-31add2c0-5932-474c-a845-1753b3d8b155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731034495 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3731034495 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.2217461642 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 275378420 ps |
| CPU time | 13.9 seconds |
| Started | Jul 20 07:40:25 PM PDT 24 |
| Finished | Jul 20 07:40:43 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-7f8ef5b1-5363-452d-92b0-0540ec5936a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217461642 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.2217461642 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.1249930979 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 133166085 ps |
| CPU time | 7.97 seconds |
| Started | Jul 20 07:40:25 PM PDT 24 |
| Finished | Jul 20 07:40:38 PM PDT 24 |
| Peak memory | 575268 kb |
| Host | smart-30e811bf-6f4a-4ebc-ad19-efc6028cccab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249930979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.1249930979 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.4153632908 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 1765061359 ps |
| CPU time | 59.75 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:41:22 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-3b72abdb-ec7f-4974-949e-10ea873d204f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153632908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.4153632908 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.3746089347 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 43227619266 ps |
| CPU time | 480.64 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:48:23 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-b9e0725c-8674-446a-af4c-ef3049d53cc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746089347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.3746089347 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.3456968657 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 30689269308 ps |
| CPU time | 618.69 seconds |
| Started | Jul 20 07:40:24 PM PDT 24 |
| Finished | Jul 20 07:50:47 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-d2e64526-72ce-406a-8f64-a02de2ed5162 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456968657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.3456968657 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.518358983 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 564321624 ps |
| CPU time | 42.86 seconds |
| Started | Jul 20 07:40:19 PM PDT 24 |
| Finished | Jul 20 07:41:04 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-cbb5f063-cf52-4c75-a32c-7539eb48e096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518358983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.518358983 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.3319777225 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 956425436 ps |
| CPU time | 29.29 seconds |
| Started | Jul 20 07:40:20 PM PDT 24 |
| Finished | Jul 20 07:40:53 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-97c81ab1-4dc9-44b9-9816-3979f8a6c283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319777225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.3319777225 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.2326583432 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 46855199 ps |
| CPU time | 5.87 seconds |
| Started | Jul 20 07:40:18 PM PDT 24 |
| Finished | Jul 20 07:40:27 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-d84ef8aa-859b-4e4c-920d-838ae2711a96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326583432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.2326583432 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2908381776 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 7077521338 ps |
| CPU time | 78.8 seconds |
| Started | Jul 20 07:40:18 PM PDT 24 |
| Finished | Jul 20 07:41:39 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-63549a4b-88d7-47bf-b1b6-2ae6623cf2c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908381776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2908381776 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.2976321781 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 6061142656 ps |
| CPU time | 96.29 seconds |
| Started | Jul 20 07:40:22 PM PDT 24 |
| Finished | Jul 20 07:42:01 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7f9003f4-5f58-472a-8fb4-0c0bf6c426aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976321781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.2976321781 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.142406792 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 45443081 ps |
| CPU time | 6.15 seconds |
| Started | Jul 20 07:40:18 PM PDT 24 |
| Finished | Jul 20 07:40:27 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-6e071cf9-2ac6-40e4-901c-d7297f2f7fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142406792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delays .142406792 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.293162948 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 7499257849 ps |
| CPU time | 293.05 seconds |
| Started | Jul 20 07:40:24 PM PDT 24 |
| Finished | Jul 20 07:45:21 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-79fb64cc-6592-4409-85f2-4c2fc169c8b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293162948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.293162948 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.2348430947 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 2361826703 ps |
| CPU time | 175.22 seconds |
| Started | Jul 20 07:40:26 PM PDT 24 |
| Finished | Jul 20 07:43:26 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-6951109b-964a-4ccd-8a86-985cd9143cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348430947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.2348430947 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.23735909 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2233028450 ps |
| CPU time | 327.34 seconds |
| Started | Jul 20 07:40:25 PM PDT 24 |
| Finished | Jul 20 07:45:57 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-4e82319b-601f-4deb-af4e-9e5ef45fc75e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23735909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_w ith_rand_reset.23735909 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.2682414475 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 263384357 ps |
| CPU time | 63.06 seconds |
| Started | Jul 20 07:40:25 PM PDT 24 |
| Finished | Jul 20 07:41:33 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-e65f4fc2-1fbb-4846-b6b0-081f1268c6e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682414475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.2682414475 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.328004630 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 784871678 ps |
| CPU time | 33.16 seconds |
| Started | Jul 20 07:40:25 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-45d30272-28b1-4391-9c92-bb9df22a1ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328004630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.328004630 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.897589296 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 822510864 ps |
| CPU time | 32.77 seconds |
| Started | Jul 20 07:40:34 PM PDT 24 |
| Finished | Jul 20 07:41:13 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-74aebf64-6998-445b-8d49-451a087ef8c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897589296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device. 897589296 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3611536792 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 105101587047 ps |
| CPU time | 2050.2 seconds |
| Started | Jul 20 07:40:34 PM PDT 24 |
| Finished | Jul 20 08:14:52 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-40bed217-a332-441c-9da1-1c20fd62257d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611536792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3611536792 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.1867183034 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 304891980 ps |
| CPU time | 34.82 seconds |
| Started | Jul 20 07:40:33 PM PDT 24 |
| Finished | Jul 20 07:41:14 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-2308373d-259a-49a0-8d41-67f490a00541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867183034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.1867183034 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.968930441 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 499633845 ps |
| CPU time | 37.85 seconds |
| Started | Jul 20 07:40:34 PM PDT 24 |
| Finished | Jul 20 07:41:19 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-449e82f3-9ed4-4d0c-b416-33d8aba56743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968930441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.968930441 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2017657202 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 54919766 ps |
| CPU time | 8.42 seconds |
| Started | Jul 20 07:40:33 PM PDT 24 |
| Finished | Jul 20 07:40:47 PM PDT 24 |
| Peak memory | 575300 kb |
| Host | smart-d9321922-3bd8-402b-bf53-e409f1f35d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017657202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2017657202 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.2934330498 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 40895945342 ps |
| CPU time | 515.52 seconds |
| Started | Jul 20 07:40:37 PM PDT 24 |
| Finished | Jul 20 07:49:22 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-af81184c-7e6d-4ac4-8b5c-ab04a02a1c8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934330498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.2934330498 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3328723465 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 5638492061 ps |
| CPU time | 93.04 seconds |
| Started | Jul 20 07:40:32 PM PDT 24 |
| Finished | Jul 20 07:42:12 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-af56fa1f-34d7-42ed-821c-efbaab6b375a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328723465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3328723465 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1539289256 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 389867098 ps |
| CPU time | 29.87 seconds |
| Started | Jul 20 07:40:35 PM PDT 24 |
| Finished | Jul 20 07:41:12 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3cef9d32-e177-47a9-b7f3-7391b1ef3fdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539289256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1539289256 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.666741286 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 113036661 ps |
| CPU time | 10.12 seconds |
| Started | Jul 20 07:40:32 PM PDT 24 |
| Finished | Jul 20 07:40:49 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-8e8ac283-17c8-46af-b752-f2ec12ead331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666741286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.666741286 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3052661014 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 47359574 ps |
| CPU time | 6.51 seconds |
| Started | Jul 20 07:40:26 PM PDT 24 |
| Finished | Jul 20 07:40:38 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-e2a6b0e7-d0e4-41ea-8981-fffc31d4b549 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052661014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3052661014 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.4279806656 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 6479836591 ps |
| CPU time | 74.98 seconds |
| Started | Jul 20 07:40:27 PM PDT 24 |
| Finished | Jul 20 07:41:47 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-0c910410-1c63-40e5-8282-40d23b7c5db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279806656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.4279806656 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.1336138024 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 5670871073 ps |
| CPU time | 93.62 seconds |
| Started | Jul 20 07:40:28 PM PDT 24 |
| Finished | Jul 20 07:42:07 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-2b6162e1-93f5-4131-81e2-168eeaf82737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336138024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.1336138024 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.188812171 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 36740117 ps |
| CPU time | 5.43 seconds |
| Started | Jul 20 07:40:27 PM PDT 24 |
| Finished | Jul 20 07:40:38 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-65463abd-9c00-4757-93f3-21382080a835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188812171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .188812171 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.4154679604 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 1362857081 ps |
| CPU time | 108.91 seconds |
| Started | Jul 20 07:40:31 PM PDT 24 |
| Finished | Jul 20 07:42:26 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-5e746a38-dbc5-44ff-879f-fa0e97d07eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154679604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.4154679604 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.3485198933 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 1974590110 ps |
| CPU time | 162.69 seconds |
| Started | Jul 20 07:40:32 PM PDT 24 |
| Finished | Jul 20 07:43:21 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1aa69490-695c-4472-a585-ef19631c4604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485198933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.3485198933 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.984863237 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 1206181254 ps |
| CPU time | 148.74 seconds |
| Started | Jul 20 07:40:32 PM PDT 24 |
| Finished | Jul 20 07:43:08 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-0187bcd3-656c-4fb0-855f-e26ce8b8b94c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984863237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.984863237 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1165866104 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 7385834 ps |
| CPU time | 4.1 seconds |
| Started | Jul 20 07:40:33 PM PDT 24 |
| Finished | Jul 20 07:40:43 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-578dcf50-760e-430b-8a31-b46ec3c95352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165866104 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.1165866104 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.3700655822 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 1297125107 ps |
| CPU time | 54.65 seconds |
| Started | Jul 20 07:40:31 PM PDT 24 |
| Finished | Jul 20 07:41:32 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-3d270480-87d3-423d-b8a0-bf7e467747d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700655822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.3700655822 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.3039030758 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 488215578 ps |
| CPU time | 40.09 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:41:50 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-1daf91ae-ee54-4f43-9f6d-d3fe4ef4a37b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039030758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .3039030758 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.1479278460 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 132271694317 ps |
| CPU time | 2664.12 seconds |
| Started | Jul 20 07:40:47 PM PDT 24 |
| Finished | Jul 20 08:25:30 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8f05f5ed-3774-4bbc-a588-d518c44d9280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479278460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.1479278460 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2401018294 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 971121778 ps |
| CPU time | 39.55 seconds |
| Started | Jul 20 07:40:50 PM PDT 24 |
| Finished | Jul 20 07:41:52 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f4edbdee-3c01-4ee3-b286-7aaad8e01ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401018294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2401018294 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.3011809204 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 179424350 ps |
| CPU time | 14.93 seconds |
| Started | Jul 20 07:40:48 PM PDT 24 |
| Finished | Jul 20 07:41:23 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-d10ca69e-e35f-4efa-9351-b50465bfa967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011809204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.3011809204 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.536798619 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 288254348 ps |
| CPU time | 24.34 seconds |
| Started | Jul 20 07:40:44 PM PDT 24 |
| Finished | Jul 20 07:41:24 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-d19c4f6e-7588-4082-a7df-6ed0f4bf2d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536798619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.536798619 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.938944068 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 59083744686 ps |
| CPU time | 763.38 seconds |
| Started | Jul 20 07:40:44 PM PDT 24 |
| Finished | Jul 20 07:53:44 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8a9d8900-e584-4d36-8854-97f061ed1a1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938944068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.938944068 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1838939485 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 20597243733 ps |
| CPU time | 401.8 seconds |
| Started | Jul 20 07:40:41 PM PDT 24 |
| Finished | Jul 20 07:47:37 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-416e1a70-42d6-462d-b448-140ff3b0a662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838939485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1838939485 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.1712927832 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 367794051 ps |
| CPU time | 33.52 seconds |
| Started | Jul 20 07:40:41 PM PDT 24 |
| Finished | Jul 20 07:41:29 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-d6737256-fd6c-4aa6-ae10-ae2bfd93c31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712927832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.1712927832 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.3729820483 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 1128648756 ps |
| CPU time | 30.48 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:41:39 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-097f1dfe-38fc-4029-948a-9202f6c45e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729820483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.3729820483 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.3487352330 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 187118757 ps |
| CPU time | 9.06 seconds |
| Started | Jul 20 07:40:42 PM PDT 24 |
| Finished | Jul 20 07:41:06 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-5cd578be-bf14-4151-bc71-55d3d752404d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487352330 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.3487352330 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2477023825 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 6537137547 ps |
| CPU time | 69.1 seconds |
| Started | Jul 20 07:40:40 PM PDT 24 |
| Finished | Jul 20 07:42:01 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-956ca0e6-4a18-4a00-80d2-5c6df5b6ccdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477023825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2477023825 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3631010721 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 4811335363 ps |
| CPU time | 85.07 seconds |
| Started | Jul 20 07:40:46 PM PDT 24 |
| Finished | Jul 20 07:42:28 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-0cbdefcd-42a0-4fc3-ae96-5637d4bb23f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631010721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3631010721 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1010400952 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 51042901 ps |
| CPU time | 7.25 seconds |
| Started | Jul 20 07:40:41 PM PDT 24 |
| Finished | Jul 20 07:41:03 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-d987c3c6-439d-495a-9368-23177997e7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010400952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1010400952 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1980432272 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 11813638177 ps |
| CPU time | 454.42 seconds |
| Started | Jul 20 07:40:50 PM PDT 24 |
| Finished | Jul 20 07:48:46 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-bff394d7-ddee-4cca-81d5-72342d0ce52d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980432272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1980432272 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3000484946 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 3048283429 ps |
| CPU time | 94.12 seconds |
| Started | Jul 20 07:40:52 PM PDT 24 |
| Finished | Jul 20 07:42:49 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-cd8c4fdb-96c3-444b-a704-f624d92d0b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000484946 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3000484946 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.2922637761 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2217950157 ps |
| CPU time | 268.28 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:45:39 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-7a308db5-7756-449d-8e4f-e073988defd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922637761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.2922637761 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2988863863 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 339917804 ps |
| CPU time | 105.09 seconds |
| Started | Jul 20 07:40:48 PM PDT 24 |
| Finished | Jul 20 07:42:53 PM PDT 24 |
| Peak memory | 576196 kb |
| Host | smart-b5040ad0-952f-40cd-952f-811ef7e9fad8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988863863 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.2988863863 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.3765095824 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 326745970 ps |
| CPU time | 13.87 seconds |
| Started | Jul 20 07:40:47 PM PDT 24 |
| Finished | Jul 20 07:41:20 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-c532712a-6285-489c-a229-a6d8004977f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765095824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.3765095824 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2700214929 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 1560065563 ps |
| CPU time | 61.69 seconds |
| Started | Jul 20 07:40:59 PM PDT 24 |
| Finished | Jul 20 07:42:25 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1b656b01-c746-4292-abd6-37ff5d33aa26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700214929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .2700214929 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2464206099 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 125272960107 ps |
| CPU time | 2308.85 seconds |
| Started | Jul 20 07:40:57 PM PDT 24 |
| Finished | Jul 20 08:19:49 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-14909024-b7ef-4659-8097-6c9231bde82b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464206099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2464206099 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.2231019180 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 279560271 ps |
| CPU time | 15.97 seconds |
| Started | Jul 20 07:40:59 PM PDT 24 |
| Finished | Jul 20 07:41:39 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-c0b55189-3451-4e4b-a620-a19b2162b2a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231019180 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.2231019180 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.1543453095 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 1293125914 ps |
| CPU time | 38.43 seconds |
| Started | Jul 20 07:40:58 PM PDT 24 |
| Finished | Jul 20 07:42:01 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-e0aab61a-0dca-49a9-8ba9-9e709eca5417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543453095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.1543453095 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.1564837624 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 2267334535 ps |
| CPU time | 82.39 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:42:33 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-48a37a38-8a99-4fce-adf0-a250ab915395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564837624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.1564837624 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1519070555 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 49483538050 ps |
| CPU time | 934.66 seconds |
| Started | Jul 20 07:40:59 PM PDT 24 |
| Finished | Jul 20 07:56:58 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-d8022360-d499-4f3b-9e09-1fb7b7d33e6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519070555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1519070555 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.806701826 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 425246906 ps |
| CPU time | 31.98 seconds |
| Started | Jul 20 07:40:51 PM PDT 24 |
| Finished | Jul 20 07:41:45 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-aca8db0c-353a-4ef7-b9ca-51ceba6f804b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806701826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.806701826 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.773718646 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 1041866801 ps |
| CPU time | 29.76 seconds |
| Started | Jul 20 07:40:58 PM PDT 24 |
| Finished | Jul 20 07:41:52 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-29425025-8d58-409f-895e-04672f4cc0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773718646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.773718646 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.666097518 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 38551564 ps |
| CPU time | 6.17 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:41:16 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-ff090992-21fc-42e7-a663-d70ef9f86acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666097518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.666097518 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.4149710628 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 6708567899 ps |
| CPU time | 73.42 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:42:24 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-db3bff1d-2b98-48ab-9f94-93a3796e7d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149710628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.4149710628 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.1114319989 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 5555018661 ps |
| CPU time | 103.22 seconds |
| Started | Jul 20 07:40:50 PM PDT 24 |
| Finished | Jul 20 07:42:55 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-5cf91840-9731-4d7f-964e-3cc791a49886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114319989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.1114319989 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.224628313 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 51836532 ps |
| CPU time | 6.13 seconds |
| Started | Jul 20 07:40:49 PM PDT 24 |
| Finished | Jul 20 07:41:17 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-698a5945-3b82-4fcc-ac57-fdad80db129e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224628313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delays .224628313 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.3299406563 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 294996007 ps |
| CPU time | 25.32 seconds |
| Started | Jul 20 07:40:58 PM PDT 24 |
| Finished | Jul 20 07:41:47 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-388edca2-cb3e-4825-aae6-7f94f234758f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299406563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.3299406563 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.213013002 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 1829198453 ps |
| CPU time | 138.66 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:44:05 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-13e3edba-d24b-4cae-9553-5d71fbd090e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213013002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.213013002 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.2931677406 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 337676980 ps |
| CPU time | 125.58 seconds |
| Started | Jul 20 07:40:59 PM PDT 24 |
| Finished | Jul 20 07:43:29 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-d9b28643-e0a7-445c-9f68-568b9ab810c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931677406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.2931677406 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2887903705 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 6805091348 ps |
| CPU time | 379.87 seconds |
| Started | Jul 20 07:41:05 PM PDT 24 |
| Finished | Jul 20 07:47:50 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-c19f26ed-f230-4b3e-95ef-c7bae1e96993 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887903705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.2887903705 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.3525426237 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 388566369 ps |
| CPU time | 19.5 seconds |
| Started | Jul 20 07:40:58 PM PDT 24 |
| Finished | Jul 20 07:41:42 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-51aa5be7-a91b-4264-bd3c-e28969912d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525426237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.3525426237 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.94637378 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 419588714 ps |
| CPU time | 18.35 seconds |
| Started | Jul 20 07:41:07 PM PDT 24 |
| Finished | Jul 20 07:41:50 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-3a02e450-beea-453f-a054-2e3f6a10a118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94637378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device.94637378 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1430750694 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 83571449514 ps |
| CPU time | 1498.45 seconds |
| Started | Jul 20 07:41:08 PM PDT 24 |
| Finished | Jul 20 08:06:31 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-a6134283-da7b-4c71-82c2-d204098ae6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430750694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1430750694 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.1380295851 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 855142784 ps |
| CPU time | 32.5 seconds |
| Started | Jul 20 07:41:07 PM PDT 24 |
| Finished | Jul 20 07:42:04 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-9bc66c6d-84f6-4b13-8bde-f1ed93346892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380295851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.1380295851 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.602385796 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 640952488 ps |
| CPU time | 26.15 seconds |
| Started | Jul 20 07:41:25 PM PDT 24 |
| Finished | Jul 20 07:42:12 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-120a8143-fcb6-46fd-9625-0d2282f940a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602385796 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.602385796 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.571685150 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 390954214 ps |
| CPU time | 35.49 seconds |
| Started | Jul 20 07:41:04 PM PDT 24 |
| Finished | Jul 20 07:42:05 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-04f0e56c-a0dd-4a62-86d6-8e552c603b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571685150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.571685150 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1573970082 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 50277096852 ps |
| CPU time | 610.82 seconds |
| Started | Jul 20 07:41:05 PM PDT 24 |
| Finished | Jul 20 07:51:41 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-497db642-c15c-47e9-bf0f-b3d302549ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573970082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1573970082 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.182212269 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 54524384495 ps |
| CPU time | 1049.21 seconds |
| Started | Jul 20 07:41:06 PM PDT 24 |
| Finished | Jul 20 07:59:00 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-d2a9c7d9-688e-4998-bc53-b6d273786ef8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182212269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.182212269 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.1382228468 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 417575108 ps |
| CPU time | 39.01 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:42:25 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-c4c6adfb-5365-4552-9daf-e49234655fdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382228468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.1382228468 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.757487148 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 304734201 ps |
| CPU time | 21.17 seconds |
| Started | Jul 20 07:41:08 PM PDT 24 |
| Finished | Jul 20 07:41:54 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-28a40c4d-e06d-440d-892c-4b5d23c055ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757487148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.757487148 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.3869769438 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 36141323 ps |
| CPU time | 5.6 seconds |
| Started | Jul 20 07:41:05 PM PDT 24 |
| Finished | Jul 20 07:41:36 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-9a1e088d-2b5f-4eca-bac4-73c29b040826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869769438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.3869769438 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1498594497 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 9781132932 ps |
| CPU time | 103.61 seconds |
| Started | Jul 20 07:41:08 PM PDT 24 |
| Finished | Jul 20 07:43:16 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-1eb09760-acf3-4790-b2ea-b301edb79bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498594497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1498594497 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1466777983 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 6460866240 ps |
| CPU time | 108.37 seconds |
| Started | Jul 20 07:41:09 PM PDT 24 |
| Finished | Jul 20 07:43:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-44fd677d-6120-4083-851a-2f33ddd73147 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466777983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1466777983 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.3922298700 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 55736887 ps |
| CPU time | 6.92 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:41:53 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-8387bdfa-258e-4d54-87f9-83a18de04c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922298700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.3922298700 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1753741826 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 11547188559 ps |
| CPU time | 437.29 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:49:04 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-fe71f729-099c-4e2c-91fe-edcff9164717 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753741826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1753741826 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.1490482526 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 9311373365 ps |
| CPU time | 364.25 seconds |
| Started | Jul 20 07:41:06 PM PDT 24 |
| Finished | Jul 20 07:47:35 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-9fc33d6e-9a05-4e65-8214-b5ee9c2fd052 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490482526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.1490482526 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2942925758 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 9539138873 ps |
| CPU time | 641.19 seconds |
| Started | Jul 20 07:41:08 PM PDT 24 |
| Finished | Jul 20 07:52:14 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-83b7d491-352c-44a4-bdc2-264973c7e402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942925758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.2942925758 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.846178939 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 8337612112 ps |
| CPU time | 379.45 seconds |
| Started | Jul 20 07:41:06 PM PDT 24 |
| Finished | Jul 20 07:47:50 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-86912cff-253e-4a42-8fe8-22cf8a453b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846178939 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.846178939 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.3986803060 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 1012183329 ps |
| CPU time | 42.92 seconds |
| Started | Jul 20 07:41:23 PM PDT 24 |
| Finished | Jul 20 07:42:29 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-f8260fe5-024e-48a3-985e-40ce52c33bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986803060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.3986803060 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.3436470551 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 379237416 ps |
| CPU time | 46.22 seconds |
| Started | Jul 20 07:41:15 PM PDT 24 |
| Finished | Jul 20 07:42:25 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-117a892e-3466-4ccc-888c-e77615b058f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436470551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .3436470551 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1099088797 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 33477876797 ps |
| CPU time | 695.24 seconds |
| Started | Jul 20 07:41:15 PM PDT 24 |
| Finished | Jul 20 07:53:15 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-9e1886b6-6663-4a14-96d3-b848b91a037f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099088797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.1099088797 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.1893455461 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 1257419826 ps |
| CPU time | 45.19 seconds |
| Started | Jul 20 07:41:15 PM PDT 24 |
| Finished | Jul 20 07:42:24 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-38d65963-dbad-462d-9b83-027124f96c56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893455461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.1893455461 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.3547815869 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 153695249 ps |
| CPU time | 14.09 seconds |
| Started | Jul 20 07:41:17 PM PDT 24 |
| Finished | Jul 20 07:41:54 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-640ade26-7829-438e-a461-bfef869270a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547815869 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3547815869 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1449600215 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2061762853 ps |
| CPU time | 77.04 seconds |
| Started | Jul 20 07:41:13 PM PDT 24 |
| Finished | Jul 20 07:42:55 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-f8a5f74f-a3fa-4b30-aadf-d1ca0133a4df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449600215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1449600215 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.1901091037 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 103811916828 ps |
| CPU time | 1279.3 seconds |
| Started | Jul 20 07:41:15 PM PDT 24 |
| Finished | Jul 20 08:02:59 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-a16c2839-f155-41a1-8d4e-e07c3f59856b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901091037 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.1901091037 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1500236948 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 71702920992 ps |
| CPU time | 1250.4 seconds |
| Started | Jul 20 07:41:14 PM PDT 24 |
| Finished | Jul 20 08:02:29 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-406ab12c-f2b7-4033-9046-04c1a3dc1278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500236948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1500236948 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.4103247066 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 339910500 ps |
| CPU time | 30.81 seconds |
| Started | Jul 20 07:41:13 PM PDT 24 |
| Finished | Jul 20 07:42:09 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-da036d02-887b-43a1-9d5f-7bf1cf96721e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103247066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.4103247066 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.554569021 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 181153290 ps |
| CPU time | 13.63 seconds |
| Started | Jul 20 07:41:15 PM PDT 24 |
| Finished | Jul 20 07:41:53 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-fce3f5b0-f0a2-4925-a8dd-513b99f7affc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554569021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.554569021 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2175867437 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 40458471 ps |
| CPU time | 5.87 seconds |
| Started | Jul 20 07:41:07 PM PDT 24 |
| Finished | Jul 20 07:41:38 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-6567071d-7f3b-47ea-b91e-312ae405ed4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175867437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2175867437 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3733165599 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 9541492395 ps |
| CPU time | 109.6 seconds |
| Started | Jul 20 07:41:25 PM PDT 24 |
| Finished | Jul 20 07:43:36 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-1c6e0b42-592d-4c67-bf7a-86419887e7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733165599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3733165599 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2209775329 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 7313182405 ps |
| CPU time | 123.95 seconds |
| Started | Jul 20 07:41:08 PM PDT 24 |
| Finished | Jul 20 07:43:37 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-9506a059-1601-427e-93d1-8b5614e91b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209775329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2209775329 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2748438509 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 47607742 ps |
| CPU time | 6.63 seconds |
| Started | Jul 20 07:41:06 PM PDT 24 |
| Finished | Jul 20 07:41:38 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-5d290f1d-0a24-4213-8b66-b76f4cac50c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748438509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2748438509 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.4016973696 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 996061673 ps |
| CPU time | 85.3 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:43:12 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-14de6b53-bfdb-47b8-8f41-c5dbc0e76fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016973696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.4016973696 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.540469640 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 2304384713 ps |
| CPU time | 184.73 seconds |
| Started | Jul 20 07:41:21 PM PDT 24 |
| Finished | Jul 20 07:44:49 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-6b8eea8c-0013-4cb9-a22f-124feff5543a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540469640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.540469640 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.2977218605 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 421565080 ps |
| CPU time | 162.12 seconds |
| Started | Jul 20 07:41:21 PM PDT 24 |
| Finished | Jul 20 07:44:26 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-c143a192-1c75-402a-92bd-c2a9273919cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977218605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.2977218605 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.162638388 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 3342806574 ps |
| CPU time | 538.37 seconds |
| Started | Jul 20 07:41:25 PM PDT 24 |
| Finished | Jul 20 07:50:45 PM PDT 24 |
| Peak memory | 577036 kb |
| Host | smart-af1f91a3-f9aa-47ae-85d8-7330a661ec16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162638388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.162638388 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1840536496 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 1188060744 ps |
| CPU time | 50.01 seconds |
| Started | Jul 20 07:41:16 PM PDT 24 |
| Finished | Jul 20 07:42:30 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-d9fddb7f-96f3-4435-beb9-70b51c71b662 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840536496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1840536496 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.291391388 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 984291424 ps |
| CPU time | 72.14 seconds |
| Started | Jul 20 07:41:22 PM PDT 24 |
| Finished | Jul 20 07:42:58 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-08a135a3-8764-419d-9623-a06ee4088b8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291391388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 291391388 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.1551582863 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 133016912881 ps |
| CPU time | 2567.1 seconds |
| Started | Jul 20 07:41:20 PM PDT 24 |
| Finished | Jul 20 08:24:31 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-f316a663-cf5f-443e-9ceb-2ca4981983ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551582863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.1551582863 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1428246984 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 1106578882 ps |
| CPU time | 41.51 seconds |
| Started | Jul 20 07:41:29 PM PDT 24 |
| Finished | Jul 20 07:42:32 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c27e2f8a-ef15-405d-ae83-04f9c4f2d356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428246984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1428246984 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3513093092 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 1829351401 ps |
| CPU time | 62.58 seconds |
| Started | Jul 20 07:41:27 PM PDT 24 |
| Finished | Jul 20 07:42:50 PM PDT 24 |
| Peak memory | 575312 kb |
| Host | smart-132cca0e-40ca-4c94-984f-cfb57111adb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513093092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3513093092 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3954487375 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2182257759 ps |
| CPU time | 90.69 seconds |
| Started | Jul 20 07:41:24 PM PDT 24 |
| Finished | Jul 20 07:43:17 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-fe472d21-ac01-4fea-a57e-39a22c707a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954487375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3954487375 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1371430474 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 101914680492 ps |
| CPU time | 1257.16 seconds |
| Started | Jul 20 07:41:22 PM PDT 24 |
| Finished | Jul 20 08:02:43 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-907e9cfe-0c10-4733-a444-82175552fa6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371430474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1371430474 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3476875231 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 45009531420 ps |
| CPU time | 747.22 seconds |
| Started | Jul 20 07:41:25 PM PDT 24 |
| Finished | Jul 20 07:54:14 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-72215a2e-6cec-4ed6-b3bc-6d46a8340361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476875231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3476875231 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.3713860578 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 359603145 ps |
| CPU time | 32.83 seconds |
| Started | Jul 20 07:41:22 PM PDT 24 |
| Finished | Jul 20 07:42:17 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-babd36df-ea0b-419e-a19d-912a0959d4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713860578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.3713860578 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2029849498 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2166571757 ps |
| CPU time | 69.04 seconds |
| Started | Jul 20 07:41:23 PM PDT 24 |
| Finished | Jul 20 07:42:55 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-42110800-6519-44e8-acf1-7ee27f912133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029849498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2029849498 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.196831268 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 240561348 ps |
| CPU time | 10.38 seconds |
| Started | Jul 20 07:41:21 PM PDT 24 |
| Finished | Jul 20 07:41:55 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-0ddf7ae2-55d4-4497-8665-37042386879a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196831268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.196831268 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1796992429 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 7802157827 ps |
| CPU time | 90.26 seconds |
| Started | Jul 20 07:41:21 PM PDT 24 |
| Finished | Jul 20 07:43:15 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f10e2021-c473-495a-ba7c-8adf7c12edb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796992429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1796992429 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.2169792737 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 6594524933 ps |
| CPU time | 118.79 seconds |
| Started | Jul 20 07:41:20 PM PDT 24 |
| Finished | Jul 20 07:43:43 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-2d1ac177-2b7c-48f1-9d90-67cb58a19b4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169792737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.2169792737 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2636336700 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 62089624 ps |
| CPU time | 6.78 seconds |
| Started | Jul 20 07:41:22 PM PDT 24 |
| Finished | Jul 20 07:41:52 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-2e223cf0-8efb-4649-89df-a25408d1cec6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636336700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2636336700 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2352939023 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4434837990 ps |
| CPU time | 418.05 seconds |
| Started | Jul 20 07:41:34 PM PDT 24 |
| Finished | Jul 20 07:48:50 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-195fc58f-5e18-49a7-b5c3-89ae1afbe673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352939023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2352939023 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1740300285 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 3544319863 ps |
| CPU time | 275.65 seconds |
| Started | Jul 20 07:41:29 PM PDT 24 |
| Finished | Jul 20 07:46:25 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-61b9d54b-9ba3-4487-9295-71b4a89095fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740300285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1740300285 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4033530598 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 561195556 ps |
| CPU time | 193.2 seconds |
| Started | Jul 20 07:41:42 PM PDT 24 |
| Finished | Jul 20 07:45:10 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-4800edf2-54bf-4dab-a233-8b51e0c27a9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033530598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.4033530598 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.124636202 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 323107446 ps |
| CPU time | 138.83 seconds |
| Started | Jul 20 07:41:29 PM PDT 24 |
| Finished | Jul 20 07:44:09 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-fc081162-c0af-494d-8590-ce977e254365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124636202 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.124636202 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1219150987 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 815706465 ps |
| CPU time | 32.72 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:42:23 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-b3e6d3ad-d606-4a36-bfc6-7a6b5c9c6d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219150987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1219150987 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.368247519 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 14594200844 ps |
| CPU time | 1793.55 seconds |
| Started | Jul 20 07:43:34 PM PDT 24 |
| Finished | Jul 20 08:13:29 PM PDT 24 |
| Peak memory | 604872 kb |
| Host | smart-c10056f7-7c02-45e5-981e-0c9f697dbcc8 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368247519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.368247519 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4209015577 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5025189662 ps |
| CPU time | 493.64 seconds |
| Started | Jul 20 07:53:27 PM PDT 24 |
| Finished | Jul 20 08:01:41 PM PDT 24 |
| Peak memory | 619864 kb |
| Host | smart-38c22af5-2b50-447f-b8e8-7dd6f9ac80ef |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4 209015577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.4209015577 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.764561516 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2791780568 ps |
| CPU time | 259.63 seconds |
| Started | Jul 20 07:49:05 PM PDT 24 |
| Finished | Jul 20 07:53:25 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-50fa7233-8d04-4fd5-b5ef-564d1be6baf7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=764561516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.764561516 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.1703738062 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2844048886 ps |
| CPU time | 346.36 seconds |
| Started | Jul 20 07:51:42 PM PDT 24 |
| Finished | Jul 20 07:57:30 PM PDT 24 |
| Peak memory | 609236 kb |
| Host | smart-da270921-e0de-463f-9ce7-9884445dde69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703738062 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.1703738062 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4284015093 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3617096465 ps |
| CPU time | 359.76 seconds |
| Started | Jul 20 07:51:10 PM PDT 24 |
| Finished | Jul 20 07:57:12 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-8938a098-c9f6-4223-8ded-492b37333bc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284 015093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.4284015093 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3285824195 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2946566842 ps |
| CPU time | 209.88 seconds |
| Started | Jul 20 07:50:26 PM PDT 24 |
| Finished | Jul 20 07:53:58 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-4d663ddb-d610-4d09-a09d-ad3b28111127 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285824195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3285824195 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.3911450928 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 3031141600 ps |
| CPU time | 264.83 seconds |
| Started | Jul 20 07:49:40 PM PDT 24 |
| Finished | Jul 20 07:54:05 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-6d2777f3-1617-4d02-ae24-9a7e66ee7514 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911450928 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3911450928 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.981339318 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2638730280 ps |
| CPU time | 262.1 seconds |
| Started | Jul 20 07:50:26 PM PDT 24 |
| Finished | Jul 20 07:54:49 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-56fa3b74-e83d-4fca-bbc7-dd9b6583cc33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981339318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.981339318 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2894750872 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 3098491324 ps |
| CPU time | 233.63 seconds |
| Started | Jul 20 07:52:51 PM PDT 24 |
| Finished | Jul 20 07:56:45 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-90373b1b-827f-4df3-89a1-014835f5803f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894750872 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2894750872 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2757829238 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2862866908 ps |
| CPU time | 308.86 seconds |
| Started | Jul 20 07:54:58 PM PDT 24 |
| Finished | Jul 20 08:00:07 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-33c35752-2c56-4a05-8f40-b31619628bd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757829238 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2757829238 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.306560848 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 4666017848 ps |
| CPU time | 728.31 seconds |
| Started | Jul 20 07:51:06 PM PDT 24 |
| Finished | Jul 20 08:03:15 PM PDT 24 |
| Peak memory | 619084 kb |
| Host | smart-f61a4895-3b79-44f2-ab58-9974ee78e81f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=306560848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.306560848 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1954008491 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 6921299640 ps |
| CPU time | 1563.86 seconds |
| Started | Jul 20 07:49:46 PM PDT 24 |
| Finished | Jul 20 08:15:50 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-07c105c7-ae87-43ec-bde0-674a66a4549e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1954008491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.1954008491 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2354414311 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 7692587540 ps |
| CPU time | 2310.33 seconds |
| Started | Jul 20 07:52:07 PM PDT 24 |
| Finished | Jul 20 08:30:37 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-838e70b3-3875-4754-95e8-c57a73fee333 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354414311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2354414311 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.4153997802 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 8212679592 ps |
| CPU time | 1456.61 seconds |
| Started | Jul 20 07:51:46 PM PDT 24 |
| Finished | Jul 20 08:16:03 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-3728211b-3a40-491d-9f2a-c1bf7f85bd6c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4153997802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.4153997802 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4212410561 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6003089816 ps |
| CPU time | 718.25 seconds |
| Started | Jul 20 07:51:07 PM PDT 24 |
| Finished | Jul 20 08:03:06 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-660c68f7-12e1-464d-9be8-6d7e0c5a509a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4212410561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.4212410561 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.845595941 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 254755162394 ps |
| CPU time | 12063.8 seconds |
| Started | Jul 20 07:50:02 PM PDT 24 |
| Finished | Jul 20 11:11:08 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-767c5601-8236-4bfe-afca-9b8bbdcf3df9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=845595941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.845595941 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.2773233625 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4113316404 ps |
| CPU time | 473.74 seconds |
| Started | Jul 20 07:51:20 PM PDT 24 |
| Finished | Jul 20 07:59:15 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-ba9afb6a-de48-4f6d-bba3-459f19f4d21b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773233625 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2773233625 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2051010759 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 7093116840 ps |
| CPU time | 393.7 seconds |
| Started | Jul 20 07:50:13 PM PDT 24 |
| Finished | Jul 20 07:56:48 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-3ecccfe5-eeac-414e-9bb3-521cc545acf9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2051010759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2051010759 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2129882805 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 2642700448 ps |
| CPU time | 249.75 seconds |
| Started | Jul 20 07:54:32 PM PDT 24 |
| Finished | Jul 20 07:58:43 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-97274fd4-e20c-4c8d-aa2a-ff31ff5a54d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129882805 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2129882805 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4132371863 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 9277521160 ps |
| CPU time | 1086.01 seconds |
| Started | Jul 20 07:52:25 PM PDT 24 |
| Finished | Jul 20 08:10:33 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-4b4375eb-594e-4084-9b16-804f3c31acfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4132371863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.4132371863 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3115371078 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 4205249940 ps |
| CPU time | 608.34 seconds |
| Started | Jul 20 07:49:25 PM PDT 24 |
| Finished | Jul 20 07:59:35 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-6f81e876-db55-4973-a591-1181c7d8d142 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3115371078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.3115371078 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4074139555 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 8573533160 ps |
| CPU time | 1154.19 seconds |
| Started | Jul 20 07:53:03 PM PDT 24 |
| Finished | Jul 20 08:12:18 PM PDT 24 |
| Peak memory | 617016 kb |
| Host | smart-397b263c-8b5e-48f2-923c-de76b57709ab |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074139555 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.4074139555 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1242663481 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 6348339893 ps |
| CPU time | 622.03 seconds |
| Started | Jul 20 07:52:32 PM PDT 24 |
| Finished | Jul 20 08:02:55 PM PDT 24 |
| Peak memory | 621340 kb |
| Host | smart-b65efdbf-7cc7-4248-8403-9e2de2adcb06 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1242663481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1242663481 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3198358729 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 3972660268 ps |
| CPU time | 710.24 seconds |
| Started | Jul 20 07:53:25 PM PDT 24 |
| Finished | Jul 20 08:05:16 PM PDT 24 |
| Peak memory | 611936 kb |
| Host | smart-749cdaf0-914a-4dfd-a55c-5ab6808b59a8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198358729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3198358729 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3757164752 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3813565492 ps |
| CPU time | 765.1 seconds |
| Started | Jul 20 07:51:10 PM PDT 24 |
| Finished | Jul 20 08:03:56 PM PDT 24 |
| Peak memory | 614052 kb |
| Host | smart-4864b210-7bd4-400f-810b-3e0375ed7579 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757164752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3757164752 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3694631701 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 4093794200 ps |
| CPU time | 771.23 seconds |
| Started | Jul 20 07:52:49 PM PDT 24 |
| Finished | Jul 20 08:05:42 PM PDT 24 |
| Peak memory | 612680 kb |
| Host | smart-15193ca5-f1b8-4895-b451-f292c7e6e82f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694631701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3694631701 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3958385787 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 4950917392 ps |
| CPU time | 741.95 seconds |
| Started | Jul 20 07:52:37 PM PDT 24 |
| Finished | Jul 20 08:04:59 PM PDT 24 |
| Peak memory | 612772 kb |
| Host | smart-81a68099-df86-4965-8c1d-9b9049fcfd60 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958385787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3958385787 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.680809350 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4825011468 ps |
| CPU time | 702.34 seconds |
| Started | Jul 20 07:52:13 PM PDT 24 |
| Finished | Jul 20 08:03:56 PM PDT 24 |
| Peak memory | 614032 kb |
| Host | smart-015eef41-faf7-476c-b3af-b8d53c392fda |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680809350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.680809350 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3490736614 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 5199639420 ps |
| CPU time | 583.73 seconds |
| Started | Jul 20 07:50:43 PM PDT 24 |
| Finished | Jul 20 08:00:28 PM PDT 24 |
| Peak memory | 612924 kb |
| Host | smart-79358802-737d-4bcc-bf5c-cb39f9bf18b0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490736614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3490736614 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1159065708 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 2558123893 ps |
| CPU time | 220.64 seconds |
| Started | Jul 20 07:53:20 PM PDT 24 |
| Finished | Jul 20 07:57:02 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-790b47da-654a-41f7-b329-10c16ade7cfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159065708 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1159065708 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2996528773 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3652092186 ps |
| CPU time | 387.5 seconds |
| Started | Jul 20 07:51:17 PM PDT 24 |
| Finished | Jul 20 07:57:45 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-a5c55194-bf22-448c-b62a-03ce925d1ebb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996528773 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2996528773 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.866680381 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 2732284142 ps |
| CPU time | 187.01 seconds |
| Started | Jul 20 07:53:52 PM PDT 24 |
| Finished | Jul 20 07:57:00 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-a5b34b1d-1b9c-48c6-9298-220bb4adb7aa |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866680381 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.866680381 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.710874977 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 5506345460 ps |
| CPU time | 481.63 seconds |
| Started | Jul 20 07:54:24 PM PDT 24 |
| Finished | Jul 20 08:02:26 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-30fb0563-4b53-4235-b5bb-74ba9cbc5ca5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710874977 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.710874977 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2788200845 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5190873864 ps |
| CPU time | 504.38 seconds |
| Started | Jul 20 07:53:40 PM PDT 24 |
| Finished | Jul 20 08:02:06 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-87699add-6712-48e8-b134-5e91f5864028 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788200845 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2788200845 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.707983841 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 5570629726 ps |
| CPU time | 657.1 seconds |
| Started | Jul 20 07:50:31 PM PDT 24 |
| Finished | Jul 20 08:01:28 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-6067734e-1ce7-444c-81e8-c16d310be71b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707983841 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.707983841 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1604906716 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 4673710900 ps |
| CPU time | 435.21 seconds |
| Started | Jul 20 07:52:45 PM PDT 24 |
| Finished | Jul 20 08:00:01 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-dc9da385-7ac3-4f47-818a-eafae2e452fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604906716 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1604906716 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2188754059 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 11575696448 ps |
| CPU time | 1711.13 seconds |
| Started | Jul 20 07:54:02 PM PDT 24 |
| Finished | Jul 20 08:22:35 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-2afd79c9-df54-4a8f-88bb-f0f62676e43b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188754059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2188754059 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2960098698 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3136556016 ps |
| CPU time | 494.7 seconds |
| Started | Jul 20 07:50:51 PM PDT 24 |
| Finished | Jul 20 07:59:06 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-df354d1c-3430-48c4-afbf-a8117605ec10 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960098698 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2960098698 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2004420555 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4982598616 ps |
| CPU time | 652.28 seconds |
| Started | Jul 20 07:51:09 PM PDT 24 |
| Finished | Jul 20 08:02:02 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-65727c00-7b1b-401b-93a5-04e8d868025f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004420555 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2004420555 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2448987906 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 2967055800 ps |
| CPU time | 199.44 seconds |
| Started | Jul 20 07:55:49 PM PDT 24 |
| Finished | Jul 20 07:59:10 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-54560190-c5d6-46a5-a6bc-cc233aa55b8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448987906 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.2448987906 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.2334467062 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 72092185400 ps |
| CPU time | 15219.3 seconds |
| Started | Jul 20 07:50:36 PM PDT 24 |
| Finished | Jul 21 12:04:18 AM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-8f90adca-9c4f-4e66-b5b7-7081024aa398 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2334467062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2334467062 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2952351791 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 23565187048 ps |
| CPU time | 5596.66 seconds |
| Started | Jul 20 07:51:59 PM PDT 24 |
| Finished | Jul 20 09:25:17 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-94cfd3d7-678f-46a0-814b-4fefaa2fe989 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952351791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2952351791 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1040054088 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 23479572104 ps |
| CPU time | 4069.1 seconds |
| Started | Jul 20 07:51:54 PM PDT 24 |
| Finished | Jul 20 08:59:44 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-a7889dd5-8d68-447b-ab26-df46507ca45b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1040054088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1040054088 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.90451407 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 5018392424 ps |
| CPU time | 622.96 seconds |
| Started | Jul 20 07:51:33 PM PDT 24 |
| Finished | Jul 20 08:01:57 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-a278a320-e315-4ace-934b-852dfb2e025d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90451 407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.90451407 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.1327960898 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 2895190702 ps |
| CPU time | 233.84 seconds |
| Started | Jul 20 07:58:26 PM PDT 24 |
| Finished | Jul 20 08:02:21 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-0d4dc055-565f-47a7-9007-003cede06d9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327960898 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.1327960898 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.97748348 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 5350365560 ps |
| CPU time | 651.55 seconds |
| Started | Jul 20 07:50:23 PM PDT 24 |
| Finished | Jul 20 08:01:15 PM PDT 24 |
| Peak memory | 611024 kb |
| Host | smart-f7059e40-eb49-4629-80b7-59173c18c77c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97748348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_lc _hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng _lc_hw_debug_en_test.97748348 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1752609236 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 3008476150 ps |
| CPU time | 244.5 seconds |
| Started | Jul 20 07:54:22 PM PDT 24 |
| Finished | Jul 20 07:58:27 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-23668eda-5c5c-41a9-a3d8-53993449ef6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752609236 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1752609236 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.965161067 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 4306885912 ps |
| CPU time | 946.74 seconds |
| Started | Jul 20 07:58:16 PM PDT 24 |
| Finished | Jul 20 08:14:03 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-8b8f2b74-edb7-44a8-8515-3641d3a84ddf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965161067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_a uto_mode.965161067 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3888225856 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 5300094288 ps |
| CPU time | 1037.88 seconds |
| Started | Jul 20 07:51:19 PM PDT 24 |
| Finished | Jul 20 08:08:38 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-b031380a-cce9-4c14-a32e-d82011bab88c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3888225856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3888225856 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2639635598 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 7438294825 ps |
| CPU time | 1375.03 seconds |
| Started | Jul 20 07:50:41 PM PDT 24 |
| Finished | Jul 20 08:13:37 PM PDT 24 |
| Peak memory | 610524 kb |
| Host | smart-468dff10-59de-46cb-810f-90c0ca757be3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639635598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.2639635598 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.3317317098 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3078671876 ps |
| CPU time | 604.68 seconds |
| Started | Jul 20 07:51:15 PM PDT 24 |
| Finished | Jul 20 08:01:21 PM PDT 24 |
| Peak memory | 615044 kb |
| Host | smart-06024484-edb3-42ea-a52c-f82ce73677e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317317098 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.3317317098 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.3671557178 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 9779032868 ps |
| CPU time | 2293.51 seconds |
| Started | Jul 20 07:52:30 PM PDT 24 |
| Finished | Jul 20 08:30:45 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-bb753fd4-c6ce-4111-a5cb-68d61c59f903 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671557178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.3671557178 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.117054419 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 2517728124 ps |
| CPU time | 174.9 seconds |
| Started | Jul 20 07:51:50 PM PDT 24 |
| Finished | Jul 20 07:54:46 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-d44bfa82-09dc-4535-bdc4-3e4d13649fed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 7054419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.117054419 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3410627458 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 2804905262 ps |
| CPU time | 301.58 seconds |
| Started | Jul 20 07:53:19 PM PDT 24 |
| Finished | Jul 20 07:58:22 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-ee19ae81-11f8-4dc7-a79e-bc932ec1b4a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410627458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.3410627458 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3236726282 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 3558783296 ps |
| CPU time | 561.61 seconds |
| Started | Jul 20 07:53:58 PM PDT 24 |
| Finished | Jul 20 08:03:21 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-801f578a-69b1-4547-a149-d82f64119804 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3236726282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3236726282 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2666477593 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3058052970 ps |
| CPU time | 308.43 seconds |
| Started | Jul 20 07:49:42 PM PDT 24 |
| Finished | Jul 20 07:54:51 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-be097e58-72ec-4f55-8b61-4341af886afa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666477593 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2666477593 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.298021906 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 2545014910 ps |
| CPU time | 218.05 seconds |
| Started | Jul 20 07:49:27 PM PDT 24 |
| Finished | Jul 20 07:53:06 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-a28477fa-5f0d-4b95-8b6c-0810c9d10150 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298021906 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.298021906 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2370222498 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2849594648 ps |
| CPU time | 215.5 seconds |
| Started | Jul 20 07:48:05 PM PDT 24 |
| Finished | Jul 20 07:51:41 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-2f1a87d6-bd0e-4310-a1fe-f6a4cab388ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370222498 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2370222498 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.1863719421 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2274281464 ps |
| CPU time | 123.55 seconds |
| Started | Jul 20 07:48:51 PM PDT 24 |
| Finished | Jul 20 07:50:55 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-084e025e-2f44-4305-91c8-be387f2ec70c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863719421 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.1863719421 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.2693251560 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 5702723540 ps |
| CPU time | 585.16 seconds |
| Started | Jul 20 07:52:25 PM PDT 24 |
| Finished | Jul 20 08:02:11 PM PDT 24 |
| Peak memory | 610956 kb |
| Host | smart-2cef927c-ca3d-42b0-ae68-86f511a1b394 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2693251560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.2693251560 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3733409567 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5986390180 ps |
| CPU time | 888.82 seconds |
| Started | Jul 20 07:48:34 PM PDT 24 |
| Finished | Jul 20 08:03:23 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-3426a76d-7b2d-4a4f-af74-23c33536a71f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733409567 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3733409567 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2275154623 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 6144948421 ps |
| CPU time | 1359.22 seconds |
| Started | Jul 20 07:57:21 PM PDT 24 |
| Finished | Jul 20 08:20:01 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-93141656-3d19-46a3-ab8f-ff3294384762 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275154623 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.2275154623 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3852741512 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 7535547843 ps |
| CPU time | 1162.77 seconds |
| Started | Jul 20 07:50:47 PM PDT 24 |
| Finished | Jul 20 08:10:11 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-f528805b-7dbc-4ae1-835f-e6edbc6e4c91 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852741512 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3852741512 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.80500802 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 6094104086 ps |
| CPU time | 1064.91 seconds |
| Started | Jul 20 07:49:18 PM PDT 24 |
| Finished | Jul 20 08:07:04 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-621162dd-c443-485d-8009-3b701d65b8e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80500802 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.80500802 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3449351202 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 3869438904 ps |
| CPU time | 433.81 seconds |
| Started | Jul 20 07:57:24 PM PDT 24 |
| Finished | Jul 20 08:04:39 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-0c035cb6-41c0-4bf8-aeb3-efd47d504e71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449351202 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3449351202 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2422093807 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 4324732524 ps |
| CPU time | 402.44 seconds |
| Started | Jul 20 07:49:29 PM PDT 24 |
| Finished | Jul 20 07:56:12 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-1a1c2a5a-c364-42ba-b1f8-b9ea4c35184b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24 22093807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2422093807 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1192750344 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 5396600052 ps |
| CPU time | 997.18 seconds |
| Started | Jul 20 07:52:25 PM PDT 24 |
| Finished | Jul 20 08:09:03 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-b159721c-296f-4d19-8cd4-d5841ee66ea4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192750344 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1192750344 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1400280339 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4792521730 ps |
| CPU time | 650.5 seconds |
| Started | Jul 20 07:56:37 PM PDT 24 |
| Finished | Jul 20 08:07:28 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-191f4533-f3bb-4ea3-96b9-3a5f2c79384c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400280339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.1400280339 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.724782210 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4478726445 ps |
| CPU time | 762.13 seconds |
| Started | Jul 20 07:58:18 PM PDT 24 |
| Finished | Jul 20 08:11:01 PM PDT 24 |
| Peak memory | 610184 kb |
| Host | smart-4efd37a3-d37d-406d-8365-f861366aa637 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=724782210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.724782210 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4214093276 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5197465479 ps |
| CPU time | 730.93 seconds |
| Started | Jul 20 07:52:43 PM PDT 24 |
| Finished | Jul 20 08:04:54 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-ad915a2d-c885-427b-97f5-2196a6eb6cc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4214093276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4214093276 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1117678642 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 3158344564 ps |
| CPU time | 301.67 seconds |
| Started | Jul 20 07:52:34 PM PDT 24 |
| Finished | Jul 20 07:57:36 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-28e66eaf-963f-45b6-8175-afae440f53fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117678 642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.1117678642 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2737422334 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 19381888277 ps |
| CPU time | 1940.65 seconds |
| Started | Jul 20 07:52:54 PM PDT 24 |
| Finished | Jul 20 08:25:16 PM PDT 24 |
| Peak memory | 614420 kb |
| Host | smart-29846feb-18a7-485c-bba9-729cabcf0f22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2737422334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.2737422334 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.95595929 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2978136626 ps |
| CPU time | 252.66 seconds |
| Started | Jul 20 07:59:10 PM PDT 24 |
| Finished | Jul 20 08:03:23 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-49766928-f93d-4656-9ea8-c6e068465978 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=95595929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.95595929 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.4155150973 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 3515464639 ps |
| CPU time | 336.46 seconds |
| Started | Jul 20 07:54:47 PM PDT 24 |
| Finished | Jul 20 08:00:24 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-5d805d36-30b3-4a64-8308-f9ae5936a929 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155150973 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.4155150973 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.910132930 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 2949984864 ps |
| CPU time | 367.42 seconds |
| Started | Jul 20 07:52:59 PM PDT 24 |
| Finished | Jul 20 07:59:07 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-1a575a8e-af97-4880-9dd8-20c063ead1d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910132930 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.910132930 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1567046902 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 3648295626 ps |
| CPU time | 304.52 seconds |
| Started | Jul 20 07:51:19 PM PDT 24 |
| Finished | Jul 20 07:56:25 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-44d73b7f-064d-44dc-a07d-caf82eaa875e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567046902 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.1567046902 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1804637548 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3187631486 ps |
| CPU time | 343.46 seconds |
| Started | Jul 20 07:50:52 PM PDT 24 |
| Finished | Jul 20 07:56:36 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-44b13319-6b06-4f7e-8b89-40fe61cb3817 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804637548 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.1804637548 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005935923 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 2534285745 ps |
| CPU time | 244.38 seconds |
| Started | Jul 20 07:54:38 PM PDT 24 |
| Finished | Jul 20 07:58:43 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-5cf9e5ac-8e53-47b1-88fd-64dbd33341b5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005935923 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005935923 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1099465329 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 8086271816 ps |
| CPU time | 1823.79 seconds |
| Started | Jul 20 07:55:34 PM PDT 24 |
| Finished | Jul 20 08:25:59 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-a9f50b7b-225c-4736-8b10-11c0546331f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099465329 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1099465329 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.3830222375 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 3026890936 ps |
| CPU time | 352.85 seconds |
| Started | Jul 20 07:51:12 PM PDT 24 |
| Finished | Jul 20 07:57:05 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-9da8d903-d723-4dcf-8359-14118641fd08 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830222375 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3830222375 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.1674988661 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 3361524096 ps |
| CPU time | 342.25 seconds |
| Started | Jul 20 07:56:45 PM PDT 24 |
| Finished | Jul 20 08:02:28 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-b38b5c86-8aa2-46f5-98cf-0e5675b2c4c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674988661 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.1674988661 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1239079245 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4286257620 ps |
| CPU time | 359.06 seconds |
| Started | Jul 20 07:48:58 PM PDT 24 |
| Finished | Jul 20 07:54:58 PM PDT 24 |
| Peak memory | 609608 kb |
| Host | smart-a2593491-a3a7-45e3-8ef8-2d4fca322a54 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239079245 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1239079245 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3077980108 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 64052652492 ps |
| CPU time | 11833.4 seconds |
| Started | Jul 20 07:48:53 PM PDT 24 |
| Finished | Jul 20 11:06:08 PM PDT 24 |
| Peak memory | 624752 kb |
| Host | smart-384c874d-1a37-423e-a662-9ff1cbbd8f9e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3077980108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3077980108 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.702500729 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 10897951486 ps |
| CPU time | 2423.72 seconds |
| Started | Jul 20 07:51:12 PM PDT 24 |
| Finished | Jul 20 08:31:36 PM PDT 24 |
| Peak memory | 616532 kb |
| Host | smart-f0a55875-86b4-412f-b928-c70a6de843b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7025 00729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.702500729 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2541569957 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 12915455297 ps |
| CPU time | 3092.02 seconds |
| Started | Jul 20 07:51:35 PM PDT 24 |
| Finished | Jul 20 08:43:08 PM PDT 24 |
| Peak memory | 617924 kb |
| Host | smart-91a03202-e74f-4d67-b570-c76ccc42f052 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2541569957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.2541569957 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2851525563 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 12694837365 ps |
| CPU time | 2164.89 seconds |
| Started | Jul 20 07:51:09 PM PDT 24 |
| Finished | Jul 20 08:27:15 PM PDT 24 |
| Peak memory | 617748 kb |
| Host | smart-5a7c9beb-a8ea-4638-9177-28bb6705afc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2851525563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2851525563 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.213553100 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 9763499340 ps |
| CPU time | 2322.27 seconds |
| Started | Jul 20 07:50:23 PM PDT 24 |
| Finished | Jul 20 08:29:06 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-3c1a0579-388c-4997-90f4-772a473d1461 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21355 3100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.213553100 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.908836271 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 3500289464 ps |
| CPU time | 272.16 seconds |
| Started | Jul 20 07:52:02 PM PDT 24 |
| Finished | Jul 20 07:56:35 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-0de26187-fac2-4a4e-9783-e11a7c091d3f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908836271 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_app_rom.908836271 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2657095738 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3207425296 ps |
| CPU time | 201.21 seconds |
| Started | Jul 20 07:54:21 PM PDT 24 |
| Finished | Jul 20 07:57:42 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-a3bf0974-b581-4ff7-80ce-2e8bf87d5f27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657095738 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2657095738 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3203062982 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3331495592 ps |
| CPU time | 333.2 seconds |
| Started | Jul 20 07:52:22 PM PDT 24 |
| Finished | Jul 20 07:57:56 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-4bbc1d3c-1dd4-4c2b-ad1c-d3333a1717ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203062982 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3203062982 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.605300911 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3783480616 ps |
| CPU time | 477.74 seconds |
| Started | Jul 20 07:52:09 PM PDT 24 |
| Finished | Jul 20 08:00:07 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-2ae55f67-7ff1-4e51-a9cd-87f5ceddb814 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605300911 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_kmac_mode_kmac.605300911 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1288807117 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 3331519377 ps |
| CPU time | 301.58 seconds |
| Started | Jul 20 07:51:38 PM PDT 24 |
| Finished | Jul 20 07:56:40 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-3aa51e2c-535c-47d9-a78a-e3c56dc45a94 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288807117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1288807117 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2490547514 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3846617117 ps |
| CPU time | 282.15 seconds |
| Started | Jul 20 07:53:23 PM PDT 24 |
| Finished | Jul 20 07:58:06 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-fdfaf89f-cf75-4d88-9847-c06e17fa7899 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905475 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2490547514 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.4270667654 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 2161236720 ps |
| CPU time | 301.9 seconds |
| Started | Jul 20 07:55:34 PM PDT 24 |
| Finished | Jul 20 08:00:36 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-973f0911-d88c-49f8-a800-8a5148b93aec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270667654 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.4270667654 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.329733177 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 3339916932 ps |
| CPU time | 308.58 seconds |
| Started | Jul 20 07:48:47 PM PDT 24 |
| Finished | Jul 20 07:53:56 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-f4f41b8b-c335-40cd-88ce-ff241889b76d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329733177 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.329733177 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4057346358 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 3280704445 ps |
| CPU time | 166.79 seconds |
| Started | Jul 20 07:49:11 PM PDT 24 |
| Finished | Jul 20 07:51:58 PM PDT 24 |
| Peak memory | 620044 kb |
| Host | smart-9b304bc3-508d-444c-8f7a-608f6babb2a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40573463 58 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.4057346358 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3391570340 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2882560134 ps |
| CPU time | 129.95 seconds |
| Started | Jul 20 07:49:45 PM PDT 24 |
| Finished | Jul 20 07:51:55 PM PDT 24 |
| Peak memory | 620456 kb |
| Host | smart-737163bc-b407-45f5-b0b4-c0b14edd0fbd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391570340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.3391570340 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.428767593 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2796827632 ps |
| CPU time | 136.83 seconds |
| Started | Jul 20 07:49:27 PM PDT 24 |
| Finished | Jul 20 07:51:45 PM PDT 24 |
| Peak memory | 620040 kb |
| Host | smart-45874f19-50eb-4f04-a5ef-8cd3ddecaaa7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=428767593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.428767593 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.479131605 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 8091792498 ps |
| CPU time | 738.38 seconds |
| Started | Jul 20 07:50:23 PM PDT 24 |
| Finished | Jul 20 08:02:43 PM PDT 24 |
| Peak memory | 621140 kb |
| Host | smart-84d1cb0a-d1ae-4033-9c55-d4fc54510154 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479131605 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.479131605 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3753031455 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2351202409 ps |
| CPU time | 108.74 seconds |
| Started | Jul 20 07:49:26 PM PDT 24 |
| Finished | Jul 20 07:51:16 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-e8c0f592-2bed-4593-995e-710a89bee347 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3753031455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.3753031455 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2038471760 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1971804514 ps |
| CPU time | 128.46 seconds |
| Started | Jul 20 07:49:35 PM PDT 24 |
| Finished | Jul 20 07:51:44 PM PDT 24 |
| Peak memory | 617724 kb |
| Host | smart-2e0d1984-527e-4268-a6b4-acdec59657ba |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038471760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2038471760 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3636002176 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 47497555448 ps |
| CPU time | 5322.84 seconds |
| Started | Jul 20 07:48:58 PM PDT 24 |
| Finished | Jul 20 09:17:43 PM PDT 24 |
| Peak memory | 617940 kb |
| Host | smart-fbd29053-9de9-4753-b3fa-dbada6431fac |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636002176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.3636002176 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3198584320 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 11384524692 ps |
| CPU time | 1157.16 seconds |
| Started | Jul 20 07:49:59 PM PDT 24 |
| Finished | Jul 20 08:09:17 PM PDT 24 |
| Peak memory | 615508 kb |
| Host | smart-d0b3ce54-8a26-4f6d-89d1-c6d54cc9e96c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198584320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.3198584320 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2881339889 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 47486589700 ps |
| CPU time | 6042.52 seconds |
| Started | Jul 20 07:49:57 PM PDT 24 |
| Finished | Jul 20 09:30:42 PM PDT 24 |
| Peak memory | 620264 kb |
| Host | smart-449fd9e1-806a-477f-9332-ec02e600277f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881339889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2881339889 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2786999687 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 31107764396 ps |
| CPU time | 2805.28 seconds |
| Started | Jul 20 07:49:54 PM PDT 24 |
| Finished | Jul 20 08:36:40 PM PDT 24 |
| Peak memory | 620176 kb |
| Host | smart-de955f90-2d11-49bb-975d-82856928676f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2786999687 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.2786999687 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2289659469 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 17395761368 ps |
| CPU time | 4278.96 seconds |
| Started | Jul 20 07:50:07 PM PDT 24 |
| Finished | Jul 20 09:01:27 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-a0340e9b-174e-4d3a-a0f2-c0c769b6d6e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2289659469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2289659469 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1971993392 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 18589467015 ps |
| CPU time | 3634.03 seconds |
| Started | Jul 20 07:49:51 PM PDT 24 |
| Finished | Jul 20 08:50:26 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-13e900b4-4054-4f16-9439-c51d5dce91cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1971993392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1971993392 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3342597441 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3688455032 ps |
| CPU time | 647.58 seconds |
| Started | Jul 20 07:50:51 PM PDT 24 |
| Finished | Jul 20 08:01:39 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-93afeb44-4fa2-4231-a78e-1915f7f53c23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342597441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3342597441 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.50079594 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5660348856 ps |
| CPU time | 1118.53 seconds |
| Started | Jul 20 07:51:31 PM PDT 24 |
| Finished | Jul 20 08:10:10 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-301fe3be-5090-46f0-ba24-0b07e6c76689 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=50079594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.50079594 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2278240477 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 9227686524 ps |
| CPU time | 2158.23 seconds |
| Started | Jul 20 07:57:46 PM PDT 24 |
| Finished | Jul 20 08:33:45 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-d5c18449-4328-4ea1-b4c8-683abc8eff60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278240477 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2278240477 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2528116930 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 28177598248 ps |
| CPU time | 6392.93 seconds |
| Started | Jul 20 07:49:53 PM PDT 24 |
| Finished | Jul 20 09:36:28 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-50608540-faba-44e0-8225-dc079f1263df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252811 6930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2528116930 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3673429698 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 3414260303 ps |
| CPU time | 351.7 seconds |
| Started | Jul 20 07:50:22 PM PDT 24 |
| Finished | Jul 20 07:56:15 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-6382af9a-64b7-439e-a697-33b87d257ea0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673429698 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3673429698 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.996807704 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4948633046 ps |
| CPU time | 528.94 seconds |
| Started | Jul 20 07:49:47 PM PDT 24 |
| Finished | Jul 20 07:58:36 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-72455c8a-ef38-4f2a-996d-0baca7cb94b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 996807704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.996807704 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3650324282 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 6627176770 ps |
| CPU time | 1035.01 seconds |
| Started | Jul 20 07:49:48 PM PDT 24 |
| Finished | Jul 20 08:07:03 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-3fd9e040-c19e-4888-bf81-f9527c7305d8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3650324282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.3650324282 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3382416996 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6960143170 ps |
| CPU time | 1322.34 seconds |
| Started | Jul 20 07:49:06 PM PDT 24 |
| Finished | Jul 20 08:11:09 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-d37a82c6-1e91-4713-af13-a27da0693fab |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3382416996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3382416996 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.188315893 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 6427500508 ps |
| CPU time | 1119.21 seconds |
| Started | Jul 20 07:49:29 PM PDT 24 |
| Finished | Jul 20 08:08:09 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-9a6e401a-45ae-4e1d-8520-ccc3dc23bebc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=188315893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.188315893 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.615313907 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 4830352520 ps |
| CPU time | 693.99 seconds |
| Started | Jul 20 07:57:56 PM PDT 24 |
| Finished | Jul 20 08:09:32 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-ee9a6ace-55b4-490a-a4c2-79983e6d46bb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=615313907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.615313907 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4289293230 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3452700256 ps |
| CPU time | 349.08 seconds |
| Started | Jul 20 07:57:35 PM PDT 24 |
| Finished | Jul 20 08:03:25 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-447aea9e-b090-4e5b-a44b-8bcebfde8bfb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289293230 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.4289293230 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.3154435704 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2944661048 ps |
| CPU time | 190.58 seconds |
| Started | Jul 20 07:48:29 PM PDT 24 |
| Finished | Jul 20 07:51:41 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-d9b70849-6886-4b1a-b592-7b5b6532ca31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154435704 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.3154435704 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1672657818 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3928647058 ps |
| CPU time | 655.54 seconds |
| Started | Jul 20 07:53:31 PM PDT 24 |
| Finished | Jul 20 08:04:28 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-a5c0ab67-fa3d-4d39-a3a8-974c826f7623 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672657818 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1672657818 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.297278128 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 10944611326 ps |
| CPU time | 436.77 seconds |
| Started | Jul 20 07:53:08 PM PDT 24 |
| Finished | Jul 20 08:00:26 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-8ff7e439-fa60-46f7-90c0-0438a3cacf87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297278128 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.297278128 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2845897371 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 9371212228 ps |
| CPU time | 1284.11 seconds |
| Started | Jul 20 07:52:46 PM PDT 24 |
| Finished | Jul 20 08:14:11 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-bc0f3609-9bad-459a-a9dc-a62eb7b9cd0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845 897371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2845897371 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1429160632 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 22042174938 ps |
| CPU time | 2304.36 seconds |
| Started | Jul 20 07:51:08 PM PDT 24 |
| Finished | Jul 20 08:29:34 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-35ad2af1-865d-4886-ad77-d59e3db6932f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142 9160632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.1429160632 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3682366821 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 14021430654 ps |
| CPU time | 1168.13 seconds |
| Started | Jul 20 07:50:09 PM PDT 24 |
| Finished | Jul 20 08:09:38 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-2280de91-dc8f-4436-9a65-90f52c3c1e89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3682366821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3682366821 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2792835593 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 7441712130 ps |
| CPU time | 811.81 seconds |
| Started | Jul 20 07:57:35 PM PDT 24 |
| Finished | Jul 20 08:11:07 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-1eb697fc-0ff9-43ad-8f40-8f6f3b082db6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792835593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2792835593 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3702846359 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 5762447680 ps |
| CPU time | 377.55 seconds |
| Started | Jul 20 07:49:29 PM PDT 24 |
| Finished | Jul 20 07:55:47 PM PDT 24 |
| Peak memory | 617124 kb |
| Host | smart-f42bd84e-775c-4133-8fc9-7f28bcc16372 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3702846359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3702846359 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2414022813 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 4768539000 ps |
| CPU time | 495.06 seconds |
| Started | Jul 20 07:50:20 PM PDT 24 |
| Finished | Jul 20 07:58:35 PM PDT 24 |
| Peak memory | 616320 kb |
| Host | smart-685e3b75-3abd-4d9f-bea5-d86e9180a471 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2414022813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2414022813 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1142930790 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 10750644423 ps |
| CPU time | 1711.17 seconds |
| Started | Jul 20 07:49:04 PM PDT 24 |
| Finished | Jul 20 08:17:36 PM PDT 24 |
| Peak memory | 611292 kb |
| Host | smart-170cbef1-f926-4d6e-98e5-c9e38c72aa36 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142930790 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1142930790 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3975034240 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 6926907492 ps |
| CPU time | 457.98 seconds |
| Started | Jul 20 07:54:06 PM PDT 24 |
| Finished | Jul 20 08:01:46 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-e29b1e74-93a4-46b7-a5cc-7f28442f152f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975034240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3975034240 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3639560181 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5662751936 ps |
| CPU time | 658.61 seconds |
| Started | Jul 20 07:50:30 PM PDT 24 |
| Finished | Jul 20 08:01:30 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-5d8a6ff8-9f3c-43f6-9679-c4842fb8d5d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639560181 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.3639560181 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.862950319 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 27625945935 ps |
| CPU time | 2877.68 seconds |
| Started | Jul 20 07:54:31 PM PDT 24 |
| Finished | Jul 20 08:42:29 PM PDT 24 |
| Peak memory | 611276 kb |
| Host | smart-74ec4990-219e-4899-97de-4ef9b0284f34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=862950319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.862950319 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.909434181 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 25402298410 ps |
| CPU time | 1909.39 seconds |
| Started | Jul 20 07:51:37 PM PDT 24 |
| Finished | Jul 20 08:23:28 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-19944ef6-2920-4db8-81ad-c6c42c33c157 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=909434181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.909434181 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2090100429 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 40460192007 ps |
| CPU time | 4235.33 seconds |
| Started | Jul 20 07:50:53 PM PDT 24 |
| Finished | Jul 20 09:01:29 PM PDT 24 |
| Peak memory | 612028 kb |
| Host | smart-a07fa2e6-78a9-4b33-97c6-3b92fc287cff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090100429 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2090100429 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.353083915 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 3417765108 ps |
| CPU time | 377.46 seconds |
| Started | Jul 20 07:54:18 PM PDT 24 |
| Finished | Jul 20 08:00:37 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-631e4dd0-098b-4be7-89cc-ac37db23c196 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353083915 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.353083915 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1532498950 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 5797689797 ps |
| CPU time | 572.9 seconds |
| Started | Jul 20 07:50:03 PM PDT 24 |
| Finished | Jul 20 07:59:37 PM PDT 24 |
| Peak memory | 617532 kb |
| Host | smart-0823ba05-5fe9-4081-abb1-e056833cbe51 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1532498950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.1532498950 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1650850154 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6789566620 ps |
| CPU time | 526.32 seconds |
| Started | Jul 20 07:50:56 PM PDT 24 |
| Finished | Jul 20 07:59:43 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-3165c777-8c49-41ca-98f0-f4b0b717d41f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1650850154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1650850154 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1279984460 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 6060537400 ps |
| CPU time | 374.65 seconds |
| Started | Jul 20 07:55:40 PM PDT 24 |
| Finished | Jul 20 08:01:55 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-00b9e527-3a02-44fe-aa7b-33e9a93aa0fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279984460 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.1279984460 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.511008428 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 7422287500 ps |
| CPU time | 1147.5 seconds |
| Started | Jul 20 07:49:33 PM PDT 24 |
| Finished | Jul 20 08:08:41 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-5d3fdefd-928f-44d0-ad5f-b269dd26905d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511008428 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.511008428 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1642126289 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 5442016896 ps |
| CPU time | 544.56 seconds |
| Started | Jul 20 07:50:46 PM PDT 24 |
| Finished | Jul 20 07:59:52 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-0430240a-283a-4856-84ec-183103a49a56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642126289 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1642126289 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2722327713 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 5555372460 ps |
| CPU time | 364.29 seconds |
| Started | Jul 20 07:55:54 PM PDT 24 |
| Finished | Jul 20 08:01:58 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-603602d0-4e5c-44c8-848f-930911dfc70b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722327713 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.2722327713 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3406685403 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 4222947520 ps |
| CPU time | 511.17 seconds |
| Started | Jul 20 07:52:43 PM PDT 24 |
| Finished | Jul 20 08:01:15 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-a59315c5-9a7f-4495-8592-934923747ad9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340 6685403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3406685403 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.169537956 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 8824800651 ps |
| CPU time | 685.09 seconds |
| Started | Jul 20 07:52:35 PM PDT 24 |
| Finished | Jul 20 08:04:01 PM PDT 24 |
| Peak memory | 623828 kb |
| Host | smart-c06f21fb-7b49-4134-9060-319eb2dc72ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169537956 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.169537956 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3746427153 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 6720873850 ps |
| CPU time | 781.81 seconds |
| Started | Jul 20 07:50:55 PM PDT 24 |
| Finished | Jul 20 08:03:58 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-75b50c4d-104b-4e9a-826d-408ef42f937a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746427153 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3746427153 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1133909260 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4715074744 ps |
| CPU time | 685.06 seconds |
| Started | Jul 20 07:55:51 PM PDT 24 |
| Finished | Jul 20 08:07:17 PM PDT 24 |
| Peak memory | 641528 kb |
| Host | smart-73dd7367-5876-4037-b6de-e9ef5a9fec61 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1133909260 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.1133909260 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1788864372 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 3253232886 ps |
| CPU time | 192.79 seconds |
| Started | Jul 20 07:53:55 PM PDT 24 |
| Finished | Jul 20 07:57:08 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-23d12d59-ade7-44c8-9002-5bb0e120f85d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788864372 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.1788864372 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2376648248 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 5144748250 ps |
| CPU time | 506.32 seconds |
| Started | Jul 20 07:49:48 PM PDT 24 |
| Finished | Jul 20 07:58:15 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-59beb1b3-533b-425d-abd4-3f0c5c969b6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376648248 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.2376648248 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4196691716 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2535101100 ps |
| CPU time | 310.89 seconds |
| Started | Jul 20 07:50:14 PM PDT 24 |
| Finished | Jul 20 07:55:26 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-a98b3c10-ac71-4ea2-bfd9-fd8c8c94be5e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196691716 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.4196691716 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.1911847698 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2937427868 ps |
| CPU time | 260.33 seconds |
| Started | Jul 20 07:51:52 PM PDT 24 |
| Finished | Jul 20 07:56:13 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-cace1fb1-8767-4089-8b2d-d202e4dcf83d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911847698 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.1911847698 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3155330104 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 5528089404 ps |
| CPU time | 1069.32 seconds |
| Started | Jul 20 07:50:16 PM PDT 24 |
| Finished | Jul 20 08:08:06 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-f614d377-fc1b-4a8c-bb36-e53b2474810c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3155330104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3155330104 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1609876587 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 4507159712 ps |
| CPU time | 479.01 seconds |
| Started | Jul 20 07:52:42 PM PDT 24 |
| Finished | Jul 20 08:00:42 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-5815b832-7fce-4fc1-a3c4-877d93a039d4 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609876587 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1609876587 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4125912812 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 6271757280 ps |
| CPU time | 342.36 seconds |
| Started | Jul 20 07:51:02 PM PDT 24 |
| Finished | Jul 20 07:56:45 PM PDT 24 |
| Peak memory | 620216 kb |
| Host | smart-5b786922-be58-4396-af63-f0c87b206c53 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125912812 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.4125912812 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2958905950 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 3422945836 ps |
| CPU time | 290.29 seconds |
| Started | Jul 20 07:53:01 PM PDT 24 |
| Finished | Jul 20 07:57:52 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-834437bf-2e75-417b-acc7-236949845d9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958905950 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2958905950 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.2636767395 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2286264320 ps |
| CPU time | 230.03 seconds |
| Started | Jul 20 07:52:40 PM PDT 24 |
| Finished | Jul 20 07:56:31 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-b2720516-946e-4ee2-93cc-34140d0a8c05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636767395 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.2636767395 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.525878755 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 2821124928 ps |
| CPU time | 264.2 seconds |
| Started | Jul 20 07:58:14 PM PDT 24 |
| Finished | Jul 20 08:02:39 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-e8599112-23e8-4831-a0e8-d639f660cef2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525878755 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_smoketest.525878755 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2569793220 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3086674405 ps |
| CPU time | 262.83 seconds |
| Started | Jul 20 07:54:51 PM PDT 24 |
| Finished | Jul 20 07:59:15 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-d70182c1-949f-4a6f-824b-4bafa07e06e7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569793 220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2569793220 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.761739406 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 3595516880 ps |
| CPU time | 407.1 seconds |
| Started | Jul 20 07:49:07 PM PDT 24 |
| Finished | Jul 20 07:55:55 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-666d7383-3df9-4e6c-bd6d-734b629f6f92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761739406 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.761739406 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3421405075 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 8751666960 ps |
| CPU time | 1465.49 seconds |
| Started | Jul 20 07:49:17 PM PDT 24 |
| Finished | Jul 20 08:13:44 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-2e3659ae-b087-45be-94cb-c01bf4370127 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421405075 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.3421405075 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1725705813 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 8269958266 ps |
| CPU time | 643.58 seconds |
| Started | Jul 20 07:52:29 PM PDT 24 |
| Finished | Jul 20 08:03:13 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-db307ef9-f33d-43da-bf13-956f022cc9f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725705813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1725705813 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1530425230 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 7212887864 ps |
| CPU time | 746.48 seconds |
| Started | Jul 20 07:52:59 PM PDT 24 |
| Finished | Jul 20 08:05:26 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-e6716002-53fc-4dd5-a1d2-199840e0d03e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530425230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1530425230 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1901860648 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 5556565031 ps |
| CPU time | 473.11 seconds |
| Started | Jul 20 07:49:51 PM PDT 24 |
| Finished | Jul 20 07:57:45 PM PDT 24 |
| Peak memory | 624820 kb |
| Host | smart-baea5935-f60a-475f-a586-2bdda5ed2873 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901860648 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1901860648 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.1074861718 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3296843618 ps |
| CPU time | 356.99 seconds |
| Started | Jul 20 07:50:14 PM PDT 24 |
| Finished | Jul 20 07:56:12 PM PDT 24 |
| Peak memory | 618424 kb |
| Host | smart-d3a50ec8-17d2-4345-8c98-836e1dc6010b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074861718 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.1074861718 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.785298749 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2830084360 ps |
| CPU time | 342.06 seconds |
| Started | Jul 20 07:48:46 PM PDT 24 |
| Finished | Jul 20 07:54:29 PM PDT 24 |
| Peak memory | 608928 kb |
| Host | smart-2fc484ca-c585-431d-9a0e-3231c03b6236 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785298749 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.785298749 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2983864060 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 4272659716 ps |
| CPU time | 497.94 seconds |
| Started | Jul 20 07:52:36 PM PDT 24 |
| Finished | Jul 20 08:00:55 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-7a0217ee-c241-4c07-a2c4-18e0258bf2ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983864060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2983864060 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3646777562 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 4767671785 ps |
| CPU time | 586.67 seconds |
| Started | Jul 20 07:51:34 PM PDT 24 |
| Finished | Jul 20 08:01:22 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-51ba1893-4254-472e-9ee4-36ea056e997a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646777562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3646777562 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1712698067 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 5193453923 ps |
| CPU time | 534.18 seconds |
| Started | Jul 20 07:51:24 PM PDT 24 |
| Finished | Jul 20 08:00:19 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-32fa95b6-e1c1-43ac-aa53-5430ee8d7fc5 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712698067 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1712698067 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3556604587 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 3131292472 ps |
| CPU time | 240.33 seconds |
| Started | Jul 20 07:54:51 PM PDT 24 |
| Finished | Jul 20 07:58:52 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-c3f650b1-f9c2-4f63-9da2-47f48d1e9b6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556604587 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3556604587 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.71278299 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 20420117556 ps |
| CPU time | 3502.13 seconds |
| Started | Jul 20 07:49:49 PM PDT 24 |
| Finished | Jul 20 08:48:12 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-645ba2a2-fb48-42a3-bc7a-8b4465d48ec1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71278299 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.71278299 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.477595784 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 4956401717 ps |
| CPU time | 596.69 seconds |
| Started | Jul 20 07:50:28 PM PDT 24 |
| Finished | Jul 20 08:00:27 PM PDT 24 |
| Peak memory | 613332 kb |
| Host | smart-0d50470d-b42f-434d-85f5-890241e8c8af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477595784 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.477595784 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3307014062 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3098686602 ps |
| CPU time | 280.07 seconds |
| Started | Jul 20 07:50:11 PM PDT 24 |
| Finished | Jul 20 07:54:53 PM PDT 24 |
| Peak memory | 613276 kb |
| Host | smart-70fdd712-7de4-4ffa-a111-13adb682478a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307014062 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.3307014062 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3857653090 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3303039024 ps |
| CPU time | 382.48 seconds |
| Started | Jul 20 07:54:34 PM PDT 24 |
| Finished | Jul 20 08:00:58 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-ce071a50-2c05-4e7d-b8dd-7450d9d70192 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857653090 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.3857653090 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.349730411 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 24248317160 ps |
| CPU time | 2138.71 seconds |
| Started | Jul 20 07:49:39 PM PDT 24 |
| Finished | Jul 20 08:25:18 PM PDT 24 |
| Peak memory | 613956 kb |
| Host | smart-725c972b-4492-4a15-9015-3c9df82244dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34973041 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.349730411 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.693517791 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4808411256 ps |
| CPU time | 409.1 seconds |
| Started | Jul 20 07:50:01 PM PDT 24 |
| Finished | Jul 20 07:56:52 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-31ade210-64d3-4690-8476-ea0a345082ab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693517791 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.693517791 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2537642898 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 3904018552 ps |
| CPU time | 585.31 seconds |
| Started | Jul 20 07:49:09 PM PDT 24 |
| Finished | Jul 20 07:58:55 PM PDT 24 |
| Peak memory | 618732 kb |
| Host | smart-b15b0ce7-b0bc-4db0-a5d5-49196b6f1545 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2537642898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2537642898 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.891787063 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 2602768980 ps |
| CPU time | 223.97 seconds |
| Started | Jul 20 07:58:46 PM PDT 24 |
| Finished | Jul 20 08:02:31 PM PDT 24 |
| Peak memory | 616112 kb |
| Host | smart-164df4eb-05b9-4a88-841d-54a06cf19287 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891787063 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_uart_smoketest.891787063 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.3217217159 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 4776295670 ps |
| CPU time | 534.99 seconds |
| Started | Jul 20 07:49:31 PM PDT 24 |
| Finished | Jul 20 07:58:27 PM PDT 24 |
| Peak memory | 624108 kb |
| Host | smart-42461b63-6dc3-4187-8464-f41e1457d04c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217217159 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.3217217159 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2901210933 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 4505129250 ps |
| CPU time | 522.29 seconds |
| Started | Jul 20 07:47:52 PM PDT 24 |
| Finished | Jul 20 07:56:35 PM PDT 24 |
| Peak memory | 624712 kb |
| Host | smart-bf157ab8-00c3-4ad2-8f70-e268a45f3b1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901210933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.2901210933 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3601381160 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8703221634 ps |
| CPU time | 1068.99 seconds |
| Started | Jul 20 07:49:25 PM PDT 24 |
| Finished | Jul 20 08:07:15 PM PDT 24 |
| Peak memory | 624668 kb |
| Host | smart-c9f94bd5-5a13-4bd9-bd96-2d379064c2e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601381160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3601381160 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1172931461 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 77806176703 ps |
| CPU time | 14441 seconds |
| Started | Jul 20 07:55:59 PM PDT 24 |
| Finished | Jul 20 11:56:43 PM PDT 24 |
| Peak memory | 635048 kb |
| Host | smart-8e208db0-d3fb-49bb-8006-7633221ff77d |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1172931461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.1172931461 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3014218341 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 4535753840 ps |
| CPU time | 636.53 seconds |
| Started | Jul 20 07:55:18 PM PDT 24 |
| Finished | Jul 20 08:05:57 PM PDT 24 |
| Peak memory | 624056 kb |
| Host | smart-fce72b1c-9b8d-4b3c-8f30-55ebc231a2c5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014218341 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3014218341 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3713087015 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 4569477368 ps |
| CPU time | 586.99 seconds |
| Started | Jul 20 07:53:27 PM PDT 24 |
| Finished | Jul 20 08:03:18 PM PDT 24 |
| Peak memory | 622788 kb |
| Host | smart-3b70717a-6a9c-46d8-a158-186f01ce0efd |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713087015 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3713087015 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1980472569 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 4753841912 ps |
| CPU time | 794.41 seconds |
| Started | Jul 20 07:49:50 PM PDT 24 |
| Finished | Jul 20 08:03:05 PM PDT 24 |
| Peak memory | 622812 kb |
| Host | smart-63432965-faf8-4482-9462-39c025d7142d |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980472569 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.1980472569 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.99996640 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3160250095 ps |
| CPU time | 360.84 seconds |
| Started | Jul 20 07:53:07 PM PDT 24 |
| Finished | Jul 20 07:59:09 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-d38de004-604f-4329-9931-a107673b9b95 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99996640 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.99996640 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3183115708 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 7933574932 ps |
| CPU time | 1800.74 seconds |
| Started | Jul 20 07:48:39 PM PDT 24 |
| Finished | Jul 20 08:18:41 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-2e1bf1cb-3ada-4e55-925a-b2bee5d78807 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831 15708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3183115708 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.3888610390 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 12290860834 ps |
| CPU time | 2849.84 seconds |
| Started | Jul 20 07:55:24 PM PDT 24 |
| Finished | Jul 20 08:42:56 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-275a0352-5f18-4087-9a0a-f875a118acf1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3888610390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.3888610390 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.2056176979 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 2176769218 ps |
| CPU time | 267.4 seconds |
| Started | Jul 20 07:55:51 PM PDT 24 |
| Finished | Jul 20 08:00:20 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-72bcda63-9cba-4829-8569-f3fc8c727e2c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056176979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.2056176979 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3348837130 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 3872895596 ps |
| CPU time | 673.24 seconds |
| Started | Jul 20 07:50:00 PM PDT 24 |
| Finished | Jul 20 08:01:14 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-558ce482-8fde-4dde-809d-5ec136345f51 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334883713 0 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3348837130 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2851966874 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 19481930052 ps |
| CPU time | 4896.66 seconds |
| Started | Jul 20 07:49:13 PM PDT 24 |
| Finished | Jul 20 09:10:51 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-a13cc661-94eb-4098-9926-30b0c9cd2cce |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2851966874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2851966874 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3839036098 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2917963032 ps |
| CPU time | 294.31 seconds |
| Started | Jul 20 07:49:26 PM PDT 24 |
| Finished | Jul 20 07:54:21 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-9d16f0de-6438-4411-8486-75526c177eaa |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839036098 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3839036098 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.2786491371 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 15278653852 ps |
| CPU time | 1824.81 seconds |
| Started | Jul 20 07:51:27 PM PDT 24 |
| Finished | Jul 20 08:21:52 PM PDT 24 |
| Peak memory | 620912 kb |
| Host | smart-ee25866a-0e41-4eac-9740-a73175f1f17d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2786491371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.2786491371 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2734349218 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2667506797 ps |
| CPU time | 201.39 seconds |
| Started | Jul 20 07:53:10 PM PDT 24 |
| Finished | Jul 20 07:56:32 PM PDT 24 |
| Peak memory | 620120 kb |
| Host | smart-3507b965-ca52-4e0b-b005-a4fadf94b67b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734349218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2734349218 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.2833239226 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 8503705505 ps |
| CPU time | 908.48 seconds |
| Started | Jul 20 07:51:32 PM PDT 24 |
| Finished | Jul 20 08:06:41 PM PDT 24 |
| Peak memory | 620944 kb |
| Host | smart-b8e9de75-a159-40cf-ab4b-9ff5dab348f5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833239226 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.2833239226 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3389890398 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 7934003707 ps |
| CPU time | 783.06 seconds |
| Started | Jul 20 07:49:58 PM PDT 24 |
| Finished | Jul 20 08:03:01 PM PDT 24 |
| Peak memory | 620976 kb |
| Host | smart-b61cac0d-61c3-43b7-be48-7db5eb16d40a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3389890398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3389890398 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3956539371 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 14839448192 ps |
| CPU time | 4016.73 seconds |
| Started | Jul 20 07:59:13 PM PDT 24 |
| Finished | Jul 20 09:06:11 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-321f51a0-860f-423b-9db6-f3b1098ff5a8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956539371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3956539371 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.1888996304 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 15377074610 ps |
| CPU time | 3815.84 seconds |
| Started | Jul 20 07:55:48 PM PDT 24 |
| Finished | Jul 20 08:59:25 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-49d3c361-19b9-4c93-8b2f-08f1b8444fea |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888996304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.1888996304 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3454734077 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 14757576733 ps |
| CPU time | 4168.12 seconds |
| Started | Jul 20 07:58:09 PM PDT 24 |
| Finished | Jul 20 09:07:38 PM PDT 24 |
| Peak memory | 611484 kb |
| Host | smart-672d8d1f-aaea-4ec9-9888-a65cf13c1396 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454734077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3454734077 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.772822373 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 15346174904 ps |
| CPU time | 3739.64 seconds |
| Started | Jul 20 07:59:36 PM PDT 24 |
| Finished | Jul 20 09:01:56 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-0350eec4-11f4-42c6-a98a-c0134c26a4e2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772822373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_rma.772822373 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2349518760 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 11423161454 ps |
| CPU time | 3828.07 seconds |
| Started | Jul 20 08:01:03 PM PDT 24 |
| Finished | Jul 20 09:04:52 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-e869b980-dd1d-48ae-948f-0f6e28506b4c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349518760 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2349518760 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2354112506 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 24183679840 ps |
| CPU time | 5817.72 seconds |
| Started | Jul 20 08:01:12 PM PDT 24 |
| Finished | Jul 20 09:38:11 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-0cb748b6-1a8a-4548-8441-975f12ae17c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2354112506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2354112506 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.923895315 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 23844882040 ps |
| CPU time | 6460.07 seconds |
| Started | Jul 20 07:55:49 PM PDT 24 |
| Finished | Jul 20 09:43:30 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-14493500-81f5-4b5e-97b8-21ceeac0e51d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=923895315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.923895315 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1472135862 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 23519039848 ps |
| CPU time | 6559.5 seconds |
| Started | Jul 20 08:01:03 PM PDT 24 |
| Finished | Jul 20 09:50:24 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-f1805446-1d29-493b-87e4-df0735a34d5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1472135862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1472135862 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2897754139 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 18737557224 ps |
| CPU time | 4663.22 seconds |
| Started | Jul 20 08:01:22 PM PDT 24 |
| Finished | Jul 20 09:19:07 PM PDT 24 |
| Peak memory | 610984 kb |
| Host | smart-f8d24ab3-eab6-49eb-873b-4dd4e224a0d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897754139 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2897754139 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3252514900 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 15729410408 ps |
| CPU time | 3425 seconds |
| Started | Jul 20 08:01:19 PM PDT 24 |
| Finished | Jul 20 08:58:25 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-9710e249-cdf1-4874-93c5-ce04904976ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3252514900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3252514900 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.842701629 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 15488768870 ps |
| CPU time | 3489.74 seconds |
| Started | Jul 20 07:59:57 PM PDT 24 |
| Finished | Jul 20 08:58:08 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-dadcca36-3fa1-4ded-982d-9d2ca75a0547 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=842701629 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.842701629 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1870878297 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 15976788692 ps |
| CPU time | 3626.05 seconds |
| Started | Jul 20 07:57:58 PM PDT 24 |
| Finished | Jul 20 08:58:24 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-348a50c8-5cc4-4fe7-8990-899431b0aa35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1870878297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1870878297 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.153641908 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 15392878800 ps |
| CPU time | 4186.53 seconds |
| Started | Jul 20 08:00:00 PM PDT 24 |
| Finished | Jul 20 09:09:47 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-5c310c61-f653-4958-a8e8-7dce3567c941 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=153641908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.153641908 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1577106535 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 11431055956 ps |
| CPU time | 3441.17 seconds |
| Started | Jul 20 07:58:36 PM PDT 24 |
| Finished | Jul 20 08:55:58 PM PDT 24 |
| Peak memory | 609948 kb |
| Host | smart-54363111-305c-4e93-a7a6-c6fd0737d441 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577106535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1577106535 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3855730872 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 15841333446 ps |
| CPU time | 4186.68 seconds |
| Started | Jul 20 07:57:41 PM PDT 24 |
| Finished | Jul 20 09:07:29 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-d25c54ab-ba2a-4f42-91a8-c10c9f0158d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855730872 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3855730872 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3330091801 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 15146480776 ps |
| CPU time | 4002.72 seconds |
| Started | Jul 20 07:59:03 PM PDT 24 |
| Finished | Jul 20 09:05:47 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-0a96d447-2af8-4b28-998b-b7ab3c5552a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330091801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3330091801 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2377340291 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 15561527256 ps |
| CPU time | 3777.77 seconds |
| Started | Jul 20 07:59:32 PM PDT 24 |
| Finished | Jul 20 09:02:31 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-fb6e4b6a-6e85-49e6-bf60-19fbc95e9b92 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237734 0291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2377340291 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4255532656 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 14383563838 ps |
| CPU time | 4572.42 seconds |
| Started | Jul 20 07:57:37 PM PDT 24 |
| Finished | Jul 20 09:13:51 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-184ffcc6-2125-4678-94ce-8fb93db44979 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255532656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4255532656 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.175916891 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 11241949944 ps |
| CPU time | 2879.82 seconds |
| Started | Jul 20 08:01:19 PM PDT 24 |
| Finished | Jul 20 08:49:19 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-fb177a50-d28a-4876-af86-56d5deb6bec1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 175916891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.175916891 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2295642795 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 11358213626 ps |
| CPU time | 1913.23 seconds |
| Started | Jul 20 07:52:43 PM PDT 24 |
| Finished | Jul 20 08:24:37 PM PDT 24 |
| Peak memory | 624200 kb |
| Host | smart-755479ff-eed1-4d38-9a51-61ba058ae2af |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956 42795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.2295642795 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3706317684 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 10946629742 ps |
| CPU time | 2007.01 seconds |
| Started | Jul 20 07:56:59 PM PDT 24 |
| Finished | Jul 20 08:30:28 PM PDT 24 |
| Peak memory | 623824 kb |
| Host | smart-e42ecaa0-165c-4904-98e8-d182c127b59c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37063 17684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.3706317684 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4016170873 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 10876671724 ps |
| CPU time | 2322 seconds |
| Started | Jul 20 07:53:22 PM PDT 24 |
| Finished | Jul 20 08:32:06 PM PDT 24 |
| Peak memory | 624200 kb |
| Host | smart-0433c8d4-cf15-42e0-bc56-f3e604fb4697 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4016170873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.4016170873 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1583809761 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 24963793195 ps |
| CPU time | 2842.85 seconds |
| Started | Jul 20 07:53:42 PM PDT 24 |
| Finished | Jul 20 08:41:06 PM PDT 24 |
| Peak memory | 620496 kb |
| Host | smart-a4a8ed8f-7fd4-4c62-94a2-d48e2fd5749f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1583809761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.1583809761 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3079557073 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 34949218505 ps |
| CPU time | 3069.87 seconds |
| Started | Jul 20 07:56:02 PM PDT 24 |
| Finished | Jul 20 08:47:13 PM PDT 24 |
| Peak memory | 621364 kb |
| Host | smart-e36ea0ee-aa6a-4d32-9ded-bcb18fb68cb6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3079557073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3079557073 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1523806693 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 39194705243 ps |
| CPU time | 2876.49 seconds |
| Started | Jul 20 07:57:15 PM PDT 24 |
| Finished | Jul 20 08:45:12 PM PDT 24 |
| Peak memory | 621708 kb |
| Host | smart-04257772-b042-4f8c-b3fa-c59e0d7abdeb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523806693 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1523806693 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3215733566 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 14966721528 ps |
| CPU time | 3713.4 seconds |
| Started | Jul 20 08:00:16 PM PDT 24 |
| Finished | Jul 20 09:02:11 PM PDT 24 |
| Peak memory | 610024 kb |
| Host | smart-8da32bcc-218c-4c45-8095-8148123dd09f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215733566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3215733566 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1300809144 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 14640798392 ps |
| CPU time | 4193.13 seconds |
| Started | Jul 20 07:58:43 PM PDT 24 |
| Finished | Jul 20 09:08:37 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-1464cb60-ee19-4338-8595-2a7708c1768d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300809144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1300809144 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2310413715 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 15055334160 ps |
| CPU time | 4345.3 seconds |
| Started | Jul 20 08:01:44 PM PDT 24 |
| Finished | Jul 20 09:14:10 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-0af499d1-a30d-4d66-a442-dda83461d7a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310413715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2310413715 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.2144518379 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 26255296024 ps |
| CPU time | 7603.71 seconds |
| Started | Jul 20 07:57:02 PM PDT 24 |
| Finished | Jul 20 10:03:46 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-e1a9d2f7-230d-46a3-9a86-bfd6a94b7ec1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144518379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2144518379 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2691102704 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 14768240756 ps |
| CPU time | 3728.78 seconds |
| Started | Jul 20 07:58:08 PM PDT 24 |
| Finished | Jul 20 09:00:18 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-6d9e96a4-e428-4496-b058-f67f38fb1a95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691102704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2691102704 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.260765937 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 27832468020 ps |
| CPU time | 3802.67 seconds |
| Started | Jul 20 07:58:31 PM PDT 24 |
| Finished | Jul 20 09:01:55 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-12fbb14e-ee4e-41b5-b714-e6275836e37e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260765937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.260765937 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.199129288 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 23326454115 ps |
| CPU time | 5890.26 seconds |
| Started | Jul 20 07:56:25 PM PDT 24 |
| Finished | Jul 20 09:34:36 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-6ff14e43-6b15-41dd-bd0a-03e34e948490 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=199129288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.199129288 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1836098142 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 23665772412 ps |
| CPU time | 5869.68 seconds |
| Started | Jul 20 08:00:48 PM PDT 24 |
| Finished | Jul 20 09:38:39 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-20a00163-9d1b-4df4-aeae-d8b2381d0618 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1836098142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1836098142 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2854284955 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 23438770176 ps |
| CPU time | 6516.45 seconds |
| Started | Jul 20 07:58:26 PM PDT 24 |
| Finished | Jul 20 09:47:04 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-02723f17-000e-41f0-b416-4bcc5c74a349 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2854284955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2854284955 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1658144439 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 22638949642 ps |
| CPU time | 5193.82 seconds |
| Started | Jul 20 07:58:46 PM PDT 24 |
| Finished | Jul 20 09:25:21 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-ac795412-0aa5-41bc-9895-7f9b7ef5d4ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1658144439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.1658144439 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.169908574 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 18230277500 ps |
| CPU time | 4323.73 seconds |
| Started | Jul 20 07:58:33 PM PDT 24 |
| Finished | Jul 20 09:10:37 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-d141e8f6-1e2e-49f5-9ea5-e25791bf0fdd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=169908574 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_ bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alwa ys_a_bad_b_bad_test_unlocked0.169908574 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2126763767 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 14128753107 ps |
| CPU time | 3976.82 seconds |
| Started | Jul 20 07:59:58 PM PDT 24 |
| Finished | Jul 20 09:06:15 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-5dbb8d03-40f7-4c93-9eed-5029b4c9bc5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126763767 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2126763767 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.532258804 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 15413958330 ps |
| CPU time | 3335.16 seconds |
| Started | Jul 20 07:59:54 PM PDT 24 |
| Finished | Jul 20 08:55:30 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-a75692dc-f996-4e41-8d96-896f8db31424 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532258804 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.532258804 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.812447448 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 13931252993 ps |
| CPU time | 3160.95 seconds |
| Started | Jul 20 07:59:05 PM PDT 24 |
| Finished | Jul 20 08:51:47 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-0de36f2a-b655-467c-be5c-150d5dec40db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812447448 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.812447448 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3864034458 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 14190528087 ps |
| CPU time | 3724.9 seconds |
| Started | Jul 20 07:57:08 PM PDT 24 |
| Finished | Jul 20 08:59:14 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-754bd9e1-23a0-4dea-97f1-3a4b4ad48c87 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864034458 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3864034458 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3439726227 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 11305997450 ps |
| CPU time | 2891.21 seconds |
| Started | Jul 20 07:57:43 PM PDT 24 |
| Finished | Jul 20 08:45:55 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-9cc36091-652e-402d-a68c-310b072d4bbd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439726227 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3439726227 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3071539798 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 15197836005 ps |
| CPU time | 3712.25 seconds |
| Started | Jul 20 07:57:10 PM PDT 24 |
| Finished | Jul 20 08:59:03 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-5538dbfe-732b-4ee7-b554-18fb00f418e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071539798 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.3071539798 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3264082634 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 14084915244 ps |
| CPU time | 3850.39 seconds |
| Started | Jul 20 07:57:03 PM PDT 24 |
| Finished | Jul 20 09:01:14 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-579f831b-4715-417c-893a-f9b7e5cb79fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264082634 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3264082634 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3892099076 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 15076003008 ps |
| CPU time | 4096.3 seconds |
| Started | Jul 20 07:58:13 PM PDT 24 |
| Finished | Jul 20 09:06:30 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-7cf4b239-e472-452f-bf83-32024f212df6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892099076 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3892099076 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2528716268 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 14962520918 ps |
| CPU time | 3438.88 seconds |
| Started | Jul 20 07:58:27 PM PDT 24 |
| Finished | Jul 20 08:55:47 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-5feccce2-1b45-4cc4-b92f-f55998411663 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528716268 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2528716268 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1986793368 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 10518831540 ps |
| CPU time | 2767.7 seconds |
| Started | Jul 20 07:56:10 PM PDT 24 |
| Finished | Jul 20 08:42:18 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-aa7d29cb-fb75-4068-b0b1-20df6efd2d56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986793368 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1986793368 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.2851287605 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 14664146568 ps |
| CPU time | 3248.27 seconds |
| Started | Jul 20 07:58:59 PM PDT 24 |
| Finished | Jul 20 08:53:08 PM PDT 24 |
| Peak memory | 610072 kb |
| Host | smart-233eeb39-8d48-4493-92fe-87fa39619f71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2851287605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2851287605 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.1466287310 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 16906646600 ps |
| CPU time | 3666.37 seconds |
| Started | Jul 20 08:00:44 PM PDT 24 |
| Finished | Jul 20 09:01:51 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-4d1f5c10-6a0a-41ab-8c0c-0cb3f14a4c1a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466287310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.1466287310 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.455413607 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 3775790312 ps |
| CPU time | 748.28 seconds |
| Started | Jul 20 07:54:06 PM PDT 24 |
| Finished | Jul 20 08:06:35 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-2ff43bf9-2628-498b-9454-6aa8412782b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455413607 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.455413607 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.1171812669 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 4514608097 ps |
| CPU time | 238.09 seconds |
| Started | Jul 20 07:54:37 PM PDT 24 |
| Finished | Jul 20 07:58:35 PM PDT 24 |
| Peak memory | 623888 kb |
| Host | smart-e6f1f376-5e19-4d16-bdab-aa04af40d7ab |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1171812669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.1171812669 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3837919309 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 2322059482 ps |
| CPU time | 106.9 seconds |
| Started | Jul 20 07:53:11 PM PDT 24 |
| Finished | Jul 20 07:54:58 PM PDT 24 |
| Peak memory | 617016 kb |
| Host | smart-34b2b187-a2cb-4e3a-9bc3-6482ff3047dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837919309 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3837919309 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.754474044 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13492077343 ps |
| CPU time | 1488.73 seconds |
| Started | Jul 20 07:55:09 PM PDT 24 |
| Finished | Jul 20 08:19:58 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-468d4c8e-8926-484e-b306-e8ca6e300275 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754474044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.754474044 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3962336531 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4042416250 ps |
| CPU time | 383.46 seconds |
| Started | Jul 20 08:02:27 PM PDT 24 |
| Finished | Jul 20 08:08:51 PM PDT 24 |
| Peak memory | 619884 kb |
| Host | smart-a1d5d164-0eb4-405d-beb0-996c24725e3d |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 962336531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3962336531 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1129769553 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2831182760 ps |
| CPU time | 358.17 seconds |
| Started | Jul 20 07:58:16 PM PDT 24 |
| Finished | Jul 20 08:04:15 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-e2e55fd3-b690-4413-8c59-ef5a38216e49 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1129769553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1129769553 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2077752046 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 19156714368 ps |
| CPU time | 800.13 seconds |
| Started | Jul 20 07:58:08 PM PDT 24 |
| Finished | Jul 20 08:11:29 PM PDT 24 |
| Peak memory | 618896 kb |
| Host | smart-145242fe-e8f0-4fda-80e7-60f544eb2d88 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2077752046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2077752046 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.988677673 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 2499966276 ps |
| CPU time | 313.2 seconds |
| Started | Jul 20 07:59:32 PM PDT 24 |
| Finished | Jul 20 08:04:46 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-fd8fe0a8-00c2-4cf0-846a-49dbd2fa17a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988677673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.988677673 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.6409815 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 3131640587 ps |
| CPU time | 247.65 seconds |
| Started | Jul 20 07:59:08 PM PDT 24 |
| Finished | Jul 20 08:03:16 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-b2636a41-e93c-4167-bb36-b020f7cf08f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6409 815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.6409815 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3622364800 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 2653785394 ps |
| CPU time | 239.74 seconds |
| Started | Jul 20 08:05:19 PM PDT 24 |
| Finished | Jul 20 08:09:19 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-a324aff9-f49f-46b4-912b-ecd76cc24df1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622364800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3622364800 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.3269240725 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 2144851456 ps |
| CPU time | 230.54 seconds |
| Started | Jul 20 07:59:00 PM PDT 24 |
| Finished | Jul 20 08:02:51 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-25cb0fcb-c1d3-4e8d-900b-c6cb88e4db53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269240725 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.3269240725 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.2853952489 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 2676443996 ps |
| CPU time | 234.26 seconds |
| Started | Jul 20 08:01:25 PM PDT 24 |
| Finished | Jul 20 08:05:20 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-cd06fc09-6ef9-4ddb-9aea-be14fe3c93c6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853952489 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.2853952489 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.605509523 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 3129957802 ps |
| CPU time | 320.84 seconds |
| Started | Jul 20 07:58:07 PM PDT 24 |
| Finished | Jul 20 08:03:28 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-50ce4d6a-6dd0-40ff-9e0e-c9fbde280b3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605509523 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.605509523 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1175688038 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 2997676510 ps |
| CPU time | 365.35 seconds |
| Started | Jul 20 08:08:17 PM PDT 24 |
| Finished | Jul 20 08:14:23 PM PDT 24 |
| Peak memory | 609260 kb |
| Host | smart-2e77da22-b9ad-4e56-869c-92dcdc56bdfc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175688038 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1175688038 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2875615446 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 4023378493 ps |
| CPU time | 386.17 seconds |
| Started | Jul 20 08:01:04 PM PDT 24 |
| Finished | Jul 20 08:07:30 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-3eaeb90c-1c7f-4b29-8a8b-29a1ffbfecec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2875615446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.2875615446 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.205056940 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 5568332746 ps |
| CPU time | 524.17 seconds |
| Started | Jul 20 07:57:14 PM PDT 24 |
| Finished | Jul 20 08:05:59 PM PDT 24 |
| Peak memory | 619440 kb |
| Host | smart-6ba7353e-dd60-4c6e-8bfc-1ec1982964cc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=205056940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.205056940 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3761272317 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 6127562808 ps |
| CPU time | 1305.02 seconds |
| Started | Jul 20 08:01:18 PM PDT 24 |
| Finished | Jul 20 08:23:04 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-50bb342e-aba8-41c5-a459-7c55dd6fcf64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3761272317 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3761272317 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.279483344 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6841823786 ps |
| CPU time | 1559.45 seconds |
| Started | Jul 20 07:58:18 PM PDT 24 |
| Finished | Jul 20 08:24:18 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-3d9063ea-4fba-49ea-ac0e-93760615dfce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279483344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.279483344 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2095740268 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 10901415476 ps |
| CPU time | 1220.87 seconds |
| Started | Jul 20 08:01:06 PM PDT 24 |
| Finished | Jul 20 08:21:28 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-28d25225-ce10-4a1e-b809-74d35255e6eb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095740268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2095740268 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2237450154 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 7180999220 ps |
| CPU time | 1438.02 seconds |
| Started | Jul 20 08:03:07 PM PDT 24 |
| Finished | Jul 20 08:27:05 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-91f9bd8e-6aa9-4ef2-9550-a565c3328513 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2237450154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.2237450154 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3908515033 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 4953699018 ps |
| CPU time | 576.5 seconds |
| Started | Jul 20 07:59:06 PM PDT 24 |
| Finished | Jul 20 08:08:43 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-33c103e4-e4ee-4290-ace5-230f49dab51d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3908515033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.3908515033 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2020342479 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 255479714002 ps |
| CPU time | 11473.4 seconds |
| Started | Jul 20 08:00:45 PM PDT 24 |
| Finished | Jul 20 11:12:00 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-c164fcb6-f60d-49e8-85ca-961cd13dfa01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020342479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2020342479 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.2238657943 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3325079780 ps |
| CPU time | 393.06 seconds |
| Started | Jul 20 07:58:14 PM PDT 24 |
| Finished | Jul 20 08:04:47 PM PDT 24 |
| Peak memory | 609240 kb |
| Host | smart-fcbf85b6-8147-4e01-b3c0-6e40caf11dc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238657943 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.2238657943 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2359970913 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3873341210 ps |
| CPU time | 562.47 seconds |
| Started | Jul 20 08:00:05 PM PDT 24 |
| Finished | Jul 20 08:09:28 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-bb0200aa-c8af-42b9-8a37-c0d0223a5f84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359970913 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2359970913 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4050545524 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7134670728 ps |
| CPU time | 478.68 seconds |
| Started | Jul 20 07:57:18 PM PDT 24 |
| Finished | Jul 20 08:05:17 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-0a3e345a-236d-4dcf-976e-e3be793be82e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4050545524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4050545524 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1431572953 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3512681888 ps |
| CPU time | 383.46 seconds |
| Started | Jul 20 08:07:01 PM PDT 24 |
| Finished | Jul 20 08:13:27 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-e3f78182-2312-4fdf-a1cf-0d8a94436a23 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431572953 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.1431572953 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2539408869 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 9701822632 ps |
| CPU time | 898.31 seconds |
| Started | Jul 20 08:00:48 PM PDT 24 |
| Finished | Jul 20 08:15:47 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-75cd7fa1-7333-45ea-ad0e-fc20fd090bc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2539408869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2539408869 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2345389419 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 5121232618 ps |
| CPU time | 556.81 seconds |
| Started | Jul 20 07:58:59 PM PDT 24 |
| Finished | Jul 20 08:08:17 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-81aa6df4-0d9d-459f-a67f-07cb27c35f0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2345389419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2345389419 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.3224420587 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 7571544260 ps |
| CPU time | 1197.02 seconds |
| Started | Jul 20 08:02:35 PM PDT 24 |
| Finished | Jul 20 08:22:32 PM PDT 24 |
| Peak memory | 617048 kb |
| Host | smart-9cfee6eb-0d3c-48ae-ac9d-468f1e52a61e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224420587 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.3224420587 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2030097315 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 25487841278 ps |
| CPU time | 3760.19 seconds |
| Started | Jul 20 08:05:50 PM PDT 24 |
| Finished | Jul 20 09:08:31 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-0b04bf33-06df-4370-8b03-fe93ae96215d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030097315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.2030097315 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2440269343 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 5169972692 ps |
| CPU time | 478.23 seconds |
| Started | Jul 20 08:05:51 PM PDT 24 |
| Finished | Jul 20 08:13:49 PM PDT 24 |
| Peak memory | 621260 kb |
| Host | smart-96fceb9a-9624-484b-9d94-0beea23c8dd0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2440269343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.2440269343 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.699666037 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 3761858316 ps |
| CPU time | 621.36 seconds |
| Started | Jul 20 08:02:23 PM PDT 24 |
| Finished | Jul 20 08:12:45 PM PDT 24 |
| Peak memory | 613988 kb |
| Host | smart-855d9bc0-15bf-454d-813e-7a8a4f61182b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699666037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.699666037 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3499258380 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3924699280 ps |
| CPU time | 769.42 seconds |
| Started | Jul 20 08:02:15 PM PDT 24 |
| Finished | Jul 20 08:15:05 PM PDT 24 |
| Peak memory | 614036 kb |
| Host | smart-6476516e-89a7-4c24-b060-9f12e0ebfecc |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499258380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3499258380 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.42773922 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3626309616 ps |
| CPU time | 697.89 seconds |
| Started | Jul 20 08:03:17 PM PDT 24 |
| Finished | Jul 20 08:14:56 PM PDT 24 |
| Peak memory | 612880 kb |
| Host | smart-7a39d618-5178-42c3-b348-53c0a97c1c1e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42773922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.42773922 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1459482460 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 3894431884 ps |
| CPU time | 610.99 seconds |
| Started | Jul 20 08:01:40 PM PDT 24 |
| Finished | Jul 20 08:11:51 PM PDT 24 |
| Peak memory | 611856 kb |
| Host | smart-a61b8068-46c3-483a-8505-4998c42a6d55 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459482460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.1459482460 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2858391040 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 4811820438 ps |
| CPU time | 571.01 seconds |
| Started | Jul 20 08:01:06 PM PDT 24 |
| Finished | Jul 20 08:10:37 PM PDT 24 |
| Peak memory | 614044 kb |
| Host | smart-aa8c3d24-4f2a-43be-abe9-0b12e842953b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858391040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2858391040 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.399495352 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 4043907320 ps |
| CPU time | 679.43 seconds |
| Started | Jul 20 08:06:04 PM PDT 24 |
| Finished | Jul 20 08:17:24 PM PDT 24 |
| Peak memory | 612656 kb |
| Host | smart-457104d4-63d3-4e07-b53e-3fa707d947b2 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399495352 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.399495352 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.3504680439 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 2994846482 ps |
| CPU time | 202.25 seconds |
| Started | Jul 20 08:06:40 PM PDT 24 |
| Finished | Jul 20 08:10:03 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-27caaea7-a324-4c54-93b6-c8ca2ac7153d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504680439 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.3504680439 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.897961315 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 3494688320 ps |
| CPU time | 492.28 seconds |
| Started | Jul 20 08:04:17 PM PDT 24 |
| Finished | Jul 20 08:12:29 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-cdc923c6-59da-4ac7-82f1-b0ffc2bdf31e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897961315 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.897961315 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1895282247 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2541582204 ps |
| CPU time | 206.85 seconds |
| Started | Jul 20 08:03:14 PM PDT 24 |
| Finished | Jul 20 08:06:41 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-e8bac838-32b8-4245-a3b3-e6477edecb24 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895282247 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1895282247 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2806952375 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 4805437068 ps |
| CPU time | 411.28 seconds |
| Started | Jul 20 08:02:02 PM PDT 24 |
| Finished | Jul 20 08:08:53 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-56d2e363-17fd-4c59-a4bf-9335545a63da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806952375 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2806952375 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2534402119 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 4584404892 ps |
| CPU time | 529.2 seconds |
| Started | Jul 20 08:01:38 PM PDT 24 |
| Finished | Jul 20 08:10:27 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-9fbd27ac-c65e-4bdd-ad75-5528be9dd7ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534402119 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.2534402119 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.423952755 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 4631353882 ps |
| CPU time | 433.99 seconds |
| Started | Jul 20 08:06:08 PM PDT 24 |
| Finished | Jul 20 08:13:22 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-75b0af69-c891-4e68-b1e8-c59baa7a9886 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423952755 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.423952755 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2274443212 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4509970892 ps |
| CPU time | 527.42 seconds |
| Started | Jul 20 08:03:59 PM PDT 24 |
| Finished | Jul 20 08:12:47 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-cb045f89-d114-4e85-aac6-a1993a49df7c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274443212 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.2274443212 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2378593628 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 11411587192 ps |
| CPU time | 1493.99 seconds |
| Started | Jul 20 08:05:44 PM PDT 24 |
| Finished | Jul 20 08:30:38 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-65aea573-4b3d-4744-8a78-2d7b8a4180c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378593628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2378593628 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2157031607 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 3670436700 ps |
| CPU time | 466.06 seconds |
| Started | Jul 20 08:02:13 PM PDT 24 |
| Finished | Jul 20 08:09:59 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-be0d83a9-4a38-4736-83c5-f79c3053b0cd |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157031607 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2157031607 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.837131127 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 4478857950 ps |
| CPU time | 559.87 seconds |
| Started | Jul 20 08:06:50 PM PDT 24 |
| Finished | Jul 20 08:16:10 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-9e6a81a9-4327-4c3d-85f6-7da0d9070080 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837131127 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.837131127 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1828480355 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2933345608 ps |
| CPU time | 321.03 seconds |
| Started | Jul 20 08:05:38 PM PDT 24 |
| Finished | Jul 20 08:11:00 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-74c3f144-0f07-4b3b-9077-629fa4c6340e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828480355 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1828480355 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2764596705 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 28362082208 ps |
| CPU time | 5280.82 seconds |
| Started | Jul 20 07:57:52 PM PDT 24 |
| Finished | Jul 20 09:25:54 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-105eb03c-ab81-4394-b1f5-77d95c2ae385 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764596705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2764596705 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.130275679 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3386830528 ps |
| CPU time | 408.48 seconds |
| Started | Jul 20 07:59:34 PM PDT 24 |
| Finished | Jul 20 08:06:23 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-412a5731-2e23-4fe2-8227-8ac0d04a78d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13027 5679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.130275679 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.3696160476 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 2393312200 ps |
| CPU time | 208.83 seconds |
| Started | Jul 20 08:01:16 PM PDT 24 |
| Finished | Jul 20 08:04:45 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-02e52c59-7bc3-45b6-ab21-574fa6966936 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696160476 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.3696160476 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1842890481 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 6608097534 ps |
| CPU time | 874 seconds |
| Started | Jul 20 07:59:12 PM PDT 24 |
| Finished | Jul 20 08:13:47 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-6f5395e8-a825-4b5e-a062-d243e0aec719 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842890481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1842890481 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.72130443 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3131803274 ps |
| CPU time | 289.27 seconds |
| Started | Jul 20 08:05:21 PM PDT 24 |
| Finished | Jul 20 08:10:11 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-fd6931bc-fba1-4b9e-aa87-d09cded7ddaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72130443 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_smoketest.72130443 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2468363150 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 5974350180 ps |
| CPU time | 934.55 seconds |
| Started | Jul 20 07:55:35 PM PDT 24 |
| Finished | Jul 20 08:11:11 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-37940fb4-fcf9-40b2-8072-fb5596e1906c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2468363150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.2468363150 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.4134193277 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 6241804624 ps |
| CPU time | 1902.21 seconds |
| Started | Jul 20 08:01:02 PM PDT 24 |
| Finished | Jul 20 08:32:45 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-ec7d03d3-e294-4dfc-a57b-57c75004ac44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134193277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.4134193277 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.4002529835 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2905846376 ps |
| CPU time | 523.17 seconds |
| Started | Jul 20 07:59:41 PM PDT 24 |
| Finished | Jul 20 08:08:25 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-099adbbb-31db-4034-9a95-34be7f319d76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002529835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.4002529835 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2448282977 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5592465760 ps |
| CPU time | 897.84 seconds |
| Started | Jul 20 08:02:05 PM PDT 24 |
| Finished | Jul 20 08:17:03 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-13147b90-5c90-4d51-bb1c-8b1dfe986caf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2448282977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.2448282977 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1840836314 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 6741741805 ps |
| CPU time | 1415.25 seconds |
| Started | Jul 20 08:01:42 PM PDT 24 |
| Finished | Jul 20 08:25:18 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-d788bc5b-2581-40f9-b285-6bd7ca3f5e51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840836314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.1840836314 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.3694003914 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 3452494488 ps |
| CPU time | 496.09 seconds |
| Started | Jul 20 07:58:28 PM PDT 24 |
| Finished | Jul 20 08:06:45 PM PDT 24 |
| Peak memory | 615068 kb |
| Host | smart-90266ed1-80b9-47cf-852a-5d1504dfa6b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694003914 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.3694003914 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.4063486145 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 7623772520 ps |
| CPU time | 1860.72 seconds |
| Started | Jul 20 08:00:06 PM PDT 24 |
| Finished | Jul 20 08:31:08 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-63065f26-81a6-4db0-907f-d17c92f65f56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063486145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.4063486145 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.490073979 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 3086069384 ps |
| CPU time | 237.27 seconds |
| Started | Jul 20 08:01:23 PM PDT 24 |
| Finished | Jul 20 08:05:20 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-f600ed27-1959-42b9-8dbb-ec8fa47133c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49 0073979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.490073979 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2085629128 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 7407731140 ps |
| CPU time | 1528.91 seconds |
| Started | Jul 20 07:59:27 PM PDT 24 |
| Finished | Jul 20 08:24:56 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-55e22a66-b054-443f-9271-0b77dcdd9d21 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2085629128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2085629128 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.48421692 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 3504557390 ps |
| CPU time | 599.03 seconds |
| Started | Jul 20 08:06:52 PM PDT 24 |
| Finished | Jul 20 08:16:51 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-b78a19fc-fd8f-4349-9300-8899acca217e |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=48421692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.48421692 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1976045993 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 3071402360 ps |
| CPU time | 276.11 seconds |
| Started | Jul 20 07:55:53 PM PDT 24 |
| Finished | Jul 20 08:00:29 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-223eeb2c-6610-4584-989b-d495ce453e7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976045993 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1976045993 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1524308801 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 2939418772 ps |
| CPU time | 198.34 seconds |
| Started | Jul 20 07:59:24 PM PDT 24 |
| Finished | Jul 20 08:02:43 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-f859e97f-09bc-4a22-b7e5-73e58a6163d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524308801 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1524308801 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.1269287577 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 2516312644 ps |
| CPU time | 232.12 seconds |
| Started | Jul 20 08:00:15 PM PDT 24 |
| Finished | Jul 20 08:04:08 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-08284cf6-ac30-47dc-9c59-e1a4e1535919 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269287577 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.1269287577 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.2392884856 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 2414506376 ps |
| CPU time | 115.78 seconds |
| Started | Jul 20 07:55:41 PM PDT 24 |
| Finished | Jul 20 07:57:39 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-68dc437e-2395-4e43-a5f9-f9cc1a3caeed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392884856 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.2392884856 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3836916175 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 59422575175 ps |
| CPU time | 11527.5 seconds |
| Started | Jul 20 07:54:00 PM PDT 24 |
| Finished | Jul 20 11:06:09 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-63231b02-412c-48d5-946d-a395dfe3b89d |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3836916175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3836916175 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.2439209280 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 4857408386 ps |
| CPU time | 700.55 seconds |
| Started | Jul 20 08:04:34 PM PDT 24 |
| Finished | Jul 20 08:16:15 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-b9af37e6-efd7-438c-88bc-5839b459d1b7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2439209280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2439209280 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2945967463 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 5775023160 ps |
| CPU time | 1144.74 seconds |
| Started | Jul 20 07:58:48 PM PDT 24 |
| Finished | Jul 20 08:17:53 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-303aef0c-b391-4137-b21d-13af8021214e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945967463 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2945967463 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2049691570 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 6804269912 ps |
| CPU time | 1197.34 seconds |
| Started | Jul 20 07:56:46 PM PDT 24 |
| Finished | Jul 20 08:16:44 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-76920d9a-d8ba-43b2-963d-ee51e82b67e7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049691570 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.2049691570 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1155154499 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 7731931834 ps |
| CPU time | 1487.76 seconds |
| Started | Jul 20 08:04:35 PM PDT 24 |
| Finished | Jul 20 08:29:23 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-0fdca9bc-fa70-41e9-baee-788698786ab8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155154499 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1155154499 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1738637703 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 5472814677 ps |
| CPU time | 1102.47 seconds |
| Started | Jul 20 07:54:39 PM PDT 24 |
| Finished | Jul 20 08:13:02 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-67ef9454-ada1-4768-9686-d9457ade30d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738637703 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.1738637703 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2954514951 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 3907400488 ps |
| CPU time | 496.02 seconds |
| Started | Jul 20 07:55:12 PM PDT 24 |
| Finished | Jul 20 08:03:29 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-d1d142d7-a4a7-4ed3-b780-3d055f6d0d79 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954514951 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2954514951 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2936824104 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 4338838020 ps |
| CPU time | 448.77 seconds |
| Started | Jul 20 07:56:08 PM PDT 24 |
| Finished | Jul 20 08:03:37 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-0c9a313d-aaaa-4cca-9a64-11910016e03b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29 36824104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.2936824104 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2625767481 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 5833369850 ps |
| CPU time | 1266.77 seconds |
| Started | Jul 20 08:04:13 PM PDT 24 |
| Finished | Jul 20 08:25:21 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-87bc7a0f-e1aa-4f72-ac47-2499e5905599 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625767481 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.2625767481 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3314922488 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3936168130 ps |
| CPU time | 693.84 seconds |
| Started | Jul 20 07:56:17 PM PDT 24 |
| Finished | Jul 20 08:07:52 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-0c4511a5-338a-4e2a-96c4-6d764adea734 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314922488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3314922488 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.805047048 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 4590527028 ps |
| CPU time | 857.96 seconds |
| Started | Jul 20 08:03:13 PM PDT 24 |
| Finished | Jul 20 08:17:31 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-92d6bb7c-d6b1-4bdb-b4cd-28ba02af6e73 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=805047048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.805047048 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1025205354 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3367724776 ps |
| CPU time | 331.39 seconds |
| Started | Jul 20 08:03:29 PM PDT 24 |
| Finished | Jul 20 08:09:03 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-96dd7553-60d2-438c-9a74-bc9fab3e8ad0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025205 354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.1025205354 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.2540644962 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 17726620720 ps |
| CPU time | 2291.6 seconds |
| Started | Jul 20 07:55:45 PM PDT 24 |
| Finished | Jul 20 08:33:58 PM PDT 24 |
| Peak memory | 614268 kb |
| Host | smart-ca34484f-cd84-47f3-a1dd-4ae5360ca6a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540644962 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2540644962 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2443254505 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 17517624434 ps |
| CPU time | 1826.75 seconds |
| Started | Jul 20 08:03:12 PM PDT 24 |
| Finished | Jul 20 08:33:40 PM PDT 24 |
| Peak memory | 614420 kb |
| Host | smart-b634026d-24b3-4db4-9c3b-6048e8015e9e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2443254505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.2443254505 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3522228691 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 2525439288 ps |
| CPU time | 272.47 seconds |
| Started | Jul 20 08:09:39 PM PDT 24 |
| Finished | Jul 20 08:14:12 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-8d54af41-bc0e-4922-bdf1-ea804002e851 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3522228691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.3522228691 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.2466507119 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 3126404595 ps |
| CPU time | 341.11 seconds |
| Started | Jul 20 08:08:12 PM PDT 24 |
| Finished | Jul 20 08:13:55 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-8e5b1367-3e0c-4571-b1e6-34a68efdd13b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466507119 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.2466507119 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.3801594821 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2730986510 ps |
| CPU time | 361.22 seconds |
| Started | Jul 20 08:01:06 PM PDT 24 |
| Finished | Jul 20 08:07:08 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-1feb5c4a-9382-4d60-b03b-76d03813e3fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801594821 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3801594821 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.1696825780 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2734187104 ps |
| CPU time | 192.52 seconds |
| Started | Jul 20 07:59:13 PM PDT 24 |
| Finished | Jul 20 08:02:26 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-60967d1c-5021-41db-8e36-d42d52d97888 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696825780 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.1696825780 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2308378491 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 2924660740 ps |
| CPU time | 316.96 seconds |
| Started | Jul 20 08:01:39 PM PDT 24 |
| Finished | Jul 20 08:06:57 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-3157b226-66d4-4553-973a-17d603ed838a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308378491 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.2308378491 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.352280774 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 3166822714 ps |
| CPU time | 262.31 seconds |
| Started | Jul 20 08:04:09 PM PDT 24 |
| Finished | Jul 20 08:08:32 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-9baeed27-5f30-4b1d-afdd-b4d72e6dd369 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352280774 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.352280774 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.967482523 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 7656832760 ps |
| CPU time | 1799.63 seconds |
| Started | Jul 20 08:02:33 PM PDT 24 |
| Finished | Jul 20 08:32:33 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-55d9337e-0e82-4827-bbf5-bd7527d5a675 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967482523 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.967482523 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2496652784 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 3039121368 ps |
| CPU time | 348.4 seconds |
| Started | Jul 20 08:00:06 PM PDT 24 |
| Finished | Jul 20 08:05:55 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-335ce061-f923-449a-b81d-5ae218e92b1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496652784 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2496652784 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.370588666 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3244040000 ps |
| CPU time | 348.18 seconds |
| Started | Jul 20 08:05:19 PM PDT 24 |
| Finished | Jul 20 08:11:07 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-d776c0bd-be74-4d20-98bc-cac439534d7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370588666 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_smoketest.370588666 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4055179313 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3672975334 ps |
| CPU time | 554.96 seconds |
| Started | Jul 20 07:55:51 PM PDT 24 |
| Finished | Jul 20 08:05:07 PM PDT 24 |
| Peak memory | 609880 kb |
| Host | smart-e0fdb698-fd66-4260-a984-f10871f095ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055179313 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.4055179313 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4095886821 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 5185282818 ps |
| CPU time | 906.04 seconds |
| Started | Jul 20 07:54:10 PM PDT 24 |
| Finished | Jul 20 08:09:17 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-64dd4805-20b8-445f-b906-7f780602e6f2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095886821 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.4095886821 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1494324945 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 4893351328 ps |
| CPU time | 826.73 seconds |
| Started | Jul 20 07:55:34 PM PDT 24 |
| Finished | Jul 20 08:09:22 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-3cb2d7df-b663-4880-9bef-35104bc19dd2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494324945 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.1494324945 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2137890131 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 6160443796 ps |
| CPU time | 1023.08 seconds |
| Started | Jul 20 07:54:55 PM PDT 24 |
| Finished | Jul 20 08:11:59 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-995c136a-10a5-4949-861a-57efde65b406 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137890131 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2137890131 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.195145873 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 64294743679 ps |
| CPU time | 11607.1 seconds |
| Started | Jul 20 07:56:44 PM PDT 24 |
| Finished | Jul 20 11:10:14 PM PDT 24 |
| Peak memory | 624732 kb |
| Host | smart-ab6790c8-9115-4bd1-8114-89038a57cd72 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=195145873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.195145873 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.180218439 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 9928139452 ps |
| CPU time | 2088.06 seconds |
| Started | Jul 20 08:02:03 PM PDT 24 |
| Finished | Jul 20 08:36:52 PM PDT 24 |
| Peak memory | 617636 kb |
| Host | smart-ffd6866d-a756-4112-9aad-a153d0ee5a45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802 18439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.180218439 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2999280725 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9847592178 ps |
| CPU time | 1872.64 seconds |
| Started | Jul 20 08:01:12 PM PDT 24 |
| Finished | Jul 20 08:32:25 PM PDT 24 |
| Peak memory | 617404 kb |
| Host | smart-603a126b-9050-4808-9f29-cb1d0b231e3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2999280725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.2999280725 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1904743538 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 10758611776 ps |
| CPU time | 1683.81 seconds |
| Started | Jul 20 08:05:15 PM PDT 24 |
| Finished | Jul 20 08:33:20 PM PDT 24 |
| Peak memory | 617412 kb |
| Host | smart-8dfbc31a-04b0-40e6-8134-87e24ab575f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1904743538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1904743538 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2216874437 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 12294062804 ps |
| CPU time | 2555.77 seconds |
| Started | Jul 20 07:59:43 PM PDT 24 |
| Finished | Jul 20 08:42:20 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-74b3aacc-c3d0-4a46-b46e-98d6836f8e44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221687 4437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2216874437 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2826368949 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 6259499436 ps |
| CPU time | 1235.86 seconds |
| Started | Jul 20 08:00:26 PM PDT 24 |
| Finished | Jul 20 08:21:02 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-18a7d70a-9e41-42ec-bce6-4d8941a42b99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28263 68949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2826368949 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2298627377 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 12896008306 ps |
| CPU time | 3782.64 seconds |
| Started | Jul 20 08:00:25 PM PDT 24 |
| Finished | Jul 20 09:03:29 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-d19b73e0-1d02-4b52-9cb3-e1b6dcc261b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22986 27377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.2298627377 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.3423687850 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2985775384 ps |
| CPU time | 291.76 seconds |
| Started | Jul 20 08:01:44 PM PDT 24 |
| Finished | Jul 20 08:06:37 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-c86fb9c7-0a29-48ef-98b8-56247bef1ec6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423687850 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.3423687850 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2140531771 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2629671004 ps |
| CPU time | 263.22 seconds |
| Started | Jul 20 07:59:18 PM PDT 24 |
| Finished | Jul 20 08:03:42 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-22624199-2f09-4f63-9dcf-d572f5a08f01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140531771 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2140531771 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1348985075 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 2568814856 ps |
| CPU time | 287.95 seconds |
| Started | Jul 20 08:02:08 PM PDT 24 |
| Finished | Jul 20 08:06:56 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-a9951bfc-0889-46a1-986a-1b2ab09aa053 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348985075 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1348985075 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.122197375 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 2652747340 ps |
| CPU time | 305.01 seconds |
| Started | Jul 20 07:59:59 PM PDT 24 |
| Finished | Jul 20 08:05:04 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-6ca5e10c-39fc-4e2f-93e4-852f0950215b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122197375 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_kmac_mode_cshake.122197375 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1454036995 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 2541532332 ps |
| CPU time | 374.51 seconds |
| Started | Jul 20 08:02:03 PM PDT 24 |
| Finished | Jul 20 08:08:18 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-87275998-db7c-4283-8bf1-b8175ae68139 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454036995 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1454036995 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3878545598 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3052895735 ps |
| CPU time | 303.8 seconds |
| Started | Jul 20 08:02:41 PM PDT 24 |
| Finished | Jul 20 08:07:45 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-1e7a9986-601a-4698-959f-aebe4014c821 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878545598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3878545598 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3681167301 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 3757124303 ps |
| CPU time | 328.41 seconds |
| Started | Jul 20 08:04:14 PM PDT 24 |
| Finished | Jul 20 08:09:43 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-00a99c22-b347-4b99-a5f2-0daf9efa9b22 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811673 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3681167301 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.668586780 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2577399952 ps |
| CPU time | 384.48 seconds |
| Started | Jul 20 08:04:56 PM PDT 24 |
| Finished | Jul 20 08:11:21 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-5006d0f2-bb1d-4bed-96d5-c43378bafac4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668586780 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_smoketest.668586780 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1253395118 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 2815728824 ps |
| CPU time | 265.34 seconds |
| Started | Jul 20 07:57:53 PM PDT 24 |
| Finished | Jul 20 08:02:20 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-33e49de8-81c3-440a-8f9b-08f75eb54533 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253395118 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.1253395118 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.922710859 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4460031640 ps |
| CPU time | 619.87 seconds |
| Started | Jul 20 08:01:45 PM PDT 24 |
| Finished | Jul 20 08:12:06 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-c0b3b716-9326-416f-a4d4-b47034852b64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=922710859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.922710859 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1880862450 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2617362161 ps |
| CPU time | 177.25 seconds |
| Started | Jul 20 07:58:15 PM PDT 24 |
| Finished | Jul 20 08:01:14 PM PDT 24 |
| Peak memory | 620212 kb |
| Host | smart-c65ad4f0-1975-41e3-803b-f71bd213d6df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808624 50 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.1880862450 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3079593619 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 5428613994 ps |
| CPU time | 516.04 seconds |
| Started | Jul 20 07:57:55 PM PDT 24 |
| Finished | Jul 20 08:06:31 PM PDT 24 |
| Peak memory | 621336 kb |
| Host | smart-b3c40a2f-de6d-4676-ba23-6da39d43ac69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079593619 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3079593619 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.589807003 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2738793447 ps |
| CPU time | 117.32 seconds |
| Started | Jul 20 08:00:16 PM PDT 24 |
| Finished | Jul 20 08:02:14 PM PDT 24 |
| Peak memory | 616844 kb |
| Host | smart-c5f3b5d2-f3b5-4a6d-ada5-d180b66abf12 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=589807003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.589807003 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2430435490 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2722599116 ps |
| CPU time | 110.52 seconds |
| Started | Jul 20 07:57:44 PM PDT 24 |
| Finished | Jul 20 07:59:34 PM PDT 24 |
| Peak memory | 617820 kb |
| Host | smart-13f4638c-55b4-43c7-9224-bc37aa7e3144 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430435490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2430435490 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1600623047 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 45771075752 ps |
| CPU time | 5729.24 seconds |
| Started | Jul 20 07:57:05 PM PDT 24 |
| Finished | Jul 20 09:32:36 PM PDT 24 |
| Peak memory | 619972 kb |
| Host | smart-95a6240b-69d2-40f1-b80d-03b338832bd0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600623047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.1600623047 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3411081669 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 50399551121 ps |
| CPU time | 6158.31 seconds |
| Started | Jul 20 07:56:09 PM PDT 24 |
| Finished | Jul 20 09:38:48 PM PDT 24 |
| Peak memory | 619416 kb |
| Host | smart-5c8c25cd-4d2d-4298-bb4d-31d0caead535 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411081669 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.3411081669 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3571379056 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 11517032216 ps |
| CPU time | 1176.2 seconds |
| Started | Jul 20 07:57:16 PM PDT 24 |
| Finished | Jul 20 08:16:53 PM PDT 24 |
| Peak memory | 620004 kb |
| Host | smart-15b4cf77-562b-4b86-9be7-808af8005b7b |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571379056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.3571379056 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3029865984 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 48779507060 ps |
| CPU time | 5622 seconds |
| Started | Jul 20 07:57:08 PM PDT 24 |
| Finished | Jul 20 09:30:51 PM PDT 24 |
| Peak memory | 620264 kb |
| Host | smart-4b43df1c-02c0-4c67-9574-db9afccef820 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029865984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.3029865984 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3407715363 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 29994448046 ps |
| CPU time | 2168.83 seconds |
| Started | Jul 20 07:59:15 PM PDT 24 |
| Finished | Jul 20 08:35:25 PM PDT 24 |
| Peak memory | 620928 kb |
| Host | smart-f597336c-67e9-4ffd-aaa9-6a3b28b95940 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3407715363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3407715363 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2168769618 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 16894513544 ps |
| CPU time | 3837.16 seconds |
| Started | Jul 20 08:01:04 PM PDT 24 |
| Finished | Jul 20 09:05:02 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-6499ad5e-578b-429f-b871-04a916e09441 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2168769618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.2168769618 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1330448312 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 19054286877 ps |
| CPU time | 3999.65 seconds |
| Started | Jul 20 08:00:37 PM PDT 24 |
| Finished | Jul 20 09:07:17 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-acc65175-cfd4-4a5b-ba00-1cbf28f1f760 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1330448312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1330448312 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.225909748 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 25232139433 ps |
| CPU time | 3696.71 seconds |
| Started | Jul 20 08:04:06 PM PDT 24 |
| Finished | Jul 20 09:05:44 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-aa26e413-5270-4f66-bf74-4a115e3ac87e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225909748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.225909748 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3731785320 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4246235960 ps |
| CPU time | 507.93 seconds |
| Started | Jul 20 07:58:37 PM PDT 24 |
| Finished | Jul 20 08:07:06 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-fee10a4b-53b7-4487-866a-884358db4825 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731785320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3731785320 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.3519682427 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 6375897850 ps |
| CPU time | 1066.26 seconds |
| Started | Jul 20 07:59:47 PM PDT 24 |
| Finished | Jul 20 08:17:33 PM PDT 24 |
| Peak memory | 610352 kb |
| Host | smart-1d5858b0-d280-4cce-8b35-c1d1c3d1181b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3519682427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.3519682427 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2028673921 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 10898631156 ps |
| CPU time | 2343.77 seconds |
| Started | Jul 20 08:06:50 PM PDT 24 |
| Finished | Jul 20 08:45:54 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-a8683897-dcb3-4d44-9b2e-4b4cc743c267 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028673921 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2028673921 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2250002453 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3064638447 ps |
| CPU time | 277.23 seconds |
| Started | Jul 20 07:56:53 PM PDT 24 |
| Finished | Jul 20 08:01:31 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-73ba0f2d-99a1-4ff0-bd60-add1a1011094 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250002453 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2250002453 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.610395576 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 8331308840 ps |
| CPU time | 1471.84 seconds |
| Started | Jul 20 07:56:44 PM PDT 24 |
| Finished | Jul 20 08:21:16 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-3129e864-8a37-4194-b999-8943c67b1b81 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=610395576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.610395576 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3936375050 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 8258442232 ps |
| CPU time | 1451.95 seconds |
| Started | Jul 20 07:57:18 PM PDT 24 |
| Finished | Jul 20 08:21:31 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-19cf1c88-a844-4167-ae97-71930752bac4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3936375050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.3936375050 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4090986180 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 7524372844 ps |
| CPU time | 1224.57 seconds |
| Started | Jul 20 07:55:18 PM PDT 24 |
| Finished | Jul 20 08:15:43 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-cd0d9a53-f2c3-4d51-be8e-24958c848ab2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4090986180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4090986180 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1801127666 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 4277542708 ps |
| CPU time | 640.75 seconds |
| Started | Jul 20 07:55:39 PM PDT 24 |
| Finished | Jul 20 08:06:20 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-501c4762-9cb6-473a-8765-4c0800b2e3ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1801127666 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1801127666 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3343087098 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3087144870 ps |
| CPU time | 283.46 seconds |
| Started | Jul 20 08:05:53 PM PDT 24 |
| Finished | Jul 20 08:10:37 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-f897175a-dd48-4a2c-ad06-cda84d662480 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343087098 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3343087098 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.1678618248 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3142523758 ps |
| CPU time | 292.44 seconds |
| Started | Jul 20 08:03:12 PM PDT 24 |
| Finished | Jul 20 08:08:05 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-de360026-5755-4994-ad12-bee033b88df7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678618248 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.1678618248 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.4041322686 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4234391272 ps |
| CPU time | 675.1 seconds |
| Started | Jul 20 08:03:23 PM PDT 24 |
| Finished | Jul 20 08:14:39 PM PDT 24 |
| Peak memory | 609020 kb |
| Host | smart-96ec0154-b5f0-46fc-b10f-e1c82d477eb9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041322686 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.4041322686 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1392073947 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 25613010256 ps |
| CPU time | 1897.1 seconds |
| Started | Jul 20 08:01:23 PM PDT 24 |
| Finished | Jul 20 08:33:00 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-f19e9c75-34a4-4ba4-9ede-34158edf9a26 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139 2073947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1392073947 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3446589468 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 14918837591 ps |
| CPU time | 1724.68 seconds |
| Started | Jul 20 08:00:50 PM PDT 24 |
| Finished | Jul 20 08:29:36 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-97bb26fb-5b33-41c5-b72f-2c04008a289c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3446589468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3446589468 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1431231000 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 23607170828 ps |
| CPU time | 1824.28 seconds |
| Started | Jul 20 08:02:12 PM PDT 24 |
| Finished | Jul 20 08:32:37 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-843394cd-5873-4a88-b6e8-615baa8fd5dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1431231000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1431231000 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3921846231 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 10871295318 ps |
| CPU time | 824.93 seconds |
| Started | Jul 20 07:56:03 PM PDT 24 |
| Finished | Jul 20 08:09:48 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-d38de628-96d0-4566-bd12-5595ff9b3e63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921846231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.3921846231 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.178021482 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 8361278792 ps |
| CPU time | 500.1 seconds |
| Started | Jul 20 07:57:44 PM PDT 24 |
| Finished | Jul 20 08:06:04 PM PDT 24 |
| Peak memory | 617180 kb |
| Host | smart-7b712628-cd78-4ad7-a3b1-745e5cdcf91e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=178021482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.178021482 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.306626568 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 7960530662 ps |
| CPU time | 476.15 seconds |
| Started | Jul 20 07:56:02 PM PDT 24 |
| Finished | Jul 20 08:03:58 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-e3a292a0-7d9f-4a72-a504-2b287b1458e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306626568 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.306626568 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.264918647 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 4060253242 ps |
| CPU time | 533.67 seconds |
| Started | Jul 20 07:58:04 PM PDT 24 |
| Finished | Jul 20 08:06:58 PM PDT 24 |
| Peak memory | 616112 kb |
| Host | smart-3655822a-c3c5-4c46-816e-29c966e93c12 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=264918647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.264918647 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1148899410 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 12906457434 ps |
| CPU time | 1438.99 seconds |
| Started | Jul 20 07:57:19 PM PDT 24 |
| Finished | Jul 20 08:21:18 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-172ec82c-7b48-414a-ba12-b8d77164a587 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148899410 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1148899410 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.213745634 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6822755634 ps |
| CPU time | 438.35 seconds |
| Started | Jul 20 08:01:51 PM PDT 24 |
| Finished | Jul 20 08:09:10 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-9f48561d-9402-4f80-ad70-11e2c806f3e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213745634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.213745634 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3052728134 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 5147488789 ps |
| CPU time | 468.26 seconds |
| Started | Jul 20 07:56:06 PM PDT 24 |
| Finished | Jul 20 08:03:55 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-a859aae2-e4b6-4f99-855e-5558c9d334eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052728134 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.3052728134 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2413620631 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 21586959899 ps |
| CPU time | 2233.7 seconds |
| Started | Jul 20 07:56:23 PM PDT 24 |
| Finished | Jul 20 08:33:37 PM PDT 24 |
| Peak memory | 611300 kb |
| Host | smart-c48c38c8-88fc-4036-9f61-4f36b996796f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2413620631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2413620631 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2919669207 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 22414814732 ps |
| CPU time | 2008.2 seconds |
| Started | Jul 20 08:02:32 PM PDT 24 |
| Finished | Jul 20 08:36:01 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-9ae03fea-221d-4625-8ce8-daf9e196f5e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2919669207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2919669207 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4157368361 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 25584793840 ps |
| CPU time | 3284.1 seconds |
| Started | Jul 20 08:01:20 PM PDT 24 |
| Finished | Jul 20 08:56:05 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-38c2a206-32ac-4901-94e6-1f2f0af8e91b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157368361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.4157368361 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2184204344 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6791568824 ps |
| CPU time | 463.63 seconds |
| Started | Jul 20 08:02:30 PM PDT 24 |
| Finished | Jul 20 08:10:14 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-73c5bb9d-e8b7-4d26-a62a-bf0659b82e60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2184204344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2184204344 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1431736250 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 2754263142 ps |
| CPU time | 296.81 seconds |
| Started | Jul 20 07:56:55 PM PDT 24 |
| Finished | Jul 20 08:01:52 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-46e6d281-7364-4149-9c71-47f5170dfa2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431736250 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.1431736250 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2418977337 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 5111732950 ps |
| CPU time | 311.93 seconds |
| Started | Jul 20 07:58:37 PM PDT 24 |
| Finished | Jul 20 08:03:50 PM PDT 24 |
| Peak memory | 617280 kb |
| Host | smart-c04a5e51-6ae1-44a2-ad7c-363f62d6a560 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2418977337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.2418977337 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.258505851 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 4871412722 ps |
| CPU time | 456.04 seconds |
| Started | Jul 20 08:00:31 PM PDT 24 |
| Finished | Jul 20 08:08:08 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-74195920-2d2d-41e1-951a-d90296a687c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25850585 1 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.258505851 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.673737240 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 6783475200 ps |
| CPU time | 424.03 seconds |
| Started | Jul 20 08:02:49 PM PDT 24 |
| Finished | Jul 20 08:09:53 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-63fda1ed-5e95-49c5-8b1d-34146574a375 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=673737240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.673737240 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1326799853 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 6244298904 ps |
| CPU time | 613.22 seconds |
| Started | Jul 20 08:06:13 PM PDT 24 |
| Finished | Jul 20 08:16:26 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-5b5d6aa3-71f7-4f17-8065-0b8d7f7d3b69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326799853 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.1326799853 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.190172844 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 7453870800 ps |
| CPU time | 1201.78 seconds |
| Started | Jul 20 07:57:42 PM PDT 24 |
| Finished | Jul 20 08:17:44 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-76afedf4-12a1-4f48-8914-f0f4dde33e1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190172844 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.190172844 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1526006517 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 5889773808 ps |
| CPU time | 670.2 seconds |
| Started | Jul 20 07:57:46 PM PDT 24 |
| Finished | Jul 20 08:08:57 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-b4523f0f-3aae-44fa-bfed-d840125a5845 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526006517 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1526006517 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.510456321 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5201581512 ps |
| CPU time | 446.69 seconds |
| Started | Jul 20 08:05:44 PM PDT 24 |
| Finished | Jul 20 08:13:11 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-3191624c-1f42-4187-bd2e-f5a85ed5241f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510456321 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.510456321 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1319398932 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 4968476708 ps |
| CPU time | 711.81 seconds |
| Started | Jul 20 08:01:13 PM PDT 24 |
| Finished | Jul 20 08:13:06 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-2f651815-4cb1-46b5-9538-39a064a454bf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131 9398932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1319398932 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4240526080 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 9819043832 ps |
| CPU time | 656.03 seconds |
| Started | Jul 20 08:02:43 PM PDT 24 |
| Finished | Jul 20 08:13:40 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-50c0f077-1156-4ffe-b0f4-2ed742045031 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240526080 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.4240526080 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.785331536 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 5159488068 ps |
| CPU time | 626.23 seconds |
| Started | Jul 20 07:57:31 PM PDT 24 |
| Finished | Jul 20 08:07:58 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-c2fb3470-a09c-42bd-b7ed-fc88477f39de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785331536 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.785331536 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1621132125 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 5415482664 ps |
| CPU time | 701.98 seconds |
| Started | Jul 20 07:55:51 PM PDT 24 |
| Finished | Jul 20 08:07:34 PM PDT 24 |
| Peak memory | 641524 kb |
| Host | smart-feed3855-151a-4063-8a03-149464500695 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1621132125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1621132125 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3589903636 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2150645160 ps |
| CPU time | 170.73 seconds |
| Started | Jul 20 08:06:52 PM PDT 24 |
| Finished | Jul 20 08:09:43 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-0c8b8e00-099b-4710-8c0a-66697bcb5d15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589903636 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3589903636 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3949719639 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3868402740 ps |
| CPU time | 562.74 seconds |
| Started | Jul 20 07:57:54 PM PDT 24 |
| Finished | Jul 20 08:07:18 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-1b72f4cf-3ab7-41c9-bc69-01eb1eeeb2e3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949719639 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3949719639 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.7534360 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 2691113480 ps |
| CPU time | 251.73 seconds |
| Started | Jul 20 07:57:42 PM PDT 24 |
| Finished | Jul 20 08:01:54 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-26b312b4-4b59-4abc-9911-8bcc223b7fa8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7534360 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_sw_rst.7534360 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3578202040 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2738505608 ps |
| CPU time | 325.91 seconds |
| Started | Jul 20 08:02:48 PM PDT 24 |
| Finished | Jul 20 08:08:15 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-ad1948aa-4d0f-47b7-a65f-edf6a4fd7a16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3578202040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3578202040 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1155010384 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3059980556 ps |
| CPU time | 270.44 seconds |
| Started | Jul 20 08:03:11 PM PDT 24 |
| Finished | Jul 20 08:07:43 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-2c800296-2283-4bb0-8f53-fbe245946959 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155010384 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1155010384 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2751364001 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 5408602600 ps |
| CPU time | 791.66 seconds |
| Started | Jul 20 07:58:14 PM PDT 24 |
| Finished | Jul 20 08:11:27 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-3bdd1cb3-f00d-406e-a979-882298cff471 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513 64001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2751364001 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1477531481 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5986097192 ps |
| CPU time | 1078.36 seconds |
| Started | Jul 20 07:57:22 PM PDT 24 |
| Finished | Jul 20 08:15:21 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-d689cf87-8297-4fca-8918-fb4ed96b2c7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1477531481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1477531481 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.206442360 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 6589647400 ps |
| CPU time | 556.51 seconds |
| Started | Jul 20 08:03:56 PM PDT 24 |
| Finished | Jul 20 08:13:13 PM PDT 24 |
| Peak memory | 620296 kb |
| Host | smart-5abaceb9-2f4e-4d1d-8618-0b9e152b5b6d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206442360 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.206442360 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3384167287 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4199469780 ps |
| CPU time | 475.39 seconds |
| Started | Jul 20 08:02:38 PM PDT 24 |
| Finished | Jul 20 08:10:33 PM PDT 24 |
| Peak memory | 623244 kb |
| Host | smart-ae1c59aa-2d0c-40ea-9091-c07f7910a893 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338416 7287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3384167287 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.127401897 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 3335503896 ps |
| CPU time | 328.75 seconds |
| Started | Jul 20 08:06:07 PM PDT 24 |
| Finished | Jul 20 08:11:37 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-3a0fe2d3-dc11-4ce6-9896-af5521f3f6bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127401897 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.127401897 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.904518250 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2972849720 ps |
| CPU time | 266.71 seconds |
| Started | Jul 20 07:58:43 PM PDT 24 |
| Finished | Jul 20 08:03:10 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-a9d0775e-02ab-47da-8e5f-05e200c87499 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904518250 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_irq.904518250 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3732282384 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2655417450 ps |
| CPU time | 274.88 seconds |
| Started | Jul 20 08:07:11 PM PDT 24 |
| Finished | Jul 20 08:11:46 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-dbee3a4a-2b86-4e87-b16a-793ecaf5d811 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732282384 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.3732282384 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2594062628 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4986290948 ps |
| CPU time | 508.87 seconds |
| Started | Jul 20 08:00:53 PM PDT 24 |
| Finished | Jul 20 08:09:22 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-580b4c3a-c81f-442a-aec9-ecfd31e841f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25940626 28 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.2594062628 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1822128768 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 2933170291 ps |
| CPU time | 247.03 seconds |
| Started | Jul 20 08:03:11 PM PDT 24 |
| Finished | Jul 20 08:07:19 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-dd2f1504-ff97-4dfe-b369-2df07998046b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822128 768 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1822128768 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.554691758 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4934137808 ps |
| CPU time | 333.98 seconds |
| Started | Jul 20 07:55:02 PM PDT 24 |
| Finished | Jul 20 08:00:36 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-2bc76347-9428-4832-aef9-b21255f2877c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554691758 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.554691758 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.392794743 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 9146543554 ps |
| CPU time | 1322.49 seconds |
| Started | Jul 20 07:54:36 PM PDT 24 |
| Finished | Jul 20 08:16:40 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-df1c5e61-92bb-412a-8089-57e531c7f364 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392794743 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.392794743 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.359426558 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 8280647024 ps |
| CPU time | 562.84 seconds |
| Started | Jul 20 08:00:30 PM PDT 24 |
| Finished | Jul 20 08:09:54 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-0b57928d-08b7-476c-84c7-ce3f518fdc57 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359426558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.359426558 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1686845159 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 6909552804 ps |
| CPU time | 687.28 seconds |
| Started | Jul 20 08:02:09 PM PDT 24 |
| Finished | Jul 20 08:13:37 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-b74e7f02-91ac-48b4-a34e-f0952c9791ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686845159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1686845159 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.1845520619 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7695177289 ps |
| CPU time | 937.55 seconds |
| Started | Jul 20 07:56:26 PM PDT 24 |
| Finished | Jul 20 08:12:04 PM PDT 24 |
| Peak memory | 624868 kb |
| Host | smart-5d357ad3-37e7-419c-ab54-b1beed432517 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845520619 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.1845520619 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1781265970 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3451946301 ps |
| CPU time | 587.98 seconds |
| Started | Jul 20 07:55:04 PM PDT 24 |
| Finished | Jul 20 08:04:53 PM PDT 24 |
| Peak memory | 624860 kb |
| Host | smart-6d15fa7b-a0fe-4a77-8d3e-8d65a0ed174c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781265970 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1781265970 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1312048572 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3844299885 ps |
| CPU time | 490.72 seconds |
| Started | Jul 20 07:58:08 PM PDT 24 |
| Finished | Jul 20 08:06:19 PM PDT 24 |
| Peak memory | 618412 kb |
| Host | smart-3904548b-0f86-4a65-9cdb-021cc0ea11c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312048572 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1312048572 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.808579966 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 6669478373 ps |
| CPU time | 701.25 seconds |
| Started | Jul 20 08:01:22 PM PDT 24 |
| Finished | Jul 20 08:13:04 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-0ca811b4-a46d-41cb-8b41-60e6013f9e9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808579966 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.808579966 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3126242805 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4020609208 ps |
| CPU time | 543.19 seconds |
| Started | Jul 20 08:01:25 PM PDT 24 |
| Finished | Jul 20 08:10:29 PM PDT 24 |
| Peak memory | 609652 kb |
| Host | smart-27426e0c-5316-4a35-8c76-714a9ca93af8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126242805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3126242805 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3053869035 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4800190853 ps |
| CPU time | 627.25 seconds |
| Started | Jul 20 08:04:29 PM PDT 24 |
| Finished | Jul 20 08:14:57 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-36907f15-81b9-4cef-b07b-1b9e57396035 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053869035 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3053869035 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1139800411 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 2800073848 ps |
| CPU time | 192.16 seconds |
| Started | Jul 20 08:05:18 PM PDT 24 |
| Finished | Jul 20 08:08:31 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-5965ab95-4c6f-40ab-b32f-1fc7a6dba551 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139800411 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1139800411 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2767946661 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 20010652350 ps |
| CPU time | 3302.2 seconds |
| Started | Jul 20 07:58:40 PM PDT 24 |
| Finished | Jul 20 08:53:43 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-e26a6cd5-e9d5-447e-9e39-834076f5c304 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767946661 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.2767946661 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1845035193 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 5126484083 ps |
| CPU time | 665.13 seconds |
| Started | Jul 20 07:59:08 PM PDT 24 |
| Finished | Jul 20 08:10:15 PM PDT 24 |
| Peak memory | 613660 kb |
| Host | smart-d9e9da35-6806-4c5d-aa34-3d0e43d4107e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845035193 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.1845035193 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3072958865 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 2668012825 ps |
| CPU time | 254.5 seconds |
| Started | Jul 20 07:59:25 PM PDT 24 |
| Finished | Jul 20 08:03:41 PM PDT 24 |
| Peak memory | 612676 kb |
| Host | smart-576dbad5-c9cb-463d-a983-7964ce7bbb3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072958865 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.3072958865 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1852509867 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4109311950 ps |
| CPU time | 429.93 seconds |
| Started | Jul 20 07:59:17 PM PDT 24 |
| Finished | Jul 20 08:06:27 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-5c98be38-692d-4686-a51f-440136494e9e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852509867 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.1852509867 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1043468004 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6045362414 ps |
| CPU time | 520.32 seconds |
| Started | Jul 20 07:57:42 PM PDT 24 |
| Finished | Jul 20 08:06:23 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-b02a0ed2-1702-4cc6-a915-1ad9667da04f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043468004 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1043468004 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1743403347 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 4957562572 ps |
| CPU time | 728.68 seconds |
| Started | Jul 20 07:54:50 PM PDT 24 |
| Finished | Jul 20 08:07:00 PM PDT 24 |
| Peak memory | 618752 kb |
| Host | smart-d8e3d20b-2724-4d01-8155-9a90253f5fb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1743403347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1743403347 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.301906689 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 2584915350 ps |
| CPU time | 202.37 seconds |
| Started | Jul 20 08:06:30 PM PDT 24 |
| Finished | Jul 20 08:09:53 PM PDT 24 |
| Peak memory | 615804 kb |
| Host | smart-1cd9c290-08f1-42c0-91c2-83bd5214435d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301906689 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.301906689 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.67706858 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 4254442756 ps |
| CPU time | 582.15 seconds |
| Started | Jul 20 07:56:13 PM PDT 24 |
| Finished | Jul 20 08:05:56 PM PDT 24 |
| Peak memory | 622444 kb |
| Host | smart-da2780f0-7004-45cd-aa8c-723f898ae420 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67706858 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.67706858 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1735612173 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 13411241960 ps |
| CPU time | 2747.83 seconds |
| Started | Jul 20 07:55:48 PM PDT 24 |
| Finished | Jul 20 08:41:37 PM PDT 24 |
| Peak memory | 624696 kb |
| Host | smart-2b72f1b5-7d9e-4510-aabb-877a62880393 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735612173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1735612173 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2808018609 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4733547380 ps |
| CPU time | 685.06 seconds |
| Started | Jul 20 07:59:13 PM PDT 24 |
| Finished | Jul 20 08:10:39 PM PDT 24 |
| Peak memory | 622764 kb |
| Host | smart-fad425cc-4a96-4be6-bb54-629f4c3a4314 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808018609 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.2808018609 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1773578134 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4714062652 ps |
| CPU time | 627.14 seconds |
| Started | Jul 20 07:55:54 PM PDT 24 |
| Finished | Jul 20 08:06:22 PM PDT 24 |
| Peak memory | 622788 kb |
| Host | smart-21415a38-e8c3-4250-a611-96871532f166 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773578134 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1773578134 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.4258519249 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 2916823610 ps |
| CPU time | 130.3 seconds |
| Started | Jul 20 08:01:58 PM PDT 24 |
| Finished | Jul 20 08:04:10 PM PDT 24 |
| Peak memory | 620900 kb |
| Host | smart-1f768871-52a0-4e48-9e80-63dcffd4c58d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4258519249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.4258519249 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.4226135809 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2758885093 ps |
| CPU time | 175.58 seconds |
| Started | Jul 20 08:03:11 PM PDT 24 |
| Finished | Jul 20 08:06:08 PM PDT 24 |
| Peak memory | 621472 kb |
| Host | smart-7c41fee6-6538-4afb-85f2-fe7c94fc2910 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226135809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4226135809 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.3895108821 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 7459258822 ps |
| CPU time | 668.99 seconds |
| Started | Jul 20 08:02:11 PM PDT 24 |
| Finished | Jul 20 08:13:20 PM PDT 24 |
| Peak memory | 630552 kb |
| Host | smart-fd93060e-481f-47d3-a774-b5f96b24ded8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3895108821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.3895108821 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.1890763880 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 15843421432 ps |
| CPU time | 3731.26 seconds |
| Started | Jul 20 08:09:31 PM PDT 24 |
| Finished | Jul 20 09:11:44 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-601a3500-a99c-4b44-9253-67aa2ece23c5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890763880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_dev.1890763880 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.2688613958 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 15949289444 ps |
| CPU time | 3233.01 seconds |
| Started | Jul 20 08:08:29 PM PDT 24 |
| Finished | Jul 20 09:02:23 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-b530fc79-4f14-4526-a376-2bdb53449f8d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688613958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.2688613958 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1418389309 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 15878738212 ps |
| CPU time | 3458.03 seconds |
| Started | Jul 20 08:10:02 PM PDT 24 |
| Finished | Jul 20 09:07:41 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-e8342bc3-6253-42ad-9aea-e9d9a3d6d0a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418389309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1418389309 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.104442773 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 14816870794 ps |
| CPU time | 3083.57 seconds |
| Started | Jul 20 08:13:29 PM PDT 24 |
| Finished | Jul 20 09:04:54 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-3da35e5d-028b-4604-86df-622bf3d8e361 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104442773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_rma.104442773 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4033408038 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 10766294149 ps |
| CPU time | 2723.16 seconds |
| Started | Jul 20 08:08:37 PM PDT 24 |
| Finished | Jul 20 08:54:01 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-fe4a8eec-3ff3-4470-8824-7184f1e04fe2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033408038 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.4033408038 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2297611989 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 15449301302 ps |
| CPU time | 3534.4 seconds |
| Started | Jul 20 08:08:52 PM PDT 24 |
| Finished | Jul 20 09:07:47 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-a92d4f98-d119-4fca-9a10-010f5a4b913e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297611989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2297611989 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1338974844 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 14895277112 ps |
| CPU time | 3492.08 seconds |
| Started | Jul 20 08:09:38 PM PDT 24 |
| Finished | Jul 20 09:07:51 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-774db74c-f5de-4c30-873d-d11793aea6c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338974844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1338974844 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2952750771 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 15040590152 ps |
| CPU time | 3542.11 seconds |
| Started | Jul 20 08:10:25 PM PDT 24 |
| Finished | Jul 20 09:09:28 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-102fe0c3-757b-4435-ad5c-aebdd63071db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952750771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.2952750771 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.512047747 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 26553656198 ps |
| CPU time | 5408.56 seconds |
| Started | Jul 20 08:13:44 PM PDT 24 |
| Finished | Jul 20 09:43:54 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-b0838ca7-9877-4fdc-8a5b-9ba981c78a13 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512047747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.512047747 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.3224368014 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 26329353208 ps |
| CPU time | 3481.68 seconds |
| Started | Jul 20 08:08:38 PM PDT 24 |
| Finished | Jul 20 09:06:41 PM PDT 24 |
| Peak memory | 612996 kb |
| Host | smart-f8c11be7-3587-41af-9283-483a8f94fd55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224368014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3224368014 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.4283227646 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 14987834674 ps |
| CPU time | 3357.09 seconds |
| Started | Jul 20 08:11:27 PM PDT 24 |
| Finished | Jul 20 09:07:25 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-031c0047-247e-49aa-a582-a25615686d2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4283227646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.4283227646 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.2769807935 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 16419784820 ps |
| CPU time | 3749.54 seconds |
| Started | Jul 20 08:08:43 PM PDT 24 |
| Finished | Jul 20 09:11:13 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-6905cdc5-ed63-4d5d-812c-c40c1853a711 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769807935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.2769807935 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2100113834 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4660648550 ps |
| CPU time | 808.71 seconds |
| Started | Jul 20 08:05:48 PM PDT 24 |
| Finished | Jul 20 08:19:17 PM PDT 24 |
| Peak memory | 609560 kb |
| Host | smart-614fe412-77ae-41f1-bb3e-03e91f785b37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100113834 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2100113834 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3375827792 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 6440277227 ps |
| CPU time | 261.72 seconds |
| Started | Jul 20 08:06:35 PM PDT 24 |
| Finished | Jul 20 08:10:57 PM PDT 24 |
| Peak memory | 623420 kb |
| Host | smart-77181520-e1b5-4678-9f19-af4b7bc9c50a |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3375827792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3375827792 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.3720547836 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 2687096867 ps |
| CPU time | 131.85 seconds |
| Started | Jul 20 08:08:12 PM PDT 24 |
| Finished | Jul 20 08:10:24 PM PDT 24 |
| Peak memory | 617640 kb |
| Host | smart-78fe7f38-c8e8-4e11-b148-e4a428e5ec53 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720547836 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.3720547836 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.417640509 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 9222511138 ps |
| CPU time | 992.76 seconds |
| Started | Jul 20 08:20:26 PM PDT 24 |
| Finished | Jul 20 08:37:01 PM PDT 24 |
| Peak memory | 623040 kb |
| Host | smart-c47e56cb-95c7-4789-9d9a-686c6545c4e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417640509 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.417640509 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3481093882 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 4506791966 ps |
| CPU time | 639.75 seconds |
| Started | Jul 20 08:19:10 PM PDT 24 |
| Finished | Jul 20 08:29:50 PM PDT 24 |
| Peak memory | 618760 kb |
| Host | smart-567ae30c-172e-450e-8f0b-0bdfb44a9450 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3481093882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3481093882 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1560062648 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 7831198293 ps |
| CPU time | 525.65 seconds |
| Started | Jul 20 08:19:51 PM PDT 24 |
| Finished | Jul 20 08:28:37 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-3352c5f6-fd73-4e56-910b-50c5b61f626b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560062648 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1560062648 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1140791341 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 4432252968 ps |
| CPU time | 733.81 seconds |
| Started | Jul 20 08:21:21 PM PDT 24 |
| Finished | Jul 20 08:33:36 PM PDT 24 |
| Peak memory | 619060 kb |
| Host | smart-f31af052-8271-426a-804c-2d1a241a4236 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1140791341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.1140791341 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.570084676 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 4088086960 ps |
| CPU time | 448.91 seconds |
| Started | Jul 20 08:18:35 PM PDT 24 |
| Finished | Jul 20 08:26:05 PM PDT 24 |
| Peak memory | 618524 kb |
| Host | smart-ceb3eebd-0379-44d5-bf97-d22e8719de66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570084676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_s w_alert_handler_lpg_sleep_mode_alerts.570084676 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2832566048 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 9095410091 ps |
| CPU time | 602.24 seconds |
| Started | Jul 20 08:18:44 PM PDT 24 |
| Finished | Jul 20 08:28:47 PM PDT 24 |
| Peak memory | 624764 kb |
| Host | smart-10bf4dc7-570a-4a3c-9737-f40022856593 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832566048 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.2832566048 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2314477294 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 13630222528 ps |
| CPU time | 2572.47 seconds |
| Started | Jul 20 08:19:22 PM PDT 24 |
| Finished | Jul 20 09:02:15 PM PDT 24 |
| Peak memory | 618988 kb |
| Host | smart-fea0a855-eefa-42a4-97c1-f6cb59c34f2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2314477294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2314477294 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.360056383 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3508061528 ps |
| CPU time | 393.39 seconds |
| Started | Jul 20 08:21:50 PM PDT 24 |
| Finished | Jul 20 08:28:24 PM PDT 24 |
| Peak memory | 618544 kb |
| Host | smart-37064c23-8d2d-4498-bae9-f6c507683a67 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360056383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_s w_alert_handler_lpg_sleep_mode_alerts.360056383 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4010733003 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 5207430252 ps |
| CPU time | 572.63 seconds |
| Started | Jul 20 08:18:37 PM PDT 24 |
| Finished | Jul 20 08:28:11 PM PDT 24 |
| Peak memory | 622368 kb |
| Host | smart-89219be9-f3e3-459a-be85-622df7436b78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010733003 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.4010733003 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1285311200 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 13679565160 ps |
| CPU time | 2461.42 seconds |
| Started | Jul 20 08:20:19 PM PDT 24 |
| Finished | Jul 20 09:01:21 PM PDT 24 |
| Peak memory | 618772 kb |
| Host | smart-8b47a5fc-3ab4-45a1-9c5d-b019950e6acb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1285311200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.1285311200 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134106517 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3749969904 ps |
| CPU time | 412.82 seconds |
| Started | Jul 20 08:19:12 PM PDT 24 |
| Finished | Jul 20 08:26:06 PM PDT 24 |
| Peak memory | 649080 kb |
| Host | smart-048fa180-964b-4a65-b8f6-2abbdbf0c7fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134106517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2134106517 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.5521912 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 12927051400 ps |
| CPU time | 861.24 seconds |
| Started | Jul 20 08:21:56 PM PDT 24 |
| Finished | Jul 20 08:36:17 PM PDT 24 |
| Peak memory | 623524 kb |
| Host | smart-eb46314f-66b9-45b4-9626-ac868bd64f88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5521912 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.5521912 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2072062622 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 8424542856 ps |
| CPU time | 1248.35 seconds |
| Started | Jul 20 08:20:26 PM PDT 24 |
| Finished | Jul 20 08:41:15 PM PDT 24 |
| Peak memory | 619048 kb |
| Host | smart-01a66b4a-a744-4a52-9207-00b5cf4690a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2072062622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2072062622 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.1094410711 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3573614896 ps |
| CPU time | 359.14 seconds |
| Started | Jul 20 08:20:10 PM PDT 24 |
| Finished | Jul 20 08:26:10 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-e7d7c437-af30-4bb8-86af-b57ca57c9a7b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094410711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1094410711 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2252187332 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 4568860496 ps |
| CPU time | 502.15 seconds |
| Started | Jul 20 08:19:41 PM PDT 24 |
| Finished | Jul 20 08:28:05 PM PDT 24 |
| Peak memory | 619084 kb |
| Host | smart-8b9a0ae0-708d-4e9b-b137-65863dce2bec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2252187332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.2252187332 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.3010698122 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 5379504484 ps |
| CPU time | 685.6 seconds |
| Started | Jul 20 08:19:02 PM PDT 24 |
| Finished | Jul 20 08:30:28 PM PDT 24 |
| Peak memory | 650024 kb |
| Host | smart-5faa30d0-55cd-4d65-b6c6-f45c2cfaa338 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3010698122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.3010698122 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2483180709 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 8159086400 ps |
| CPU time | 1623.89 seconds |
| Started | Jul 20 08:20:19 PM PDT 24 |
| Finished | Jul 20 08:47:24 PM PDT 24 |
| Peak memory | 618788 kb |
| Host | smart-4091b256-e687-460e-b3f5-dc2aaa21e352 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2483180709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2483180709 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.49004673 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 13911920114 ps |
| CPU time | 2353.74 seconds |
| Started | Jul 20 08:20:34 PM PDT 24 |
| Finished | Jul 20 08:59:48 PM PDT 24 |
| Peak memory | 618780 kb |
| Host | smart-44f90edd-b30f-4c13-973f-6b7908c4eb20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=49004673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.49004673 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.412348111 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4255780522 ps |
| CPU time | 656.44 seconds |
| Started | Jul 20 08:20:33 PM PDT 24 |
| Finished | Jul 20 08:31:31 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-a980d174-fa24-46d5-af28-3e96a4d412ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 412348111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.412348111 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.490627876 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 4684462144 ps |
| CPU time | 574.1 seconds |
| Started | Jul 20 08:20:48 PM PDT 24 |
| Finished | Jul 20 08:30:22 PM PDT 24 |
| Peak memory | 618796 kb |
| Host | smart-3aa91f1b-9c3b-462a-89ed-91ca874cf12d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=490627876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.490627876 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4284223348 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3630377052 ps |
| CPU time | 348.79 seconds |
| Started | Jul 20 08:20:55 PM PDT 24 |
| Finished | Jul 20 08:26:44 PM PDT 24 |
| Peak memory | 618800 kb |
| Host | smart-182ca7a9-4050-4209-97be-77a399d8e5cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284223348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4284223348 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3552936360 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 8206638646 ps |
| CPU time | 1499.51 seconds |
| Started | Jul 20 08:19:45 PM PDT 24 |
| Finished | Jul 20 08:44:45 PM PDT 24 |
| Peak memory | 618772 kb |
| Host | smart-01635459-862d-4427-8a48-5a36fd8923c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3552936360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3552936360 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.566815654 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 13706062664 ps |
| CPU time | 1400.84 seconds |
| Started | Jul 20 08:04:59 PM PDT 24 |
| Finished | Jul 20 08:28:20 PM PDT 24 |
| Peak memory | 607992 kb |
| Host | smart-ef04e5b0-5a15-4879-bb8e-a65fe6a4b034 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566815654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.566815654 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2217618582 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3880016064 ps |
| CPU time | 487.32 seconds |
| Started | Jul 20 08:12:21 PM PDT 24 |
| Finished | Jul 20 08:20:29 PM PDT 24 |
| Peak memory | 619596 kb |
| Host | smart-11dbe331-dc18-4561-af4b-dd8f31bd7252 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 217618582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2217618582 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3181076455 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 3583024364 ps |
| CPU time | 388.95 seconds |
| Started | Jul 20 08:06:14 PM PDT 24 |
| Finished | Jul 20 08:12:43 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-6eeb3006-46f3-4bf6-baa4-f3a2e42f4521 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3181076455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3181076455 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3322610703 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 19315819004 ps |
| CPU time | 676.7 seconds |
| Started | Jul 20 08:10:06 PM PDT 24 |
| Finished | Jul 20 08:21:24 PM PDT 24 |
| Peak memory | 619444 kb |
| Host | smart-194846bc-4b35-4958-ab04-54dc84e15d19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3322610703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3322610703 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1823754907 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2876550790 ps |
| CPU time | 431.11 seconds |
| Started | Jul 20 08:12:44 PM PDT 24 |
| Finished | Jul 20 08:19:56 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-b2999cf9-053f-4a2a-bc83-1c2734e0c32b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823754907 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1823754907 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2718567912 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 2569303356 ps |
| CPU time | 257.92 seconds |
| Started | Jul 20 08:08:43 PM PDT 24 |
| Finished | Jul 20 08:13:02 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-fa501e49-9bd1-42e7-a232-92b550d350fd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718 567912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.2718567912 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3620184701 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 2392140793 ps |
| CPU time | 235.74 seconds |
| Started | Jul 20 08:12:35 PM PDT 24 |
| Finished | Jul 20 08:16:32 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-5de120b2-6046-4578-b0cd-4b48e3226190 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620184701 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3620184701 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3939890833 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2894243318 ps |
| CPU time | 236.73 seconds |
| Started | Jul 20 08:13:50 PM PDT 24 |
| Finished | Jul 20 08:17:48 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-a3807d8e-e8b5-45be-abad-631052ab0336 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939890833 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3939890833 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.1703326566 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3520378856 ps |
| CPU time | 332.99 seconds |
| Started | Jul 20 08:09:35 PM PDT 24 |
| Finished | Jul 20 08:15:09 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-563f82fc-f62f-4a51-8abc-cbae97c0c0c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703326566 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.1703326566 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.1434991824 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3479309857 ps |
| CPU time | 339.26 seconds |
| Started | Jul 20 08:08:47 PM PDT 24 |
| Finished | Jul 20 08:14:27 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-a6513208-e7cc-4625-b870-71632fee877e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434991824 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.1434991824 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.836781640 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 3144694232 ps |
| CPU time | 429.94 seconds |
| Started | Jul 20 08:15:21 PM PDT 24 |
| Finished | Jul 20 08:22:31 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-2492c435-7836-4638-bfc5-8a0cfc579e72 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836781640 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.836781640 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.3469667903 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 3526397927 ps |
| CPU time | 318.45 seconds |
| Started | Jul 20 08:09:59 PM PDT 24 |
| Finished | Jul 20 08:15:18 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-c12a3a5a-1b21-4736-917b-e9aecd861a1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3469667903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.3469667903 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2389430575 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 4459454550 ps |
| CPU time | 559.55 seconds |
| Started | Jul 20 08:09:15 PM PDT 24 |
| Finished | Jul 20 08:18:35 PM PDT 24 |
| Peak memory | 619388 kb |
| Host | smart-e98904b6-9fff-4c12-a4a6-cd57e7724bdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2389430575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2389430575 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.710479809 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7545105348 ps |
| CPU time | 1788.91 seconds |
| Started | Jul 20 08:11:06 PM PDT 24 |
| Finished | Jul 20 08:40:56 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-c0b277fc-6c60-4b64-8676-790dfa060adc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=710479809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.710479809 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2705433390 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7829897064 ps |
| CPU time | 1763.51 seconds |
| Started | Jul 20 08:10:51 PM PDT 24 |
| Finished | Jul 20 08:40:15 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-1799d947-fa57-450a-8bc4-b500f774fc46 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705433390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2705433390 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.437758323 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 13589086960 ps |
| CPU time | 1761.83 seconds |
| Started | Jul 20 08:10:26 PM PDT 24 |
| Finished | Jul 20 08:39:49 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-ef115d34-8a56-4f76-89a5-3cf22db85cf4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437758323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.437758323 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1753991149 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 8102035492 ps |
| CPU time | 1270.45 seconds |
| Started | Jul 20 08:09:21 PM PDT 24 |
| Finished | Jul 20 08:30:32 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-750a2468-bbca-4b07-8e9a-aad1ceee35b1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1753991149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.1753991149 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.328212202 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3663063680 ps |
| CPU time | 473.35 seconds |
| Started | Jul 20 08:09:40 PM PDT 24 |
| Finished | Jul 20 08:17:34 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-33a3e9ae-f1c1-4a18-9d22-9a0d35c349f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=328212202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.328212202 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.215614006 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 255149989440 ps |
| CPU time | 11372.7 seconds |
| Started | Jul 20 08:10:33 PM PDT 24 |
| Finished | Jul 20 11:20:07 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-e2c7a237-be66-4f63-95e4-4e7d6872fa06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=215614006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.215614006 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.4190204856 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2842559400 ps |
| CPU time | 363.53 seconds |
| Started | Jul 20 08:10:52 PM PDT 24 |
| Finished | Jul 20 08:16:57 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-819a6ef4-ed0f-4886-ae26-d89c6fabe454 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190204856 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.4190204856 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.906525639 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 5311479860 ps |
| CPU time | 606.4 seconds |
| Started | Jul 20 08:06:24 PM PDT 24 |
| Finished | Jul 20 08:16:31 PM PDT 24 |
| Peak memory | 650220 kb |
| Host | smart-4dc99ae1-e746-481d-adec-29dac524206c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 906525639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.906525639 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1451094457 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 3860955930 ps |
| CPU time | 369.28 seconds |
| Started | Jul 20 08:09:08 PM PDT 24 |
| Finished | Jul 20 08:15:19 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-6b6b4091-654c-46a6-bf77-c6dd09a4cf17 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451094457 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1451094457 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.381491171 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 7804401152 ps |
| CPU time | 414.36 seconds |
| Started | Jul 20 08:09:15 PM PDT 24 |
| Finished | Jul 20 08:16:10 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-bc5e3c8e-10f3-4586-b713-0b4af4d8c4a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=381491171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.381491171 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3297878077 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 2522229480 ps |
| CPU time | 274.24 seconds |
| Started | Jul 20 08:14:38 PM PDT 24 |
| Finished | Jul 20 08:19:12 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-1a2694d4-624a-46ab-985c-4834bf3f1ab2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297878077 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3297878077 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1352020672 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 8333031528 ps |
| CPU time | 925.96 seconds |
| Started | Jul 20 08:08:48 PM PDT 24 |
| Finished | Jul 20 08:24:14 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-b089a780-94e3-404e-a717-07c6e0131eaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1352020672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1352020672 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.146572441 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 5114689686 ps |
| CPU time | 717.57 seconds |
| Started | Jul 20 08:11:06 PM PDT 24 |
| Finished | Jul 20 08:23:04 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-4d48b60b-d434-47a9-8e80-24bfec6ebe55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =146572441 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.146572441 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2935793313 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 7157418400 ps |
| CPU time | 978.29 seconds |
| Started | Jul 20 08:11:58 PM PDT 24 |
| Finished | Jul 20 08:28:17 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-b36b7d8e-37d2-4bfa-848c-1155b2f77e4e |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935793313 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2935793313 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3233636731 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 18362380196 ps |
| CPU time | 2104.57 seconds |
| Started | Jul 20 08:13:56 PM PDT 24 |
| Finished | Jul 20 08:49:01 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-df601e04-2c1a-4163-9d53-ec59afb5dccd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233636731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3233636731 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.1585993054 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 11053648138 ps |
| CPU time | 1132.15 seconds |
| Started | Jul 20 08:11:33 PM PDT 24 |
| Finished | Jul 20 08:30:27 PM PDT 24 |
| Peak memory | 624696 kb |
| Host | smart-8515e588-569f-4b41-9d78-6a3938301823 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1585993054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.1585993054 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1324152361 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 4219214052 ps |
| CPU time | 695.3 seconds |
| Started | Jul 20 08:11:45 PM PDT 24 |
| Finished | Jul 20 08:23:21 PM PDT 24 |
| Peak memory | 614008 kb |
| Host | smart-9918b840-3e69-45b6-8897-2d8c753d05f8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324152361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1324152361 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4231495584 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 3754688264 ps |
| CPU time | 784.08 seconds |
| Started | Jul 20 08:11:58 PM PDT 24 |
| Finished | Jul 20 08:25:02 PM PDT 24 |
| Peak memory | 612804 kb |
| Host | smart-9148812a-bb48-47ed-8b07-eb0d9c6b16d8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231495584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.4231495584 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.260989402 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 5056697080 ps |
| CPU time | 860.34 seconds |
| Started | Jul 20 08:13:26 PM PDT 24 |
| Finished | Jul 20 08:27:47 PM PDT 24 |
| Peak memory | 611896 kb |
| Host | smart-242d7664-988f-4bc7-93c5-9f4927dd8913 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260989402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.260989402 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3130364291 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 4550139980 ps |
| CPU time | 808.55 seconds |
| Started | Jul 20 08:12:34 PM PDT 24 |
| Finished | Jul 20 08:26:04 PM PDT 24 |
| Peak memory | 612764 kb |
| Host | smart-9163c151-ef01-459b-9649-9586700e55ad |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130364291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3130364291 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2898084113 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 4901534024 ps |
| CPU time | 827.3 seconds |
| Started | Jul 20 08:11:45 PM PDT 24 |
| Finished | Jul 20 08:25:34 PM PDT 24 |
| Peak memory | 612896 kb |
| Host | smart-f2950d12-09b5-4d7c-a568-b8b35725db6f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898084113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2898084113 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2227191733 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3083896838 ps |
| CPU time | 207.8 seconds |
| Started | Jul 20 08:13:19 PM PDT 24 |
| Finished | Jul 20 08:16:47 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-b3f78c33-788a-480e-8a02-ed796db0be40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227191733 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.2227191733 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.80412122 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 3077593800 ps |
| CPU time | 379.06 seconds |
| Started | Jul 20 08:12:11 PM PDT 24 |
| Finished | Jul 20 08:18:30 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-d5d936d9-57a2-46db-b6a8-e14c5dcb8bef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80412122 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.80412122 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3270693332 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2938460364 ps |
| CPU time | 189.93 seconds |
| Started | Jul 20 08:14:43 PM PDT 24 |
| Finished | Jul 20 08:17:53 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-e46e6e9c-d2a9-48ce-a285-68eab3f96b15 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270693332 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.3270693332 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3607904794 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4512785040 ps |
| CPU time | 453.89 seconds |
| Started | Jul 20 08:11:32 PM PDT 24 |
| Finished | Jul 20 08:19:06 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-ce2ef791-c2ea-4876-949a-271583ca19c4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607904794 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3607904794 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4061095179 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4532505624 ps |
| CPU time | 510.13 seconds |
| Started | Jul 20 08:10:38 PM PDT 24 |
| Finished | Jul 20 08:19:09 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-d47b88d5-4965-4990-aad9-806acb039175 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061095179 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.4061095179 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4072982257 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 5659271100 ps |
| CPU time | 526.66 seconds |
| Started | Jul 20 08:12:33 PM PDT 24 |
| Finished | Jul 20 08:21:20 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-597d277e-3362-4dba-b2f1-1022de2bbef5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072982257 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.4072982257 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3010064845 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 4476602264 ps |
| CPU time | 369.28 seconds |
| Started | Jul 20 08:12:15 PM PDT 24 |
| Finished | Jul 20 08:18:24 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-a496ebe6-7388-4644-84ed-5c84a44ff898 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010064845 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.3010064845 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3402822097 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 10285922030 ps |
| CPU time | 1178.73 seconds |
| Started | Jul 20 08:12:24 PM PDT 24 |
| Finished | Jul 20 08:32:03 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-2ab82628-efe4-440d-a7c3-3ce87467eec7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402822097 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3402822097 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2335914011 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3021602780 ps |
| CPU time | 475.57 seconds |
| Started | Jul 20 08:11:59 PM PDT 24 |
| Finished | Jul 20 08:19:55 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-e30df60f-26c3-43d6-937e-fa2a4eb2ddae |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335914011 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.2335914011 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.16071900 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 4872487320 ps |
| CPU time | 748.09 seconds |
| Started | Jul 20 08:14:33 PM PDT 24 |
| Finished | Jul 20 08:27:01 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-273dab0d-d470-4c8e-bd3c-6a1725ff6a0d |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16071900 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.16071900 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.278134538 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 2946527352 ps |
| CPU time | 194.62 seconds |
| Started | Jul 20 08:15:43 PM PDT 24 |
| Finished | Jul 20 08:18:59 PM PDT 24 |
| Peak memory | 609852 kb |
| Host | smart-e324e570-5765-48f0-bae7-dae6e4eb03df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278134538 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.278134538 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2974171577 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 8844328928 ps |
| CPU time | 2100.71 seconds |
| Started | Jul 20 08:10:34 PM PDT 24 |
| Finished | Jul 20 08:45:35 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-8215c94b-67a7-4572-9051-ed22070e3a7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974171577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.2974171577 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.704334388 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 28984466090 ps |
| CPU time | 5833.26 seconds |
| Started | Jul 20 08:14:29 PM PDT 24 |
| Finished | Jul 20 09:51:44 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-73cfc1ef-2a23-41b5-987e-345951990f41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=704334388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.704334388 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2684318563 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 5002283492 ps |
| CPU time | 454.51 seconds |
| Started | Jul 20 08:15:05 PM PDT 24 |
| Finished | Jul 20 08:22:40 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-b8f55b0a-9abc-4ffa-b465-0fe08ced32ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26843 18563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.2684318563 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.296583302 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3019882280 ps |
| CPU time | 279.43 seconds |
| Started | Jul 20 08:10:12 PM PDT 24 |
| Finished | Jul 20 08:14:52 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-5613da86-6824-4eca-8a39-931e445c3479 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296583302 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.296583302 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.4023562492 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 6491925185 ps |
| CPU time | 748.88 seconds |
| Started | Jul 20 08:11:17 PM PDT 24 |
| Finished | Jul 20 08:23:46 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-997f4a7d-e145-4ce8-8be0-771965d7d558 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023562492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.4023562492 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.418677336 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2479379552 ps |
| CPU time | 206.64 seconds |
| Started | Jul 20 08:14:40 PM PDT 24 |
| Finished | Jul 20 08:18:07 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-21a3dc37-35fc-4f97-ad73-eebd1bad0cdf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418677336 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.418677336 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2696966120 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 4729678042 ps |
| CPU time | 530.53 seconds |
| Started | Jul 20 08:07:13 PM PDT 24 |
| Finished | Jul 20 08:16:04 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-b56f5a9e-7c38-4749-8e21-5a8951756a44 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2696966120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2696966120 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.101820600 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3393190720 ps |
| CPU time | 649.23 seconds |
| Started | Jul 20 08:13:42 PM PDT 24 |
| Finished | Jul 20 08:24:33 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-d28bcb22-2b4b-4ddc-9070-1114e1d21b83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101820600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.101820600 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.463361000 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 6526809200 ps |
| CPU time | 1496.1 seconds |
| Started | Jul 20 08:12:31 PM PDT 24 |
| Finished | Jul 20 08:37:27 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-579dade9-32d3-4032-b1d6-7f725b0a53cf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=463361000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.463361000 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.2682644977 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3007705230 ps |
| CPU time | 762.29 seconds |
| Started | Jul 20 08:11:47 PM PDT 24 |
| Finished | Jul 20 08:24:30 PM PDT 24 |
| Peak memory | 616344 kb |
| Host | smart-98132ebd-952e-4a96-b96f-bc2231097bf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682644977 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.2682644977 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1310247217 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 9144926992 ps |
| CPU time | 1865.2 seconds |
| Started | Jul 20 08:14:47 PM PDT 24 |
| Finished | Jul 20 08:45:53 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-7db4fc26-f814-4591-8217-449b9d8461b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310247217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1310247217 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2534682933 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 2751959000 ps |
| CPU time | 255.82 seconds |
| Started | Jul 20 08:10:33 PM PDT 24 |
| Finished | Jul 20 08:14:49 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-c2358d64-6596-43c7-8bb1-18b0f62c7b79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 34682933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2534682933 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.1643887523 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 7875083184 ps |
| CPU time | 1568.95 seconds |
| Started | Jul 20 08:10:55 PM PDT 24 |
| Finished | Jul 20 08:37:04 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-01c33ec7-e3d8-4da0-87e9-b9a43f1a3bac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=1643887523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.1643887523 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.639603635 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 3360004502 ps |
| CPU time | 197.54 seconds |
| Started | Jul 20 08:10:00 PM PDT 24 |
| Finished | Jul 20 08:13:18 PM PDT 24 |
| Peak memory | 609264 kb |
| Host | smart-34ef5e79-3ee9-47a9-991c-370ba6a7426f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639603635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.639603635 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2149265762 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3426172298 ps |
| CPU time | 501.83 seconds |
| Started | Jul 20 08:16:10 PM PDT 24 |
| Finished | Jul 20 08:24:32 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-75627524-3788-4c12-8a19-01f6fae46e52 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2149265762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2149265762 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2769337107 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2874402890 ps |
| CPU time | 324.96 seconds |
| Started | Jul 20 08:08:22 PM PDT 24 |
| Finished | Jul 20 08:13:48 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-6cd5a7e7-0df2-442c-8020-c538167bb2ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769337107 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2769337107 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.2043879690 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 2825757520 ps |
| CPU time | 246.15 seconds |
| Started | Jul 20 08:05:13 PM PDT 24 |
| Finished | Jul 20 08:09:19 PM PDT 24 |
| Peak memory | 609668 kb |
| Host | smart-ddb82ea8-e008-4003-ab58-17c29afb241b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043879690 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2043879690 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.312864790 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 3036066080 ps |
| CPU time | 219.59 seconds |
| Started | Jul 20 08:05:53 PM PDT 24 |
| Finished | Jul 20 08:09:33 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-2f6aaba1-2268-46bb-bda5-7b35ede6476e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312864790 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_example_manufacturer.312864790 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.3271950323 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 2513889776 ps |
| CPU time | 141.68 seconds |
| Started | Jul 20 08:05:54 PM PDT 24 |
| Finished | Jul 20 08:08:16 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-83bc8a54-2637-45e7-b4fb-055628f60817 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271950323 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.3271950323 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2057420880 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 5564125800 ps |
| CPU time | 687.87 seconds |
| Started | Jul 20 08:14:37 PM PDT 24 |
| Finished | Jul 20 08:26:06 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-948a58bd-e393-4056-ae6b-07174c8915e9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2057420880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2057420880 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3204854258 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 5736403428 ps |
| CPU time | 1034.71 seconds |
| Started | Jul 20 08:06:43 PM PDT 24 |
| Finished | Jul 20 08:23:58 PM PDT 24 |
| Peak memory | 610080 kb |
| Host | smart-b8af8025-9125-422b-9aca-f5fb593809e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204854258 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3204854258 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2352862988 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 6072801763 ps |
| CPU time | 938.1 seconds |
| Started | Jul 20 08:07:55 PM PDT 24 |
| Finished | Jul 20 08:23:34 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-1e599cad-0621-45bb-832c-3e295ed81182 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352862988 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2352862988 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.397698479 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 7992985884 ps |
| CPU time | 1075.96 seconds |
| Started | Jul 20 08:13:15 PM PDT 24 |
| Finished | Jul 20 08:31:11 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-464e6b35-260c-4c71-bef1-8f814fb839d6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397698479 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.397698479 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1206992293 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6125819154 ps |
| CPU time | 1222.79 seconds |
| Started | Jul 20 08:07:18 PM PDT 24 |
| Finished | Jul 20 08:27:41 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-43f8425b-1fdb-498f-a0ba-7bbf96fd0b9d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206992293 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.1206992293 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.278696973 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 3621829020 ps |
| CPU time | 330.34 seconds |
| Started | Jul 20 08:10:43 PM PDT 24 |
| Finished | Jul 20 08:16:15 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-68a1808d-7c4d-425f-a7dc-835fcba87b4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278696973 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.278696973 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3215315324 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 5593672672 ps |
| CPU time | 1027.79 seconds |
| Started | Jul 20 08:15:16 PM PDT 24 |
| Finished | Jul 20 08:32:24 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-91b21e67-209d-4ae0-b192-545a5536d79a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215315324 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.3215315324 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2526179386 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4031806414 ps |
| CPU time | 657.4 seconds |
| Started | Jul 20 08:07:05 PM PDT 24 |
| Finished | Jul 20 08:18:03 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-65883c27-57cb-45c1-bfe6-1635861f8a0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526179386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2526179386 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3705148442 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 5392852526 ps |
| CPU time | 686.05 seconds |
| Started | Jul 20 08:15:27 PM PDT 24 |
| Finished | Jul 20 08:26:53 PM PDT 24 |
| Peak memory | 610212 kb |
| Host | smart-2d275288-5595-4857-bd9d-167e2f448b98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3705148442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3705148442 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1262561406 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3731813200 ps |
| CPU time | 408.42 seconds |
| Started | Jul 20 08:14:58 PM PDT 24 |
| Finished | Jul 20 08:21:47 PM PDT 24 |
| Peak memory | 609256 kb |
| Host | smart-44986a23-d6ee-4473-8fff-1eb695fb75ca |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262561 406 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.1262561406 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.4281093953 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 25408062500 ps |
| CPU time | 2240.98 seconds |
| Started | Jul 20 08:06:48 PM PDT 24 |
| Finished | Jul 20 08:44:10 PM PDT 24 |
| Peak memory | 615228 kb |
| Host | smart-6ac23db8-cea6-49e7-b776-e38f926e9689 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281093953 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.4281093953 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3653305697 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 21067025951 ps |
| CPU time | 1588.45 seconds |
| Started | Jul 20 08:12:35 PM PDT 24 |
| Finished | Jul 20 08:39:04 PM PDT 24 |
| Peak memory | 614440 kb |
| Host | smart-c523ef1a-74fd-46de-aa1a-0b08653e7dce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3653305697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3653305697 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.476099974 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2191802248 ps |
| CPU time | 277.92 seconds |
| Started | Jul 20 08:18:08 PM PDT 24 |
| Finished | Jul 20 08:22:47 PM PDT 24 |
| Peak memory | 609792 kb |
| Host | smart-1698f7a3-60d7-4275-b094-6da4ff3375ba |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=476099974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.476099974 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1328107587 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 3214626002 ps |
| CPU time | 235.5 seconds |
| Started | Jul 20 08:15:12 PM PDT 24 |
| Finished | Jul 20 08:19:08 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-75bde66f-0912-4f33-86a1-6fc22ac5865a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328107587 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1328107587 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.4050533442 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2731850928 ps |
| CPU time | 320.98 seconds |
| Started | Jul 20 08:10:23 PM PDT 24 |
| Finished | Jul 20 08:15:44 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-7028fdd4-fc5b-4984-8f3d-25b2ec0b620e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050533442 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.4050533442 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3804063197 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 2920129658 ps |
| CPU time | 318.78 seconds |
| Started | Jul 20 08:09:40 PM PDT 24 |
| Finished | Jul 20 08:14:59 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-33c903b9-de5f-42de-af39-fa73ef48638b |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804063197 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3804063197 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1090947900 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 2878856913 ps |
| CPU time | 276.3 seconds |
| Started | Jul 20 08:15:28 PM PDT 24 |
| Finished | Jul 20 08:20:04 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-1d678e00-a4ba-4f18-81b2-ba378d15da7a |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090947900 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1090947900 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.212625461 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 7320367800 ps |
| CPU time | 1544.29 seconds |
| Started | Jul 20 08:11:04 PM PDT 24 |
| Finished | Jul 20 08:36:49 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-23fd2b25-497e-4e40-9a94-a63b57f8d43c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212625461 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.212625461 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2534862748 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 2681076062 ps |
| CPU time | 369.99 seconds |
| Started | Jul 20 08:15:04 PM PDT 24 |
| Finished | Jul 20 08:21:14 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-3800be26-532d-41b8-898a-fb14be648ed6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534862748 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2534862748 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.1961286187 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 3079412248 ps |
| CPU time | 405.36 seconds |
| Started | Jul 20 08:14:58 PM PDT 24 |
| Finished | Jul 20 08:21:44 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-b9c5dc2d-ca48-46b7-891b-1eb59d6ef3d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961286187 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.1961286187 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4131641651 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4368641444 ps |
| CPU time | 625.83 seconds |
| Started | Jul 20 08:08:01 PM PDT 24 |
| Finished | Jul 20 08:18:27 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-e8886d45-7722-4a36-92ba-b018a07fbb00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131641651 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.4131641651 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2306036585 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5284902870 ps |
| CPU time | 849.54 seconds |
| Started | Jul 20 08:07:29 PM PDT 24 |
| Finished | Jul 20 08:21:41 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-0afb157f-3e88-43fb-b137-4beeb99ee51a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306036585 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.2306036585 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3726913370 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 5371544824 ps |
| CPU time | 736.79 seconds |
| Started | Jul 20 08:09:51 PM PDT 24 |
| Finished | Jul 20 08:22:10 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-84988202-56de-4beb-9025-5a1d7714f057 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726913370 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.3726913370 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2602754457 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 5797311556 ps |
| CPU time | 1040.71 seconds |
| Started | Jul 20 08:07:55 PM PDT 24 |
| Finished | Jul 20 08:25:17 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-221b0d14-9f9e-4b6b-8fc0-54d9c16177e5 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602754457 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.2602754457 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1422564711 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 64400581605 ps |
| CPU time | 11126.3 seconds |
| Started | Jul 20 08:05:52 PM PDT 24 |
| Finished | Jul 20 11:11:20 PM PDT 24 |
| Peak memory | 624728 kb |
| Host | smart-cd66d25c-b710-4775-aa63-8ac90f791927 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1422564711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.1422564711 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3918547204 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 11483091292 ps |
| CPU time | 2081.49 seconds |
| Started | Jul 20 08:10:37 PM PDT 24 |
| Finished | Jul 20 08:45:19 PM PDT 24 |
| Peak memory | 616636 kb |
| Host | smart-b56a6c5b-a1a7-46cc-9899-87c2a8f8fd6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918 547204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3918547204 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.740475858 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 11853195756 ps |
| CPU time | 1977.56 seconds |
| Started | Jul 20 08:10:48 PM PDT 24 |
| Finished | Jul 20 08:43:46 PM PDT 24 |
| Peak memory | 617720 kb |
| Host | smart-d6529b8b-6447-4321-a174-d10a5be712a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=740475858 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.740475858 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1585559453 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 13002076164 ps |
| CPU time | 1841.28 seconds |
| Started | Jul 20 08:13:44 PM PDT 24 |
| Finished | Jul 20 08:44:26 PM PDT 24 |
| Peak memory | 618008 kb |
| Host | smart-893b3a20-1a42-48a0-a06f-157fab53b614 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1585559453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1585559453 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.582543375 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 8449221800 ps |
| CPU time | 1226.12 seconds |
| Started | Jul 20 08:11:46 PM PDT 24 |
| Finished | Jul 20 08:32:13 PM PDT 24 |
| Peak memory | 616412 kb |
| Host | smart-0d83e3cc-f301-4870-87b2-6de126554853 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=582543375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.582543375 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1296696427 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 11233445924 ps |
| CPU time | 1960.6 seconds |
| Started | Jul 20 08:12:23 PM PDT 24 |
| Finished | Jul 20 08:45:04 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-741605b8-986c-4520-92c6-a30c0a41a624 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129669 6427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1296696427 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1666598010 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 9669233002 ps |
| CPU time | 1741.05 seconds |
| Started | Jul 20 08:11:37 PM PDT 24 |
| Finished | Jul 20 08:40:38 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-47118511-6951-4fde-825c-607e6cc905ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16665 98010 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1666598010 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3320520063 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 16117437960 ps |
| CPU time | 4287.64 seconds |
| Started | Jul 20 08:11:43 PM PDT 24 |
| Finished | Jul 20 09:23:11 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-e58af499-8502-454a-85b9-1ef4d9c83e23 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33205 20063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.3320520063 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.260184999 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 3208434870 ps |
| CPU time | 271.83 seconds |
| Started | Jul 20 08:14:36 PM PDT 24 |
| Finished | Jul 20 08:19:08 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-88f37553-97e6-4946-b858-e101af14b451 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260184999 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.260184999 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3683808578 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 2768134560 ps |
| CPU time | 293.37 seconds |
| Started | Jul 20 08:07:01 PM PDT 24 |
| Finished | Jul 20 08:11:55 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-2992190a-e84f-4cf3-b7d4-c29439af3c8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683808578 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3683808578 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2464319937 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 3554310750 ps |
| CPU time | 274.55 seconds |
| Started | Jul 20 08:11:26 PM PDT 24 |
| Finished | Jul 20 08:16:01 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-700b199e-c9df-4c96-b076-ca8bcd1ca4b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464319937 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2464319937 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3979098741 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2712629534 ps |
| CPU time | 268.45 seconds |
| Started | Jul 20 08:09:55 PM PDT 24 |
| Finished | Jul 20 08:14:24 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-39150cf8-09d3-4e6d-a62e-b815b5b390a5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979098741 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.3979098741 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1508125886 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 2865982890 ps |
| CPU time | 259.67 seconds |
| Started | Jul 20 08:10:50 PM PDT 24 |
| Finished | Jul 20 08:15:10 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-2ae91942-9a8e-4898-bf1b-65066039c88d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508125886 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.1508125886 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1548585372 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2828589594 ps |
| CPU time | 240.44 seconds |
| Started | Jul 20 08:11:03 PM PDT 24 |
| Finished | Jul 20 08:15:04 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-ef262d64-69a3-485c-a6bb-7daf309033db |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548585372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1548585372 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4087225192 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2896984280 ps |
| CPU time | 274.66 seconds |
| Started | Jul 20 08:12:49 PM PDT 24 |
| Finished | Jul 20 08:17:24 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-5f716848-f8d4-4df3-8bbd-9eb4cd205be8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872251 92 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4087225192 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.241743665 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 3276271680 ps |
| CPU time | 365.2 seconds |
| Started | Jul 20 08:15:04 PM PDT 24 |
| Finished | Jul 20 08:21:10 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-ea55419a-a7b2-4a50-8ae0-4cfe97ef66b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241743665 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_smoketest.241743665 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3360650697 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 2844708680 ps |
| CPU time | 332.52 seconds |
| Started | Jul 20 08:08:10 PM PDT 24 |
| Finished | Jul 20 08:13:44 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-8b6c4dd4-1f41-43ed-b7ae-7a21e0fe4f19 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360650697 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.3360650697 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2044395676 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 5235079320 ps |
| CPU time | 500.38 seconds |
| Started | Jul 20 08:14:31 PM PDT 24 |
| Finished | Jul 20 08:22:52 PM PDT 24 |
| Peak memory | 610904 kb |
| Host | smart-862b46bf-5c01-484b-8ab5-e0c34dc38de5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2044395676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.2044395676 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3223314410 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 3058504330 ps |
| CPU time | 143.5 seconds |
| Started | Jul 20 08:08:54 PM PDT 24 |
| Finished | Jul 20 08:11:18 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-49e0a0fe-9a38-4e33-a53b-4963346a7c6e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233144 10 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.3223314410 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3475326081 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 5828494958 ps |
| CPU time | 621.53 seconds |
| Started | Jul 20 08:11:26 PM PDT 24 |
| Finished | Jul 20 08:21:49 PM PDT 24 |
| Peak memory | 621056 kb |
| Host | smart-60cb8d2d-fee7-468c-a635-57506bdd3ec1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475326081 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.3475326081 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.373858613 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2485021672 ps |
| CPU time | 110.67 seconds |
| Started | Jul 20 08:09:38 PM PDT 24 |
| Finished | Jul 20 08:11:29 PM PDT 24 |
| Peak memory | 617640 kb |
| Host | smart-f9c3aaea-1642-4580-8963-178fd203ab7f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=373858613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.373858613 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3456656397 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 2302969990 ps |
| CPU time | 111.81 seconds |
| Started | Jul 20 08:09:27 PM PDT 24 |
| Finished | Jul 20 08:11:19 PM PDT 24 |
| Peak memory | 617808 kb |
| Host | smart-e2d1283f-3ad1-49b5-a800-11e5441a2c11 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456656397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3456656397 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3301333734 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 50313103082 ps |
| CPU time | 5584.72 seconds |
| Started | Jul 20 08:07:25 PM PDT 24 |
| Finished | Jul 20 09:40:31 PM PDT 24 |
| Peak memory | 620536 kb |
| Host | smart-c9821b9e-79fc-429c-b59f-c77921e7f328 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301333734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.3301333734 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.4214004647 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 9456395490 ps |
| CPU time | 1193.04 seconds |
| Started | Jul 20 08:09:11 PM PDT 24 |
| Finished | Jul 20 08:29:05 PM PDT 24 |
| Peak memory | 618992 kb |
| Host | smart-5a68eda3-8b9a-447a-a65b-d25a1934c10c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214004647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.4214004647 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1387836247 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 46619489272 ps |
| CPU time | 5731.74 seconds |
| Started | Jul 20 08:09:02 PM PDT 24 |
| Finished | Jul 20 09:44:35 PM PDT 24 |
| Peak memory | 620168 kb |
| Host | smart-350b7ed3-14a3-4207-b6ae-12b98fb55b69 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387836247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.1387836247 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.172885376 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 24587143786 ps |
| CPU time | 2076.92 seconds |
| Started | Jul 20 08:06:43 PM PDT 24 |
| Finished | Jul 20 08:41:20 PM PDT 24 |
| Peak memory | 619756 kb |
| Host | smart-fb0e4c72-b0c1-47db-90f0-3a51c13c1246 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=172885376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testunl ocks.172885376 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2456509388 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 17367958306 ps |
| CPU time | 3576.49 seconds |
| Started | Jul 20 08:11:01 PM PDT 24 |
| Finished | Jul 20 09:10:38 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-49c49bcb-7800-4488-a21c-68b2160c74dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2456509388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2456509388 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3445340793 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 18984225031 ps |
| CPU time | 3826.24 seconds |
| Started | Jul 20 08:08:46 PM PDT 24 |
| Finished | Jul 20 09:12:33 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-1683257b-b15f-4da0-a87f-d370cdfeeb2c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3445340793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3445340793 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.512690655 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 25434267933 ps |
| CPU time | 3690.81 seconds |
| Started | Jul 20 08:12:48 PM PDT 24 |
| Finished | Jul 20 09:14:19 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-4660c5ab-b9fc-448f-b032-1badb6792c8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512690655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduc ed_freq.512690655 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4090150458 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3914881472 ps |
| CPU time | 623.25 seconds |
| Started | Jul 20 08:08:42 PM PDT 24 |
| Finished | Jul 20 08:19:06 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-0cef186c-57b8-49e5-93e9-62ca0f9f4515 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090150458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.4090150458 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1034771736 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 5756102700 ps |
| CPU time | 1033.16 seconds |
| Started | Jul 20 08:08:12 PM PDT 24 |
| Finished | Jul 20 08:25:26 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-f1835b9c-0f0e-447b-afa5-7c59e96571c3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1034771736 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1034771736 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.4277085245 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 5595146812 ps |
| CPU time | 985.47 seconds |
| Started | Jul 20 08:18:45 PM PDT 24 |
| Finished | Jul 20 08:35:11 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-0b09bbcb-d3ad-4ef0-9d43-0036825e557e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277085245 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.4277085245 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3082230206 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 2950385356 ps |
| CPU time | 325.04 seconds |
| Started | Jul 20 08:09:17 PM PDT 24 |
| Finished | Jul 20 08:14:43 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-991d1506-3e96-4c92-bd5e-c5cc9c9f57f5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082230206 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3082230206 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1991436557 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 8813502874 ps |
| CPU time | 1364.93 seconds |
| Started | Jul 20 08:07:26 PM PDT 24 |
| Finished | Jul 20 08:30:12 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-c6c9ea59-cfb4-480f-966e-4e6bb84b5126 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1991436557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.1991436557 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.258748805 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 8599292280 ps |
| CPU time | 1158.49 seconds |
| Started | Jul 20 08:07:21 PM PDT 24 |
| Finished | Jul 20 08:26:40 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-fafa4669-d26a-46b0-9940-94ee10e72117 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=258748805 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.258748805 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.420503469 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 6547763528 ps |
| CPU time | 1167.89 seconds |
| Started | Jul 20 08:08:04 PM PDT 24 |
| Finished | Jul 20 08:27:32 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-307b8848-3a0d-4b16-b115-e7249fdf6731 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=420503469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.420503469 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2380431787 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 4398189792 ps |
| CPU time | 646.7 seconds |
| Started | Jul 20 08:11:53 PM PDT 24 |
| Finished | Jul 20 08:22:40 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-662a7fba-2a03-4904-abf1-cf37755f9f7f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2380431787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2380431787 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1255216100 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 2598293682 ps |
| CPU time | 266.46 seconds |
| Started | Jul 20 08:17:04 PM PDT 24 |
| Finished | Jul 20 08:21:30 PM PDT 24 |
| Peak memory | 609664 kb |
| Host | smart-b792854d-99bd-4d63-b5ee-b5df655c676e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255216100 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1255216100 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1504854233 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2748243472 ps |
| CPU time | 228.86 seconds |
| Started | Jul 20 08:06:17 PM PDT 24 |
| Finished | Jul 20 08:10:07 PM PDT 24 |
| Peak memory | 611228 kb |
| Host | smart-ed63cac3-c18c-4b93-abc2-4a05e3f7d720 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504854233 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1504854233 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.891117334 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3024325586 ps |
| CPU time | 295.72 seconds |
| Started | Jul 20 08:11:28 PM PDT 24 |
| Finished | Jul 20 08:16:24 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-fe0f8e4a-49cd-467b-8e28-523108926a45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891117334 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_plic_sw_irq.891117334 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.3143441818 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 4914864740 ps |
| CPU time | 707.5 seconds |
| Started | Jul 20 08:15:41 PM PDT 24 |
| Finished | Jul 20 08:27:29 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-76bd452e-fccc-49a6-93af-b4596948cc69 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143441818 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.3143441818 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.4106823886 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 10158987904 ps |
| CPU time | 552.96 seconds |
| Started | Jul 20 08:14:28 PM PDT 24 |
| Finished | Jul 20 08:23:41 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-34c07418-48c5-4081-a4e1-fd751421007e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106823886 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4106823886 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3131811784 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 11973386971 ps |
| CPU time | 1594.73 seconds |
| Started | Jul 20 08:08:29 PM PDT 24 |
| Finished | Jul 20 08:35:05 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-515aa8b5-2091-4095-ba46-65304b7c9587 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131 811784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3131811784 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.3625107723 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 30607590733 ps |
| CPU time | 2197.43 seconds |
| Started | Jul 20 08:10:55 PM PDT 24 |
| Finished | Jul 20 08:47:33 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-a7a23689-aab8-4f1e-9336-845b2c9c14ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362 5107723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.3625107723 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3252610595 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 14020176940 ps |
| CPU time | 1187.2 seconds |
| Started | Jul 20 08:13:42 PM PDT 24 |
| Finished | Jul 20 08:33:29 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-db262420-a56b-490f-a82d-665b09ade7ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3252610595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3252610595 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.362278759 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 21714273480 ps |
| CPU time | 1323.31 seconds |
| Started | Jul 20 08:13:15 PM PDT 24 |
| Finished | Jul 20 08:35:18 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-215c4c35-4eef-42db-9d3e-4122a0760853 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 362278759 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.362278759 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.1614219030 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 10092468230 ps |
| CPU time | 500.94 seconds |
| Started | Jul 20 08:07:49 PM PDT 24 |
| Finished | Jul 20 08:16:10 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-353bead9-d918-45fb-9ace-62a159daa3b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614219030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.1614219030 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1748992518 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 10191514067 ps |
| CPU time | 505.79 seconds |
| Started | Jul 20 08:08:07 PM PDT 24 |
| Finished | Jul 20 08:16:33 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-a112dd4a-0618-4028-91fb-2f4c3429cbc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748992518 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1748992518 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3975760158 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 4575669320 ps |
| CPU time | 450.64 seconds |
| Started | Jul 20 08:16:49 PM PDT 24 |
| Finished | Jul 20 08:24:20 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-f2872ece-a75c-4a6a-9d34-9429ecf8c0d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975760158 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.3975760158 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3287092285 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 4811888810 ps |
| CPU time | 402.08 seconds |
| Started | Jul 20 08:08:14 PM PDT 24 |
| Finished | Jul 20 08:14:57 PM PDT 24 |
| Peak memory | 616380 kb |
| Host | smart-5cdf5740-df6d-42b1-b6fd-fa2c1e47d352 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3287092285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3287092285 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.877704071 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 11775927904 ps |
| CPU time | 1162.5 seconds |
| Started | Jul 20 08:10:39 PM PDT 24 |
| Finished | Jul 20 08:30:02 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-a9c4f008-ad01-4399-a596-02f40070fb04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877704071 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.877704071 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3931417168 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 6880782732 ps |
| CPU time | 488.61 seconds |
| Started | Jul 20 08:12:48 PM PDT 24 |
| Finished | Jul 20 08:20:58 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-e79fadd8-3f52-4e80-b104-8bbeb14af77a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931417168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3931417168 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.264290684 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 6689915577 ps |
| CPU time | 515.18 seconds |
| Started | Jul 20 08:13:39 PM PDT 24 |
| Finished | Jul 20 08:22:15 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-68cf6306-db7e-461c-9a7c-292e7fa4bddf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264290684 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.264290684 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4185662688 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 20584854023 ps |
| CPU time | 1774.32 seconds |
| Started | Jul 20 08:08:00 PM PDT 24 |
| Finished | Jul 20 08:37:35 PM PDT 24 |
| Peak memory | 611284 kb |
| Host | smart-ff9d9481-a7a4-410f-9d27-a24b290dbf16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4185662688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4185662688 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3674041192 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 22557643976 ps |
| CPU time | 1053.44 seconds |
| Started | Jul 20 08:12:36 PM PDT 24 |
| Finished | Jul 20 08:30:10 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-4a095977-dfe2-49e3-ae99-0d8b1185ca67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3674041192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3674041192 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2503507203 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 40813583040 ps |
| CPU time | 3382.54 seconds |
| Started | Jul 20 08:08:19 PM PDT 24 |
| Finished | Jul 20 09:04:43 PM PDT 24 |
| Peak memory | 612028 kb |
| Host | smart-963016db-4009-4f62-b8a6-ad8574ed6e70 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503507203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2503507203 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3955078028 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 6179079774 ps |
| CPU time | 668.82 seconds |
| Started | Jul 20 08:13:15 PM PDT 24 |
| Finished | Jul 20 08:24:25 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-0c3d4c46-e4cd-4fc4-b574-3bdcb60cd1d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3955078028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3955078028 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.179180358 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3052710840 ps |
| CPU time | 297.4 seconds |
| Started | Jul 20 08:09:59 PM PDT 24 |
| Finished | Jul 20 08:14:57 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-25b64f2d-1255-43b2-89dd-37247376dcaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179180358 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.179180358 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2960477350 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 6655017983 ps |
| CPU time | 422.77 seconds |
| Started | Jul 20 08:09:38 PM PDT 24 |
| Finished | Jul 20 08:16:42 PM PDT 24 |
| Peak memory | 616520 kb |
| Host | smart-e5297088-851f-4ae2-ab61-30af4de24121 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2960477350 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.2960477350 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2277142280 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 4862293060 ps |
| CPU time | 482.92 seconds |
| Started | Jul 20 08:12:37 PM PDT 24 |
| Finished | Jul 20 08:20:42 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-d803b364-d1c6-49e6-b4bc-be36d14cb727 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22771422 80 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2277142280 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.2718549393 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 5547519330 ps |
| CPU time | 580.21 seconds |
| Started | Jul 20 08:11:54 PM PDT 24 |
| Finished | Jul 20 08:21:35 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-efab60a4-b9a1-4026-a8c4-ea2ccc99e974 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2718549393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.2718549393 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1619245810 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 5030793088 ps |
| CPU time | 344.34 seconds |
| Started | Jul 20 08:16:51 PM PDT 24 |
| Finished | Jul 20 08:22:36 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-285cfee7-1576-42c8-917a-92f0424393e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619245810 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1619245810 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3669691319 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 8900694187 ps |
| CPU time | 1610.24 seconds |
| Started | Jul 20 08:07:32 PM PDT 24 |
| Finished | Jul 20 08:34:22 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-e6acbf2f-b25f-4ceb-bdf2-7b40a201f4bc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669691319 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3669691319 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4100288021 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4768381246 ps |
| CPU time | 387.49 seconds |
| Started | Jul 20 08:13:55 PM PDT 24 |
| Finished | Jul 20 08:20:23 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-ce177a54-e41d-4fb3-873c-4adc43efe631 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100288021 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.4100288021 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1592562513 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 5319268632 ps |
| CPU time | 565.67 seconds |
| Started | Jul 20 08:15:21 PM PDT 24 |
| Finished | Jul 20 08:24:47 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-8f92c90a-e1b3-40c3-90ef-8b580dcb1cc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592562513 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1592562513 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2690770056 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 4862001800 ps |
| CPU time | 583.92 seconds |
| Started | Jul 20 08:10:53 PM PDT 24 |
| Finished | Jul 20 08:20:37 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-ad1376d3-4aee-4d5f-94bb-9744b70c4730 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269 0770056 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2690770056 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2496195252 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 9019515790 ps |
| CPU time | 592.12 seconds |
| Started | Jul 20 08:12:31 PM PDT 24 |
| Finished | Jul 20 08:22:23 PM PDT 24 |
| Peak memory | 623772 kb |
| Host | smart-29db99e6-6417-4488-8599-ea50ecba7646 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496195252 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.2496195252 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.227114180 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 13376836780 ps |
| CPU time | 2116.78 seconds |
| Started | Jul 20 08:07:56 PM PDT 24 |
| Finished | Jul 20 08:43:14 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-b9cae53f-cc00-4b74-a16c-6771f59c04ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=227114180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.227114180 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.3941060518 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 6489774874 ps |
| CPU time | 553.78 seconds |
| Started | Jul 20 08:08:43 PM PDT 24 |
| Finished | Jul 20 08:17:58 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-aa5866a1-19ce-4fea-880b-69d8da02c48b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941060518 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.3941060518 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.427623400 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5661824312 ps |
| CPU time | 608.24 seconds |
| Started | Jul 20 08:05:43 PM PDT 24 |
| Finished | Jul 20 08:15:52 PM PDT 24 |
| Peak memory | 641552 kb |
| Host | smart-b3595e0e-f080-44ac-9fd4-1e95a58d3ca1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 427623400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.427623400 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1108893703 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 2320553256 ps |
| CPU time | 315.08 seconds |
| Started | Jul 20 08:16:30 PM PDT 24 |
| Finished | Jul 20 08:21:45 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-33b4ae2e-f010-4e05-b0c4-a9890df197a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108893703 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.1108893703 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1789052359 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 3893821512 ps |
| CPU time | 494.71 seconds |
| Started | Jul 20 08:06:57 PM PDT 24 |
| Finished | Jul 20 08:15:12 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-17cf238e-10ea-47ec-8076-8890717a3756 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789052359 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1789052359 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.615616042 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3304373834 ps |
| CPU time | 329.42 seconds |
| Started | Jul 20 08:07:25 PM PDT 24 |
| Finished | Jul 20 08:12:54 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-c383cbd7-3f91-43c0-b1ba-0d8daf63e211 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615616042 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.615616042 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3856862548 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3076591400 ps |
| CPU time | 336.53 seconds |
| Started | Jul 20 08:15:39 PM PDT 24 |
| Finished | Jul 20 08:21:16 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-34bb83a5-2655-4252-8445-57974236e2ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3856862548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3856862548 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1072253611 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3018709582 ps |
| CPU time | 252.46 seconds |
| Started | Jul 20 08:14:41 PM PDT 24 |
| Finished | Jul 20 08:18:54 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-16e48e88-1b02-40fa-bfb0-65ef7d6ce2d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072253611 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.1072253611 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3213331579 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 4885530320 ps |
| CPU time | 837.97 seconds |
| Started | Jul 20 08:09:12 PM PDT 24 |
| Finished | Jul 20 08:23:11 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-1a7b3d2e-b6ef-47f6-a672-0353f25caa0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32133 31579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3213331579 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3193468503 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 6254444066 ps |
| CPU time | 1018.24 seconds |
| Started | Jul 20 08:09:02 PM PDT 24 |
| Finished | Jul 20 08:26:01 PM PDT 24 |
| Peak memory | 609888 kb |
| Host | smart-02e01e94-fad0-4b57-9ad6-346ba1fabfaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3193468503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.3193468503 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.656579110 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 4918785786 ps |
| CPU time | 748.14 seconds |
| Started | Jul 20 08:13:36 PM PDT 24 |
| Finished | Jul 20 08:26:05 PM PDT 24 |
| Peak memory | 624100 kb |
| Host | smart-a0e5bdfd-5903-4891-8751-00f4033bc267 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656579110 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.656579110 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.205173768 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 6790354390 ps |
| CPU time | 590.51 seconds |
| Started | Jul 20 08:12:28 PM PDT 24 |
| Finished | Jul 20 08:22:19 PM PDT 24 |
| Peak memory | 620236 kb |
| Host | smart-9be50362-41f5-491c-a0d6-2203520e872f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205173768 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.205173768 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4028844098 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4232979940 ps |
| CPU time | 501.92 seconds |
| Started | Jul 20 08:12:55 PM PDT 24 |
| Finished | Jul 20 08:21:17 PM PDT 24 |
| Peak memory | 619216 kb |
| Host | smart-b71d00af-d9c6-4e68-9254-6070194a4052 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402884 4098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4028844098 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.442780746 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 2853867116 ps |
| CPU time | 298.23 seconds |
| Started | Jul 20 08:15:13 PM PDT 24 |
| Finished | Jul 20 08:20:11 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-1cd94d22-8767-406b-9428-abb5018bcaaf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442780746 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.442780746 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.998611755 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2615308022 ps |
| CPU time | 297.11 seconds |
| Started | Jul 20 08:07:55 PM PDT 24 |
| Finished | Jul 20 08:12:53 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-4f5c65fc-f7a6-4a76-b6db-a700b27a4088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998611755 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_rv_timer_irq.998611755 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4129768123 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2536711504 ps |
| CPU time | 248.54 seconds |
| Started | Jul 20 08:14:54 PM PDT 24 |
| Finished | Jul 20 08:19:03 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-c00fbbdc-e2a0-4e23-a9b3-38d61baf88bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129768123 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.4129768123 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2578231506 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 4818011784 ps |
| CPU time | 556.81 seconds |
| Started | Jul 20 08:11:51 PM PDT 24 |
| Finished | Jul 20 08:21:08 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-7711773b-a33f-4a64-b6e7-1398dd01471a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782315 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.2578231506 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1881611012 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 2811442539 ps |
| CPU time | 294.45 seconds |
| Started | Jul 20 08:13:38 PM PDT 24 |
| Finished | Jul 20 08:18:34 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-ca86f7e4-f2c4-4d74-8905-a53b52ca51ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881611 012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.1881611012 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3028807772 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3919703368 ps |
| CPU time | 324.62 seconds |
| Started | Jul 20 08:07:07 PM PDT 24 |
| Finished | Jul 20 08:12:32 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-f152aa94-c481-43e0-b4d7-0ca88770e5be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028807772 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.3028807772 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3816696977 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 9078000680 ps |
| CPU time | 1412.8 seconds |
| Started | Jul 20 08:07:19 PM PDT 24 |
| Finished | Jul 20 08:30:52 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-a42a338c-4013-437c-8ae9-6a11326d6734 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816696977 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3816696977 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3729757398 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 6497825008 ps |
| CPU time | 459.63 seconds |
| Started | Jul 20 08:11:50 PM PDT 24 |
| Finished | Jul 20 08:19:30 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-f18bac63-7609-42d4-941e-0bdb5fd0584b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729757398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3729757398 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.652849014 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 8033900716 ps |
| CPU time | 623.62 seconds |
| Started | Jul 20 08:15:27 PM PDT 24 |
| Finished | Jul 20 08:25:51 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-ec587701-eb7c-404a-bb94-2e7d8b0d84f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652849014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.652849014 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1841854520 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 6614242925 ps |
| CPU time | 807.05 seconds |
| Started | Jul 20 08:07:19 PM PDT 24 |
| Finished | Jul 20 08:20:47 PM PDT 24 |
| Peak memory | 624852 kb |
| Host | smart-f6dd5c33-da86-459a-9883-2e8fbed2de6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841854520 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1841854520 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2670435398 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 5351649624 ps |
| CPU time | 693.79 seconds |
| Started | Jul 20 08:07:46 PM PDT 24 |
| Finished | Jul 20 08:19:21 PM PDT 24 |
| Peak memory | 624860 kb |
| Host | smart-cbe8bd60-8fe6-4a25-929c-83757ed8d139 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670435398 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2670435398 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3975353624 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3116242369 ps |
| CPU time | 341.04 seconds |
| Started | Jul 20 08:08:05 PM PDT 24 |
| Finished | Jul 20 08:13:47 PM PDT 24 |
| Peak memory | 618420 kb |
| Host | smart-5fd9d592-8358-4242-8358-0ef81729d164 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975353624 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3975353624 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3741750367 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2621111984 ps |
| CPU time | 410.43 seconds |
| Started | Jul 20 08:06:32 PM PDT 24 |
| Finished | Jul 20 08:13:23 PM PDT 24 |
| Peak memory | 608920 kb |
| Host | smart-53e29f66-400e-49c1-8f12-d0ae07b7327a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741750367 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3741750367 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1338990255 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 7369436219 ps |
| CPU time | 614.78 seconds |
| Started | Jul 20 08:12:19 PM PDT 24 |
| Finished | Jul 20 08:22:35 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-997a5e90-7d55-4e03-8ef6-68eee8b041cc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338990255 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1338990255 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.772901232 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 4457795756 ps |
| CPU time | 626.15 seconds |
| Started | Jul 20 08:10:46 PM PDT 24 |
| Finished | Jul 20 08:21:13 PM PDT 24 |
| Peak memory | 609804 kb |
| Host | smart-7e4ade7a-2fc7-4afe-9532-06b3a4cfc6ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772901232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.772901232 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4158956530 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 5349770663 ps |
| CPU time | 591.47 seconds |
| Started | Jul 20 08:10:12 PM PDT 24 |
| Finished | Jul 20 08:20:05 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-02bd5420-9639-4e07-8cf7-25a143d61928 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158956530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4158956530 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.600098972 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5575700282 ps |
| CPU time | 796.19 seconds |
| Started | Jul 20 08:13:18 PM PDT 24 |
| Finished | Jul 20 08:26:35 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-f52366f1-af5c-4a8c-8748-d8fdf6fefc8f |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600098972 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.600098972 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2666600594 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 1933848476 ps |
| CPU time | 176.9 seconds |
| Started | Jul 20 08:15:35 PM PDT 24 |
| Finished | Jul 20 08:18:32 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-c9a74796-c482-46f6-bc4a-aa7c5eca409a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666600594 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2666600594 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3193454141 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 19929824486 ps |
| CPU time | 3239.48 seconds |
| Started | Jul 20 08:09:18 PM PDT 24 |
| Finished | Jul 20 09:03:18 PM PDT 24 |
| Peak memory | 610448 kb |
| Host | smart-9c4d4835-ba2a-4965-b30a-2b6d01518049 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193454141 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.3193454141 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1968626025 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4053045658 ps |
| CPU time | 712.73 seconds |
| Started | Jul 20 08:07:52 PM PDT 24 |
| Finished | Jul 20 08:19:47 PM PDT 24 |
| Peak memory | 613360 kb |
| Host | smart-6b3c1b6c-1c1a-481c-b248-88c065381d5d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968626025 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.1968626025 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3683109788 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 3667627531 ps |
| CPU time | 326.46 seconds |
| Started | Jul 20 08:08:47 PM PDT 24 |
| Finished | Jul 20 08:14:15 PM PDT 24 |
| Peak memory | 613232 kb |
| Host | smart-0f5e2588-e065-4da3-b723-91d930a6b10a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683109788 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.3683109788 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1990433754 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 3437051658 ps |
| CPU time | 380.47 seconds |
| Started | Jul 20 08:08:56 PM PDT 24 |
| Finished | Jul 20 08:15:17 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-884fe1e2-dcbd-41b2-83a6-24fe462b73e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990433754 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1990433754 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1572225614 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 24417574224 ps |
| CPU time | 1834.49 seconds |
| Started | Jul 20 08:08:03 PM PDT 24 |
| Finished | Jul 20 08:38:39 PM PDT 24 |
| Peak memory | 613964 kb |
| Host | smart-c38d24b6-72d9-4415-94b6-1c6c6f105667 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15722256 14 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.1572225614 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1593106901 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4705011436 ps |
| CPU time | 479.86 seconds |
| Started | Jul 20 08:08:49 PM PDT 24 |
| Finished | Jul 20 08:16:49 PM PDT 24 |
| Peak memory | 610472 kb |
| Host | smart-edbd73bb-14a7-47b9-96cd-578aa1c9bcf9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593106901 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1593106901 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.4024872911 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 4256185132 ps |
| CPU time | 582.53 seconds |
| Started | Jul 20 08:07:04 PM PDT 24 |
| Finished | Jul 20 08:16:48 PM PDT 24 |
| Peak memory | 617756 kb |
| Host | smart-cf1b1de1-ca67-42a6-a1e5-d0df79bc00bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4024872911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.4024872911 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.1932320561 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 3579356148 ps |
| CPU time | 247.4 seconds |
| Started | Jul 20 08:15:44 PM PDT 24 |
| Finished | Jul 20 08:19:52 PM PDT 24 |
| Peak memory | 616124 kb |
| Host | smart-57d8a7eb-7350-4961-af7c-0bfcea07931e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932320561 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.1932320561 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.3824563161 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4164122954 ps |
| CPU time | 620.86 seconds |
| Started | Jul 20 08:05:51 PM PDT 24 |
| Finished | Jul 20 08:16:13 PM PDT 24 |
| Peak memory | 623792 kb |
| Host | smart-c4c209e4-ebad-461e-8cba-45d275c6cd97 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824563161 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.3824563161 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2610186766 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3786002133 ps |
| CPU time | 650.36 seconds |
| Started | Jul 20 08:07:10 PM PDT 24 |
| Finished | Jul 20 08:18:02 PM PDT 24 |
| Peak memory | 624680 kb |
| Host | smart-27addd8c-1b0a-447b-8e16-535a23bd4307 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610186766 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.2610186766 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4202373662 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3702237929 ps |
| CPU time | 377.56 seconds |
| Started | Jul 20 08:07:26 PM PDT 24 |
| Finished | Jul 20 08:13:44 PM PDT 24 |
| Peak memory | 624668 kb |
| Host | smart-2632a813-0e15-4a8f-962b-5f3af3b1d831 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202373662 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.4202373662 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1800211725 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 77809339256 ps |
| CPU time | 14199.3 seconds |
| Started | Jul 20 08:07:36 PM PDT 24 |
| Finished | Jul 21 12:04:17 AM PDT 24 |
| Peak memory | 634040 kb |
| Host | smart-e5d81e5d-816f-45a9-bbcc-c8aa02c9a7b8 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1800211725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1800211725 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1246647075 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 4173881678 ps |
| CPU time | 700.01 seconds |
| Started | Jul 20 08:07:15 PM PDT 24 |
| Finished | Jul 20 08:18:57 PM PDT 24 |
| Peak memory | 622516 kb |
| Host | smart-1a04314b-d21b-4d32-887d-5ee9c5090db1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246647075 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1246647075 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1511605494 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 4387479360 ps |
| CPU time | 638.6 seconds |
| Started | Jul 20 08:07:22 PM PDT 24 |
| Finished | Jul 20 08:18:02 PM PDT 24 |
| Peak memory | 623748 kb |
| Host | smart-f03ebd43-849f-43cb-b41a-f8fb495bf8de |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511605494 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.1511605494 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1282610223 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 4842026100 ps |
| CPU time | 697.52 seconds |
| Started | Jul 20 08:05:47 PM PDT 24 |
| Finished | Jul 20 08:17:25 PM PDT 24 |
| Peak memory | 624040 kb |
| Host | smart-21025845-872e-4853-bfb6-0aba3062aa21 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282610223 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1282610223 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3284375253 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 11453726809 ps |
| CPU time | 1238.31 seconds |
| Started | Jul 20 08:11:54 PM PDT 24 |
| Finished | Jul 20 08:32:33 PM PDT 24 |
| Peak memory | 620908 kb |
| Host | smart-f41f696d-5a32-4f08-8129-294522594e34 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3284375253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3284375253 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.3847294169 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 1985334506 ps |
| CPU time | 147.48 seconds |
| Started | Jul 20 08:13:44 PM PDT 24 |
| Finished | Jul 20 08:16:13 PM PDT 24 |
| Peak memory | 621424 kb |
| Host | smart-e261cf90-37bc-4807-a514-a51e3864e5bd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847294169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.3847294169 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1411998834 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 2634332771 ps |
| CPU time | 222.43 seconds |
| Started | Jul 20 08:12:18 PM PDT 24 |
| Finished | Jul 20 08:16:02 PM PDT 24 |
| Peak memory | 620812 kb |
| Host | smart-31fd9cef-0585-4679-8a64-dd396faccb23 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1411998834 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1411998834 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.1936321531 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 14855989366 ps |
| CPU time | 3550.76 seconds |
| Started | Jul 20 08:18:20 PM PDT 24 |
| Finished | Jul 20 09:17:32 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-25746b05-1b1d-4ea1-ad4d-7d30f94ff7e2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936321531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.1936321531 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.3716448906 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 15791434385 ps |
| CPU time | 3735.89 seconds |
| Started | Jul 20 08:19:58 PM PDT 24 |
| Finished | Jul 20 09:22:14 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-17777784-46a2-43b3-a0d3-d8f09fdc80ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716448906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.3716448906 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3278760841 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 15805993659 ps |
| CPU time | 3428.78 seconds |
| Started | Jul 20 08:19:11 PM PDT 24 |
| Finished | Jul 20 09:16:21 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-c09db856-9a40-4557-86cd-b3449ae64437 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278760841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.3278760841 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.300048752 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 14233013694 ps |
| CPU time | 3046.24 seconds |
| Started | Jul 20 08:20:59 PM PDT 24 |
| Finished | Jul 20 09:11:46 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-c7d4cf93-1adc-4dd1-b2c6-5ffdede867c5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300048752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.300048752 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3177141057 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 11674918077 ps |
| CPU time | 2891.03 seconds |
| Started | Jul 20 08:21:47 PM PDT 24 |
| Finished | Jul 20 09:10:00 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-0d9d181b-03a8-4696-af16-f057654952d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177141057 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.3177141057 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.573913101 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 14913215240 ps |
| CPU time | 2891.55 seconds |
| Started | Jul 20 08:22:20 PM PDT 24 |
| Finished | Jul 20 09:10:52 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-74418238-1a2b-444f-a735-e20ad1a8ed0f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573913101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.573913101 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3341752187 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15298055050 ps |
| CPU time | 3832.09 seconds |
| Started | Jul 20 08:20:30 PM PDT 24 |
| Finished | Jul 20 09:24:23 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-dc86d4e2-866e-4dae-8868-323432c70d05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341752187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.3341752187 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.674476181 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 15121502048 ps |
| CPU time | 3456.07 seconds |
| Started | Jul 20 08:19:46 PM PDT 24 |
| Finished | Jul 20 09:17:23 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-1a5447cb-ed58-4be2-9cb5-cd378f6870bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674476181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_ no_meas.674476181 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.580761336 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 25396579536 ps |
| CPU time | 5151.5 seconds |
| Started | Jul 20 08:20:42 PM PDT 24 |
| Finished | Jul 20 09:46:35 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-916cd90f-2eae-45ef-8129-ab92207e130a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580761336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.580761336 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3499213792 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 14603408840 ps |
| CPU time | 2862.96 seconds |
| Started | Jul 20 08:19:21 PM PDT 24 |
| Finished | Jul 20 09:07:04 PM PDT 24 |
| Peak memory | 611380 kb |
| Host | smart-a0e702d1-47fb-40fb-9b53-4d6f87c90595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499213792 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.3499213792 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1636251863 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 25965103394 ps |
| CPU time | 3295.62 seconds |
| Started | Jul 20 08:20:52 PM PDT 24 |
| Finished | Jul 20 09:15:48 PM PDT 24 |
| Peak memory | 611892 kb |
| Host | smart-c63184d0-e8bf-4190-8c13-8451a567b366 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636251863 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1636251863 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.4176939096 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 15712495160 ps |
| CPU time | 3386.55 seconds |
| Started | Jul 20 08:19:31 PM PDT 24 |
| Finished | Jul 20 09:15:59 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-802cdfae-d09a-4ab3-8b61-eea61e5bbcd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=4176939096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.4176939096 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2988895294 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 17709905324 ps |
| CPU time | 3880.19 seconds |
| Started | Jul 20 08:18:40 PM PDT 24 |
| Finished | Jul 20 09:23:21 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-3e23cdbf-6689-4035-83db-caa686950243 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988895294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2988895294 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.2675824358 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4421860400 ps |
| CPU time | 519.56 seconds |
| Started | Jul 20 08:14:02 PM PDT 24 |
| Finished | Jul 20 08:22:43 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-8e0a57ac-d2d9-4913-abc1-e6215ef23bfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675824358 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.2675824358 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.2045112911 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 6027933907 ps |
| CPU time | 240.78 seconds |
| Started | Jul 20 08:17:42 PM PDT 24 |
| Finished | Jul 20 08:21:43 PM PDT 24 |
| Peak memory | 623844 kb |
| Host | smart-246664d1-3c94-41a0-8d61-3d5dbaa13c74 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2045112911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2045112911 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2904906973 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2219627049 ps |
| CPU time | 103.2 seconds |
| Started | Jul 20 08:15:00 PM PDT 24 |
| Finished | Jul 20 08:16:43 PM PDT 24 |
| Peak memory | 617636 kb |
| Host | smart-5c9b21a0-d3c5-4ada-b7ed-56660f91dcb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904906973 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2904906973 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.2122205763 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5317100720 ps |
| CPU time | 605.16 seconds |
| Started | Jul 20 08:19:57 PM PDT 24 |
| Finished | Jul 20 08:30:03 PM PDT 24 |
| Peak memory | 650036 kb |
| Host | smart-54b67930-bbd3-486a-9cef-b62042f237af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2122205763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.2122205763 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.915122992 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3832857704 ps |
| CPU time | 352.88 seconds |
| Started | Jul 20 08:23:17 PM PDT 24 |
| Finished | Jul 20 08:29:44 PM PDT 24 |
| Peak memory | 648780 kb |
| Host | smart-71c37088-929c-4876-95b4-72adb040bb80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915122992 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_s w_alert_handler_lpg_sleep_mode_alerts.915122992 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1770597883 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 6480922688 ps |
| CPU time | 737.05 seconds |
| Started | Jul 20 08:21:52 PM PDT 24 |
| Finished | Jul 20 08:34:10 PM PDT 24 |
| Peak memory | 619712 kb |
| Host | smart-e3735d0b-6fae-4a1e-9f06-26ef07a054a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1770597883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1770597883 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.659041880 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 3906834380 ps |
| CPU time | 370.61 seconds |
| Started | Jul 20 08:22:31 PM PDT 24 |
| Finished | Jul 20 08:29:36 PM PDT 24 |
| Peak memory | 648760 kb |
| Host | smart-0866e1fc-9e31-4bc2-b5b8-a2eda9780975 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659041880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.659041880 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1127374091 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5794174832 ps |
| CPU time | 623.57 seconds |
| Started | Jul 20 08:22:26 PM PDT 24 |
| Finished | Jul 20 08:33:38 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-a0049ba6-8509-43b2-a6be-5b61f9d5e870 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1127374091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1127374091 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.444825272 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4734100840 ps |
| CPU time | 615.85 seconds |
| Started | Jul 20 08:18:27 PM PDT 24 |
| Finished | Jul 20 08:28:44 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-2fd9cad3-efcb-48c2-af17-5346aaf93854 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 444825272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.444825272 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2970851425 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 7205856784 ps |
| CPU time | 516.48 seconds |
| Started | Jul 20 08:16:11 PM PDT 24 |
| Finished | Jul 20 08:24:48 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-c8667c40-ecef-4250-8812-e795294dca34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2970851425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2970851425 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3936521955 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 17066144348 ps |
| CPU time | 3850.7 seconds |
| Started | Jul 20 08:17:13 PM PDT 24 |
| Finished | Jul 20 09:21:25 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-db441a30-f9b6-4f97-a099-863ecabc5467 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936521955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.3936521955 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.794135393 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 6927631260 ps |
| CPU time | 881.07 seconds |
| Started | Jul 20 08:15:54 PM PDT 24 |
| Finished | Jul 20 08:30:36 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-d89cbc64-2e5f-4b24-89b7-b78c5498c56f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=794135393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.794135393 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2682114488 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 11045238781 ps |
| CPU time | 758.58 seconds |
| Started | Jul 20 08:16:25 PM PDT 24 |
| Finished | Jul 20 08:29:04 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-8ec1737c-f6fd-4439-9ef5-9d3af77188ae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682114488 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2682114488 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3929130307 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 4115040960 ps |
| CPU time | 532.64 seconds |
| Started | Jul 20 08:16:49 PM PDT 24 |
| Finished | Jul 20 08:25:42 PM PDT 24 |
| Peak memory | 617780 kb |
| Host | smart-91e28262-236a-4a7a-b9f6-13e71fc29e00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3929130307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3929130307 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.1135035783 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 4686535746 ps |
| CPU time | 799.16 seconds |
| Started | Jul 20 08:16:56 PM PDT 24 |
| Finished | Jul 20 08:30:16 PM PDT 24 |
| Peak memory | 624024 kb |
| Host | smart-542c57e0-a877-4074-8c76-b08b5937c9b4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135035783 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.1135035783 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.729254237 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 8603992458 ps |
| CPU time | 1112.47 seconds |
| Started | Jul 20 08:17:31 PM PDT 24 |
| Finished | Jul 20 08:36:05 PM PDT 24 |
| Peak memory | 624660 kb |
| Host | smart-fa5563b6-a244-46e2-be95-bdab75110ceb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729254237 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.729254237 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2575134642 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 5164443760 ps |
| CPU time | 605.51 seconds |
| Started | Jul 20 08:15:49 PM PDT 24 |
| Finished | Jul 20 08:25:55 PM PDT 24 |
| Peak memory | 624076 kb |
| Host | smart-49481cd8-46ba-4bb6-a778-e7874cca4e86 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575134642 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2575134642 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2596484506 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 3867122344 ps |
| CPU time | 499.25 seconds |
| Started | Jul 20 08:18:24 PM PDT 24 |
| Finished | Jul 20 08:26:44 PM PDT 24 |
| Peak memory | 623752 kb |
| Host | smart-2faf0515-1114-4788-a9ab-39e9efe08ea1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596484506 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.2596484506 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3919028791 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 3866238344 ps |
| CPU time | 777.8 seconds |
| Started | Jul 20 08:17:11 PM PDT 24 |
| Finished | Jul 20 08:30:09 PM PDT 24 |
| Peak memory | 623732 kb |
| Host | smart-806e7772-8d8f-4a6b-9387-b21a20adb361 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919028791 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.3919028791 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.3262398266 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8683227186 ps |
| CPU time | 1114.57 seconds |
| Started | Jul 20 08:15:45 PM PDT 24 |
| Finished | Jul 20 08:34:20 PM PDT 24 |
| Peak memory | 620976 kb |
| Host | smart-480f4cc4-8ebc-4807-b60c-b74c71a41c60 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3262398266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3262398266 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3824927476 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 2877354403 ps |
| CPU time | 175.1 seconds |
| Started | Jul 20 08:15:48 PM PDT 24 |
| Finished | Jul 20 08:18:43 PM PDT 24 |
| Peak memory | 620952 kb |
| Host | smart-efbff587-1cd8-4bd6-bfe4-afe7b56ae7be |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824927476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3824927476 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.29836385 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 5541654863 ps |
| CPU time | 417.45 seconds |
| Started | Jul 20 08:15:05 PM PDT 24 |
| Finished | Jul 20 08:22:03 PM PDT 24 |
| Peak memory | 620924 kb |
| Host | smart-3c3fe598-03a6-4b34-8763-b14c00ccdeee |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836385 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.29836385 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.3718997989 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3561383126 ps |
| CPU time | 328.27 seconds |
| Started | Jul 20 08:16:20 PM PDT 24 |
| Finished | Jul 20 08:21:49 PM PDT 24 |
| Peak memory | 620880 kb |
| Host | smart-5b45faa1-e28b-41db-b629-2bd3322d39d1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3718997989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.3718997989 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.837475180 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4101668920 ps |
| CPU time | 318.74 seconds |
| Started | Jul 20 08:21:14 PM PDT 24 |
| Finished | Jul 20 08:26:33 PM PDT 24 |
| Peak memory | 648788 kb |
| Host | smart-edf80c4c-882c-48b1-b4cd-014bece695e0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837475180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.837475180 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.127213739 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5583093230 ps |
| CPU time | 881.85 seconds |
| Started | Jul 20 08:21:21 PM PDT 24 |
| Finished | Jul 20 08:36:03 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-a411222b-0e40-4016-8aa6-1509642a4607 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 127213739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.127213739 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295017242 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 3933960520 ps |
| CPU time | 351.97 seconds |
| Started | Jul 20 08:21:00 PM PDT 24 |
| Finished | Jul 20 08:26:53 PM PDT 24 |
| Peak memory | 649052 kb |
| Host | smart-f1491256-ca2b-4340-932b-7ca331e9c8af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295017242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1295017242 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.2385321235 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 4775081456 ps |
| CPU time | 572.16 seconds |
| Started | Jul 20 08:21:48 PM PDT 24 |
| Finished | Jul 20 08:31:20 PM PDT 24 |
| Peak memory | 649968 kb |
| Host | smart-19740a5c-89f9-49c6-9e86-f29864ca4c72 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2385321235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.2385321235 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1104409870 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 3852290840 ps |
| CPU time | 331.4 seconds |
| Started | Jul 20 08:21:26 PM PDT 24 |
| Finished | Jul 20 08:26:58 PM PDT 24 |
| Peak memory | 648800 kb |
| Host | smart-7110a61a-7ef1-443d-88d8-7ad7db3dd9a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104409870 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1104409870 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233765363 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3668176696 ps |
| CPU time | 466.29 seconds |
| Started | Jul 20 08:20:51 PM PDT 24 |
| Finished | Jul 20 08:28:38 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-ee8af07e-f385-4a70-8d7b-425a0864952a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233765363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2233765363 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.4059219627 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 6262877064 ps |
| CPU time | 749.26 seconds |
| Started | Jul 20 08:21:14 PM PDT 24 |
| Finished | Jul 20 08:33:44 PM PDT 24 |
| Peak memory | 649976 kb |
| Host | smart-5f2b8a9b-af0f-413e-b621-1ec6cc70c791 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4059219627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.4059219627 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2783140599 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 4527969338 ps |
| CPU time | 621.81 seconds |
| Started | Jul 20 08:23:39 PM PDT 24 |
| Finished | Jul 20 08:34:15 PM PDT 24 |
| Peak memory | 616764 kb |
| Host | smart-560539c2-7dbd-4105-ab0a-a6fb4167e7f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2783140599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2783140599 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.1384737926 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 5782441754 ps |
| CPU time | 588.71 seconds |
| Started | Jul 20 08:21:22 PM PDT 24 |
| Finished | Jul 20 08:31:11 PM PDT 24 |
| Peak memory | 619696 kb |
| Host | smart-0badc3f6-4853-46ea-a903-d7dc4fac3930 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1384737926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.1384737926 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.409809739 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4889428968 ps |
| CPU time | 551.01 seconds |
| Started | Jul 20 08:24:05 PM PDT 24 |
| Finished | Jul 20 08:33:16 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-c36b41ef-255f-44cf-b2df-1f0e19eda3e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 409809739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.409809739 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3171723156 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3745004472 ps |
| CPU time | 362.36 seconds |
| Started | Jul 20 08:23:24 PM PDT 24 |
| Finished | Jul 20 08:29:54 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-42a77d51-fd68-4759-a3d8-9b92486f8f22 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171723156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3171723156 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3106724419 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4571094892 ps |
| CPU time | 587.98 seconds |
| Started | Jul 20 08:24:30 PM PDT 24 |
| Finished | Jul 20 08:34:19 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-a1860d0f-fa39-470d-ac68-6c223518e910 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3106724419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3106724419 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.814598088 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5938499120 ps |
| CPU time | 375.82 seconds |
| Started | Jul 20 08:16:43 PM PDT 24 |
| Finished | Jul 20 08:22:59 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-f1076353-bc0f-447c-aeba-f455ba3c978b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=814598088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.814598088 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.241705153 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 27794461624 ps |
| CPU time | 6157.97 seconds |
| Started | Jul 20 08:20:15 PM PDT 24 |
| Finished | Jul 20 10:02:55 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-6848e04c-abd8-4324-a366-e9181517b029 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241705153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.241705153 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.847386734 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 5339126490 ps |
| CPU time | 789.41 seconds |
| Started | Jul 20 08:16:39 PM PDT 24 |
| Finished | Jul 20 08:29:49 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-8a39b014-2f04-4115-bdad-714a1d42f7e5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=847386734 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.847386734 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2427869122 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 10604799860 ps |
| CPU time | 1251.34 seconds |
| Started | Jul 20 08:17:07 PM PDT 24 |
| Finished | Jul 20 08:37:59 PM PDT 24 |
| Peak memory | 621348 kb |
| Host | smart-34e595cd-c78b-4b72-913e-2dba1470b026 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427869122 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2427869122 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1945395906 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 7661607896 ps |
| CPU time | 734.86 seconds |
| Started | Jul 20 08:19:11 PM PDT 24 |
| Finished | Jul 20 08:31:27 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-ebf08919-f5c5-42d8-850f-68146b38e7ad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453959 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.1945395906 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1921969817 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 13128343400 ps |
| CPU time | 2473.84 seconds |
| Started | Jul 20 08:16:04 PM PDT 24 |
| Finished | Jul 20 08:57:19 PM PDT 24 |
| Peak memory | 618464 kb |
| Host | smart-db34507b-6442-4471-a67f-68ad550fe648 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1921969817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.1921969817 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3888357890 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4024326510 ps |
| CPU time | 668.17 seconds |
| Started | Jul 20 08:16:19 PM PDT 24 |
| Finished | Jul 20 08:27:28 PM PDT 24 |
| Peak memory | 623816 kb |
| Host | smart-13c6a984-3727-4d75-ba52-2546178bae78 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888357890 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3888357890 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3099517219 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 8462334430 ps |
| CPU time | 1455.39 seconds |
| Started | Jul 20 08:16:17 PM PDT 24 |
| Finished | Jul 20 08:40:33 PM PDT 24 |
| Peak memory | 622156 kb |
| Host | smart-efc0494c-3f4e-40bf-8a8f-047bbcb7cc9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099517219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3099517219 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3210359178 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 8391349219 ps |
| CPU time | 1064.78 seconds |
| Started | Jul 20 08:16:57 PM PDT 24 |
| Finished | Jul 20 08:34:43 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-f41b7b39-4175-4de0-8fa1-fe9622a1777d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210359178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3210359178 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3500060602 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4419818904 ps |
| CPU time | 673.03 seconds |
| Started | Jul 20 08:16:49 PM PDT 24 |
| Finished | Jul 20 08:28:03 PM PDT 24 |
| Peak memory | 624116 kb |
| Host | smart-0fd218f1-9b1b-44cc-a96b-0eccfa6976bc |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500060602 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3500060602 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.569444451 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 3983035132 ps |
| CPU time | 585.37 seconds |
| Started | Jul 20 08:18:02 PM PDT 24 |
| Finished | Jul 20 08:27:48 PM PDT 24 |
| Peak memory | 623736 kb |
| Host | smart-6781734b-ef6a-450e-bc38-5c3277734c79 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569444451 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.569444451 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1388887914 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 4225078734 ps |
| CPU time | 563.07 seconds |
| Started | Jul 20 08:18:05 PM PDT 24 |
| Finished | Jul 20 08:27:28 PM PDT 24 |
| Peak memory | 622504 kb |
| Host | smart-2db433f0-52b4-4e78-abcd-fb76ddce5d7a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388887914 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1388887914 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2672164092 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 3338946831 ps |
| CPU time | 250.27 seconds |
| Started | Jul 20 08:16:28 PM PDT 24 |
| Finished | Jul 20 08:20:39 PM PDT 24 |
| Peak memory | 621036 kb |
| Host | smart-e2a5587f-a29b-453f-bc69-e01e08132b83 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2672164092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2672164092 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.4070008828 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 4817102492 ps |
| CPU time | 469.91 seconds |
| Started | Jul 20 08:17:48 PM PDT 24 |
| Finished | Jul 20 08:25:38 PM PDT 24 |
| Peak memory | 630360 kb |
| Host | smart-ae7a67a1-a721-4fdd-b1d7-5aad1ecd095c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070008828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.4070008828 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.3022749610 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 3278364949 ps |
| CPU time | 227.93 seconds |
| Started | Jul 20 08:15:55 PM PDT 24 |
| Finished | Jul 20 08:19:44 PM PDT 24 |
| Peak memory | 620968 kb |
| Host | smart-23203a45-5f38-4bae-a072-138fc431492d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3022749610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.3022749610 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1463852694 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 4422085800 ps |
| CPU time | 415.38 seconds |
| Started | Jul 20 08:22:05 PM PDT 24 |
| Finished | Jul 20 08:29:00 PM PDT 24 |
| Peak memory | 649084 kb |
| Host | smart-e4f921c3-b2e8-4166-850d-35d804322a8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463852694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1463852694 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.257731164 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5486035552 ps |
| CPU time | 760.05 seconds |
| Started | Jul 20 08:24:00 PM PDT 24 |
| Finished | Jul 20 08:36:41 PM PDT 24 |
| Peak memory | 649944 kb |
| Host | smart-e9c67f2c-16fd-489a-ab3f-f615494c7934 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 257731164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.257731164 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2769233475 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 4407069744 ps |
| CPU time | 459.41 seconds |
| Started | Jul 20 08:22:56 PM PDT 24 |
| Finished | Jul 20 08:31:22 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-26f98e38-6e88-4430-87fe-4c942826ceb0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769233475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2769233475 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010986621 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 3806302132 ps |
| CPU time | 392.08 seconds |
| Started | Jul 20 08:24:33 PM PDT 24 |
| Finished | Jul 20 08:31:06 PM PDT 24 |
| Peak memory | 648728 kb |
| Host | smart-475a2bc9-3fbe-43fe-b4ee-ab32d2633d93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010986621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3010986621 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1326916209 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5513787792 ps |
| CPU time | 637.26 seconds |
| Started | Jul 20 08:22:17 PM PDT 24 |
| Finished | Jul 20 08:32:58 PM PDT 24 |
| Peak memory | 650008 kb |
| Host | smart-9b2db567-1ad9-4b29-88c8-098c9c1f8c5d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1326916209 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1326916209 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.561539210 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5329426300 ps |
| CPU time | 707.73 seconds |
| Started | Jul 20 08:21:58 PM PDT 24 |
| Finished | Jul 20 08:33:46 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-5e189ac1-4d25-4a4b-9015-811a663f5de6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 561539210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.561539210 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.2246098251 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 5070438596 ps |
| CPU time | 519.32 seconds |
| Started | Jul 20 08:22:39 PM PDT 24 |
| Finished | Jul 20 08:32:13 PM PDT 24 |
| Peak memory | 649812 kb |
| Host | smart-26f567cf-76be-4989-9895-4fb0704ecb2e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2246098251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.2246098251 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3516686594 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 5799938748 ps |
| CPU time | 749.23 seconds |
| Started | Jul 20 08:22:20 PM PDT 24 |
| Finished | Jul 20 08:35:24 PM PDT 24 |
| Peak memory | 649892 kb |
| Host | smart-b3f32091-97cf-469f-baa5-dda131b2c536 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3516686594 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3516686594 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.3295066957 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5696507020 ps |
| CPU time | 696.38 seconds |
| Started | Jul 20 08:23:12 PM PDT 24 |
| Finished | Jul 20 08:35:26 PM PDT 24 |
| Peak memory | 650056 kb |
| Host | smart-647e4dd7-e8f6-4937-9bf3-02770bd6565d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3295066957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.3295066957 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.459822646 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3640190536 ps |
| CPU time | 392.71 seconds |
| Started | Jul 20 08:23:12 PM PDT 24 |
| Finished | Jul 20 08:30:23 PM PDT 24 |
| Peak memory | 648700 kb |
| Host | smart-0641a648-883a-4804-9f3d-6de3248fd9d1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459822646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_s w_alert_handler_lpg_sleep_mode_alerts.459822646 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2547921788 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 5114731840 ps |
| CPU time | 673.77 seconds |
| Started | Jul 20 08:22:35 PM PDT 24 |
| Finished | Jul 20 08:34:43 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-0f623001-9c33-41d0-91ad-cce422bfd039 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2547921788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2547921788 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520270293 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3938264424 ps |
| CPU time | 461.9 seconds |
| Started | Jul 20 08:18:42 PM PDT 24 |
| Finished | Jul 20 08:26:25 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-0112e89a-b9fc-43ef-8072-a2a179cca5fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520270293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1520270293 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2539324735 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5923667564 ps |
| CPU time | 793.32 seconds |
| Started | Jul 20 08:20:26 PM PDT 24 |
| Finished | Jul 20 08:33:41 PM PDT 24 |
| Peak memory | 619704 kb |
| Host | smart-a5041a5f-109a-4518-953f-01138966edfd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2539324735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2539324735 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1768372113 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 21634515808 ps |
| CPU time | 4364.43 seconds |
| Started | Jul 20 08:18:06 PM PDT 24 |
| Finished | Jul 20 09:30:51 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-bc49c236-2849-4f7e-85fa-afaa36a28000 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768372113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.1768372113 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2591837382 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5353403668 ps |
| CPU time | 610.04 seconds |
| Started | Jul 20 08:17:15 PM PDT 24 |
| Finished | Jul 20 08:27:25 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-c7ae81b4-ce32-4302-a626-f54c504dbbf0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2591837382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2591837382 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1519323042 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 12313422292 ps |
| CPU time | 680.87 seconds |
| Started | Jul 20 08:17:23 PM PDT 24 |
| Finished | Jul 20 08:28:44 PM PDT 24 |
| Peak memory | 623828 kb |
| Host | smart-23ae5f47-a3d3-420d-8a7e-2053b9c16022 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519323042 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.1519323042 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2441341334 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 3822675720 ps |
| CPU time | 399.99 seconds |
| Started | Jul 20 08:16:45 PM PDT 24 |
| Finished | Jul 20 08:23:25 PM PDT 24 |
| Peak memory | 618596 kb |
| Host | smart-ca730629-2050-4a13-b79e-ed83ceae31ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2441341334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.2441341334 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.704769192 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3392371590 ps |
| CPU time | 304.52 seconds |
| Started | Jul 20 08:23:16 PM PDT 24 |
| Finished | Jul 20 08:28:55 PM PDT 24 |
| Peak memory | 648856 kb |
| Host | smart-2418d1a8-5fd6-4870-8215-412b6b2f5083 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704769192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_s w_alert_handler_lpg_sleep_mode_alerts.704769192 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.3043701126 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 4401325970 ps |
| CPU time | 574.21 seconds |
| Started | Jul 20 08:22:58 PM PDT 24 |
| Finished | Jul 20 08:33:18 PM PDT 24 |
| Peak memory | 650052 kb |
| Host | smart-24311e31-5f74-4533-916b-2041eda2b470 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3043701126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.3043701126 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3657734853 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 5076039064 ps |
| CPU time | 585.96 seconds |
| Started | Jul 20 08:24:28 PM PDT 24 |
| Finished | Jul 20 08:34:15 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-229658e4-369e-4954-abcc-b24d889c4719 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3657734853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3657734853 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.1948990544 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5835448432 ps |
| CPU time | 636.54 seconds |
| Started | Jul 20 08:22:56 PM PDT 24 |
| Finished | Jul 20 08:34:19 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-8de63673-096b-411a-906d-48cc887d836f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1948990544 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.1948990544 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.1490952368 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3967448134 ps |
| CPU time | 560.24 seconds |
| Started | Jul 20 08:27:04 PM PDT 24 |
| Finished | Jul 20 08:36:25 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-6acfa3d5-139d-4053-9795-3695d8a08ffa |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1490952368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.1490952368 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001543232 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3505855850 ps |
| CPU time | 325.8 seconds |
| Started | Jul 20 08:22:19 PM PDT 24 |
| Finished | Jul 20 08:28:06 PM PDT 24 |
| Peak memory | 648876 kb |
| Host | smart-c3b3b139-436e-40ca-8657-c163ed84db72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001543232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3001543232 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447310315 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3632263548 ps |
| CPU time | 380.01 seconds |
| Started | Jul 20 08:22:44 PM PDT 24 |
| Finished | Jul 20 08:29:58 PM PDT 24 |
| Peak memory | 648844 kb |
| Host | smart-1d53d7cc-610b-475b-8395-aa2e7895b5b8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447310315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3447310315 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3859362968 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5994863826 ps |
| CPU time | 929.29 seconds |
| Started | Jul 20 08:23:35 PM PDT 24 |
| Finished | Jul 20 08:39:22 PM PDT 24 |
| Peak memory | 650096 kb |
| Host | smart-96a3a9e8-ce05-4ae0-80f0-63cd654b2de9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3859362968 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3859362968 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931960891 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3791600930 ps |
| CPU time | 333.74 seconds |
| Started | Jul 20 08:26:20 PM PDT 24 |
| Finished | Jul 20 08:31:54 PM PDT 24 |
| Peak memory | 649028 kb |
| Host | smart-e85d5aab-18d6-484a-8e0d-a0d020a68ca5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931960891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2931960891 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552206452 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3036673900 ps |
| CPU time | 350.25 seconds |
| Started | Jul 20 08:31:02 PM PDT 24 |
| Finished | Jul 20 08:36:52 PM PDT 24 |
| Peak memory | 648836 kb |
| Host | smart-8fcb73ae-8898-4ccd-a809-3a0dd4c3a555 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552206452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3552206452 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.719776584 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4903999000 ps |
| CPU time | 655.4 seconds |
| Started | Jul 20 08:23:10 PM PDT 24 |
| Finished | Jul 20 08:34:44 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-c3d33cc3-d50b-4ccf-ae16-70db8994f2fe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 719776584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.719776584 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.828804521 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 3764896420 ps |
| CPU time | 472.94 seconds |
| Started | Jul 20 08:31:04 PM PDT 24 |
| Finished | Jul 20 08:38:57 PM PDT 24 |
| Peak memory | 648588 kb |
| Host | smart-fe6a71c2-d99b-4d7c-947c-db1a133ecc6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828804521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_s w_alert_handler_lpg_sleep_mode_alerts.828804521 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.130003813 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6343601752 ps |
| CPU time | 619.69 seconds |
| Started | Jul 20 08:22:39 PM PDT 24 |
| Finished | Jul 20 08:33:55 PM PDT 24 |
| Peak memory | 650124 kb |
| Host | smart-83243364-5b19-4b5f-98b9-9c2cf1eb6992 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 130003813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.130003813 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1579531430 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 3836671056 ps |
| CPU time | 403.36 seconds |
| Started | Jul 20 08:17:06 PM PDT 24 |
| Finished | Jul 20 08:23:50 PM PDT 24 |
| Peak memory | 648428 kb |
| Host | smart-b745a0d6-d50c-4271-a163-8e464f4392be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579531430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.1579531430 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1562848825 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 18798110248 ps |
| CPU time | 3783.2 seconds |
| Started | Jul 20 08:20:50 PM PDT 24 |
| Finished | Jul 20 09:23:54 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-9715d419-8e2b-4505-8a23-2746e3818b52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562848825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1562848825 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.932136873 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 8454062210 ps |
| CPU time | 1331.76 seconds |
| Started | Jul 20 08:18:29 PM PDT 24 |
| Finished | Jul 20 08:40:41 PM PDT 24 |
| Peak memory | 618772 kb |
| Host | smart-08e4c851-ea3b-4d7a-bda2-e0d48f5623e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=932136873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.932136873 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454036173 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3561113764 ps |
| CPU time | 392.5 seconds |
| Started | Jul 20 08:25:21 PM PDT 24 |
| Finished | Jul 20 08:31:54 PM PDT 24 |
| Peak memory | 648752 kb |
| Host | smart-132397d6-ce26-45c9-a8a1-e5c48a35ebba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454036173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2454036173 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3460688983 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4010312000 ps |
| CPU time | 548.42 seconds |
| Started | Jul 20 08:30:04 PM PDT 24 |
| Finished | Jul 20 08:39:13 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-f9ab2675-7f29-4add-8a67-fc6b7d8f8c1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460688983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3460688983 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.3686377173 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 5934534248 ps |
| CPU time | 620.63 seconds |
| Started | Jul 20 08:23:19 PM PDT 24 |
| Finished | Jul 20 08:34:12 PM PDT 24 |
| Peak memory | 649984 kb |
| Host | smart-fbd00ae0-0746-4443-9fed-4e6c37d0264d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3686377173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3686377173 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.869446121 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4048282296 ps |
| CPU time | 582.45 seconds |
| Started | Jul 20 08:23:04 PM PDT 24 |
| Finished | Jul 20 08:33:28 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-069ecb6f-8eb9-4452-9af2-ea2ed036a3aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869446121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.869446121 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982228354 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 3081755062 ps |
| CPU time | 392.98 seconds |
| Started | Jul 20 08:24:17 PM PDT 24 |
| Finished | Jul 20 08:30:51 PM PDT 24 |
| Peak memory | 648616 kb |
| Host | smart-df5528cb-ca4d-4658-98a4-cd4e1e7f4ca5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982228354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3982228354 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152032983 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3739470800 ps |
| CPU time | 356.67 seconds |
| Started | Jul 20 08:24:22 PM PDT 24 |
| Finished | Jul 20 08:30:19 PM PDT 24 |
| Peak memory | 648480 kb |
| Host | smart-57558b0a-3897-4fcc-9f63-4b937fef6130 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152032983 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4152032983 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455163096 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 4481953480 ps |
| CPU time | 387.98 seconds |
| Started | Jul 20 08:24:44 PM PDT 24 |
| Finished | Jul 20 08:31:13 PM PDT 24 |
| Peak memory | 648832 kb |
| Host | smart-a6f190b9-e9c4-48c8-b77e-4c518e3ce3c1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455163096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2455163096 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.2068912927 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 6071509978 ps |
| CPU time | 767.27 seconds |
| Started | Jul 20 08:23:05 PM PDT 24 |
| Finished | Jul 20 08:36:34 PM PDT 24 |
| Peak memory | 616868 kb |
| Host | smart-afe8ee3b-3ff8-419a-b100-01ef3250e59e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2068912927 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2068912927 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725672110 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3816281528 ps |
| CPU time | 369.88 seconds |
| Started | Jul 20 08:23:54 PM PDT 24 |
| Finished | Jul 20 08:30:05 PM PDT 24 |
| Peak memory | 648604 kb |
| Host | smart-09d27e5b-f4b4-4e74-83f1-39a53b4eb6fa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725672110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2725672110 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194959650 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 4579004088 ps |
| CPU time | 449.83 seconds |
| Started | Jul 20 08:23:51 PM PDT 24 |
| Finished | Jul 20 08:31:24 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-82524a49-2d9a-4095-ad01-259540ac7147 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194959650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4194959650 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.3377873322 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 5563909584 ps |
| CPU time | 632.93 seconds |
| Started | Jul 20 08:25:48 PM PDT 24 |
| Finished | Jul 20 08:36:22 PM PDT 24 |
| Peak memory | 616860 kb |
| Host | smart-78d9607e-1f41-4a89-b8b0-37d1843c2c89 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3377873322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.3377873322 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658134656 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4067106432 ps |
| CPU time | 544.33 seconds |
| Started | Jul 20 08:18:34 PM PDT 24 |
| Finished | Jul 20 08:27:39 PM PDT 24 |
| Peak memory | 648676 kb |
| Host | smart-0005e700-5d75-4b80-9323-fa085c4247e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658134656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3658134656 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.4266520473 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 4861369836 ps |
| CPU time | 550.5 seconds |
| Started | Jul 20 08:20:33 PM PDT 24 |
| Finished | Jul 20 08:29:44 PM PDT 24 |
| Peak memory | 650020 kb |
| Host | smart-39827d3e-2ce9-4d2a-b650-00b5d8289f02 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4266520473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.4266520473 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3858384600 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 21739833740 ps |
| CPU time | 4107.42 seconds |
| Started | Jul 20 08:18:45 PM PDT 24 |
| Finished | Jul 20 09:27:14 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-75691010-9521-4fb5-8863-d394e43b837a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858384600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3858384600 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1416449461 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 10535763310 ps |
| CPU time | 911.08 seconds |
| Started | Jul 20 08:19:06 PM PDT 24 |
| Finished | Jul 20 08:34:18 PM PDT 24 |
| Peak memory | 622984 kb |
| Host | smart-69975b31-9780-40a9-9f7c-1c988e3f8d53 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416449461 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.1416449461 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.439343643 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 13346669406 ps |
| CPU time | 2057.81 seconds |
| Started | Jul 20 08:18:21 PM PDT 24 |
| Finished | Jul 20 08:52:40 PM PDT 24 |
| Peak memory | 618680 kb |
| Host | smart-39c40fc4-7e85-43a3-b2f3-bb39f1201c99 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=439343643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.439343643 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4279727299 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 3478967288 ps |
| CPU time | 277.17 seconds |
| Started | Jul 20 08:22:38 PM PDT 24 |
| Finished | Jul 20 08:28:11 PM PDT 24 |
| Peak memory | 648532 kb |
| Host | smart-a0eb3417-8144-4294-894a-5c8bd22195a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279727299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4279727299 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.3606090643 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 6154578164 ps |
| CPU time | 507.41 seconds |
| Started | Jul 20 08:23:50 PM PDT 24 |
| Finished | Jul 20 08:32:22 PM PDT 24 |
| Peak memory | 649944 kb |
| Host | smart-a52d871b-7e47-4b80-a06a-eb1c1f0173f7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3606090643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.3606090643 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862196173 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4179393024 ps |
| CPU time | 374.01 seconds |
| Started | Jul 20 08:25:36 PM PDT 24 |
| Finished | Jul 20 08:31:50 PM PDT 24 |
| Peak memory | 649104 kb |
| Host | smart-d59ed666-4ab6-487b-8871-494f6ad81c3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862196173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2862196173 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.1657303505 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4269014916 ps |
| CPU time | 543.44 seconds |
| Started | Jul 20 08:24:32 PM PDT 24 |
| Finished | Jul 20 08:33:36 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-872c5438-c6f6-465c-a22a-2daabfdd845d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1657303505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1657303505 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809745559 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 4182598398 ps |
| CPU time | 422.69 seconds |
| Started | Jul 20 08:23:56 PM PDT 24 |
| Finished | Jul 20 08:31:00 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-e3d48018-7045-4fc9-a34b-cb9e2fcbe6c0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809745559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1809745559 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.949962063 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 4075707400 ps |
| CPU time | 664.59 seconds |
| Started | Jul 20 08:24:52 PM PDT 24 |
| Finished | Jul 20 08:35:57 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-5977975c-29de-44ca-8bfd-c404148f3f9b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 949962063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.949962063 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021346348 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 3288124392 ps |
| CPU time | 351.62 seconds |
| Started | Jul 20 08:26:29 PM PDT 24 |
| Finished | Jul 20 08:32:21 PM PDT 24 |
| Peak memory | 648516 kb |
| Host | smart-2f7928dc-1173-4d13-b2ad-eced37c0c500 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021346348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3021346348 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.2729227796 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5647920000 ps |
| CPU time | 654.71 seconds |
| Started | Jul 20 08:24:40 PM PDT 24 |
| Finished | Jul 20 08:35:35 PM PDT 24 |
| Peak memory | 650048 kb |
| Host | smart-d6c058a0-5188-4f05-a031-0b7e00f5fb31 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2729227796 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.2729227796 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491705263 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3857829910 ps |
| CPU time | 390.45 seconds |
| Started | Jul 20 08:25:31 PM PDT 24 |
| Finished | Jul 20 08:32:01 PM PDT 24 |
| Peak memory | 648892 kb |
| Host | smart-054dec19-de7a-4cec-84db-f80efe33e414 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491705263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3491705263 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1667787655 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4439396000 ps |
| CPU time | 596.89 seconds |
| Started | Jul 20 08:24:07 PM PDT 24 |
| Finished | Jul 20 08:34:06 PM PDT 24 |
| Peak memory | 650124 kb |
| Host | smart-789fbc3d-5324-47fe-bee1-2f27aca9a81c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1667787655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1667787655 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2917349181 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4228431780 ps |
| CPU time | 285.9 seconds |
| Started | Jul 20 08:26:31 PM PDT 24 |
| Finished | Jul 20 08:31:17 PM PDT 24 |
| Peak memory | 648504 kb |
| Host | smart-a0512c84-6712-4a4f-b75b-4e2e7661a725 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917349181 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2917349181 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2142437256 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 5558297392 ps |
| CPU time | 634.1 seconds |
| Started | Jul 20 08:24:35 PM PDT 24 |
| Finished | Jul 20 08:35:09 PM PDT 24 |
| Peak memory | 649768 kb |
| Host | smart-12d594a3-283b-4731-95ef-e9a4c3810c15 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2142437256 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2142437256 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318979652 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 4026918850 ps |
| CPU time | 528.11 seconds |
| Started | Jul 20 08:24:38 PM PDT 24 |
| Finished | Jul 20 08:33:27 PM PDT 24 |
| Peak memory | 649036 kb |
| Host | smart-168f9b0e-d36a-484c-b221-25194c5773f7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318979652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3318979652 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1277025411 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 5079936184 ps |
| CPU time | 464.47 seconds |
| Started | Jul 20 08:26:38 PM PDT 24 |
| Finished | Jul 20 08:34:23 PM PDT 24 |
| Peak memory | 649956 kb |
| Host | smart-51c47182-a44b-4e9a-adf6-1ad2769f5216 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1277025411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1277025411 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120578479 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3179925116 ps |
| CPU time | 393.61 seconds |
| Started | Jul 20 08:24:35 PM PDT 24 |
| Finished | Jul 20 08:31:09 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-ffe4aef2-3658-46d7-b9cb-3be13734794a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120578479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4120578479 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.2404725847 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6014579880 ps |
| CPU time | 415.56 seconds |
| Started | Jul 20 08:24:41 PM PDT 24 |
| Finished | Jul 20 08:31:37 PM PDT 24 |
| Peak memory | 619656 kb |
| Host | smart-3ebbce56-dbd9-4dad-ada7-9107263efbb2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2404725847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.2404725847 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.922951640 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 3282433290 ps |
| CPU time | 318.32 seconds |
| Started | Jul 20 08:25:28 PM PDT 24 |
| Finished | Jul 20 08:30:47 PM PDT 24 |
| Peak memory | 648852 kb |
| Host | smart-fe4609a1-e572-41f9-89d0-cb86c0eedf8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922951640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.922951640 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1019306677 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 6464383552 ps |
| CPU time | 644.64 seconds |
| Started | Jul 20 08:25:31 PM PDT 24 |
| Finished | Jul 20 08:36:16 PM PDT 24 |
| Peak memory | 649972 kb |
| Host | smart-d70ba3d2-441d-44ab-ad2d-38893670c5d0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1019306677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1019306677 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3068031982 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3899644830 ps |
| CPU time | 425.81 seconds |
| Started | Jul 20 08:25:21 PM PDT 24 |
| Finished | Jul 20 08:32:27 PM PDT 24 |
| Peak memory | 648852 kb |
| Host | smart-62712821-56a6-4ee5-89e3-fd89bf348d88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068031982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3068031982 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879928341 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3410950844 ps |
| CPU time | 322.98 seconds |
| Started | Jul 20 08:18:09 PM PDT 24 |
| Finished | Jul 20 08:23:32 PM PDT 24 |
| Peak memory | 648864 kb |
| Host | smart-d4782906-2df1-43f0-be6d-63702dded2aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879928341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2879928341 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.2962417308 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 4896799400 ps |
| CPU time | 501.67 seconds |
| Started | Jul 20 08:18:32 PM PDT 24 |
| Finished | Jul 20 08:26:54 PM PDT 24 |
| Peak memory | 619752 kb |
| Host | smart-3479c99c-312a-4b6d-93a0-bd3be86e1061 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2962417308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.2962417308 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.930323361 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 16432863070 ps |
| CPU time | 3710.31 seconds |
| Started | Jul 20 08:18:39 PM PDT 24 |
| Finished | Jul 20 09:20:30 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-59cb1069-3452-40c9-95bf-6daae7637080 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930323361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.930323361 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1308492754 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 12649172321 ps |
| CPU time | 919.82 seconds |
| Started | Jul 20 08:17:36 PM PDT 24 |
| Finished | Jul 20 08:32:56 PM PDT 24 |
| Peak memory | 621788 kb |
| Host | smart-cf6f671a-7b8d-48d2-8f2b-ef93ff4854dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308492754 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1308492754 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.526759493 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4275462648 ps |
| CPU time | 499.62 seconds |
| Started | Jul 20 08:18:28 PM PDT 24 |
| Finished | Jul 20 08:26:48 PM PDT 24 |
| Peak memory | 617768 kb |
| Host | smart-c310278e-1a2c-443a-a389-b971077503a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=526759493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.526759493 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767300552 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3224788396 ps |
| CPU time | 367.7 seconds |
| Started | Jul 20 08:27:22 PM PDT 24 |
| Finished | Jul 20 08:33:30 PM PDT 24 |
| Peak memory | 648916 kb |
| Host | smart-7d10b378-25d1-440b-b325-c0f0afc85bf7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767300552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2767300552 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1408579053 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 5097707440 ps |
| CPU time | 483.21 seconds |
| Started | Jul 20 08:25:31 PM PDT 24 |
| Finished | Jul 20 08:33:35 PM PDT 24 |
| Peak memory | 616784 kb |
| Host | smart-d3393987-126d-4b16-9219-0fc034cdf854 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1408579053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1408579053 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278073634 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 3404269880 ps |
| CPU time | 351.62 seconds |
| Started | Jul 20 08:26:25 PM PDT 24 |
| Finished | Jul 20 08:32:17 PM PDT 24 |
| Peak memory | 618832 kb |
| Host | smart-4ea1a898-6758-445f-9fbb-e0cd8278e797 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278073634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2278073634 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3246697595 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 4804518712 ps |
| CPU time | 552.6 seconds |
| Started | Jul 20 08:24:45 PM PDT 24 |
| Finished | Jul 20 08:33:58 PM PDT 24 |
| Peak memory | 650076 kb |
| Host | smart-81214aad-69a8-4eea-a8ae-b731468f3947 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3246697595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3246697595 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242544580 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3687202890 ps |
| CPU time | 383.83 seconds |
| Started | Jul 20 08:25:09 PM PDT 24 |
| Finished | Jul 20 08:31:34 PM PDT 24 |
| Peak memory | 648500 kb |
| Host | smart-bcd4fcd8-f65e-4105-b11a-9cd774e72ef5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242544580 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4242544580 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.6246501 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 5135406860 ps |
| CPU time | 439.62 seconds |
| Started | Jul 20 08:24:55 PM PDT 24 |
| Finished | Jul 20 08:32:15 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-cfc354ea-ac42-4bf3-80b9-1dd94390c7e0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 6246501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.6246501 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2587599747 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3668285636 ps |
| CPU time | 406.08 seconds |
| Started | Jul 20 08:25:55 PM PDT 24 |
| Finished | Jul 20 08:32:41 PM PDT 24 |
| Peak memory | 649064 kb |
| Host | smart-40417aff-8797-4c99-9b8e-59c1f1bcfbe0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587599747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2587599747 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383175367 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3630080096 ps |
| CPU time | 390.58 seconds |
| Started | Jul 20 08:24:45 PM PDT 24 |
| Finished | Jul 20 08:31:16 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-51fa4987-6538-4d18-9a51-6a73db1eae06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383175367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2383175367 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3865842241 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 6095351000 ps |
| CPU time | 621.7 seconds |
| Started | Jul 20 08:23:55 PM PDT 24 |
| Finished | Jul 20 08:34:17 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-cc1047ad-9ccf-4cab-8ead-9b7de4971876 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3865842241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3865842241 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.2536594636 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 5205302312 ps |
| CPU time | 535.6 seconds |
| Started | Jul 20 08:24:09 PM PDT 24 |
| Finished | Jul 20 08:33:06 PM PDT 24 |
| Peak memory | 619692 kb |
| Host | smart-f7d98fc2-d15d-45c3-8b23-971ed3198fb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2536594636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.2536594636 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562002077 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3541721422 ps |
| CPU time | 339.02 seconds |
| Started | Jul 20 08:24:43 PM PDT 24 |
| Finished | Jul 20 08:30:23 PM PDT 24 |
| Peak memory | 648552 kb |
| Host | smart-b8205a21-a7fe-4119-86d9-845c10698cc9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562002077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2562002077 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1785248491 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 5595811774 ps |
| CPU time | 707.43 seconds |
| Started | Jul 20 08:24:35 PM PDT 24 |
| Finished | Jul 20 08:36:23 PM PDT 24 |
| Peak memory | 650016 kb |
| Host | smart-ce017b5d-a22d-427a-baa9-fe7db1e35579 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1785248491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1785248491 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3950900378 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 3916205144 ps |
| CPU time | 384.79 seconds |
| Started | Jul 20 08:26:11 PM PDT 24 |
| Finished | Jul 20 08:32:36 PM PDT 24 |
| Peak memory | 648528 kb |
| Host | smart-1d089286-1062-44bf-94f1-57d43bcfe25a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950900378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3950900378 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.1716763247 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 6269569832 ps |
| CPU time | 571.64 seconds |
| Started | Jul 20 08:25:17 PM PDT 24 |
| Finished | Jul 20 08:34:49 PM PDT 24 |
| Peak memory | 650068 kb |
| Host | smart-b06122ab-cc99-4473-ae04-f6ac4380a4e3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1716763247 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.1716763247 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483759658 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3648073156 ps |
| CPU time | 281.05 seconds |
| Started | Jul 20 08:28:56 PM PDT 24 |
| Finished | Jul 20 08:33:38 PM PDT 24 |
| Peak memory | 648480 kb |
| Host | smart-606cc941-b8e2-4424-a9df-e4ea81d7ea43 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483759658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3483759658 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.323661837 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 5353043096 ps |
| CPU time | 475.37 seconds |
| Started | Jul 20 08:24:53 PM PDT 24 |
| Finished | Jul 20 08:32:49 PM PDT 24 |
| Peak memory | 650004 kb |
| Host | smart-8ac6f06f-604b-43be-9152-a6a2ec5a3555 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 323661837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.323661837 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219828690 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4377388408 ps |
| CPU time | 346.11 seconds |
| Started | Jul 20 08:24:26 PM PDT 24 |
| Finished | Jul 20 08:30:12 PM PDT 24 |
| Peak memory | 649348 kb |
| Host | smart-108f359f-0ab7-4c44-a1fc-1e35049687a9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219828690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1219828690 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2255936540 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5591358340 ps |
| CPU time | 630.33 seconds |
| Started | Jul 20 08:26:46 PM PDT 24 |
| Finished | Jul 20 08:37:16 PM PDT 24 |
| Peak memory | 616768 kb |
| Host | smart-48cf8320-3c36-4e06-99f8-3b3cf8f557d8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2255936540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2255936540 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066894640 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 3722864808 ps |
| CPU time | 374.69 seconds |
| Started | Jul 20 08:19:24 PM PDT 24 |
| Finished | Jul 20 08:25:39 PM PDT 24 |
| Peak memory | 648848 kb |
| Host | smart-0e2ba3bd-68fa-4600-955e-7683f8a1e0f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066894640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.1066894640 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.1207482096 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5241404878 ps |
| CPU time | 661.65 seconds |
| Started | Jul 20 08:19:29 PM PDT 24 |
| Finished | Jul 20 08:30:31 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-e32eb7d6-fad6-40b0-9bd5-af6e5da0a837 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1207482096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.1207482096 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.836559491 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 15904530600 ps |
| CPU time | 3113.82 seconds |
| Started | Jul 20 08:19:19 PM PDT 24 |
| Finished | Jul 20 09:11:14 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-db12a19f-11ac-4893-a710-e8710a947ad5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836559491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.836559491 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1749035998 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 7172441427 ps |
| CPU time | 500.21 seconds |
| Started | Jul 20 08:17:37 PM PDT 24 |
| Finished | Jul 20 08:25:57 PM PDT 24 |
| Peak memory | 624756 kb |
| Host | smart-4ea8b175-d30f-464b-8db0-70823d1c0958 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749035998 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.1749035998 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3592369239 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 3936734080 ps |
| CPU time | 446.54 seconds |
| Started | Jul 20 08:18:55 PM PDT 24 |
| Finished | Jul 20 08:26:22 PM PDT 24 |
| Peak memory | 618596 kb |
| Host | smart-7e523ab7-c8b4-4268-a383-23ae1dcbde14 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3592369239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3592369239 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2418515949 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5899397240 ps |
| CPU time | 690.76 seconds |
| Started | Jul 20 08:25:05 PM PDT 24 |
| Finished | Jul 20 08:36:37 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-e27d5391-ae98-465d-aaf9-02849e7ca522 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2418515949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2418515949 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.2523709184 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 4764506946 ps |
| CPU time | 481.81 seconds |
| Started | Jul 20 08:24:51 PM PDT 24 |
| Finished | Jul 20 08:32:53 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-9d4b755a-0d74-477a-a2bf-a6b9150382b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2523709184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.2523709184 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.811384292 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 5834362456 ps |
| CPU time | 611.66 seconds |
| Started | Jul 20 08:26:52 PM PDT 24 |
| Finished | Jul 20 08:37:04 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-7a5fc33c-ae9b-447b-8585-1c96c16756d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 811384292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.811384292 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.3882108614 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 4337749330 ps |
| CPU time | 535.09 seconds |
| Started | Jul 20 08:24:53 PM PDT 24 |
| Finished | Jul 20 08:33:48 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-c440b299-7e99-43e0-8d46-73911bef905f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3882108614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.3882108614 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.1189282362 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 4493854752 ps |
| CPU time | 574.41 seconds |
| Started | Jul 20 08:28:59 PM PDT 24 |
| Finished | Jul 20 08:38:34 PM PDT 24 |
| Peak memory | 649912 kb |
| Host | smart-fd4d2922-e1cf-42a3-87b2-4f2e6409b538 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1189282362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.1189282362 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.2161887463 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 5821028178 ps |
| CPU time | 690.08 seconds |
| Started | Jul 20 08:24:54 PM PDT 24 |
| Finished | Jul 20 08:36:25 PM PDT 24 |
| Peak memory | 650004 kb |
| Host | smart-b3edb470-87dc-488e-9e2e-e7e93b965933 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2161887463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.2161887463 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.2435459882 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4880010452 ps |
| CPU time | 566.14 seconds |
| Started | Jul 20 08:26:03 PM PDT 24 |
| Finished | Jul 20 08:35:30 PM PDT 24 |
| Peak memory | 650024 kb |
| Host | smart-7f2c1174-6a04-4c9c-91a2-9ee93783b3ea |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2435459882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.2435459882 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.145449058 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 5535420876 ps |
| CPU time | 630.32 seconds |
| Started | Jul 20 08:28:18 PM PDT 24 |
| Finished | Jul 20 08:38:49 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-1d850a09-6248-4da3-ba34-b527c4a11484 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 145449058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.145449058 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3060219978 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 5974390616 ps |
| CPU time | 733.89 seconds |
| Started | Jul 20 08:24:29 PM PDT 24 |
| Finished | Jul 20 08:36:43 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-0503c2c1-9b9c-4445-b626-5dda49cc21b7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3060219978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3060219978 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1452800166 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3762038000 ps |
| CPU time | 174.39 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:44:45 PM PDT 24 |
| Peak memory | 654304 kb |
| Host | smart-52658a7e-93bd-45ce-b061-8a4187c0d13b |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452800166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1452800166 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.747808695 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5121140141 ps |
| CPU time | 225.46 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:45:36 PM PDT 24 |
| Peak memory | 649096 kb |
| Host | smart-9e0540c0-4a59-435e-8c35-e275c979296a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747808695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.747808695 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4039200814 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 5284559002 ps |
| CPU time | 246.63 seconds |
| Started | Jul 20 07:41:32 PM PDT 24 |
| Finished | Jul 20 07:45:58 PM PDT 24 |
| Peak memory | 657344 kb |
| Host | smart-71707b2f-c632-4549-9f45-b577e25ce6ec |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039200814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.4039200814 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.264792659 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 5771284512 ps |
| CPU time | 307.18 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:46:58 PM PDT 24 |
| Peak memory | 649188 kb |
| Host | smart-a50265d2-b459-4625-a476-7ce5052f83fa |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264792659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 4.chip_padctrl_attributes.264792659 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4027032859 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4667073856 ps |
| CPU time | 177.27 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:44:48 PM PDT 24 |
| Peak memory | 641200 kb |
| Host | smart-620afbe9-7c02-4aa4-9f19-4f227b65a931 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027032859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.4027032859 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.268207362 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 5815907938 ps |
| CPU time | 332.48 seconds |
| Started | Jul 20 07:41:31 PM PDT 24 |
| Finished | Jul 20 07:47:24 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-ad7f6b0a-b1ce-460c-a385-64629e8d6d45 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268207362 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 7.chip_padctrl_attributes.268207362 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2860518876 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 5130929542 ps |
| CPU time | 227.34 seconds |
| Started | Jul 20 07:41:37 PM PDT 24 |
| Finished | Jul 20 07:45:40 PM PDT 24 |
| Peak memory | 640916 kb |
| Host | smart-653efd01-d8e5-4cf7-8757-e4728a8526d8 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860518876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2860518876 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1140481835 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4997750715 ps |
| CPU time | 249.41 seconds |
| Started | Jul 20 07:41:37 PM PDT 24 |
| Finished | Jul 20 07:46:03 PM PDT 24 |
| Peak memory | 654792 kb |
| Host | smart-5c283947-057f-4090-93fb-a1f2e55563d0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140481835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1140481835 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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