| T138 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.227603802 |
|
|
Jul 22 08:14:34 PM PDT 24 |
Jul 22 08:27:48 PM PDT 24 |
5544062138 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2460566247 |
|
|
Jul 22 08:30:26 PM PDT 24 |
Jul 22 08:55:23 PM PDT 24 |
9448368664 ps |
| T121 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2920931676 |
|
|
Jul 22 08:20:11 PM PDT 24 |
Jul 22 08:38:17 PM PDT 24 |
5522785021 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.912575358 |
|
|
Jul 22 08:14:07 PM PDT 24 |
Jul 22 09:35:13 PM PDT 24 |
18755982500 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3034549078 |
|
|
Jul 22 08:15:03 PM PDT 24 |
Jul 22 08:24:14 PM PDT 24 |
5070401035 ps |
| T941 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.354613714 |
|
|
Jul 22 08:30:15 PM PDT 24 |
Jul 22 08:59:08 PM PDT 24 |
7167312424 ps |
| T710 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.602160957 |
|
|
Jul 22 08:44:28 PM PDT 24 |
Jul 22 08:59:28 PM PDT 24 |
5757381574 ps |
| T259 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.853400250 |
|
|
Jul 22 08:22:21 PM PDT 24 |
Jul 22 08:27:41 PM PDT 24 |
3298969614 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1537654545 |
|
|
Jul 22 08:16:48 PM PDT 24 |
Jul 22 09:41:27 PM PDT 24 |
46627060119 ps |
| T942 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3546842020 |
|
|
Jul 22 08:21:26 PM PDT 24 |
Jul 22 08:29:24 PM PDT 24 |
5459429894 ps |
| T943 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.574042837 |
|
|
Jul 22 08:27:38 PM PDT 24 |
Jul 22 08:34:53 PM PDT 24 |
3646507764 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1150288617 |
|
|
Jul 22 08:26:13 PM PDT 24 |
Jul 22 08:31:10 PM PDT 24 |
2890637163 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1232534426 |
|
|
Jul 22 08:27:05 PM PDT 24 |
Jul 22 08:41:51 PM PDT 24 |
5145466746 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1474123217 |
|
|
Jul 22 08:29:28 PM PDT 24 |
Jul 22 08:46:48 PM PDT 24 |
7253881388 ps |
| T945 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.417331831 |
|
|
Jul 22 08:39:39 PM PDT 24 |
Jul 22 09:31:40 PM PDT 24 |
14153130673 ps |
| T946 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3213599651 |
|
|
Jul 22 08:23:43 PM PDT 24 |
Jul 22 09:01:48 PM PDT 24 |
9262966648 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3833413505 |
|
|
Jul 22 08:31:20 PM PDT 24 |
Jul 22 08:34:18 PM PDT 24 |
1986126252 ps |
| T794 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1314263056 |
|
|
Jul 22 08:42:15 PM PDT 24 |
Jul 22 08:56:27 PM PDT 24 |
5235716464 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1952516464 |
|
|
Jul 22 08:18:16 PM PDT 24 |
Jul 22 09:00:05 PM PDT 24 |
11758859100 ps |
| T289 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.118500539 |
|
|
Jul 22 08:37:44 PM PDT 24 |
Jul 22 08:46:57 PM PDT 24 |
6042715744 ps |
| T674 |
/workspace/coverage/default/2.chip_sw_edn_kat.3497169329 |
|
|
Jul 22 08:32:12 PM PDT 24 |
Jul 22 08:41:09 PM PDT 24 |
3345380088 ps |
| T450 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3988237832 |
|
|
Jul 22 08:26:08 PM PDT 24 |
Jul 22 08:30:29 PM PDT 24 |
3353333280 ps |
| T278 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3324063235 |
|
|
Jul 22 08:11:14 PM PDT 24 |
Jul 22 08:13:07 PM PDT 24 |
2448851403 ps |
| T949 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2443695242 |
|
|
Jul 22 08:36:27 PM PDT 24 |
Jul 22 08:40:50 PM PDT 24 |
3204119760 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4084460730 |
|
|
Jul 22 08:14:15 PM PDT 24 |
Jul 22 08:18:29 PM PDT 24 |
2630904159 ps |
| T951 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.657777749 |
|
|
Jul 22 08:35:27 PM PDT 24 |
Jul 22 08:46:32 PM PDT 24 |
4344282912 ps |
| T204 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.474236698 |
|
|
Jul 22 08:29:59 PM PDT 24 |
Jul 22 11:11:48 PM PDT 24 |
59237099810 ps |
| T803 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3182610742 |
|
|
Jul 22 08:17:15 PM PDT 24 |
Jul 22 08:22:39 PM PDT 24 |
3766808580 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3805493343 |
|
|
Jul 22 08:31:23 PM PDT 24 |
Jul 22 08:58:38 PM PDT 24 |
25477440316 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.237932560 |
|
|
Jul 22 08:23:21 PM PDT 24 |
Jul 22 08:28:50 PM PDT 24 |
3253495215 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2680878717 |
|
|
Jul 22 08:24:32 PM PDT 24 |
Jul 22 08:42:43 PM PDT 24 |
8821326538 ps |
| T954 |
/workspace/coverage/default/1.rom_e2e_self_hash.355060246 |
|
|
Jul 22 08:41:32 PM PDT 24 |
Jul 22 10:18:28 PM PDT 24 |
25287586152 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1551137529 |
|
|
Jul 22 08:34:18 PM PDT 24 |
Jul 22 08:38:30 PM PDT 24 |
2658271600 ps |
| T133 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4169335370 |
|
|
Jul 22 08:38:08 PM PDT 24 |
Jul 22 08:54:33 PM PDT 24 |
6914656480 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2724086563 |
|
|
Jul 22 08:29:05 PM PDT 24 |
Jul 22 09:25:36 PM PDT 24 |
18189133560 ps |
| T759 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.180443734 |
|
|
Jul 22 08:44:11 PM PDT 24 |
Jul 22 08:51:30 PM PDT 24 |
3811908448 ps |
| T758 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1084369322 |
|
|
Jul 22 08:42:18 PM PDT 24 |
Jul 22 08:53:16 PM PDT 24 |
6366750946 ps |
| T956 |
/workspace/coverage/default/0.rom_e2e_self_hash.571064443 |
|
|
Jul 22 08:30:42 PM PDT 24 |
Jul 22 10:03:28 PM PDT 24 |
26206887450 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3318167223 |
|
|
Jul 22 08:11:43 PM PDT 24 |
Jul 22 08:18:39 PM PDT 24 |
3297134826 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3446634832 |
|
|
Jul 22 08:11:43 PM PDT 24 |
Jul 22 08:30:12 PM PDT 24 |
8990356300 ps |
| T959 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1988843121 |
|
|
Jul 22 08:35:11 PM PDT 24 |
Jul 22 08:45:29 PM PDT 24 |
3932163564 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.951641588 |
|
|
Jul 22 08:30:16 PM PDT 24 |
Jul 22 08:38:25 PM PDT 24 |
6210838476 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1235221585 |
|
|
Jul 22 08:32:03 PM PDT 24 |
Jul 22 08:43:04 PM PDT 24 |
4276986960 ps |
| T962 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2654208359 |
|
|
Jul 22 08:20:55 PM PDT 24 |
Jul 22 08:28:56 PM PDT 24 |
6239153996 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.395825196 |
|
|
Jul 22 08:11:09 PM PDT 24 |
Jul 22 11:01:38 PM PDT 24 |
58472373997 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2229743478 |
|
|
Jul 22 08:15:06 PM PDT 24 |
Jul 22 08:20:28 PM PDT 24 |
2486137640 ps |
| T279 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.154162293 |
|
|
Jul 22 08:20:35 PM PDT 24 |
Jul 22 09:24:35 PM PDT 24 |
14562965363 ps |
| T771 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.168156268 |
|
|
Jul 22 08:45:14 PM PDT 24 |
Jul 22 08:54:26 PM PDT 24 |
4591789700 ps |
| T725 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1263648229 |
|
|
Jul 22 08:11:42 PM PDT 24 |
Jul 22 08:35:39 PM PDT 24 |
8938805074 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_edn_kat.3938171495 |
|
|
Jul 22 08:29:01 PM PDT 24 |
Jul 22 08:41:23 PM PDT 24 |
3768076800 ps |
| T334 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2711749540 |
|
|
Jul 22 08:39:01 PM PDT 24 |
Jul 22 09:01:23 PM PDT 24 |
8249569008 ps |
| T206 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.328784547 |
|
|
Jul 22 08:10:58 PM PDT 24 |
Jul 22 11:57:13 PM PDT 24 |
78217417219 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1104593927 |
|
|
Jul 22 08:31:28 PM PDT 24 |
Jul 22 09:46:13 PM PDT 24 |
47653647394 ps |
| T760 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.150067064 |
|
|
Jul 22 08:40:07 PM PDT 24 |
Jul 22 08:45:26 PM PDT 24 |
4102821662 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2546520350 |
|
|
Jul 22 08:14:26 PM PDT 24 |
Jul 22 08:19:28 PM PDT 24 |
3307845216 ps |
| T280 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4026517361 |
|
|
Jul 22 08:22:16 PM PDT 24 |
Jul 22 09:30:23 PM PDT 24 |
14431233902 ps |
| T461 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2913933553 |
|
|
Jul 22 08:14:50 PM PDT 24 |
Jul 22 08:36:28 PM PDT 24 |
7531247706 ps |
| T160 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2868838938 |
|
|
Jul 22 08:31:06 PM PDT 24 |
Jul 22 08:40:38 PM PDT 24 |
4000508104 ps |
| T965 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1729701035 |
|
|
Jul 22 08:38:20 PM PDT 24 |
Jul 22 08:57:30 PM PDT 24 |
11226547099 ps |
| T323 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.319874619 |
|
|
Jul 22 08:28:54 PM PDT 24 |
Jul 22 08:45:19 PM PDT 24 |
5924437496 ps |
| T731 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2654566130 |
|
|
Jul 22 08:20:18 PM PDT 24 |
Jul 22 08:54:41 PM PDT 24 |
11303475935 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.852852947 |
|
|
Jul 22 08:26:42 PM PDT 24 |
Jul 22 08:39:26 PM PDT 24 |
3928315208 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1093750953 |
|
|
Jul 22 08:18:48 PM PDT 24 |
Jul 22 08:23:05 PM PDT 24 |
2629254080 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3117750397 |
|
|
Jul 22 08:26:06 PM PDT 24 |
Jul 22 09:10:59 PM PDT 24 |
9575243102 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1406767185 |
|
|
Jul 22 08:23:14 PM PDT 24 |
Jul 22 08:28:36 PM PDT 24 |
3029689853 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3682412043 |
|
|
Jul 22 08:14:44 PM PDT 24 |
Jul 22 08:18:02 PM PDT 24 |
2572171910 ps |
| T970 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1181054806 |
|
|
Jul 22 08:37:36 PM PDT 24 |
Jul 22 09:33:20 PM PDT 24 |
14696563128 ps |
| T821 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.643680360 |
|
|
Jul 22 08:42:15 PM PDT 24 |
Jul 22 08:48:36 PM PDT 24 |
3881124652 ps |
| T690 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1117606806 |
|
|
Jul 22 08:27:38 PM PDT 24 |
Jul 22 08:29:31 PM PDT 24 |
2482607093 ps |
| T815 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.693445540 |
|
|
Jul 22 08:41:30 PM PDT 24 |
Jul 22 08:48:29 PM PDT 24 |
3324365082 ps |
| T41 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.2591711534 |
|
|
Jul 22 08:17:03 PM PDT 24 |
Jul 22 08:21:02 PM PDT 24 |
3270027725 ps |
| T779 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663707660 |
|
|
Jul 22 08:45:38 PM PDT 24 |
Jul 22 08:52:33 PM PDT 24 |
3999241120 ps |
| T971 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3484335183 |
|
|
Jul 22 08:28:57 PM PDT 24 |
Jul 22 08:44:07 PM PDT 24 |
8789193296 ps |
| T972 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2891011188 |
|
|
Jul 22 08:15:20 PM PDT 24 |
Jul 22 08:39:30 PM PDT 24 |
5921632562 ps |
| T71 |
/workspace/coverage/default/4.chip_tap_straps_rma.2819268642 |
|
|
Jul 22 08:36:25 PM PDT 24 |
Jul 22 08:41:05 PM PDT 24 |
4345883050 ps |
| T762 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491411824 |
|
|
Jul 22 08:42:27 PM PDT 24 |
Jul 22 08:48:32 PM PDT 24 |
4143993916 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1829848966 |
|
|
Jul 22 08:14:44 PM PDT 24 |
Jul 22 08:20:40 PM PDT 24 |
3970007002 ps |
| T365 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1275132822 |
|
|
Jul 22 08:37:07 PM PDT 24 |
Jul 22 08:44:49 PM PDT 24 |
5228300534 ps |
| T367 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.151534738 |
|
|
Jul 22 08:39:31 PM PDT 24 |
Jul 22 08:52:15 PM PDT 24 |
5688406528 ps |
| T973 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1272236261 |
|
|
Jul 22 08:16:58 PM PDT 24 |
Jul 23 12:06:48 AM PDT 24 |
77964286790 ps |
| T974 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1152034597 |
|
|
Jul 22 08:23:26 PM PDT 24 |
Jul 22 08:26:39 PM PDT 24 |
2698427768 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.165440013 |
|
|
Jul 22 08:19:37 PM PDT 24 |
Jul 22 08:24:33 PM PDT 24 |
3232313868 ps |
| T431 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3993798206 |
|
|
Jul 22 08:26:14 PM PDT 24 |
Jul 22 08:37:39 PM PDT 24 |
4461528536 ps |
| T341 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.389312390 |
|
|
Jul 22 08:12:08 PM PDT 24 |
Jul 22 08:24:51 PM PDT 24 |
4244371340 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1020461968 |
|
|
Jul 22 08:31:36 PM PDT 24 |
Jul 22 08:46:01 PM PDT 24 |
5881799685 ps |
| T432 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1597990165 |
|
|
Jul 22 08:36:02 PM PDT 24 |
Jul 22 08:46:11 PM PDT 24 |
9485124108 ps |
| T393 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3064522055 |
|
|
Jul 22 08:18:10 PM PDT 24 |
Jul 22 08:24:29 PM PDT 24 |
3714562339 ps |
| T433 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.390619700 |
|
|
Jul 22 08:17:27 PM PDT 24 |
Jul 22 08:21:15 PM PDT 24 |
3000124652 ps |
| T434 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1292590172 |
|
|
Jul 22 08:43:35 PM PDT 24 |
Jul 22 08:52:08 PM PDT 24 |
5640076264 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3531043024 |
|
|
Jul 22 08:20:10 PM PDT 24 |
Jul 22 08:24:19 PM PDT 24 |
2782184390 ps |
| T435 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4245311637 |
|
|
Jul 22 08:18:55 PM PDT 24 |
Jul 22 09:22:35 PM PDT 24 |
16999401330 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2977521090 |
|
|
Jul 22 08:26:43 PM PDT 24 |
Jul 22 08:30:46 PM PDT 24 |
3436354988 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.626436189 |
|
|
Jul 22 08:12:44 PM PDT 24 |
Jul 22 08:25:11 PM PDT 24 |
4697902240 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3649207585 |
|
|
Jul 22 08:41:28 PM PDT 24 |
Jul 22 08:50:28 PM PDT 24 |
6166055785 ps |
| T284 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2824471741 |
|
|
Jul 22 08:31:32 PM PDT 24 |
Jul 22 08:51:41 PM PDT 24 |
5898695867 ps |
| T285 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.992533508 |
|
|
Jul 22 08:32:16 PM PDT 24 |
Jul 22 09:55:42 PM PDT 24 |
16051058204 ps |
| T38 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4160874571 |
|
|
Jul 22 08:25:59 PM PDT 24 |
Jul 22 08:34:27 PM PDT 24 |
6610999860 ps |
| T286 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1115540139 |
|
|
Jul 22 08:12:20 PM PDT 24 |
Jul 22 08:17:04 PM PDT 24 |
3146511350 ps |
| T287 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.672600949 |
|
|
Jul 22 08:14:34 PM PDT 24 |
Jul 22 08:18:41 PM PDT 24 |
2690918744 ps |
| T134 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2722274237 |
|
|
Jul 22 08:12:02 PM PDT 24 |
Jul 22 08:18:05 PM PDT 24 |
5415670260 ps |
| T166 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1746076753 |
|
|
Jul 22 08:42:12 PM PDT 24 |
Jul 22 08:51:50 PM PDT 24 |
5102963000 ps |
| T288 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3057376203 |
|
|
Jul 22 08:28:26 PM PDT 24 |
Jul 22 08:34:39 PM PDT 24 |
2935551576 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3908819723 |
|
|
Jul 22 08:32:33 PM PDT 24 |
Jul 22 08:39:15 PM PDT 24 |
3211443674 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2908489117 |
|
|
Jul 22 08:28:54 PM PDT 24 |
Jul 22 08:33:06 PM PDT 24 |
3495230204 ps |
| T20 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.1322888508 |
|
|
Jul 22 08:10:12 PM PDT 24 |
Jul 22 09:23:55 PM PDT 24 |
19113765628 ps |
| T410 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3216573560 |
|
|
Jul 22 08:41:54 PM PDT 24 |
Jul 22 08:49:41 PM PDT 24 |
6718962052 ps |
| T251 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2802831602 |
|
|
Jul 22 08:47:06 PM PDT 24 |
Jul 22 08:55:54 PM PDT 24 |
4703674840 ps |
| T179 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1460969459 |
|
|
Jul 22 08:13:11 PM PDT 24 |
Jul 22 08:18:22 PM PDT 24 |
3954419456 ps |
| T297 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.578997897 |
|
|
Jul 22 08:46:04 PM PDT 24 |
Jul 22 08:55:35 PM PDT 24 |
5895031950 ps |
| T298 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1726240482 |
|
|
Jul 22 08:11:12 PM PDT 24 |
Jul 22 08:19:20 PM PDT 24 |
3110576260 ps |
| T299 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.620576956 |
|
|
Jul 22 08:36:41 PM PDT 24 |
Jul 22 08:42:42 PM PDT 24 |
7084197462 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.428507514 |
|
|
Jul 22 08:29:25 PM PDT 24 |
Jul 22 09:20:52 PM PDT 24 |
20059960596 ps |
| T300 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.370529293 |
|
|
Jul 22 08:33:27 PM PDT 24 |
Jul 22 08:39:00 PM PDT 24 |
3558431316 ps |
| T301 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1385862554 |
|
|
Jul 22 08:38:08 PM PDT 24 |
Jul 22 08:48:14 PM PDT 24 |
3967886386 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2330743043 |
|
|
Jul 22 08:30:50 PM PDT 24 |
Jul 22 08:42:03 PM PDT 24 |
19529470124 ps |
| T303 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2015590456 |
|
|
Jul 22 08:45:00 PM PDT 24 |
Jul 22 08:50:54 PM PDT 24 |
3555324550 ps |
| T233 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2088605821 |
|
|
Jul 22 08:37:10 PM PDT 24 |
Jul 22 09:02:38 PM PDT 24 |
25851679191 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.1456323340 |
|
|
Jul 22 08:35:02 PM PDT 24 |
Jul 22 09:01:07 PM PDT 24 |
7658306600 ps |
| T978 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.516185213 |
|
|
Jul 22 08:38:42 PM PDT 24 |
Jul 22 09:32:10 PM PDT 24 |
15877510100 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1284436897 |
|
|
Jul 22 08:11:11 PM PDT 24 |
Jul 22 08:14:44 PM PDT 24 |
2809178000 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3723640849 |
|
|
Jul 22 08:29:31 PM PDT 24 |
Jul 22 08:51:13 PM PDT 24 |
8212128436 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1981510692 |
|
|
Jul 22 08:16:59 PM PDT 24 |
Jul 22 08:25:31 PM PDT 24 |
4585483742 ps |
| T744 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1998117844 |
|
|
Jul 22 08:46:58 PM PDT 24 |
Jul 22 08:57:41 PM PDT 24 |
6218828840 ps |
| T687 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1471000807 |
|
|
Jul 22 08:17:53 PM PDT 24 |
Jul 22 08:26:06 PM PDT 24 |
4369137227 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3317060546 |
|
|
Jul 22 08:18:15 PM PDT 24 |
Jul 22 08:23:43 PM PDT 24 |
3182791064 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2522368642 |
|
|
Jul 22 08:21:23 PM PDT 24 |
Jul 22 08:30:52 PM PDT 24 |
4830049900 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2099338646 |
|
|
Jul 22 08:12:43 PM PDT 24 |
Jul 22 08:23:07 PM PDT 24 |
4682025089 ps |
| T982 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.46274188 |
|
|
Jul 22 08:29:29 PM PDT 24 |
Jul 22 09:40:40 PM PDT 24 |
14214738066 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2566109783 |
|
|
Jul 22 08:35:23 PM PDT 24 |
Jul 22 08:39:02 PM PDT 24 |
2874325094 ps |
| T984 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.768596432 |
|
|
Jul 22 08:20:39 PM PDT 24 |
Jul 22 09:31:41 PM PDT 24 |
14389229570 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1528707540 |
|
|
Jul 22 08:12:33 PM PDT 24 |
Jul 22 08:17:32 PM PDT 24 |
3150119337 ps |
| T39 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3091451877 |
|
|
Jul 22 08:12:25 PM PDT 24 |
Jul 22 08:21:01 PM PDT 24 |
5991915460 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3287781347 |
|
|
Jul 22 08:17:10 PM PDT 24 |
Jul 22 08:28:22 PM PDT 24 |
5884489496 ps |
| T986 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3100829644 |
|
|
Jul 22 08:13:20 PM PDT 24 |
Jul 22 08:21:52 PM PDT 24 |
3938561524 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1584410561 |
|
|
Jul 22 08:13:52 PM PDT 24 |
Jul 22 08:18:09 PM PDT 24 |
2853893960 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2114555615 |
|
|
Jul 22 08:16:50 PM PDT 24 |
Jul 22 08:24:38 PM PDT 24 |
3727932572 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.3308083324 |
|
|
Jul 22 08:26:27 PM PDT 24 |
Jul 22 08:32:33 PM PDT 24 |
3617598856 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1596790959 |
|
|
Jul 22 08:16:54 PM PDT 24 |
Jul 22 08:27:12 PM PDT 24 |
4769006160 ps |
| T676 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.1284473114 |
|
|
Jul 22 08:19:12 PM PDT 24 |
Jul 22 08:24:21 PM PDT 24 |
3265164311 ps |
| T111 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.725547541 |
|
|
Jul 22 08:13:59 PM PDT 24 |
Jul 22 08:21:57 PM PDT 24 |
5305818846 ps |
| T441 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.158017280 |
|
|
Jul 22 08:34:13 PM PDT 24 |
Jul 22 08:39:24 PM PDT 24 |
3133615830 ps |
| T442 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1270638630 |
|
|
Jul 22 08:28:26 PM PDT 24 |
Jul 22 08:39:32 PM PDT 24 |
4231732400 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.844970649 |
|
|
Jul 22 08:15:30 PM PDT 24 |
Jul 22 08:20:54 PM PDT 24 |
2691419409 ps |
| T443 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.314051444 |
|
|
Jul 22 08:35:38 PM PDT 24 |
Jul 22 08:45:37 PM PDT 24 |
4499889003 ps |
| T444 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2849136843 |
|
|
Jul 22 08:32:42 PM PDT 24 |
Jul 22 09:53:50 PM PDT 24 |
16006748020 ps |
| T445 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1853469975 |
|
|
Jul 22 08:15:05 PM PDT 24 |
Jul 22 08:32:12 PM PDT 24 |
7063540600 ps |
| T190 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2104230925 |
|
|
Jul 22 08:11:25 PM PDT 24 |
Jul 22 09:36:16 PM PDT 24 |
45191604781 ps |
| T446 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1453536998 |
|
|
Jul 22 08:47:01 PM PDT 24 |
Jul 22 08:55:55 PM PDT 24 |
5925776132 ps |
| T447 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.650163472 |
|
|
Jul 22 08:24:47 PM PDT 24 |
Jul 22 09:26:45 PM PDT 24 |
15134254352 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.4135366757 |
|
|
Jul 22 08:19:11 PM PDT 24 |
Jul 22 08:23:06 PM PDT 24 |
3459964020 ps |
| T992 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2235150851 |
|
|
Jul 22 08:30:28 PM PDT 24 |
Jul 22 09:33:54 PM PDT 24 |
15253760709 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.3921108530 |
|
|
Jul 22 08:28:36 PM PDT 24 |
Jul 22 08:36:17 PM PDT 24 |
4204470356 ps |
| T697 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.506797514 |
|
|
Jul 22 08:24:23 PM PDT 24 |
Jul 22 08:32:33 PM PDT 24 |
4719353174 ps |
| T994 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3266455361 |
|
|
Jul 22 08:15:57 PM PDT 24 |
Jul 22 08:39:15 PM PDT 24 |
7202514984 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3210592790 |
|
|
Jul 22 08:10:51 PM PDT 24 |
Jul 22 08:23:58 PM PDT 24 |
12649660409 ps |
| T739 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.4028392195 |
|
|
Jul 22 08:40:16 PM PDT 24 |
Jul 22 08:51:00 PM PDT 24 |
3877915672 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2650902831 |
|
|
Jul 22 08:11:22 PM PDT 24 |
Jul 22 08:58:21 PM PDT 24 |
12133171880 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1863886449 |
|
|
Jul 22 08:35:58 PM PDT 24 |
Jul 22 08:41:02 PM PDT 24 |
2821266372 ps |
| T321 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2544632981 |
|
|
Jul 22 08:14:18 PM PDT 24 |
Jul 22 08:29:33 PM PDT 24 |
4899783644 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_coremark.1616357659 |
|
|
Jul 22 08:12:44 PM PDT 24 |
Jul 23 12:06:06 AM PDT 24 |
71878356568 ps |
| T997 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3742737114 |
|
|
Jul 22 08:26:48 PM PDT 24 |
Jul 22 08:58:38 PM PDT 24 |
8384343242 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1345368254 |
|
|
Jul 22 08:33:36 PM PDT 24 |
Jul 22 08:38:13 PM PDT 24 |
2553236072 ps |
| T780 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1543298564 |
|
|
Jul 22 08:43:32 PM PDT 24 |
Jul 22 08:55:17 PM PDT 24 |
4343615788 ps |
| T822 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.4056858663 |
|
|
Jul 22 08:43:55 PM PDT 24 |
Jul 22 08:52:11 PM PDT 24 |
4383027412 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1271956931 |
|
|
Jul 22 08:18:11 PM PDT 24 |
Jul 22 08:21:29 PM PDT 24 |
3182093272 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3524601418 |
|
|
Jul 22 08:24:56 PM PDT 24 |
Jul 22 08:52:36 PM PDT 24 |
9980050261 ps |
| T707 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2397790362 |
|
|
Jul 22 08:44:02 PM PDT 24 |
Jul 22 08:49:58 PM PDT 24 |
3180887464 ps |
| T751 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.487987314 |
|
|
Jul 22 08:41:57 PM PDT 24 |
Jul 22 08:51:46 PM PDT 24 |
4453354096 ps |
| T1000 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.50076006 |
|
|
Jul 22 08:28:38 PM PDT 24 |
Jul 22 09:14:24 PM PDT 24 |
10752613413 ps |
| T161 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.1822124018 |
|
|
Jul 22 08:13:38 PM PDT 24 |
Jul 22 08:23:40 PM PDT 24 |
3922661780 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4056437064 |
|
|
Jul 22 08:23:43 PM PDT 24 |
Jul 22 08:58:35 PM PDT 24 |
19626332185 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_power_idle_load.538718065 |
|
|
Jul 22 08:35:07 PM PDT 24 |
Jul 22 08:46:21 PM PDT 24 |
4647188616 ps |
| T688 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.461892789 |
|
|
Jul 22 08:37:13 PM PDT 24 |
Jul 22 08:46:23 PM PDT 24 |
4826836521 ps |
| T1003 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1999123610 |
|
|
Jul 22 08:42:06 PM PDT 24 |
Jul 22 08:52:03 PM PDT 24 |
4843640160 ps |
| T781 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4291680439 |
|
|
Jul 22 08:40:43 PM PDT 24 |
Jul 22 08:49:31 PM PDT 24 |
4084245792 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.307272206 |
|
|
Jul 22 08:11:53 PM PDT 24 |
Jul 22 08:18:00 PM PDT 24 |
3434494936 ps |
| T711 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3079405858 |
|
|
Jul 22 08:21:11 PM PDT 24 |
Jul 22 08:30:28 PM PDT 24 |
4572273908 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2767922569 |
|
|
Jul 22 08:32:05 PM PDT 24 |
Jul 22 08:58:45 PM PDT 24 |
10225461260 ps |
| T335 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1191095957 |
|
|
Jul 22 08:28:39 PM PDT 24 |
Jul 22 08:37:43 PM PDT 24 |
4161243492 ps |
| T1004 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.823326917 |
|
|
Jul 22 08:38:10 PM PDT 24 |
Jul 22 08:54:20 PM PDT 24 |
13435759005 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.368205985 |
|
|
Jul 22 08:28:48 PM PDT 24 |
Jul 22 08:32:46 PM PDT 24 |
2450394256 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2084790466 |
|
|
Jul 22 08:15:03 PM PDT 24 |
Jul 22 08:18:52 PM PDT 24 |
2946457848 ps |
| T816 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.19885365 |
|
|
Jul 22 08:44:48 PM PDT 24 |
Jul 22 08:52:06 PM PDT 24 |
4090845380 ps |
| T675 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2725751072 |
|
|
Jul 22 08:33:10 PM PDT 24 |
Jul 22 08:42:09 PM PDT 24 |
2810291422 ps |
| T737 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3533102476 |
|
|
Jul 22 08:41:50 PM PDT 24 |
Jul 22 08:49:40 PM PDT 24 |
4901127504 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.4018397694 |
|
|
Jul 22 08:12:03 PM PDT 24 |
Jul 22 08:20:50 PM PDT 24 |
4473099858 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.600984884 |
|
|
Jul 22 08:28:31 PM PDT 24 |
Jul 22 08:35:36 PM PDT 24 |
7419831366 ps |
| T804 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2378928842 |
|
|
Jul 22 08:45:33 PM PDT 24 |
Jul 22 08:54:11 PM PDT 24 |
5292666572 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2125589301 |
|
|
Jul 22 08:31:43 PM PDT 24 |
Jul 22 08:40:14 PM PDT 24 |
3879361890 ps |
| T42 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2172459910 |
|
|
Jul 22 08:12:04 PM PDT 24 |
Jul 22 08:19:57 PM PDT 24 |
3095938458 ps |
| T85 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4062400879 |
|
|
Jul 22 08:13:46 PM PDT 24 |
Jul 22 11:44:42 PM PDT 24 |
255071220630 ps |
| T691 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2745869341 |
|
|
Jul 22 08:13:07 PM PDT 24 |
Jul 22 08:15:43 PM PDT 24 |
2751454405 ps |
| T1009 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.2597192755 |
|
|
Jul 22 08:19:14 PM PDT 24 |
Jul 22 08:23:38 PM PDT 24 |
2715398784 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1505269453 |
|
|
Jul 22 08:31:25 PM PDT 24 |
Jul 22 08:35:07 PM PDT 24 |
3005790100 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.173693074 |
|
|
Jul 22 08:11:50 PM PDT 24 |
Jul 22 08:15:24 PM PDT 24 |
2800260200 ps |
| T763 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.421617487 |
|
|
Jul 22 08:44:13 PM PDT 24 |
Jul 22 08:51:51 PM PDT 24 |
3996865016 ps |
| T1012 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.944382538 |
|
|
Jul 22 08:27:51 PM PDT 24 |
Jul 22 09:38:39 PM PDT 24 |
15103297028 ps |
| T767 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3705384966 |
|
|
Jul 22 08:41:31 PM PDT 24 |
Jul 22 08:51:50 PM PDT 24 |
5411936260 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3630687126 |
|
|
Jul 22 08:32:20 PM PDT 24 |
Jul 22 08:43:20 PM PDT 24 |
4762006708 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.1677144379 |
|
|
Jul 22 08:25:26 PM PDT 24 |
Jul 22 08:34:09 PM PDT 24 |
5042799690 ps |
| T820 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330070047 |
|
|
Jul 22 08:44:16 PM PDT 24 |
Jul 22 08:51:13 PM PDT 24 |
3504148840 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_flash_init.1624929427 |
|
|
Jul 22 08:25:39 PM PDT 24 |
Jul 22 09:02:46 PM PDT 24 |
23154430744 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.692717790 |
|
|
Jul 22 08:35:10 PM PDT 24 |
Jul 22 08:40:10 PM PDT 24 |
3782199840 ps |
| T1015 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2335743947 |
|
|
Jul 22 08:35:21 PM PDT 24 |
Jul 22 08:48:30 PM PDT 24 |
4066799528 ps |
| T74 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3855753375 |
|
|
Jul 22 08:23:45 PM PDT 24 |
Jul 22 08:44:30 PM PDT 24 |
21483977592 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2859161396 |
|
|
Jul 22 08:20:26 PM PDT 24 |
Jul 22 08:38:34 PM PDT 24 |
7604266081 ps |
| T713 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3330213323 |
|
|
Jul 22 08:28:39 PM PDT 24 |
Jul 22 08:32:22 PM PDT 24 |
3500026764 ps |
| T101 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4201483195 |
|
|
Jul 22 08:31:53 PM PDT 24 |
Jul 22 09:05:54 PM PDT 24 |
24840919548 ps |
| T64 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.1367914967 |
|
|
Jul 22 08:22:08 PM PDT 24 |
Jul 22 08:25:21 PM PDT 24 |
3270561180 ps |
| T1016 |
/workspace/coverage/default/1.chip_sw_aes_idle.2267046606 |
|
|
Jul 22 08:20:11 PM PDT 24 |
Jul 22 08:23:46 PM PDT 24 |
2849515256 ps |
| T712 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377428613 |
|
|
Jul 22 08:45:59 PM PDT 24 |
Jul 22 08:53:32 PM PDT 24 |
4664870344 ps |
| T774 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.529920723 |
|
|
Jul 22 08:44:21 PM PDT 24 |
Jul 22 08:54:18 PM PDT 24 |
5231525024 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.842130003 |
|
|
Jul 22 08:27:11 PM PDT 24 |
Jul 22 08:40:03 PM PDT 24 |
4381077656 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2793142342 |
|
|
Jul 22 08:30:42 PM PDT 24 |
Jul 22 09:01:53 PM PDT 24 |
28793968425 ps |
| T1018 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3202157352 |
|
|
Jul 22 08:40:47 PM PDT 24 |
Jul 22 09:32:04 PM PDT 24 |
15002968924 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1542273012 |
|
|
Jul 22 08:32:02 PM PDT 24 |
Jul 22 08:37:57 PM PDT 24 |
3102942760 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1110154939 |
|
|
Jul 22 08:24:55 PM PDT 24 |
Jul 22 08:32:14 PM PDT 24 |
5993463944 ps |
| T394 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1303801052 |
|
|
Jul 22 08:26:38 PM PDT 24 |
Jul 22 08:31:59 PM PDT 24 |
3918446772 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1440466538 |
|
|
Jul 22 08:18:45 PM PDT 24 |
Jul 22 08:26:27 PM PDT 24 |
5615285448 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2503363528 |
|
|
Jul 22 08:13:26 PM PDT 24 |
Jul 22 08:51:42 PM PDT 24 |
23816637449 ps |
| T396 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2492426518 |
|
|
Jul 22 08:15:40 PM PDT 24 |
Jul 22 08:19:39 PM PDT 24 |
2338982014 ps |
| T397 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3716510643 |
|
|
Jul 22 08:33:38 PM PDT 24 |
Jul 22 08:50:42 PM PDT 24 |
11681296232 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1495563312 |
|
|
Jul 22 08:24:26 PM PDT 24 |
Jul 22 08:29:48 PM PDT 24 |
3051895100 ps |
| T399 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2377382214 |
|
|
Jul 22 08:30:32 PM PDT 24 |
Jul 22 08:55:04 PM PDT 24 |
12141411009 ps |
| T252 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3941159912 |
|
|
Jul 22 08:45:46 PM PDT 24 |
Jul 22 08:57:54 PM PDT 24 |
6020510464 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2265394627 |
|
|
Jul 22 08:15:36 PM PDT 24 |
Jul 22 08:24:26 PM PDT 24 |
5322263664 ps |
| T1020 |
/workspace/coverage/default/4.chip_tap_straps_prod.2716353949 |
|
|
Jul 22 08:36:33 PM PDT 24 |
Jul 22 08:56:25 PM PDT 24 |
13365698221 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3079320978 |
|
|
Jul 22 08:25:52 PM PDT 24 |
Jul 22 08:45:24 PM PDT 24 |
5962622120 ps |
| T1022 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3554098330 |
|
|
Jul 22 08:35:53 PM PDT 24 |
Jul 22 08:57:23 PM PDT 24 |
12657009200 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3818800686 |
|
|
Jul 22 08:15:30 PM PDT 24 |
Jul 22 08:20:44 PM PDT 24 |
3540581750 ps |
| T51 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2865238910 |
|
|
Jul 22 08:25:09 PM PDT 24 |
Jul 22 08:47:23 PM PDT 24 |
12702944048 ps |
| T423 |
/workspace/coverage/default/2.chip_sw_aes_enc.3599638837 |
|
|
Jul 22 08:30:14 PM PDT 24 |
Jul 22 08:35:43 PM PDT 24 |
2892560014 ps |
| T424 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3568840556 |
|
|
Jul 22 08:17:08 PM PDT 24 |
Jul 22 09:52:09 PM PDT 24 |
23778054472 ps |
| T425 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386367439 |
|
|
Jul 22 08:42:53 PM PDT 24 |
Jul 22 08:49:20 PM PDT 24 |
3702967176 ps |
| T426 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4108632163 |
|
|
Jul 22 08:15:57 PM PDT 24 |
Jul 22 08:24:53 PM PDT 24 |
6661413972 ps |
| T427 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2112368637 |
|
|
Jul 22 08:12:22 PM PDT 24 |
Jul 22 08:24:22 PM PDT 24 |
4682692474 ps |
| T291 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1033157786 |
|
|
Jul 22 08:26:39 PM PDT 24 |
Jul 22 08:39:55 PM PDT 24 |
5218003400 ps |
| T428 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4064930449 |
|
|
Jul 22 08:30:08 PM PDT 24 |
Jul 22 08:43:13 PM PDT 24 |
5540206328 ps |
| T429 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1727418529 |
|
|
Jul 22 08:46:06 PM PDT 24 |
Jul 22 08:56:10 PM PDT 24 |
5831537710 ps |
| T413 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2985837061 |
|
|
Jul 22 08:14:15 PM PDT 24 |
Jul 22 08:18:14 PM PDT 24 |
2987613340 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1819550513 |
|
|
Jul 22 08:19:53 PM PDT 24 |
Jul 22 09:47:12 PM PDT 24 |
51337003807 ps |
| T389 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.571418269 |
|
|
Jul 22 08:32:41 PM PDT 24 |
Jul 22 10:09:48 PM PDT 24 |
18019970340 ps |
| T1024 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.4141382249 |
|
|
Jul 22 08:26:39 PM PDT 24 |
Jul 22 08:30:51 PM PDT 24 |
2692907064 ps |
| T1025 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.388349455 |
|
|
Jul 22 08:17:55 PM PDT 24 |
Jul 22 08:26:59 PM PDT 24 |
5994109053 ps |
| T799 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3120771101 |
|
|
Jul 22 08:47:01 PM PDT 24 |
Jul 22 08:55:55 PM PDT 24 |
4451344008 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3838535523 |
|
|
Jul 22 08:20:39 PM PDT 24 |
Jul 22 08:29:12 PM PDT 24 |
5955145704 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.4190782383 |
|
|
Jul 22 08:32:01 PM PDT 24 |
Jul 22 09:04:21 PM PDT 24 |
9912028880 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3985510373 |
|
|
Jul 22 08:25:57 PM PDT 24 |
Jul 22 08:30:46 PM PDT 24 |
3022053496 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.4180586027 |
|
|
Jul 22 08:19:12 PM PDT 24 |
Jul 22 08:23:08 PM PDT 24 |
2788346028 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2500213146 |
|
|
Jul 22 08:28:34 PM PDT 24 |
Jul 22 08:33:10 PM PDT 24 |
3262474413 ps |